2-instruction set architecture
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8/3/2019 2-Instruction Set Architecture
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Organisasi dan ArsitekturOrganisasi dan Arsitektur
KomputerKomputerPertemuan 2
Instruction Set Architecture
8/3/2019 2-Instruction Set Architecture
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What is a program?What is a program?
A sequence of stepsFor each step, an arithmetic or
logical operation is done
For each operation, a differentset of control signals is needed
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Computer Components:Top LevelComputer Components:Top Level
ViewView
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Instruction CycleInstruction Cycle
Two steps:◦ Fetch
◦ Execute
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Fetch CycleFetch Cycle
Program Counter (PC) holds addressof next instruction to fetchProcessor fetches instruction from
memory location pointed to by PCIncrement PC◦ Unless told otherwise
Instruction loaded into Instruction
Register (IR)Processor interprets instruction and
performs required actions
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Execute CycleExecute Cycle
Processor-memory◦ data transfer between CPU and main
memory
Processor I/O◦ Data transfer between CPU and I/O
module
Data processing◦
Some arithmetic or logical operation ondata
Control◦ Alteration of sequence of operations
◦ e.g. jump
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Example of ProgramExample of Program
ExecutionExecution
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Instruction Cycle -Instruction Cycle -
State DiagramState Diagram
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InterruptsInterrupts
Mechanism by which other modules (e.g. I/O) mayinterrupt normal sequence of processing
Program Timer
◦ Generated by internal processor timer
◦ Used in pre-emptive multi-tasking
I/O◦ from I/O controller
Hardware failure◦ e.g. memory parity error
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Program Flow ControlProgram Flow Control
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Interrupt CycleInterrupt Cycle
Added to instruction cycle
Processor checks for interrupt
◦ Indicated by an interrupt signal
If no interrupt, fetch next instruction If interrupt pending:
◦ Suspend execution of current program
◦ Save context
◦
Set PC to start address of interrupt handler routine◦ Process interrupt
◦ Restore context and continue interrupted program
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Transfer of Control via Transfer of Control via
InterruptsInterrupts
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Instruction Cycle withInstruction Cycle with
InterruptsInterrupts
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Instruction Cycle (withInstruction Cycle (with
Interrupts) - State DiagramInterrupts) - State Diagram
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Memory ConnectionMemory Connection
Receives and sends dataReceives addresses (of locations)
Receives control signals
◦ Read
◦ Write
◦ Timing
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Input/Output ConnectionInput/Output Connection
Similar to memory fromcomputer’s viewpoint
Output
◦ Receive data from computer
◦ Send data to peripheral
Input
◦ Receive data from peripheral◦ Send data to computer
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CPU ConnectionCPU Connection
Reads instruction and dataWrites out data (after processing)
Sends control signals to other
unitsReceives (& acts on) interrupts
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BusesBuses
There are a number of possibleinterconnection systems
Single and multiple BUS
structures are most commone.g. Control/Address/Data bus
(PC)
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What is a Bus?What is a Bus?
A communication pathwayconnecting two or more devices
Usually broadcast
Often grouped◦ A number of channels in one bus
◦ e.g. 32 bit data bus is 32 separate
single bit channelsPower lines may not be shown
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Data BusData Bus
Carries data◦ Remember that there is no
difference between “data” and
“instruction” at this levelWidth is a key determinant of
performance
◦
8, 16, 32, 64 bit
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Address busAddress bus
Identify the source or destinationof data
e.g. CPU needs to read an
instruction (data) from a givenlocation in memory
Bus width determines maximum
memory capacity of system◦ e.g. 8080 has 16 bit address bus
giving 64k address space
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Control BusControl Bus
Control and timing information◦ Memory read/write signal
◦ Interrupt request
◦ Clock signals
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Bus InterconnectionBus Interconnection
SchemeScheme
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Big and Yellow?Big and Yellow?
What do buses look like?◦ Parallel lines on circuit boards
◦ Ribbon cables
◦ Strip connectors on mother boardse.g. PCI
◦ Sets of wires
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Traditional (ISA) Traditional (ISA)
(with cache)(with cache)
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Tugas (1) Tugas (1)
1. Jelaskan mengapa keberadaancache dapat meningkatkanperforma komputer!
2. Jelaskan fungsi setiap komponendi dalam CPU!
3. Jelaskan secara lengkap
mengenai Instruction Cycle padaCPU!
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Tugas (2) Tugas (2)
1. Dikumpulkan dalam bentukhardcopy.
2. Deadline: pertemuan minggu
depan.3. Sertakan Nama dan NIM.
4. Tugas bersifat perseorangan.
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