12-sided polygonal voltage space vector structure for induction motor drive by prof. k. gopakumar...
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12-sided polygonal voltage space vector structure for induction motor
drive
ByProf. K. Gopakumar
CEDT, Indian Institute of Science, Bangalore
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 2
Motivation for the present research.
Some of the schemes to be presented Hybrid space vector PWM strategy in linear and over-modulation
region involving hexagonal and 12-sided polygonal space vector structure.
Development of two concentric 12-sided polygons using conventional 3-level inverters with capacitor balancing.
Further refinement of the above space vector structure into multiple 12-sided polygons with conventional 3-level inverters.
Discussion on experimental verification of the above schemes Steady state operation. Transient results with motor accelerated upto rated speed with
open-loop V/f control Harmonic performance of phase voltage and phase current under
these conditions
Conclusion
Flow of presentation
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 3
Current Technology- Multilevel inverters
• Multi level inverters are popular for high power drives because of low switching losses and low harmonic distortion in the output voltage.
• In conventional structure ,voltage vectors lie on the vertices of a hexagon. So in the extreme modulation range there is a possibility of producing (6n±1) harmonics in the phase current waveform.
•With low switching frequency for high power drives, the (6n±1) harmonics in the current waveform can produce torque pulsation in the drive . The problem is particularly severe in over-modulation region where the (6n±1) harmonics constitute a major portion of the total current.
• In this respect polygonal voltage space vector structures with
sides more than six, is very desirable for high power drives.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 4
Proposed research schemes
• A 12-sided polygonal space vector structure for IM drive has already been proposed using conventional 2-level inverters. This has the advantage of eliminating all (6n±1) harmonics in the phase
current waveform throughout the modulating range. However, one drawback of the scheme is the high dv/dt stress on the devices, since each inverter switches between the vertex of the 12-sided polygon and the zero vector at the centre.
• In the proposed work, a multilevel inverter topology is described which produces a hexagonal space vector structure in lower-modulation region and a 12-sided polygonal space vector structure in the higher modulation region.
• In another scheme, a multilevel voltage space vector structure with vectors on the 12-sided polygon is generated by feeding an open-end winding IM drive by two three level inverters.
•In a third scheme, a high resolution PWM technique is proposed involving multiple 12-sided polygonal space vector structure, that can generate highly sinusoidal voltages at a reduced switching frequency.
A Hybrid Space Vector PWM involving Hexagonal and 12-sided
polygonal voltage space vector structures
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 6
Topology of a multilevel inverter for generation of 12-sided polygonal voltage space vector
R-phase
Pole voltage Level S11 S21 S31
1.366kVdc 3 1 1 1
1.0kVdc 2 0 1 1
0.366kVdc 1 1 0 1
0Vdc 0 1 0 0
• Consists of three cascaded 2-level inverters.
• The switch status for different levels of pole voltage are shown below. These are defined with respect to the lower rail of the dc bus.
Switch status for different levels of pole voltage
A
O
B
D
C
Pole voltage of overall inverter-vAO
Pole voltage of INV3- vBO
Pole voltage of INV2-vAB
Pole voltage of INV1-vCD
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 7
Transformer connection for generation of 12-sided polygonal voltage space vector
•Asymmetrical DC-links are easily realized by a combination of star-delta transformers, since 0.634kVdc=√3 x 0.366kVdc.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 8
Voltage space vector structure of the proposed scheme
• Consists of four concentric hexagonal structures with different radii (0.366kVdc, 0.634kVdc, 1kVdc and 1.366kVdc)
• Operates in the inner hexagons at lower voltage to retain the advantages of multilevel inverter like low switching frequency.
• At higher voltage, the outermost hexagon and the 12-sided polygonal space vector structure is used resulting in highly suppressed 5th and 7th order harmonics.
• The leads to 12-step operation at rated voltage operation, leading to the complete elimination of 6n±1 harmonics. (n=odd) from the phase voltage.
End of linear modulation
OE: 1.225kVdc
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 9
•The modulation index (m), is defined as the ratio of the length of the reference vector to the length of the radius of the 12-sided polygon which extends upto 0.965 in linear modulation range and is equal to 1 at 12-step operation.
•The total dc link voltage for the inverter is 1.366kVdc and the radius of the 12-sided polygon is 1.225kVdc. If the radius of the 12-sided polygonal space vector structure is equal to the radius of a conventional hexagonal space vector structure, then the value of ‘k’ is taken as 1/1.225=0.816.
•For k = 0.816, the maximum phase voltage available in linear modulation is 0.637Vdc and equal to 0.658Vdc in 12-step mode of operation.
• For comparison purpose, if the maximum fundamental voltage available in 6-step mode and 12-step mode are made equal to 0.637Vdc, then ‘k’ is to be chosen as 0.789.
•For k = 0.789, in 12-sided polygonal structure, the maximum phase voltage available in linear modulation is 0.615Vdc and equal to 0.637Vdc in 12-step mode of operation. There is an increase in linear modulation range.
Some additional points on generation of space vectors
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 10
Modulating waveform
• The modulating waveform for phase-A for 35Hz operation (linear modulation range) is shown.
• The modulating waveform is synchronized with the start of the sector (sampling interval is always a multiple of twelve).
• Because of asymmetric voltage levels, three asymmetric synchronized triangles are used; their amplitudes are in the ratio 0.366:0.634:0.366.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 11
Switching sequence analysis
• Three pole voltages are shown for a 60 degree interval at 35Hz operation.
•In ‘A’ phase the voltage level fluctuate between levels ‘3 ’ and ‘2 ’, and in ‘C’ phase the voltage level fluctuates between levels ‘1 ’ and ‘0 ’.
• The sequence in which the switches are operated are as follows: (200), (210), (211), (311), (321), (311), (211), (210), (211), (311), (321), (211), (221), (321), (221), (210), (220), (221), (321), (331), (221), (220), where the numbers in brackets indicate the level of voltage.
• This sequence corresponds to 2
samples per sector.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 12
Experimental Setup
•A digital signal processor (DSP), TMS320LF2812 is used for experimental verification.
•For different levels of output in the pole voltage, three carriers are required. However, it is difficult to synthesize three carrier waves in the DSP, as such only one carrier is used and the modulating wave is appropriately scaled and level shifted.
• A 3.7kW induction motor was fed by the proposed inverter operating under open loop constant V/f control at no load. The motor was made to run under no load in order to show the effect of changing PWM patterns of the generated voltage on the motor current, particularly during transient conditions.
•In order to keep the overall switching frequency within 1 KHz, number of samples is decided as follow:Upto 20 Hz operation: 4 samples per sector.20 Hz-40 Hz: 2 samples per sector.Beyond 40 Hz: 1 sample per sector-extending up to final 12-step mode. Individual inverters are switched less than half of the total cycle.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 13
Experimental results-Operation at 10 Hz
Pole voltage waveforms
Phase voltage and current waveforms
Phase voltage
Phase current
Overall inverter
INV3
INV2
INV1
• Switching happens within the innermost hexagon space vector locations.
• As seen from the pole voltage waveforms, only the lower inverter is switched while the other two inverters are off, hence the switching loss is low.
• Four samples are taken in each sector, so INV3 switching frequency is (12x4X10=480Hz). The first carrier band harmonics also reside around 48 times fundamental.
[Inverter Topology]
Normalized harmonic spectrum of Phase voltage
Phase current
[Space Vector]
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 14
Experimental results-Operation at 30 Hz
• The space vector locations that are switched lie on the boundaries of the second and third hexagon from the center.
• Number of samples are reduced from four to two, thus switching frequency is (fs=12X2x30=720Hz).
• INV3 and INV1 are switched about 1/3rd of the total cycle, while INV2 is switched about 20% of the cycle.
Pole voltage waveforms
Phase voltage and current waveforms
Phase voltage
Phase current
Overall inverter
INV3
INV2
INV1
Normalized harmonic spectrum of Phase voltage
Phase current
[Space Vector]
[Inverter Topology]
INV2 switches
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 15
Operation at 47 Hz ( end of linear modulation range)
• One sample is taken at the start of a sector, so switching frequency is only around (12X47=564Hz).
• The space vector locations that are switched lie between the outer hexagon and the 12-sided polygon.Pole voltage waveforms
Phase voltage and current waveforms
Phase voltage
Phase current
Overall inverter
INV3
INV2
INV1
Normalized harmonic spectrum of Phase voltage
Phase current
[Space Vector]
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 16
Operation at 50 Hz ( 12-step operation)
Inverter Topology
• Complete elimination of 6n±1 harmonics (n=odd) from the phase voltage.
• One sample is taken at the start of a sector (fs=12X1x50=600Hz).
• Each inverter is switched only once in a cycle.
Pole voltage waveforms
Phase voltage and current waveforms
Phase voltage
Phase current
Overall inverter
INV3
INV2
INV1
Normalized harmonic spectrum of Phase voltage
Phase current
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 17
Input current at 50 Hz ( 12-step operation)
• The input current to the inverter is not peaky in nature, because of the presence of the star-delta transformers.
Phase voltage
Phase current
Input phase voltage
Input line current
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 18
Motor acceleration with open loop V/f Control
Transition of motor phase voltage and current from 24 samples to 12 samples per
cycle at 40Hz• Because of the suppression of the 5th and 7th order harmonics, the motor current changes smoothly during the transition when the number of samples per sector is reduced from two to one at 40Hz operation.
• As the speed of the motor is further increased, the inverter switching states pass through the inner hexagons and ultimately the phase voltage becomes a 12-step waveform.
• Under all operating conditions, the carrier is synchronized with the start of the sector.
Transition of motor phase voltage and current from outermost hexagon to 12-
step operation.
Phase voltage
Phase current
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 19
Total Harmonic Distortion upto 100th harmonic
•It is seen that voltage WTHD is quite low for all the operating conditions, as such the torque pulsation and harmonic heating in the
machine is minimized.
Harmonic performance of phase voltage and current
10Hz 30 Hz 48.25 Hz 50Hz
Voltage THD 57.59% 27.51% 14.67% 17.54%
Voltage WTHD 0.81% 0.7% 0.97% 1.04%
Current THD 12.31% 10.59% 15.6% 19.54%
Current WTHD 0.28% 0.45% 1.2% 1.5%
1002
2
1
nn
V
THDV
2100
2
1
n
n
V
nWTHD
V
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 20
• A simplified comparative study is made between the proposed topology and the existing multilevel inverter configurations viz. 3-level NPC and 4-level NPC inverters used for induction motor drives.
•The conduction and switching losses incurred in the inverter, and motor phase voltage harmonic distortions are numerically calculated by computer simulation for comparison.
•A linear turn-on and turn-off switching profile is used for loss calculation. Losses incurred in snubber circuits, protection circuits, gate drives and due to leakage currents are neglected.
•A 2.3kV, 373kW induction motor is driven by a 3-level NPC, 4-level
NPC and the proposed inverter. The inverter drives the induction motor under full load condition at around 0.85 p.f. lagging. Numbers
of samples in a cycle are taken as 24.
Comparison with conventional structures
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 21
Loss comparison with conventional structures
Phase voltage WTHD
IGBT Switchin
g loss
IGBT Conductio
n loss
Conduction loss in
anti-parallel diodes
Clamping diode conduction loss
Total Loss
unit % W W W W W
40 Hz Linear modulation
3-level NPC 0.68 95 2180 272 240 2787
4-level NPC 0.46 61 2400 414 350 3225
Proposed Inv 0.46 96 1884 306 0 2286
48 Hz Over modulation
3-level NPC 1.22 27 2370 165 130 2692
4-level NPC 0.89 20 2616 243 169 3049
Proposed Inv 0.55 25 1995 207 0 2227
50 Hz Square wave mode of operation
3-level NPC 4.64 6 2511 184 0 2701
4-level NPC 4.64 12 2730 258 0 3000
Proposed Inv 1.04 10 2034 180 0 2224
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 22
Observations
The phase voltage WTHD for the proposed inverter shows considerable improvement, particularly at higher modulation indices and the 12-step mode of operation, because of the suppression or elimination of the 6n±1 (n=odd) harmonics.
Conduction losses are more dominant than switching losses for IGBT made inverters. As such, presence of the clamping diodes in NPC inverters increases the total losses of the inverter. The proposed inverter does not have any clamping diode and is devoid of any such losses. The switching losses also remain low for the proposed inverter.
It is seen that the conduction losses in the proposed inverter are always less than the conventional inverters. This is because in the proposed inverter, for any ‘level’ of pole voltage output, two current carrying switches remain in conduction. This is not always the case in NPC inverters; e.g. for a four level inverter, at higher modulation indices, three switches per phase carry the phase load current when the total dc bus voltage is obtained at the pole. Conduction losses in the proposed inverter are further less in over-modulation region because of the fact that the r.m.s. current in the inverter is less compared to conventional NPC inverters, due to the suppression or elimination of the 6n±1 (n=odd) harmonics.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 23
Synopsis
• A multilevel inverter topology is described which produces a hexagonal space vector structure in lower-modulation region and a 12-sided polygonal space vector structure in the higher modulation region.
• In the extreme modulation range, voltage vectors at the vertices of the outer 12-sided polygon and the vertices from the outer most hexagonal structure is used for PWM control, resulting in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at 50Hz where all the 5th and 7th order harmonics are completely eliminated.
• At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible.
• Apart from this, the switching frequency of the multilevel inverter output is always limited within 1 kHz. The middle inverter ( high voltage inverter) devices are switched less than 25% of the output fundamental switching period.
Multilevel 12-sided polygonal voltage space vector structures
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 25
O P
Q
R
SE
F
G
H
I
J K
L
1
2345
6
7
89
1011
12
Hexagonal space vectors.
12-sided polygonal space vectors.
Evolution of space vector structures (Hexagonal and 12-sided)
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 26
Multilevel 12-sided polygonal space vector structure
• This is an extension of the single 12-sided polygonal space vector structure into a multilevel 12-sided structure.
• Compared to conventional 12-sided space vector structure, the device ratings and dv/dt stress on them are reduced to half.
• The switching frequency is also reduced to maintain the same output voltage quality.
• Here the added advantage is the complete elimination of 6n±1 harmonics, n=odd, from the phase voltage throughout the modulation index.
• The linear modulation range is also extended compared to the hexagonal structure.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 27
Multilevel 12-sided polygonal space vector structure
• Consists of two concentric 12-sided polygonal space vector structure.
• Unlike conventional hexagonal multilevel structure, here the sub-sectors are isosceles triangles rather than equilateral triangles.
• Each sector is thus divided into four sub-sectors as shown.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 28
Inverter Structure
• In order to realize the proposed space vector structure, two conventional three level NPC inverters are used to feed an open ended induction motor.
• The two inverters are fed from asymmetrical dc voltage sources which can be obtained from the mains with the help of star-delta transformers and uncontrolled rectifiers.
• Because of capacitor voltage balancing of the NPC inverters, only two dc sources are used.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 29
• Here, the timings for which adjacent vectors are switched are obtained as,
•This requires calculation of sine values through a look-up table, which takes unnecessary memory and time in a DSP.
• A better algorithm is proposed here which can calculate the timings by sampling the reference rotating phasor.
1 1
2 2
0 1 2
6* ;
6
* ;
6
;
sin
sin
sin
sin
ref
ref
s
s
s
V T T
V T T
T T T T
V
V
Algorithm for calculating switching times for multilevel 12-sided polygonal space vector structure
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 30
1. Any rotating phasor can be expressed as,
,ref jV v v t
2. Transform (α,β) into (a,b,c) and (a’,b’,c’) coordinates as
' ' '
2 2 3 2 3, ,3 3 2 2 3 2 2
2 2 2cos( ) sin ( ) , cos( ) sin ( ) ,3 6 6 3 6 6 3
a cb
a cb
v vv v v v v v
v v v v v v v v
3. Multiply va, vb, vc etc. with the sampling period Ts. Thus, / /. , . , .DC DCa s sba bV VT v T T v T etc
4. Calculate the following
' ' ' ' ' ' ' ' ' ' ' ' ' '
1
1
2
2
, , ; , , ;
, , ; , , ;
max , , mid , ,
max , , mid , ,
mid min
mid mina c a c a c a cb b b b
a c a c a c a cb b b b
T
T
T T T T T T T T T T T T T
T T T T T T T T T T T T T
Algorithm for calculating switching times for multilevel 12-sided polygonal space vector structure
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 31
5. Calculate the following
' ' ' '
' ' ' '
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1_12
2_12
3 13 1 *2 , , * , ,
12 2 2
33 * 1 , , 2 , ,
12 2
2 sin max , max ,
2 sin max , max ,
s
s
nd
nd
T
T
T T T T T T T T
T T T T T T T T
6. Since the timings change for each alternate sector, an additional step is needed for interchanging T1_12s and T2_12s.
Then interchange the values of T1_12s and
T2_12s.
OR
OR
OR
if AND ' '1 2 1 21 , ,max ,T T T T T ' ' '
1 2 1 21 , ,2 max ,T nd T T T T
if AND ' ' '1 2 1 21 , ,max ,T T T T T ' '
1 2 1 22 , ,2 max ,T nd T T T T
if AND
if AND ' ' '1 2 1 22 , ,max ,T T T T T ' '
1 2 1 21 , ,2 max ,T nd T T T T
' '1 2 1 22 , ,max ,T T T T T ' ' '
1 2 1 22 , ,2 max ,T nd T T T T
Algorithm for calculating switching times for multilevel 12-sided polygonal space vector structure
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 32
7. For determining the sub-sectors following comparison is made,
If T1_12s <= 0.5Ts If T2_12s <= 0.5Ts If (T1_12s + T2_12s ) <= 0.5Ts then
Subsector-1. else
Subsector-2. else Subsector-3.else Subsector-4.
8. In sub-sector 1, T1= T1_12s, T2= T2_12s, T0=Ts-T1-T2.
In sub-sector 2, T1= 0.5Ts – T1_12s, T2= 0.5Ts – T2_12s, T0=Ts-T1-T2.
In sub-sector 3, T1= T1_12s, T2= 0.5Ts – T2_12s, T0=Ts-T1-T2.
In sub-sector 4, T1= 0.5Ts – T1_12s, T2= T2_12s, T0=Ts-T1-T2.
Algorithm for calculating switching times for multilevel 12-sided polygonal space vector structure
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 33
Experimental results-15 Hz operation
Phase voltage
Pole voltage- high voltage inverter
Pole voltage-low voltage inverter
Phase current
• Four samples are taken in each sector and switching takes place entirely in the inner 12-sided polygon.
• The phase voltage harmonics reside at 15x12x4=720 Hz, which is 48 times the fundamental. However, the switching frequency of the pole voltage of INV1 is (24x15=) 360Hz, while that of INV2 is (32x15=) 480Hz.
• The higher voltage inverter switches about 50% of the cycle.
Normalized harmonic spectrum of Phase
voltage
Phase current
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 34
Experimental results-23 Hz operation
Phase voltage
Pole voltage- high voltage inverter
Pole voltage-low voltage inverter
Phase current
• Three samples are taken in each sector and switching takes place at the boundary the inner 12-sided polygon. All the 6n±1 harmonics, n=odd, are absent from the phase voltage, while the rest are highly suppressed.
• The switching frequencies of the pole voltage of INV1 and INV2 are respectively (18x23=) 414Hz and (24x23=) 552Hz, with output phase voltage switching frequency at 828Hz (=23x12x3).
Normalized harmonic spectrum of Phase
voltage
Phase current
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 35
Experimental results-40 Hz operation
Phase voltage
Pole voltage- high voltage inverter Pole voltage-low voltage inverter
Phase current
• Two samples are taken in each sector and switching takes place between the inner and outer dodecagons.
• This is also seen in the phase voltage waveform, since the outer envelope of the waveform at lower frequency becomes the inner envelope at higher frequency.
• The harmonic spectrum of the phase voltage and current shows the absence of peaky harmonics throughout the range.
Normalized harmonic spectrum of Phase
voltage
Phase current
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 36
Experimental results-48 Hz operation
Phase voltage
Pole voltage- high voltage inverter
Pole voltage-low voltage inverter
Phase current
• This is the end of the linear modulation of operation.• Here the number of samples per sector is two, as such the switching
frequency sidebands reside around 24 times the fundamental. The switching frequency of the pole voltages of INV1 and INV2 is respectively (48x12=) 576Hz and (48x16=) 768Hz, with an output phase voltage switching frequency of 1152Hz (48x12x2).
Normalized harmonic spectrum of Phase
voltage
Phase current
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 37
•At the end of end over-modulation region, 24 samples are taken in a sector, corresponding to the vertices of the polygon. The figure shows 24 steps in the phase voltage.
Experimental results-49.9 Hz operation
Phase voltage
Pole voltage- high voltage inverter
Pole voltage-low voltage inverter
Phase current
Normalized harmonic spectrum of Phase
voltage
Phase current
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 38
Experimental results-50 Hz operation
• This is the 12-step operation, where one sample is taken at the start of a sector. The phase voltage and current is completely devoid of any 5th and 7th order harmonics.
Normalized harmonic spectrum of Phase
voltage
Phase current
Phase voltage
Pole voltage- high voltage inverter
Pole voltage-low voltage inverter
Phase current
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 39
Total Harmonic Distortion upto 100th harmonic
•It is seen that voltage WTHD is quite low for all the operating conditions, as such the torque pulsation and harmonic heating in the
machine is minimized.
1002
2
1
nn
V
THDV
2100
2
1
n
n
V
nWTHD
V
Voltage THD
Voltage WTHD
Current THD
Current WTHD
15Hz 75.4% 1.48% 24.49% 0.56%
23Hz 21.2% 0.54% 9.19% 0.48%
40Hz24.85
%0.71% 12.08% 0.65%
48Hz 9.67% 0.33% 5.52% 0.26%
49.9Hz
7.26% 0.28% 4.68% 0.24%
50Hz17.54
%1.04% 19.54% 1.5%
Harmonic performance of phase voltage and current
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 40
Acceleration of the motor
Transition of motor phase voltage and current from inner to outer 12-sided
polygon
Transition of motor phase voltage and current from over-modulation to 12-step
operation.
Phase voltage
Phase current
• In both the cases, the motor current changes smoothly as the motor accelerates. This happens because of the use synchronized PWM and total elimination of 6n±1 harmonics, n=odd, from the phase voltage throughout the modulation index.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 41
Capacitor balancing scheme
• The inner 12-sided polygonal space vector locations ( points 1-12) have four multiplicities which are complementary in nature in terms of capacitor balancing.
• The outer 12-sided polygonal space vector locations ( points 13-36) either do not cause any capacitor unbalancing, or have complementary states to maintain capacitor balancing.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 42
Inner 12-sided polygon-switching multiplicities for point-1
C2 is discharged, C4 is charged.
C2 is discharged, C3 is charged.
C1 is discharged, C4 is charged.
C1 is discharged, C3 is charged.
The four switching multiplicities are complementary in nature in terms of capacitor balancing.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 43
Outer 12-sided polygon-switching multiplicities
C4 is discharged, C1 & C2 are
undisturbed.
Point-13, two multiplicities
C3 is discharged, C1 & C2 are
undisturbed.
Point-36: no multiplicity, no capacitor disturbance
Point-14: no multiplicity, no capacitor disturbance
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 44
Controller action takenDeliberate unbalancing
Vc1, Vc2
Vc3, Vc4
• Capacitor unbalance is done at steady state with the motor running at 20 Hz speed.
• Both side capacitors are deliberately unbalanced and after some time controller action is taken.
C1,C2 : higher voltage side capacitorsC3,C4 : lower voltage side capacitors
Experimental Results-capacitor unbalancing at 20 Hz
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 45
Experimental Results-capacitor unbalancing at 40Hz
Controller action taken
Deliberate unbalancing
Vc1, Vc2
Vc3, Vc4
• Both the sides are made unbalanced at the same time and are seen to come back to the balanced state.
• Compared to the 20 Hz case, it requires more time to restore voltage balance, since the number of multiplicities in the outer polygon is less.
C1,C2 : higher voltage side capacitorsC3,C4 : lower voltage side capacitors
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 46
capacitor balancing during acceleration
• Capacitor voltages, pole voltages and phase currents during acceleration, showing the capacitor voltages are balanced throughout the operation.
INV1 Pole voltage
Phase current
INV2 Pole voltage
vC1, vC2
vC3, vC4
vC1-vC2
Capacitor voltages
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 47
Publication
• Anandarup Das, K. Sivakumar, Gopal Mondal, K Gopakumar, “A Multilevel Inverter with Hexagonal and 12-sided Polygonal Space Vector Structure for Induction Motor Drive” , published in IECON 2008, Nov 2008, pp 1077-1082.
• Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, “Multilevel Dodecagonal Space Vector Generation for Open-end Winding Induction Motor Drive Using Conventional Three Level Inverters ”, accepted for publication in EPE 2009.
• Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, “A Combination of Hexagonal and 12-sided Polygonal Voltage Space Vector PWM control for IM Drives Using Cascaded Two Level Inverters”, to be published in May 2009 issue of IEEE Transaction on Industrial Electronics.
• Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, “A Pulse Width Modulated Control of Induction Motor Drive Using Multilevel 12-sided Polygonal Voltage Space Vectors”, accepted for publication in IEEE Transaction on Industrial Electronics.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 48
Multiple 12-sided polygons
• With the same power circuit as above, it is possible to have multiple 12-sided polygonal space vector structure.
• Consists of six concentric 12-sided polygonal space vector structure.
• Very low voltage THD can be achieved using low switching frequency.
• Suitable for high power drives.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 49
Conclusion
1. A multilevel inverter topology is described which produces a hexagonal space vector structure in lower-modulation region and a 12-sided polygonal space vector structure in the over-modulation region. This leads to the complete elimination of 6n±1 harmonics (n=odd) from the phase voltage at higher modulation index.
2. A multilevel 12-sided polygonal space vector structure is proposed that does not have 6n±1 harmonics (n=odd) throughout the modulation index. Capacitor balancing scheme is also proposed for the above scheme.
3. These schemes result in improved voltage THD in the motor phase voltage and lower switching frequency operation which are very much desirable in high power drives.
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