10 gigabit ethernet test and measurement challenges · presented by: brian scott geoff waters 10...
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presented by:
Brian Scott
Geoff Waters
10 Gigabit Ethernet Test and Measurement Challenges10 Gigabit Ethernet Test and Measurement Challenges
August 1, 2002
Page 2
10 Gigabit Ethernet Standard10 Gigabit Ethernet Standard• 10 Gigabit Ethernet standard is IEEE 802.3ae • Draft P802.3aeD5.0 was ratified on June 14, 2002• Original intention: Scale 1 Gigabit Ethernet (802.3z) to
10 Gb/s• Some tests proved to be extremely difficult to execute
at 10 Gb/s • 10 GbE Serial Optics Test:
• Stressed-eye receiver sensitivity• Building in the calibrated levels of
deterministic and random jitter • Transmitter jitter through bathtub curve
analysis
Page 3
AgendaAgenda• Standard specifies test
and measurement requirements at all layers
• Today’s topics:• Clause 52: Physical
Medium Dependentsublayer
• Clause 47: 10 Gigabit Attachment Unit Interface (XAUI)
Page 4
The Evolution of IEEE 802.3aeThe Evolution of IEEE 802.3ae• Clause 52: 10 GbE PMD Sublayer Serial Optics Tests:
• New Stressed Receiver Conformance Test• Simplified and changed stressed eye
• Transmitter and Dispersion Penalty Test• Replaces bathtub curve analysis
• XAUI Test:• New 10 Gigabit Ethernet Attachment Unit Interface
(XAUI) between MAC and PCS with 4 lanes of 3.125 Gb/s
• Allows the elimination of the 74 signal-wide interface (XGMII) and associated skew problems
• New 64b/66b line coding (translates 8b/10b)
Page 5
“Golden” Test Fiber
Error Detector
O/E
DUT
CDR
40 MHz Source
>40 MHz Jitter
10.3125 GHz Source
LPF
Modulator
OpticalAtten.
Laser1310 Rx
Tx
10 dB Coupler
Stressed Conditioner
Reference Receiver
Transmitter and Dispersion Penalty Test
Stressed Receiver Conformance Test
IEEE 802.3ae Clause 52 Test SetupIEEE 802.3ae Clause 52 Test Setup
Pattern Generator
1-2 GHz Source
OpticalAtten.
Page 6
Stressed Receiver Conformance TestStressed Receiver Conformance Test• Sinusoidal jitter
modulates the clock timing of the pattern generator
• Sinusoidal interference signal summed with jittered data pattern
• Summed signal low-pass filtered
• Apply the worst case compliant transmitter signal to the receiver
• Verify a BER of better than 1x10-12 is achieved
0 to 40MHz
10.3125GHz
Clock
PatternGenerator
~1-2 GHzsine
7.5 GHzLPF Laser
0 to 40MHz
10.3125GHz
Clock
PatternGenerator
~1-2 GHzsine
7.5 GHzLPF Laser Atten.
Page 7
The “Stressed Eye”The “Stressed Eye”
• Eye impairments include:• Sinusoidal jitter• Horizontal eye
closure • Inter-symbol
interference (ISI)/ Vertical Eye Closure Penalty (VECP)
• Attenuation
Page 8
Stressed Eye ExampleStressed Eye Example• While the concept is
straightforward, construction of the stressed eye requires a careful, systematic approach
• Insufficient stress allows weak parts to appear compliant
• Excessive stress makes possibly good receivers appear non-compliant
Page 9
Building the Stressed EyeBuilding the Stressed Eye• 52.9.10 Stress receiver
conformance test• The standard defines
the test equipment and the procedure
Page 10
Receiver Test Block DiagramReceiver Test Block Diagram
• Stressed eye construction process• PRBS >= 210-1• Set transmitter extinction ratio• Measure Optical Modulation
Amplitude (OMA)• Add ISI induced VECP relative to
OMA• <67% due to filtering
• Add remaining VECP through sinusoidal interferer and sinusoidal jitter
• Iterate (all) to achieve correct VECP
• Attenuate signal to required OMA
• Step through complete sinusoidal jitter template
71612CPG
N1015AJitter Testset
E4422B1-2 GHz
83732B10.3125 GHz
71501D
StressedEye
Testset
Switch
86100B86107A86106B
DUT
DCA
Attenuation
8163B81560A81591A
Rx
70820AJitter Calibration
N1016A
40 MHz 33250A
Page 11
Building the Stressed EyeBuilding the Stressed Eye
• PRBS >= 210-1• Set transmitter
extinction ratio
71612CPG
Stressed EyeTestset
N1016A
Page 12
• Measure Optical Modulation Amplitude (OMA)
• Set nominal Vertical Eye Closure
Building the Stressed EyeBuilding the Stressed Eye
Nominal “1” level
Nominal “0” level
Page 13
Building the Stressed EyeBuilding the Stressed Eye
• Add ISI induced VECP relative to OMA
• <67% due to filtering
71612CPG
Stressed EyeTestset
N1016A
Page 14
Building the Stressed EyeBuilding the Stressed Eye
• Add VECP through sinusoidal jitter
Stressed EyeTestset
N1016AN1015AJitter Testset
83732B10.3125 GHz
70820AJitter Calibration
40 MHz 33250A
Page 15
Building the Stressed EyeBuilding the Stressed Eye
• Add remaining VECP through sinusoidal interferer
Stressed EyeTestset
N1016A
E4422B1-2 GHz
Page 16
71612C
70820AJitter Calibration
Building the Stressed EyeBuilding the Stressed Eye
• Stressed eye construction process
• Iterate (all) to achieve correct VECP
• Attenuate signal to required OMA
• Step through complete sinusoidal jitter template
• Monitor BER at the receiver
PG
N1015AJitter Testset
E4422B1-2 GHz
83732B10.3125 GHz
71501D
opticalSwitch
86100B86107A86106B
DUT
DCA
Attenuation
8163B81560A81591A
Rx
StressedEye
Testset
N1016A
40 MHz 33250A
Page 17
Transmitter and Dispersion Penalty TestTransmitter and Dispersion Penalty Test• 1 Gigabit Ethernet tested with the jitter bathtub
curve• Initial attempts to do 10 Gb/s bathtubs were
unsuccessful as most devices failed!• Some test system error detectors had jitter
problems which masked the true performance of transmitters
• While error detectors existed that generated accurate bathtubs, the clause 52 standards committee chose an alternative test methodology for characterizing optical 10 Gb/s transmitters
• Overall transmitter performance (including jitter) characterized through the “Transmitter and Dispersion Penalty” test or “TDP”
Page 18
Transmitter and Dispersion Penalty TestTransmitter and Dispersion Penalty Test
• 52.9.11 Transmitter and Dispersion Penalty Measurement• The standard defines
the test equipment and the procedure
Page 19
Transmitter and Dispersion Penalty TestTransmitter and Dispersion Penalty Test
71612CError Detector11982A
O/E
83434A CDR
DUT
Tx10 dB Coupler
“Golden” Test Fiber
OpticalAtten.
opticalSwitch
Reference Transmitter
N1016A
8163B81560A
8163B81591A
Amp.
• A test bed including a reference transmitter and reference receiver is characterized for BER with a known level of signal attenuation
• The transmitter under test is substituted for the reference transmitter.
• The TDP figure is the sensitivity level that the system attenuation must be reduced to in order to return to the test bed BER level.
10-12
+/- 5 ps
X X
Page 20
Clause 52 PMD Measurement SummaryClause 52 PMD Measurement Summary
• Stressed Receiver Conformance Test:
• Difficult to construct
• Solution is available that is compliant, calibrated, repeatable and adjustable.
• Transmitter and Dispersion Penalty Test:
• Test Solution can be constructed to successfully complete the test Reference Transmitter Eye
N1016A Stressed Eye Test Set
Stressed Eye
Page 22
Benefits of Using XAUIBenefits of Using XAUI
• Self-clocked XAUI eliminate clock-to-data and data skew issues• Robust CML differential, un-clocked interface allows trace
lengths of 18”on FR4• Commonality with emerging Fibre Channel, Infiniband and
SONET standards• Bi-directional interface requires only 16 point-to-point
connections
Page 24
XAUI - A Self-Managed InterfaceXAUI - A Self-Managed Interface
• Supports robust 8B/10B transmission code• Extra code groups are used for control
signaling• Control words used during IPG and idle
periods for word and lane alignment• This happens without upper layer support• Therefore XAUI functions as a self-managed
interface
Page 25
XGXS DeskewXGXS DeskewSkewed data at receiver input. Skew - 18 bits
Deskew lanes by lining up Align code-groups
Taken from IEEE 802.3ae task force XAUI/XGXS proposal
Page 26
Clock Tolerance Compensation Clock Tolerance Compensation
• XAUI allows for independent clock domains on each side of the link
• Clocks will be at different rates within specified tolerance limits
• Clock Tolerance Compensation (CTC) adds or deletes R code/word to equalize the data rates
Page 27
Challenges of XAUI BER TestingChallenges of XAUI BER Testing
• XENPAK Clock tolerance compensation (CTC) mechanism can make the output non-deterministic
• Scrambler/de-scrambler complicates testing from 3G XAUI to 10G serial optical
• Turning scrambler off results in long runs of zeros with inadequate timing information
• De-skew pattern must be transmitted before required data
• BER is not measured during the transmission of the de-skew pattern
Page 28
XENPAK BER Testing - SolutionsXENPAK BER Testing - Solutions
• CTC ‘frozen’ by synchronizing test equipment to 156.25 MHz reference oscillator in XENPAK
• Generation of four 3.125 Gb/s outputs • Required de-skew pattern may be transmitted • Data capture and post processing allows
direct input to output testing
Page 29
802.3ae Loopback & Embedded Testing802.3ae Loopback & Embedded Testing
• Loopback at PCS, WIS and PMA proposed• Internal pattern generator and error detector• Range of test patterns including PRBS• Identical patterns may be stored in test
equipment custom pattern memory • XAUI i/o and serial optical i/o may be tested• Vendor-specific implementation of these
features offers more testing flexibility• Many vendors loop-back at 10G
Page 30
Serial vs. Parallel BERTSerial vs. Parallel BERT
71612C Serial BERT:• Up to 12.5 Gb/s• General purpose/simple• Differential serial output• One single-ended error
detector input• Four single-ended outputs
up to 3.125 Gb/s• Custom pattern memory• Flexible interfacing• Bathtub jitter (XAUI)• CJPAT/CRPAT etc• 10G Stressed Eye (802.3ae)
81250 Parallel BERT:• Up to 10.8 Gb/s• Modular/expandable/complex• Multiplex to higher rates (PRWS)• Differential inputs and outputs• Adjustable skew between outputs• Variable timing & levels for all
channels• Custom pattern memory• Data capture/post processing
DITO (3G->10G) • CJPAT/CRPAT etc• Bathtub jitter (XAUI)
Page 31
71612C BERT – XAUI Test Applications 71612C BERT – XAUI Test Applications
• Sub-rate outputs:• Four outputs at 1/4 of the main serial
output rate (max 12.5 Gb/s) are available
• Alternate pattern mode – synchronous selection of two different custom transmit patterns
• Enables de-skewing of the XAUI lanes before BER measurement is performed on the required data pattern
Page 32
XAUI BER using XENPAK Clock InputXAUI BER using XENPAK Clock Input
1 2 3
XENPAKDUT
10Gb/s Tx
10Gb/s Rx
XAUI-out
Patterns A & B
1 of 4
Referenceclock in
156.25MHz
10MHz ReferenceE8241A RF Source
86100B DCA(optional)
Electrical
Optical
2.5 GHz/16
0
XAUI-in
3.125 Gb/s clock
from 71612C
Pattern C
12.5 GHz
clock
71612C Pattern Generator 70843C Error Detector
Page 33
XAUI BER using CDR & Multiplier XAUI BER using CDR & Multiplier
1 2 3
XENPAKDUT
10Gb/s Tx
10Gb/s Rx
XAUI-out
PatternsA & B
1 of 4
86100B DCA(optional)
Electrical
Optical
0
XAUI-in
3.125 Gb/s clock
from 71612C
Pattern C12.5 GHz
clock
71612C Pattern Generator 70843C Error Detector
3.125 Gb/s CDR
Clock DataX4 Clockmultiplier
Page 34
XAUI BER using XENPAK Clock Input XAUI BER using XENPAK Clock Input
1 2 3
XENPAKDUT
10Gb/s Tx
10Gb/s Rx
XAUI-out
Patterns A & B
Referenceclock in
156.25MHz
86100B DCA(optional)
Electrical
Optical
0
XAUI-in
81250 ParBERT
Color Key to Modules
• Firewire interface• E4808A Clock Module• E4866A 10.8Gb/s ParBERT• E4861/62B 3.35Gb/s ParBERT
Page 35
10 Gb/s BER using CDR10 Gb/s BER using CDR
XENPAK DUT
10Gb/s Tx
10Gb/s Rx
86100B DCA(optional)Optical
10.3125 Gb/s clock
from 71612C
10.3125 GHz
clock
71612C Pattern Generator 70843C Error Detector
83433AE/O
83434A O/E
Internal
loop-back
Data Input
Page 36
Serial BERT Sub-rate ProgrammingSerial BERT Sub-rate Programming
• Low Frequency Test Pattern (802.3ae)• Pattern consists of alternating groups of
five ones and zeros• BERT programmed with appropriate 12.5
Gb/s serial pattern such that required 3.125 Gb/s patterns appears at sub-rate outputs
111111111111111111110000000000000000000011111111111111111111…Sub-rate 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1…Sub-rate 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1…Etc.
Page 37
Creation of Deskew Pattern Creation of Deskew Pattern
Pattern Bp00000000111111111111111111110000111100001111111100000000000000000000111100001111000000001111111111111111….
0011111010 1100000101 00111110101100000101…-K28.5 +K28.5 -K28.5
This is the required repeating K28.5 sync or ‘K’ word taking into account running disparity rules
The alignment word (A word) and start-of-data word are similarly programmed according to the pattern structure defined in 802.3ae
3.125 Gb/s outputs would output every fourth bit
Page 38
Deskew Pattern (continued)Deskew Pattern (continued)
• Alternate de-skew pattern is run once before the main data pattern
• Both de-skew and main data alternate patterns must be of equal length
• Follow pattern structure rules and fill the end of de-skew pattern out with data characters -not more special control characters
• The characters chosen must end with negative disparity because rules require data to start with negative disparity
Page 39
81250 ParBERT Sequence Editor81250 ParBERT Sequence Editor
• Select appropriate pre-defined test patterns
Page 40
Post-processing with ParBERT Post-processing with ParBERT
• Data used from Ethernet Frame Editor
• XAUI and Serial Analysis
Results:# of frames# of CRC Errors# of Frame Bits# of Idle BitsErrors per LaneError Rate per Lane
Page 41
SummarySummary
• 10 GbE Specifications require new test procedures
• 10 GbE Measurement Resources & Solutions• www.agilent.com/find/10ge
• Specific Product Information:• www.agilent.com/comms/jitter• www.agilent.com/comms/71612c• www.agilent.com/find/parbert• www.agilent.com/comms/routertester
Page 43
Clock Multiplication and DivisionClock Multiplication and Division
• 81250 ParBERT can change an external clock input frequency by ratio m/n; m and n = 1- 255
• XENPAK internal clock 3.125GHz +/-100ppm,1 Hz resolution (RefClk)
• XAUI/RefClk: m/n = 20
• Serial/RefClk: m/n = 66
• Serial/XAUI: m/n = 33/10
Page 44
XAUI BER using CDRXAUI BER using CDR
XENPAKDUT
10Gb/s Tx
10Gb/s Rx
XAUI-out
86100B DCA(optional)
Electrical
Optical
XAUI-in
83434A O/E
Clock Input Data Input
81250 ParBERT Color Key to Modules
• Firewire interface• E4808A Clock Module• E4866A 10.8Gb/s• E4861/62B 3.35Gb/s
Page 45
10Gb/s BER using XENPAK Clock Input10Gb/s BER using XENPAK Clock Input
XENPAK DUT
10Gb/s Tx
10Gb/s Rx
Referenceclock in
156.25 MHz
10MHz ReferenceE8241A RF Source
86100B DCA(optional)Optical
2.5 GHz/16
10.3125 GHz
clock
71612C Pattern Generator 70843C Error Detector
83433A E/O
83434A O/EClock Input Data Input
Internal
loop-back
Page 46
10Gb/s BER using XENPAK Clock Input 10Gb/s BER using XENPAK Clock Input
XENPAK DUT
10Gb/s Tx
10Gb/s Rx
Referenceclock in
156.25MHz
86100B DCA(optional)Optical
83433A E/O
83434A O/E
Clock Input Data Input
Internal
loop-back
81250 ParBERT Color Key to Modules
• Firewire interface• E4808A Clock Module• E4866A 10.8Gb/s• E4861/62B 3.35Gb/s
Page 47
10Gb/s BER using CDR10Gb/s BER using CDR
XENPAK DUT
10Gb/s Tx
10Gb/s Rx
86100B DCA(optional)Optical
83433A E/O
83434A O/E
Clock Input Data Input
Internal
loop-back
1 2 3 Patterns A & B0
E486
7A 1
0.8G
Par
BERT
E480
8A C
lock
Mod
ule
Fire
wire
inte
rfac
e
E480
8A C
lock
Mod
ule
E486
1/63
B 3.
35Gb
Par
BERT
E486
1/63
B 3.
35Gb
Par
BERT
E486
6A 1
0.8G
Par
BERT
E480
8A C
lock
Mod
ule
E480
8A C
lock
Mod
ule
E486
1/62
B 3.
35Gb
Par
BERT
E486
1/62
B 3.
35Gb
Par
BERT
81250 ParBERT
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