1-1 gen module gen module overview gen module initialization general system control / status...
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1-1
GEN Module
•GEN Module Overview
•GEN Module Initialization
•General System Control / Status
•Watchdog Timer
•Cache Control
•PLL configuration
•Independent Programmable Timers
•General Purpose / Special Function Ports
•Interrupt Control
1-2
Gen Module Configuration Space
Address Description
0xffb00000
0xffb00004
0xffb00008
0xffb0000c
System Control Register
System Status Register
PLL Control Register
Software Service Register
0xffb00010
0xffb00014
0xffb00018
0xffb0001c
Timer 1 Control Register
Timer 1 Status Register
Timer 2 Control Register
Timer 2 Status Register
0xffb00020
0xffb00024
Port A Register
Port B Register
Address Description
0xffb00028
0xffb00030
0xffb00034
0xffb00038
Port C Register
Interrupt Enable Register
Interrupt Enable Register - SET
Interrupt Enable Register - CLEAR
0xffb00034
0xffb00038
0xffb00040
0xffb00044
Interrupt Status Register - Enabled
Interrupt Status Register - Raw
Cache Control Register 0
Cache Control Register 1
1-3
Gen Module Initialization
RESETRESET* Low for 40 msec (512 Clocks)
Followed By 1 usec pulse
ADD DON STONES COMMENT
Address Line Bootstrapping
Internal pull up constant current sources on Address Bus; Pull down with 1K Resistor.
ADDR[09:19] GEN_ID11 Bit field with no H/W Implications.Used for Miscellaneous Board Info.
ADDR09..
ADDR19
ADDR25
ADDR26
ADDR27
ADDR[25] IARB0-External Bus Arbiter1-Internal Bus Arbiter
ADDR[26] BUSER0-ARM CPU Disabled.1-ARM CPU Enabled.
ADDR[27] LENDIAN0-Little Endian1-Big Endian
1-4
System Control / Status Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USER BUSER IARB DMATST TEALAST MISALIGN CACHE - CINIT DMARST BSYNC - - - -
LENDIAN BSPEED BCLKD - - - SWE SWRI SWT - BME BMT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - - GEN_ID
REV SW - - LOCK
System Control Register (SCR)
System Status Register (SSR)
POWEXT RSTIO -
1-5
SCR LENDIAN, BSPEED, BCLKD
D31
BSPEED
D30:29
BCLK Runs at00 1/4 SysClk*01 1/2 SysClk10 SysClk11 Not Used
LENDIAN
0x0 0x1 0x2 0x3
0x3 0x2 0x1 0x0
0
1
Big Endian
Little Endian
LSByte of Address
*Net+ARM Power-Up Default
BCLKD
D28
BCLKD
BCLKD Pin0 Enabled1 Low Ouptut
1-6
SCR SWE, SWRI, SWT
D24
SWRI
D23:22
Watchdog Expiry Causes00 IRQ01 FIQ10 Reset11 Not Used
SWE
Watchdog Timer0 Disabled1 Enabled
SWT
D21:20
Watchdog Timeout00 220 / FXTAL
01 222 / FXTAL
10 224 / FXTAL
11 225 / FXTAL
Note: This is a write once operation. There is no changing once set.
1-7
Software Service Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWSR
SWSR
SWSR0xA5 SWSR0x5AD31 D00 D31 D00
Watchdog Acknowledged
SWSR0x123 SWSR0x321D31 D00 D31 D00
FollowedBy
FollowedBy
“Kick the Dog”
Perform Software Reset
Software Reset
1-8
NET+ARM Cache
CacheTags
CacheRAM
CBus
BBus
BIU&
CacheController
Pre-FetchController
ARM7CPUCore
CCR0CCR1
Note: Data fetched from Cache RAM need not assert BBUS.
0xFFF0 0000
0xFFF0 3FFF
1-9
Cache RAM
SCR CACHE, CINIT
D9
CACHE
Cache Memory0 Disabled1 Enabled
CINIT
D7
Cache InitializationNote: Disabling cache saves power.
0x0000 0000
0xFFF0 0000
0xFFFF FFFFCINIT = 1
Write ‘0’ from0xFFF0 0000
thru 0xFFFF 3FFF
CINIT = 0
0xFFF0 3FFF16 Kbytes
Net+ARMMemory
1234
Cache Sets
1-10
Cache Control Registers
• Two Identical Registers– Independent Regions of Memory for each
– Four Sets for each CCR
• Example – Net+OS BSP– Start Address = 0x0A00 0000 (BASE=0x0A)
– Size = 32Mbytes (MASK=0xFE; Use Upper 7 Bits)• End Address = 0x0BFF FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE SUPV RESERVED WP FRC32 RESERVED - - - - - SET1
BASE MASK
SET2 SET3 SET4
1-11
CCR0, 1 BASE, MASK
D23
MASK
Net+ARMMemory
0x0000 0000
0xFFFF FFFF
D16
0xXXFF FFFF
D31
BASE
D24
0xXX00 0000
START of Cacheable Region
END of Cacheable Region*
*Note: MASK does not directly define the END of cacheable region. Cache Hit is Defined When: (MASK & Cbus{A31:A24}}) == (BASE & MASK)
1-12
Cache Example - Net+OS BSP
D23
MASK = FE
Net+ARMMemory
0x0000 0000
0xFFFF FFFF
D16
0x0BFF FFFF
D31
BASE = 0A
D24
0x0A00 0000
START of Cacheable Region
END of Cacheable Region*
*Note: MASK does not directly define the END of cacheable region. Cache Hit is Defined When: (MASK & Cbus{A31:A24}}) == (BASE & MASK)
MASK = 1111 1110BASE = 0000 0100 = 0x0A = 0000 0101 = 0x0B
1-13
CCR0, 1 ENABLE, WP, SET
D15
ENABLE
Cache Region Enable0 Disabled1 Enabled
WP
D12
Write Protect0 R/W Access1 Read Only
SET1 SET2 SET3 SET4
D03 D00
Cache SET Enable0 SET not used with this region1 SET used with this region
Cache RAM
0xFFF0 0000
0xFFF0 3FFF
SET1
SET2
SET3
SET4
1-14
Cache Considerations
Stack
Heap
Data
Text
Vector Table
Aliasing
To Top of Mem
Stack
Heap
Data
Text
Vector Table
Stack
Heap
Data
TextVector Table
Make Cacheable
1-15
SSR REV, GEN_ID
D31
HardCoded Revision ID
REV
GEN_ID
D10
Determined by Address Lines ADDR09:19 at Powerup
Note: Net+ARM H/W unaffected by GEN_ID.
D24 Net+ARM REV
5&1012-115-015-115-215-315-440-040-140-240-340-450
0x00x10x20x30x40x50x60x70x70x80x90xb
0x19
RESET
ADDR09..
ADDR19
D00
1-16
SSR EXT, POW, SW, RSTIO
EXT POW SW RSTIO
D23 D20
Read-Only Reset Status Indicators
Indicates last reset wascaused by RESET* pin.
Indicates last reset wascaused by Power-UP.
Indicates last reset wascaused by WatchDog.
Indicates last reset wascaused by ENI RSTIO* pin.
1-17
PLL Control Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - POLTST INDIV ICP OUTDIV
- - - - PLLCNT - - - - - - - -
• PLLCNT– Controls FSYSCLK when PLLTST* is left floating (internal pull-up)
– Controls FXTAL (always)
– POLTST, INDIV, ICP, OUTDIV– PLL Manufacturer parameters
1-18
PLLCNT & FSYSCLK
NA+50
NA+15/40
PLLCNT FSYSCLK (MHz)
0*123456789
101112131415
22.118422.118422.118422.118425.804829.491233.177636.868440.550044.236847.923251.609655.296058.982462.668866.3552
PLLTST*
XTAL1
XTAL218.432 MHz
IF (PLLCNT <=3)
FSYSCLK = (FCRYSTAL / 5) x 6
ELSE
FSYSCLK = (FCRYSTAL / 5) x (PLLCNT + 3)
*Note: Net+ARM Initialization default.
1-19
Timer Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITC
TE TIE TIRQ TPRE TCLK ITC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- TIP - - - CTC
Timer Control Register (TCR)
Timer Status Register (TSR)
CTC
1-20
TCR TE, TIE, TIRQ, TPRE, TCLK
TE TIE TIRQ TPRE
D31 D27
PreScalar0 Disable1 Enable - Allows for longer timeouts.
Interrupt Type0 IRQ1 FIQ
Interrupt Enable0 Disable Interrupt1 Enable Interrupt
Timer Enable0 Disable Timer1 Enable Time
TCLK
Timer Clock Source0 FXTAL
1 FSYSCLK
1-21
TCR ITC
ITC
D26 D00
Initial Timer Count Determines Timeout Value
Using FSYSCLK Using FXTAL
With Prescalar Without Prescalar With Prescalar Without Prescalar
18ITC
FSYSCLK 14096
ITCFSYSCLK
14096ITC
FXTAL 18
ITCFXTAL
Timeout Values
1-22
TSR TIP, CTC
TIP
D30
Timer Interrupt Pending 0 No Interrupt Pending 1 Interrupt Pending Set when CTC = 0 Firmware must acknowledge by writing a ‘1’ to this position.
D26
CTC
D00
Current Time Counter Firmware can read at any time.
1-23
NET+ARM Interrupts
StatusRegister Raw
Interrupt EnableRegister
Interrupt SourcesFrom DMA1 to PortC0
32
323
TimerInterruptControl*
3
IRQ
FIRQ
Bit-WiseAND
32
3
Status RegisterEnabled
32
OR
OR
*FIRQ Option for Timers 1 & 2, and Watchdog Timer
1-24
Interrupt Assignments
•No Hardware Priority Mechanism For Interrupts•When IRQ Occurs, Firmware Must Find Cause
Format For All 5 Interrupt-Related Registers31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0SER1
RXSER1
TXSER2
RXSER2
TX- - - - - WATCH
DOGTIMER
1TIMER
2PORT
C3PORT
C2PORT
C1PORT
C0
DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 DMA10 ENI1 ENI2 ENI3 ENI4ENET
RXENET
TX
1-25
General Purpose Port Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - - - - - DATA
MODE DIR
• Each DATA bit in a port register is configured with two bits in the same register.– DATA Bit X is controlled by Bit X + 16 (DIR) and Bit X+24 (MODE)
• MODE bit determines either GPIO(0) or Special Purpose(1)
• DIR bit determines direction for GPIO, or defines the Special Purpose
1-26
GPIO Port Register Addresses
• Port A: 0xFFB0 0020
• Port B: 0xFFB0 0024
• Port C: 0xFFB0 0028
1-27
PORTA MODE, DIR, DATA
DATA Bit
MODE = 0GPIO Mode
MODE = 1Special Function
DIR = 1Output Mode
DIR = 0Input Mode
DIR = 0Output Mode
PORTA7PORTA6PORTA5PORTA4
PORTA3PORTA2PORTA1PORTA0
GPIO INGPIO INGPIO INGPIO IN
GPIO INGPIO INGPIO INGPIO IN
GPIO OUTGPIO OUTGPIO OUTGPIO OUT
GPIO OUTGPIO OUTGPIO OUTGPIO OUT
DREQ1*
SPI-S-CLK_IN-A*RXCA-IN
RXDADSRA*CTSA*DCDA*
DONE-IN1*
TXDADTRA*RTSA*
SPI-M-CLK_OUT-ARXCA-OUT
OUT1A*
DACK1*
DONE-OUT1*
DIR = 0Input Mode
SPI-Related Setting
External DMA-Related Setting
1-28
PORTB MODE, DIR, DATA
DATA Bit
MODE = 0GPIO Mode
MODE = 1Special Function
DIR = 1Output Mode
DIR = 0Input Mode
DIR = 0Output Mode
PORTB7PORTB6PORTB5PORTB4
PORTB3PORTB2PORTB1PORTB0
GPIO INGPIO INGPIO INGPIO IN
GPIO INGPIO INGPIO INGPIO IN
GPIO OUTGPIO OUTGPIO OUTGPIO OUT
GPIO OUTGPIO OUTGPIO OUTGPIO OUT
DREQ2*
SPI-S-CLK_IN-B*RXCB-IN
RXDBDSRB*CTSB*DCDB*
DONE-IN2*
TXDBDTRB*RTSB*
SPI-M-CLK_OUT-B*RXCB-OUT
OUT1B*
DACK2*
DONE-OUT2*
DIR = 0Input Mode
SPI-Related Setting
External DMA-Related Setting
1-29
PORTC MODE, DIR, DATA
DATA Bit
MODE = 0GPIO Mode
MODE = 1Special Function
DIR = 1Output Mode
DIR = 0Input Mode
DIR = 0Output Mode
PORTC7
PORTC6PORTC5
PORTC4PORTC3PORTC2PORTC1PORTC0
GPIO IN
GPIO INGPIO IN
GPIO INGPIO IN**GPIO INGPIO INGPIO IN
GPIO OUT
GPIO OUTGPIO OUT
GPIO OUTGPIO OUTGPIO OUTGPIO OUTGPIO OUT
SPI-S-ENABLE-A*TXCA-IN
RIA*SPI-S-ENABLE-B*
TXCB-IN
RIB*CI3-0CI2-0CI1-0CI0-0
SPI-M-ENABLE-A*TXCA-OUT
OUT2A*IRQ-OUT*
SPI-M-ENABLE-B*TXCB-OUT
OUT2B*
CI3-1CI2-1CI1-1CI0-1
DIR = 0Input Mode
**Configuration for AMUX Setting in MMCR
SPI-Related Setting
Interrupt-Related Setting
1-30
Example Port Settings
PORTA7 / TXDAPORTA6 / DTRA* / DRQ1*
PORTA5 / RTSA*PORTA4 / OUT1A* / RXCA
PORTA3 / RXDAPORTA2 / DSRA* / DACK1*
PORTA1 / CTSA*PORTA0 / DCDA* / DONE1*
4-WireSerial
Interface
TX
RTS
RX
CTS
Port A ConfigurationPin MODE DIRA7 1 1A6 0 XA5 1 1A4 0 XA3 1 0A2 0 XA1 1 0A0 0 X
X = Don’t Care
1-31
GPIO Drive Levels - mA
PORTA7 / TXDAPORTA6 / DTRA* / DRQ1*
PORTA5 / RTSA*PORTA4 / OUT1A* / RXCA
PORTA3 / RXDAPORTA2 / DSRA* / DACK1*
PORTA1 / CTSA*PORTA0 / DCDA* / DONE1*
PORTB7 / TXDBPORTB6 / DTRB* / DRQ2*
PORTB5 / RTSB*PORTB4 / OUT1B* / RXCB
PORTB3 / RXDBPORTB2 / DSRB* / DACK2*
PORTB1 / CTSB*PORTB0 / DCDB* / DONE2*
PORTC7 / OUT2A / TXCAPORTC6 / RIA* / IRQO*
PORTC5 / OUT2B / TXCBPORTC4 / RIB*
PORTC3 / AMUXPORTC2PORTC1PORTC0
22222222
22222222
44448888
1-32
Port C Special Function - Interrupts
InterruptConfiguration
PORTC7 / OUT2A / TXCAPORTC6 / RIA* / IRQO*
PORTC5 / OUT2B / TXCBPORTC4 / RIB*
PORTC3 / AMUX
PORTC2
PORTC1
PORTC0
Port C ConfigurationPin MODE DIRC3 1 0-Hi to LowC2 1 1-Low to HiC1 1 0C0 1 1
1-33
GPIO Port Interrupt Operation Requirements
• Interrupt source connected to GPIO Port X’s pins
• Interrupts applied to a GPIO Port X’s pins and interrupts processed by GPIO Port X’s ISR can be tracked (Optional)
• Interrupt source can be deactivated (or cleared) by GPIO Port X’s ISR
1-34
Summary of GPIO Port Interrupts
• GPIO Port interrupts are EXTERNAL interrupts
• Interrupt source MUST be deactivated by the ISR or system locks up
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