© digital integrated circuits 2nd devices 1 digital integrated circuits a design perspective the...

© Digital Integrated Circuits2nd Devices1

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

The DevicesThe Devices

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

July 30, 2002

© Digital Integrated Circuits2nd Devices2

A model for manual analysisA model for manual analysis

© Digital Integrated Circuits2nd Devices3

Simulation versus Model (NMOS)Simulation versus Model (NMOS)

The square-law model doesn’t match well with simulations Only fits for low Vgs, low Vds (low E-field) conditions

Chris Kim

© Digital Integrated Circuits2nd Devices4

Simulation versus Model (PMOS)Simulation versus Model (PMOS)

Not as bad as the NMOS device Still large discrepancies at high E-field conditions

Chris Kim

© Digital Integrated Circuits2nd Devices5

Simulation versus Model (ISimulation versus Model (Idsds vs. V vs. Vgsgs))

Saturation current does not increase quadratically The simulated curves looks like a straight line Main reason for discrepancy: velocity saturation

Chris Kim

© Digital Integrated Circuits2nd Devices6

Velocity SaturationVelocity Saturation

E-fields have gone up as dimensions scale Unfortunately, carrier velocity in silicon is limited Electron velocity saturates at a lower E-field than holes Mobility (μe=v/E) degrades at higher E-fields Simple piecewise linear model can be used

Chris Kim

© Digital Integrated Circuits2nd Devices7

Velocity SaturationVelocity Saturation

csat

cnn

c

e

EEforv

EEfor

EE

Ev

1

1

e

satc

vE

2

[Toh, Ko, Meyer, JSSC, 8/1988]

Modeled through a variable mobility n=1 for PMOS, n=2 for NMOS To get an analytical expression, assume n=1

Chris Kim, Kia

L Vds

xdVdx0 0

)((...)(...)W

EdxxdVdx

xdV

xVVVCI

c

e

tgsoxds .1.)(

1

)(

)).((

© Digital Integrated Circuits2nd Devices8

Velocity SaturationVelocity Saturation Plug it into the original current equation

LEVV

LEVVV

VVVVVWvC

VV

LEV

VVVV

L

WC

I

ctgs

ctgsdsat

dsatdsdsattgssatox

dsatds

c

ds

dsdstgsoxe

ds

)(

)(

)()(

)(1

1

2)(

2

Equate the two expressions to get

Chris Kim, Kia

tgstgstgs VVVVVV )).((

)( dsV

© Digital Integrated Circuits2nd Devices9

Simulation versus ModelSimulation versus Model

Model incorporating velocity saturation matches fairly well with simulation

Chris Kim

© Digital Integrated Circuits2nd Devices10

Current-Voltage RelationsCurrent-Voltage RelationsThe Deep-Submicron EraThe Deep-Submicron Era

LinearRelationship

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Early Saturation

© Digital Integrated Circuits2nd Devices11

PerspectivePerspective

IDLong-channel device

Short-channel device

VDSVDSAT VGS - VT

VGS = VDD

© Digital Integrated Circuits2nd Devices12

IIDD versus V versus VGSGS

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VGS (V)

I D (

A)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VGS (V)

I D (

A)

quadratic

quadratic

linear

Long Channel Short Channel

© Digital Integrated Circuits2nd Devices13

IIDD versus V versus VDSDS

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

ResistiveSaturation

VDS = VGS - VT

Long Channel Short Channel

© Digital Integrated Circuits2nd Devices14

A unified modelA unified modelfor manual analysisfor manual analysis

S D

G

B

© Digital Integrated Circuits2nd Devices15

Simple Model versus SPICE Simple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS

(V)

I D (

A)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT

© Digital Integrated Circuits2nd Devices16

A PMOS TransistorA PMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0-1

-0.8

-0.6

-0.4

-0.2

0x 10

-4

VDS (V)

I D (

A)

Assume all variablesnegative!

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V

© Digital Integrated Circuits2nd Devices17

The Transistor as a SwitchThe Transistor as a SwitchID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

dsatdsat

tgsoxdsat

gs

dsdsatds

VV

VVL

WCI

VddV

VII

).2

(

)1(

)6

51(.

4

3

))2

1(2

11.(

2

))2/1(

2/

)1((2

1

VddI

Vdd

VddVdd

I

Vdd

VddI

Vdd

VddI

VddR

dsat

dsat

VddVgsdsatVddVgsdsateq

Eq added by Kia

© Digital Integrated Circuits2nd Devices18

The Transistor as a SwitchThe Transistor as a SwitchID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

dsatdsat

tgsoxdsat

gs

dsdsatds

VV

VVL

WCI

VddV

VII

).2

(

)1(

)9

71(.

4

3

)1(2/

12/

VddI

Vdd

dvVI

V

VddR

dsat

Vdd

Vdddsat

eq

Eq added by Kia

© Digital Integrated Circuits2nd Devices19

MOS CapacitancesMOS CapacitancesDynamic BehaviorDynamic Behavior

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Dynamic Behavior of MOS TransistorDynamic Behavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB

© Digital Integrated Circuits2nd Devices21

The Gate CapacitanceThe Gate Capacitance

tox

n+ n+

Cross section

L

Gate oxide

xd xd

L d

Polysilicon gate

Top view

Gate-bulkoverlap

Source

n+

Drain

n+W

© Digital Integrated Circuits2nd Devices22

Gate CapacitanceGate Capacitance

S D

G

CGC

S D

G

CGC

S D

G

CGC

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

© Digital Integrated Circuits2nd Devices23

Gate CapacitanceGate Capacitance

WLCox

WLCox

2

2WLCox

3

CGC

CGCS

VDS /(VGS-VT)

CGCD

0 1

CGC

CGCS = CGCDCGC B

WLCox

WLCox

2

VGS

Capacitance as a function of VGS(with VDS = 0)

Capacitance as a function of the degree of saturation

© Digital Integrated Circuits2nd Devices24

Diffusion CapacitanceDiffusion Capacitance

Bottom

Side wall

Side wallChannel

SourceND

Channel-stop implant NA1

SubstrateNA

W

xj

LS

© Digital Integrated Circuits2nd Devices25

Capacitances in 0.25 Capacitances in 0.25 m CMOS m CMOS processprocess