© 2000 morgan kaufman overheads for computers as components system components ztiming diagrams....
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© 2000 Morgan Kaufman
Overheads for Computers as Components
System components
Timing diagrams.Memory.Busses and interconnect.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Timing diagrams
A timing diagram shows a trace through the operation of a system. Generally used for asynchronous machines with timing
constraints.
enq
ack
© 2000 Morgan Kaufman
Overheads for Computers as Components
Timing diagram syntax
Constant value:
Stable:
Changing:
Unknown:
0
1
© 2000 Morgan Kaufman
Overheads for Computers as Components
Timing constraints
Minimum time between two events:
enq
ack
20 ns
© 2000 Morgan Kaufman
Overheads for Computers as Components
Origin of timing constraints
Control signals are passed on the bus:
a
20 ns
c
D Q
© 2000 Morgan Kaufman
Overheads for Computers as Components
Memory device organization
Memory arrayn r
c
© 2000 Morgan Kaufman
Overheads for Computers as Components
Memory parameters
Size. Address width.
Aspect ratio. Data width.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Types of memory
ROM: Mask-programmable. Flash programmable.
RAM: DRAM. SRAM.
© 2000 Morgan Kaufman
Overheads for Computers as Components
SRAM vs. DRAM
SRAM: Faster. Easier to integrate with logic. Higher power consumption.
DRAM: Denser. Must be refreshed.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Typical generic SRAM
SRAM
CE’
R/W’
Adrs
Data
© 2000 Morgan Kaufman
Overheads for Computers as Components
Generic SRAM timing
time
CE’
R/W’
Adrs
Data
read write
From SRAM From CPU
© 2000 Morgan Kaufman
Overheads for Computers as Components
Generic DRAM device
DRAM
CE’
R/W’
Adrs
Data
RAS’
CAS’
© 2000 Morgan Kaufman
Overheads for Computers as Components
Generic DRAM timing
time
CE’
R/W’
RAS’
CAS’
Adrs
Data
rowadrs
coladrs
data
© 2000 Morgan Kaufman
Overheads for Computers as Components
Page mode access
time
CE’
R/W’
RAS’
CAS’
Adrs
Data
rowadrs
coladrs
data
coladrs
coladrs
data data
© 2000 Morgan Kaufman
Overheads for Computers as Components
RAM refresh
Value decays in approx. 1 ms.Refresh value by reading it.
Can’t access memory during refresh.CAS-before-RAS refresh.Hidden refresh.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Other types of memory
Extended data out (EDO): improved page mode access.
Synchronous DRAM: clocked access for pipelining.
Rambus: highly pipelined DRAM.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Flash issues
Flash is programmed at system voltages.
Erasure time is long.Must be erased in blocks.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Generic bus structure
Address:
Data:
Control:
m
c
n
© 2000 Morgan Kaufman
Overheads for Computers as Components
Electrical bus design
Bus signals are usually tri-stated.Address and data lines may be
multiplexed.Every device on the bus must be able to
drive the maximum bus load: Bus wires. Other bus devices.
Bus may include clock signal. Timing is relative to clock.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Four-cycle handshake
enq
ack
4
1
data
2
3
© 2000 Morgan Kaufman
Overheads for Computers as Components
Busses as communicating machines
enq = 1
enq = 0
0
1
1
0
M1
ack = 0
ack = 1
0
1
1
0
M2
ack
ack
enq
enq
© 2000 Morgan Kaufman
Overheads for Computers as Components
When should you handshake?
When response time cannot be guaranteed in advance: Data-dependent delay. Component variations.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Fixed-delay memory access
CPU
memory
R/W
data = mem[adrs]
R
Wmem[adrs] =data
R/W
data
adrs
read = 1adrs = A
reg = data
© 2000 Morgan Kaufman
Overheads for Computers as Components
Variable-delay memory access
CPU
memory
read = 1adrs = A
reg = data
R/W
done = 0
data = mem[adrs]done = 1
mem[adrs] =data
done = 1R
W
R/W
data
adrsdone
y
n
done
© 2000 Morgan Kaufman
Overheads for Computers as Components
Typical bus access
time
clock
R/W’
Addressenable
adrs
DataReady’
data
read write
© 2000 Morgan Kaufman
Overheads for Computers as Components
Bus mastership
Bus master controls operations on the bus.
CPU is default bus master.Other devices may request bus
mastership. Separate set of handshaking lines. CPU can’t use bus when it is not master.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Direct memory access (DMA)
DMA provides parallelism on bus by controlling transfers without CPU.
CPU
memory I/O
DMA
© 2000 Morgan Kaufman
Overheads for Computers as Components
DMA operation
CPU sets up DMA transfer: Start address. Length. Transfer block length. Style of transfer.
DMA controller performs transfer, signals when done: Cycle-stealing. Priority.
© 2000 Morgan Kaufman
Overheads for Computers as Components
PowerPC busses
© 2000 Morgan Kaufman
Overheads for Computers as Components
USB 2.0
Goals: Easy to use. Low cost for consumer devices. Up to 480 Mb/s. Real-time audio, video. Both isochronous and asynchronous
communication.
© 2000 Morgan Kaufman
Overheads for Computers as Components
USB architecture
host
device
device
device
interconnect
Bus topology.Stack.
Data flow model.Schedule.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Bus tiers
host
function
hub
hub
function
function
function
Tier 1 tier 2 tier 3 tier 4 …. tier 7
Device = {hub, function}
© 2000 Morgan Kaufman
Overheads for Computers as Components
USB signaling
Speeds: High-speed is 480 Mb/s. Full-speed is 12 Mb/s. Low-speed is 1.5 Mb/s.
Signals: Vbus, Gnd. D+, D-.
© 2000 Morgan Kaufman
Overheads for Computers as Components
USB power
USB devices can pull a limited amount of power from the bus. May also supply their own power.
System may provide a power-management protocol. Independent of USB.
© 2000 Morgan Kaufman
Overheads for Computers as Components
USB bus protocol
Polled bus, all transfers initiated by host.
Basic transaction: Host sends token packet:
Type and direction.USB device number.Endpoint number (subdevice).
Data transfer packet. Acknowledge packet.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Robustness
Error detection/correction.Automatic handling of device
attach/detach.Self-recovery in protocol.Streaming data management.Pipes for data management.
© 2000 Morgan Kaufman
Overheads for Computers as Components
USB pipes
Functions are allocated to data pipes. Pipes limit interference between
functions.Bandwidth is allocated among pipes.Devices must supply buffer memory.
© 2000 Morgan Kaufman
Overheads for Computers as Components
USB data flow model
Four types of implementation: Device hardware. Client software to
connect to application.
USB system software.
USB host controller (host side system interface).
host device
Client SW
USB systemSW
USB hostcontroller
function
USB logicaldevice
USB businterface
Physicalcommunication
© 2000 Morgan Kaufman
Overheads for Computers as Components
Logical bus topology
Bus appears to be a simple host/device system:
host
devicedevice
device
© 2000 Morgan Kaufman
Overheads for Computers as Components
Client software view
Each client sees its own function but not the whole system:
function
Client SW
function
Client SW
function
Client SWfunction
Client SW
© 2000 Morgan Kaufman
Overheads for Computers as Components
Endpoints
Each logical device is a collection of endpoints.
Each endpoint is simplex (input or output).Endpoint description:
Bus frequency/latency. Bandwidth requirement. Endpoint number. Error handling requirements. Maximum packet size. Transfer type. Transfer direction.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Pipes
Two types of pipes: Stream. Message.
Pipe description includes: Pipe type. Direction. Bus access and bandwidth.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Bus transfer types
Data goes through the pipe in FIFO order.
Four types of transfers: Control. Isochronous—periodic data stream. Interrupt. Bulk—non-periodic, large data transfer.
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