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Inductive Adder Modulators for ILC DR Kickers

Craig Burkhart SLAC

For SLAC-LLNL Team

Ed Cook, C. Brooksby LLNLR. Cassel, T. Beukers, C. Burkhart,

M. Nguyen, R. Larsen SLAC

September 26, 2006

9/26/2006 Cornell ILC DR Workshop SLAC/LLNL 2

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Inductive Adder Modulators for ILC DR Kickers

• SLAC/LLNL Program

• Inductive Adder Topology

• Inductive Adder Modulators

• Areas of Advanced Development for ILC DR Applications

9/26/2006 Cornell ILC DR Workshop SLAC/LLNL 3

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System Topology

10-20 pulsers will be needed in a High

Availability topology with auto-failover and access

for replacement

C. Brooksby BN/LLNL

Shield Wall

Control/Timing/

CalibrationSerialLinks

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DR Kicker Modulator Requirements

Intra-pulse Stability: 7x10-4

Bunch spacing: 20 ns

Burst Repetition Rate: ~3MHz

Burst Duration: ~ 3000 Pulses

Average Repetition Rate: 15,000 PPS (5 bursts per second)

Pulse Length: ~5 nsOutput Voltage: ± 10 kV (two simultaneous pulses

of opposite polarity required)Load Impedance: 50 Ω

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SLAC/LLNL High Availability (HA) Damping Ring Kicker System Development Program

• Goal: Demonstrate Full System Architecture for HA Damping Ring Kicker System – Develop prototype– Multiple unit operation– System timing– Calibration– Diagnostics– Auto-failover– Demonstrate reliability– Evaluate System Trade-offs

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SLAC/LLNL High Availability (HA) Damping Ring Kicker System Development Program

• Motivation– System Development: Many groups working on kickers

to optimize pulse shape, but overall system needs prototype demonstration.

– High Availability: Reliability/Availability critical for system of ~ 10-20 or more pulsers in series.

– Inductive Adder: Induction modulator has ideal balanced output architecture (+/- 10kV output) but needs optimization for rise & fall time, impedance matching, stability of calibration, HA service features.

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Basic Design• Modular Inductive Adder Topology

– Extra modules and auto-failover if one or two modules fail

– Each module has multiple MOSFETs in parallel– Balanced output for identical pulses to each side

of kicker e.g. 200A into 50 Ohms– Multiple units to make full kicker system– Small units easily substituted when one fails– Redundancy in form of extra kickers for >99%

Availability– Sophisticated card-level diagnostics for HA

management

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FY ’07 Goals

• Complete development and testing of short pulse (~5 ns) module

• Initiate development of prototype modulator: 5 ns, ±10 kV, 50 Ω , 3 MHz

• Start design of calibration system

• Initiate design of timing system

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SLAC/LLNL FY ’07 Budget (pro-forma)

• LLNL– $225k M&S (transfer from SLAC)– Fractional support: E. Cook, designer, & tech– Prototype development

• SLAC– 0.3 FTE– Prototype support systems development:

controls, timing, & calibration

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Inductive Adder Circuit Topology

Inductive Adder Concept - Simplified Schematic

0 v

-V chg

V chg

Vout

Transformer Secondary

+ -

0 v

-V chg

0 v

-V chg

+ -

( ~ 4* V chg

)Vpk

0

Vpk

Vout

Transformers

Transformer Core

Transformer Primary0 v

-V chg

RLNote:Conceptually, for fast pulses, the mechanical structure of an inductive adder is virtually identical to that of an induction accelerator

E. Cook LLNL

Trigger circuit

Capacitor bank

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Inductive Adder Topology: Advantages– Modular: Adder comprised of a stack of identical modules

• Topology arrays discrete switching devices: parallel/series

• All modules triggered independently

• Scaleable to higher voltages by adding modules

• Redundant: can run n/N

– Single-turn transformer has high bandwidth

– All drive components ground referenced

– No dc high voltage

– Pulse format defined by external trigger generator• Pulse width and PRF agility

• High burst frequency: >1 MHz

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LLNL Inductive Adder Systems

• Dual-Axis Radiographic Hydrodynamics Test Facility (LANL)– ±18kV 10% into 50 Ω– 10ns rise and fall times– 16–200ns adjustable pulse width

• Plasma Electrode Pockel Cell (LLE/LLNL)– 0-20kV into capacitive load (Z ~ 12.5 Ω)– 0-200ns flattop to ±1%

• Accelerator Test Facility (KEK)– ±8.5kV into 50 Ω– ~10 ns flattop, ~20 ns FWHM

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±18kV Pulsers for DARHT Dipole Kicker

E. Cook LLNL

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DARHT Modulator Output Characteristics

4-Pulse Agile Burst: Amplitude Modulation

Output:120 ns, 20 kV,50 Ω

Output:30 ns, 18 kV,50 Ω

4-Pulse Agile Burst:Pulse WidthFrequency

E. Cook LLNL

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NIF PEPC ModulatorCompleted assembly w/ temporary control panel

Controls, power supplies, and trigger interface

E. Cook LLNL

9/26/2006 Cornell ILC DR Workshop SLAC/LLNL 16

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NIF PEPC Modulator: Stalk Impedance

Initial Stalk Design: Corrected Stalk Design:Top: Vload @ 5kV/div (resistive load) Btm: Vload @ 5kV/divBtm: Vdrain @ 200V/div

Initially did not meet risetime requirement into load. This was due to stalk impedance being too high resulting in multiple reflections within modulator which slow down output risetime. MOSFET switching transitions are fast enough to meet requirements.

E. Cook LLNL

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KEK ATF Adder Conceptual LayoutMOSFET drive bd. with surface-mount capacitors

Cross-Sectionof adder cells

Diode clamp bd. (MOSFET over-voltage protection)

Center Stalk - will beconnected to kicker structure with cables(configuration shown for pos. & neg. polarity pulses)

E. Cook LLNL

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Prototype Components - MOSFET Drive Board

Master Trigger Circuit

Trigger Distribution Traces

Capacitor Array - Surface Mount Ceramics

MOSFET Drivers

MOSFETs

Charge Circuit

E. Cook LLNL

9/26/2006 Cornell ILC DR Workshop SLAC/LLNL 19

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Partial Assembly of Prototype

E. Cook LLNL

9/26/2006 Cornell ILC DR Workshop SLAC/LLNL 20

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Finished Prototype

Output connectors

Trigger Cables

Houses trigger distribution, power supplies, etc

E. Cook LLNL

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KEK ATF Modulator Output Characteristics

Negative Output, -9.6 kV Flattop

Simultaneous bi-polar outputs: 50 Ω load on each end

E. Cook LLNL

Positive Output, +9.6 kV Flattop

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Areas of Advanced Development for the DR Application

• Decrease output pulse length– Improve MOSFET switching– Decrease propagation delays

• Improve pulse-to-pulse stability– Reset adder core / stabilize hysteresis– Recharge energy storage caps

• Address transmission line effects– Degradation of rise/fall time

• Cooling– Ppeak ~ 8 MW, <Pburst > ~ 100 kW, <P> ~ 0.5 kW

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Output Pulse Length Reduction

• Propagation delay through IC drivers typically 10 ns (or greater)– Discrete component driver– Advanced topology, e.g. Cascode

• Overcome package inductance: LG ~ LS ~ 5 nH, dI/dt ~ 1010 A/s– Higher voltage driver– Hybrid packaging

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Discrete Driver

E. Cook LLNL

Si4532ADY

G2

G1

S2

D2

D1

S1 12

3

4

7,8

5,6

Vcc

VS-

EL7158

1

2

3

45

6

8VH

Out

VS-

VS+

OE

IN

Gnd

VL

VS+

VS+

T2

Vgate

VS-

EL7158

1

2

3

45

6

7

8VH

Out

VS-

VS+

OE

IN

Gnd

7

VS-

10ž

VH

VH

T1

RL

1µF

VL

VL

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Test Results: 50 Pulse Burst @ 3 MHz, 10 Ω Load, 500 V Charge

2 pulses from burst

1st pulse of burst

40th pulse of burst

10th pulse of burst

E. Cook LLNL

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Cascode Driver

E. Cook LLNL

Si4532ADY

G2

G1

S2

D2

D1

S1 12

3

4

7,8

5,6

Vcc

VS-

EL7158

1

2

3

4

5

6

8VH

Out

VS-

VS+

OE

IN

Gnd

VL

VS+

VS+

T2

Vgate

EL7158

1

2

3

45

6

7

8VH

Out

VS-

VS+

OE

IN

Gnd

7

10ž

VH

VH

T1

RL

1µF

VL

Vgate

Vclamp

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Pulse-to-Pulse Stability

• LLNL adders typically reset/recharge between bursts– 3000 pulses, ~3 ns → 9 μs– ~1 kV → ~10-2 V•s (Alt: use remnant flux)– ~400 A → ~4 mC

• First Point Scientific adders reset/recharge between pulses– Minimum voltage on load α 1/D.F.

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Transmission Line Effects

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Summary

• SLAC/LLNL program is designed to demonstrate Full System Architecture for a High Availability Damping Ring Kicker System

• Inductive adder modulator topology – Inherently redundant– Mature technology– Demonstrated over wide range of parameters

• Focus of SLAC/LLNL program is advanced development areas required to meet ILC parameters– Short-pulse prototype– Timing, calibration, and controls– System testing