am29f010b - chip eprom
TRANSCRIPT
-
8/10/2019 AM29F010B - Chip EPROM
1/33
PRELIMINARY
Publication# 22336 Rev: B Amendment/0Issue Date: November 12, 1999
Am29F010B1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation
5.0 V 10% for read, erase, and program operations
Simplifies system-level power requirements
Manufactured on 0.32 m process technology
Compatible with Am29F010 and Am29F010Adevice
High performance
45 ns maximum access time
Low power consumption 12 mA typical active read current
30 mA typical program/erase current
-
8/10/2019 AM29F010B - Chip EPROM
2/332 Am29F010B
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash
memory organized as 131,072 bytes. The Am29F010Bis offered in 32-pin PDIP, PLCC and TSOP packages.
The byte-wide data appears on DQ0-DQ7. The de-vice is designed to be programmed in-system with the
standard system 5.0 Volt VCCsupply. A 12.0 volt VPPis notrequired for program or erase operations. The device can
also be programmed or erased in standard EPROMprogrammers.
This device is manufactured using AMDs 0.32 m pro-cess technology, and offers all the features and benefits
of the Am29F010 and Am29F010A.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessorsto operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), writeenable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internallygenerated and regulated voltages are provided for theprogram and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register usingstandard microprocessor write timings. Register con-
tents serve as input to an internal state machine thatcontrols the erase and programming circuitry. Write
cycles also internally latch addresses and data neededfor the programming and erase operations. Reading
data out of the device is similar to reading from otherFlash or EPROM devices.
Device programming occurs by executing the programcommand sequence. This invokes the Embedded
Programalgorithman internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This invokes the Embedded Erasealgorithman internal algorithm that automatically pre-
programs the array (if it is not already programmed)before executing the erase operation. During erase,
the device automatically times the erase pulse widthsand verifies proper cell margin.
The host system can detect whether a program orerase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a programor erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architectureallows memory sectors
to be erased and reprogrammed without affecting thedata contents of other sectors. The device is erased
when shipped from the factory.
The hardware data protectionmeasures include alow VCCdetector automatically inhibits write operations
during power transitions. The hardware sector protec-tion feature disables both program and erase
operations in any combination of the sectors of memory,and is implemented us ing s tandard EPROM
programmers.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMDs Flash technology combines years of Flash
memory manufacturing experience to produce thehighest levels of qual i ty, rel iabi l i ty, and cost
effectiveness. The device electrically erases all bitswithin a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at atime using the EPROM programming mechanism of
hot electron injection.
-
8/10/2019 AM29F010B - Chip EPROM
3/33Am29F010B 3
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Note:See the AC Characteristics section for full specifications.
BLOCK DIAGRAM
Family Part Number Am29F010B
Speed OptionVCC = 5.0 V 5% -45
VCC = 5.0 V 10% -55 -70 -90 -120
Max Access Time (ns) 45 55 70 90 120
CE# Access (ns) 45 55 70 90 120
OE# Access (ns) 25 30 30 35 50
Input/OutputBuffers
X-Decoder
Y-Decoder
Chip EnableOutput Enable
Logic
Erase VoltageGenerator
PGM VoltageGenerator
TimerVCCDetector
StateControl
CommandRegister
VCC
VSS
WE#
CE#
OE#
STB
STB
DQ0DQ7
DataLatch
Y-Gating
Cell Matrix
22336B-1
AddressLatch
A0A16
-
8/10/2019 AM29F010B - Chip EPROM
4/334 Am29F010B
P R E L I M I N A R Y
CONNECTION DIAGRAMS
3
4
5
2
1
9
10
11
12
13
27
26
25
24
23
7
8
22
21
6
32
31
20
14
30
29
28
15
16
19
18
17
A6
A5
A4
A3
A2
A1
A0
A16
DQ0
A15
A12
A7
DQ1
DQ2
VSS
A8
A9
A11
OE#
A10
CE#
DQ7
VCC
WE#
DQ6
NC
A14
A13
DQ5
DQ4
DQ3
NC
PDIP
22336B-2
D
Q6
NC
D
Q5
D
Q4
D
Q3
1 31 30234
5
6
7
8
9
10
11
12
13
17 18 19 20161514
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A12
A15
A16
VCC
WE#
NC
D
Q1
D
Q2
VSS
PLCC
22336B-3
-
8/10/2019 AM29F010B - Chip EPROM
5/33Am29F010B 5
P R E L I M I N A R Y
CONNECTION DIAGRAMS
1234567
8910111213141516
Standard TSOP
22336B-4
A11A9A8
A13A14NC
WE#
VCCNC
A16A15A12
A7A6A5A4
32313029282726
252423222120191817
OE#A10CE#DQ7DQ6DQ5DQ4
DQ3VSSDQ2DQ1DQ0A0A1A2A3
22336B-5
12
345678910111213141516
A11A9
A8A13A14NCWE#VCCNCA16A15A12A7A6A5A4
3231
3029282726252423222120191817
OE#A10
CE#DQ7DQ6DQ5DQ4DQ3VSS
DQ2DQ1DQ0
A0A1A2A3
Reverse TSOP
-
8/10/2019 AM29F010B - Chip EPROM
6/336 Am29F010B
P R E L I M I N A R Y
PIN CONFIGURATION
A0A16 = 17 Addresses
DQ0DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
VCC = +5.0 Volt Single Power Supply(See Product Selector Guide for speed
options and voltage supply tolerances)
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
17
8
DQ0DQ7
A0A16
CE#
OE#
WE#
22336B-6
-
8/10/2019 AM29F010B - Chip EPROM
7/33Am29F010B 7
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29F010B 70 E C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0C to +70C)
I = Industrial (40C to +85C)
E = Extended (55C to +125C)
PACKAGE TYPE
P = 32-Pin Plastic PDIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F010B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
Valid Combinations
Am29F010B-45
VCC= 5.0 V 5%
PC, PI, PE,JC, JI, JE,
EC, EI, EE,
FC, FI, FE
Am29F010B-55VCC= 5.0 V 10%
Am29F010B-70
Am29F010B-90
Am29F010B-120
-
8/10/2019 AM29F010B - Chip EPROM
8/338 Am29F010B
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through theinternal command register. The command register itself
does not occupy any addressable memory location.The register is composed of latches that store the com-
mands, along with the address and data informationneeded to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of thedevice. The appropriate device bus operations table
lists the inputs and control levels required, and the re-sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F010B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID= 12.0 0.5 V, X = Dont Care, AIN= Addresses In, DIN= Data In, DOUT= Data Out
Notes:
1. Addresses are A16:A0.
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the Sector Pro-
tection/Unprotectionsection.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the powercontrol and selects the device. OE# is the output con-trol and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. Thisensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command isnecessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresseson the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents arealtered.
See Reading Array Datafor more information. Refer
to the AC Read Operations table for timing specifica-tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristicstable represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasingsectors of memory), the system must drive WE# andCE# to VIL, and OE# to VIH.
An erase operation can erase one sector, multiple sec-tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.A sector addressconsists of the address bits required
to uniquely select a sector. See the Command Defini-tionssection for details on erasing a sector or the
entire chip.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. Thesystem can then read autoselect codes from the inter-
nal register (which is separate from the memory array)on DQ7DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Modeand AutoselectCommand Sequencesections for more information.
ICC2in the DC Characteristics table represents the ac-tive current specification for the write mode. The AC
Characteristicssection contains timing specificationtables and timing diagrams for write operations.
Operation CE# OE# WE#
Addresses
(Note 1) DQ0DQ7
Read L L H AIN DOUT
Write L H L AIN DIN
Standby VCC 0.5 V X X X High-Z
Output Disable L H H X High-Z
Hardware Reset X X X X High-Z
-
8/10/2019 AM29F010B - Chip EPROM
9/33Am29F010B 9
P R E L I M I N A R Y
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the statusbits on DQ7DQ0. Standard read cycle timings and ICCread specifications apply. Refer to Write OperationStatusfor more information, and to each AC Charac-
teristics section in the appropriate data sheet for timingdiagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In thismode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# pin is held at VCC 0.5 V. (Note that this is a morerestricted voltage range than VIH.) The device enters
the TTL standby mode when CE# is held at V IH. Thedevice requires the standard access time (tCE) before
it is ready to read data.
If the device is deselected during erasure or program-ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics tables represents the
standby current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device isdisabled. The output pins are placed in the high imped-
ance state.
Table 2. Am29F010B Sector Addresses Table
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,through identifier codes output on DQ7DQ0. This
mode is primarily intended for programming equipmentto automatically match a device to be programmed with
its corresponding programming algorithm. However,the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins A6,
A1, and A0 must be as shown in Autoselect Codes(High Voltage Method) table. In addition, when verify-ing sector protection, the sector address must appear
on the appropriate highest order address bits. Refer to
the corresponding Sector Address Tables. The Com-mand Definitions table shows the remaining address
bits that are dont care. When all necessary bits havebeen set as required, the programming equipment may
then read the corresponding identifier code on DQ7DQ0.
To access the autoselect codes in-system, the hostsystem can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require VID. SeeCommand Definitionsfor details on using the autose-lect mode.
Sector A16 A15 A14 Address Range
SA0 0 0 0 00000h-03FFFh
SA1 0 0 1 04000h-07FFFh
SA2 0 1 0 08000h-0BFFFh
SA3 0 1 1 0C000h-0FFFFh
SA4 1 0 0 10000h-13FFFh
SA5 1 0 1 14000h-17FFFh
SA6 1 1 0 18000h-1BFFFh
SA7 1 1 1 1C000h-1FFFFh
-
8/10/2019 AM29F010B - Chip EPROM
10/3310 Am29F010B
P R E L I M I N A R Y
Table 3. Am29F010B Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Dont care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-ware sector unprotection feature re-enables both
program and erase operations in previously protectedsectors.
Sector protection/unprotection must be implementedusing programming equipment. The procedure re-
quires a high voltage (VID) on address pin A9 and thecontrol pins. Details on this method are provided in a
supplement, publication number 22337. Contact anAMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protectingsectors at its factory prior to shipping the device
through AMDs ExpressFlashService. Contact anAMD representative for details.
It is possible to determine whether a sector is protectedor unprotected. See Autoselect Modefor details.
Hardware Data Protection
The command sequence requirement of unlock cyclesfor programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
spurious system level signals during VCC power-upand power-down transitions, or from system noise.
Low VCCWrite Inhibit
When VCCis less than VLKO, the device does not ac-cept any write cycles. This protects data during VCCpower-up and power-down. The command register and
all internal program/erase circuits are disabled, and thedevice resets. Subsequent writes are ignored until VCCis greater than VLKO. The system must provide theproper signals to the control pins to prevent uninten-
tional writes when VCCis greater than VLKO.
Write Pulse GlitchProtection
Noise pulses of less than 5 ns (typical) on OE#, CE# orWE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIHor WE# = VIH. To initiate a write cycle,CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VILand OE# = VIHduring power up, thedevice does not accept commands on the rising edge
of WE#. The internal state machine is automaticallyreset to reading array data on power-up.
Description CE# OE# WE#
A16
to
A14
A13
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID X L X L L 01h
Device ID: Am29F010B L L H X X VID X L X L H 20h
Sector Protection Verification L L H SA X VID X L X H L
01h
(protected)
00h
(unprotected)
-
8/10/2019 AM29F010B - Chip EPROM
11/33Am29F010B 11
P R E L I M I N A R Y
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates deviceoperations. The Command Definitions table defines the
valid register command sequences. Writing incorrectaddress and data valuesor writing them in the im-
proper sequenceresets the device to reading array
data.
All addresses are latched on the fall ing edge of WE# orCE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happensfirst. Refer to the appropriate timing diagrams in the
AC Characteristicssection.
Reading Array Data
The device is automatically set to reading array dataafter device power-up. No commands are required to
retrieve data. The device is also ready to read arraydata after completing an Embedded Program or Em-
bedded Erase algorithm.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,or while in the autoselect mode. See the Reset Com-
mandsection, next.
See also Requirements for Reading Array Datain the
Device Bus Operationssection for more information.
The Read Operations table provides the read parame-ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-vice to reading array data. Address bits are don t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence beforeerasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence
before programming begins. This resets the device toreading array data. Once programming begins, how-
ever, the device ignores reset commands until theoperation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command mustbe written to return to reading array data.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-ing array data.
Autoselect Command Sequence
The autoselect command sequence allows the hostsystem to access the manufacturer and devices codes,
and determine whether or not a sector is protected.The Command Definitions table shows the address
and data requirements. This method is an alternative tothat shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-mers and requires VIDon address bit A9.
The autoselect command sequence is initiated by writ-ing two unlock cycles, followed by the autoselect
command. The device then enters the autoselectmode, and the system may read at any address any
number of times, without initiating another commandsequence.
A read cycle at address XX00h or retrieves the manu-facturer code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector ad-
dress (SA) and the address 02h in returns 01h if thatsector is protected, or 00h if it is unprotected. Refer tothe Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-upcommand. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is notrequired to provide furthercontrols or timings. The device automatically providesinternally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions takeshows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-dresses are no longer latched. The system can
determine the status of the program operation by usingDQ7or DQ6. See Write Operation Statusfor informa-
tion on these status bits.
Any commands written to the device during the Em-bedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a 0back to a 1. Attempting to do so may halt
the operation and set DQ5 to 1, or cause the Data#Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that thedata is still 0. Only erase operations can convert a 0
to a 1.
-
8/10/2019 AM29F010B - Chip EPROM
12/3312 Am29F010B
P R E L I M I N A R Y
Note:See the appropriate Command Definitions table for
program command sequence.
Figure 1. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlockcycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erasecommand, which in turn invokes the Embedded Erase
algorithm. The device does notrequire the system topreprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entirememory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-trols or timings during these operations. The Command
Definitions table shows the address and data require-ments for the chip erase command sequence.
Any commands written to the chip during the Embed-ded Erase algorithm are ignored.
The system can determine the status of the erase op-
eration by using DQ7 or DQ6. See Write Operation
Statusfor information on these status bits. When theEmbedded Erase algorithm is complete, the device re-
turns to reading array data and addresses are no
longer latched.
Figure 2illustrates the algorithm for the erase opera-tion. See the Erase/Program Operations tables in AC
Characteristicsfor parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sectorerase command sequence is initiated by writing twounlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by theaddress of the sector to be erased, and the sector
erase command. The Command Definitions tableshows the address and data requirements for the sec-
tor erase command sequence.
The device does notrequire the system to preprogram
the memory prior to erase. The Embedded Erase algo-rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 s begins. During the time-out period,additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffermay be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The timebetween these additional cycles must be less than 50
s, otherwise the last address and command might notbe accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The in-terrupts can be re-enabled after the last Sector Erasecommand is written. If the time between additional sec-
tor erase commands can be assumed to be less than
50 s, the system need not monitor DQ3. Any com-
mand during the time-out period resets the device
to reading array data.The system must rewrite thecommand sequence and any additional sector ad-
dresses and commands.
The system can monitor DQ3 to determine if the sectorerase timer has timed out. (See the DQ3: Sector
Erase Timersection.) The time-out begins from the ris-
ing edge of the final WE# pulse in the commandsequence.
Once the sector erase operation has begun, all other
commands are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses areno longer latched. The system can determine the sta-
tus of the erase operation by using DQ7 or DQ6. Referto Write Operation Status for information on these
status bits.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?No
Yes
Last Address?No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
22336B-7
-
8/10/2019 AM29F010B - Chip EPROM
13/33Am29F010B 13
P R E L I M I N A R Y
Figure 2illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables inthe AC Characteristicssection for parameters, and to
the Sector Erase Operations Timing diagram for timingwaveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read datafrom, or program data to, any sector not selected for
erasure. This command is valid only during the sectorerase operation, including the 50 s time-out period
during the sector erase command sequence. TheErase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates thetime-out period and suspends the erase operation. Ad-
dresses are dont-careswhen writing the EraseSuspend command.
When the Erase Suspend command is written during asector erase operation, the device requires a maximum
of 20 s to suspend the erase operation. However,when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, thesystem can read array data from any sector not se-
lected for erasure. (The device erase suspendsall
sectors selected for erasure.) Normal read and writetimings and command definitions apply. Reading at any
address within erase-suspended sectors produces sta-tus data on DQ7DQ0. The system can use DQ7 to
determine if a sector is actively erasing or is erase-sus-pended. See Write Operation Status for information
on these status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data withinnon-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6status bits, just as in the standard program operation.
See Write Operation Statusfor more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspendmode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When thedevice exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for anothervalid operation. See Autoselect Command Sequence
for more information.
The system must write the Erase Resume command
(address bits are dont care) to exit the erase suspend
mode and continue the sector erase operation. Furtherwrites of the Resume command are ignored. AnotherErase Suspend command can be written after the de-
vice has resumed erasing.
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See DQ3: Sector Erase Timerfor more information.
Figure 2. Erase Operation
START
Write EraseCommand Sequence
Data Poll
from System
Data = FFh?No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
22336B-8
-
8/10/2019 AM29F010B - Chip EPROM
14/3314 Am29F010B
P R E L I M I N A R Y
Table 4. Am29F010B Command Definitions
Legend:
X = Dont care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A16A14 uniquely select any sector.
Notes:
1. See Table 1for description of bus operations.2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all command
bus cycles are write operations.
4. No unlock or command cycles required when reading array
data.
5. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
6. The device accepts the three-cycle reset command
sequence for backward compatibility.
7. The fourth cycle of the autoselect command sequence is aread operation.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See Autoselect Command Sequencefor
more information.
9. The system may read in non-erasing sectors, or enter the
autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation.
10. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2-3)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 4) 1 RA RD
Reset (Note 5) 1 XXXX F0
Reset (Note 6) 3 555 AA 2AA 55 555 F0
Autoselect
(Note 7)
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID 4 555 AA 2AA 55 555 90 X01 20
Sector Protect Verify
(Note 8)4 555 AA 2AA 55 555 90
(SA)
X02
00
01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30
Cycles
-
8/10/2019 AM29F010B - Chip EPROM
15/33Am29F010B 15
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ3, DQ5, DQ6, and DQ7.Table 5and the following subsections describe the
functions of these bits. DQ7 and DQ6 each offer amethod for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress orcompleted. Data# Polling is valid after the rising edge
of the final WE# pulse in the program or erase com-mand sequence.
During the Embedded Program algorithm, the deviceoutputs on DQ7 the complement of the datum pro-
grammed to DQ7. When the Embedded Programalgorithm is complete, the device outputs the datum
programmed to DQ7. The system must provide the
program address to read valid status information onDQ7. If a program address falls within a protected sec-tor, Data# Polling on DQ7 is active for approximately 2
s, then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling
produces a 0on DQ7. When the Embedded Erase al-gorithm is complete, Data# Polling produces a 1on
DQ7. This is analogous to the complement/true datumoutput described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to 1;prior to this, the device outputs the complement,or
0.The system must provide an address within any of
the sectors selected for erasure to read valid status in-formation on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Pollingon DQ7 is active for approximately 100 s, then the de-
vice returns to reading array data. If not all selectedsectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-lected sectors that are protected.
When the system detects DQ7 has changed from thecomplement to true data, it can read valid data at DQ7
DQ0 on the followingread cycles. This is because DQ7
may change asynchronously with DQ0DQ6 whileOutput Enable (OE#) is asserted low. The Data# Poll-ing Timings (During Embedded Algorithms) figure in
the AC Characteristicssection illustrates this.
Table 5shows the outputs for Data# Polling on DQ7.
Figure 3shows the Data# Polling algorithm.
DQ7 = Data?Yes
No
No
DQ5 = 1?No
Yes
Yes
FAIL PASS
Read DQ7DQ0
Addr = VA
Read DQ7DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1becauseDQ7 may change simultaneously with DQ5.
22336B-9
Figure 3. Data# Polling Algorithm
-
8/10/2019 AM29F010B - Chip EPROM
16/3316 Am29F010B
P R E L I M I N A R Y
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete.Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE# pulse in the com-mand sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address causeDQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation iscomplete, DQ6 stops toggling.
After an erase command sequence is written, if all sec-tors selected for erasing are protected, DQ6 toggles for
approximately 100 s, then returns to reading arraydata. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotectedsectors, and ignores the selected sectors that are
protected.
If a program address falls within a protected sector,DQ6 toggles for approximately 2 s after the programcommand sequence is written, then returns to reading
array data.
The Write Operation Status table shows the outputs forToggle Bit I on DQ6. Refer to Figure 4for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
AC Characteristicssection for the timing diagram.
Reading Toggle Bit DQ6
Refer to Figure 4 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7DQ0 at least twice in a row todetermine whether a toggle bit is toggling. Typically, asystem would note and store the value of the toggle bit
after the first read. After the second read, the systemwould compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system canread array data on DQ7DQ0 on the following read
cycle.
However, if after the initial two read cycles, the systemdetermines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system shouldthen determine again whether the toggle bit is toggling,since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program orerase operation. If it is still toggling, the device did not
complete the operation successfully, and the systemmust write the reset command to return to reading
array data.
The remaining scenario is that the system initially de-termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor thetoggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previousparagraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-termine the status of the operation (top of Figure 4).
START
No
Yes
Yes
DQ5 = 1?No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7DQ0
Toggle Bit
= Toggle?
Read DQ7DQ0
Twice
Read DQ7DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to 1. See text.
22336B-10
Figure 4. Toggle Bit Algorithm
(Notes1, 2)
(Note 1)
-
8/10/2019 AM29F010B - Chip EPROM
17/33Am29F010B 17
P R E L I M I N A R Y
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Underthese conditions DQ5 produces a 1.This is a failure
condition that indicates the program or erase cycle wasnot successfully completed.
The DQ5 failure condition may appear if the systemtries to program a 1to a location that is previously
programmed to 0.Only an erase operation canchange a 0back to a 1.Under this condition, the
device halts the operation, and when the operation hasexceeded the timing limits, DQ5 produces a 1.
Under both these conditions, the system must issuethe reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timerdoes not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-mand. When the time-out is complete, DQ3 switches
from 0to 1.The system may ignore DQ3 if the sys-tem can guarantee that the time between additional
sector erase commands will always be less than 50 s.See also the Sector Erase Command Sequence
section.
After the sector erase command sequence is written,the system should read the status on DQ7 (Data# Poll-ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.If DQ3 is 1, the internally controlled erase cycle has
begun; all further commands are ignored until theerase operation is complete. If DQ3 is 0, the device
will accept additional sector erase commands. To en-sure the command has been accepted, the system
software should check the status of DQ3 prior to andfollowing each subsequent sector erase command. If
DQ3 is high on the second status check, the last com-mand might not have been accepted. Table 5shows
the outputs for DQ3.
Table 5. Write Operation Status
Notes:
1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to 1when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See DQ5: Exceeded Timing Limitsfor more information.
Operation
DQ7
(Note 1) DQ6
DQ5
(Note 2) DQ3
StandardMode
Embedded Program Algorithm DQ7# Toggle 0 N/A
Embedded Erase Algorithm 0 Toggle 0 1
Erase
Suspend
Mode
Reading within Erase Suspended Sector 1 No toggle 0 N/A
Reading within Non-Erase Suspended Sector Data Data Data Data
-
8/10/2019 AM29F010B - Chip EPROM
18/3318 Am29F010B
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . .65C to +125C
Ambient Temperaturewith Power Applied . . . . . . . . . . . . .55C to +125C
Voltage with Respect to GroundVCC(Note 1). . . . . . . . . . . . . . . . . . . . 2.0 V to +7.0 V
A9 (Note 2). . . . . . . . . . . . . . . . . . . .2.0 V to +13.0 VAll other pins (Note 1) . . . . . . . . . . . .2.0 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pin is 0.5 V. During
voltage transitions, inputs may overshoot VSSto 2.0 V
for periods of up to 20 ns. See Figure 5. Maximum DC
voltage on input and I/O pins is VCC+ 0.5 V. During volt-
age transitions, input and I/O pins may overshoot to VCC+ 2.0 V for periods up to 20 ns. See Figure 6.
2. Minimum DC input voltage on A9 pin is 0.5V. During
voltage transitions, A9 pins may overshoot VSSto 2.0 V
for periods of up to 20 ns. See Figure 5. Maximum DC in-
put voltage on A9 is +12.5 V which may overshoot to 14.0
V for periods up to 20 ns.
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
Stresses above those listed under Absolute Maximum
Ratingsmay cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the op-
erational sections of this specification is not implied. Expo-
sure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Case Temperature (TA) . . . . . . . . . . . . . .0C to +70C
Industrial (I) Devices
Case Temperature (TA) . . . . . . . . . . . .40C to +85C
Extended (E) Devices
Case Temperature (TA) . . . . . . . . . . .55C to +125CVCC Supply Voltages
VCCfor 5% devices. . . . . . . . . . . +4.75 V to +5.25 V
VCCfor 10% devices. . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Figure 5. Maximum Negative OvershootWaveform
Figure 6. Maximum Positive OvershootWaveform
20 ns
20 ns
+0.8 V
0.5 V
20 ns
2.0 V
22336B-11
20 ns
20 ns
VCC+2.0 V
VCC+0.5 V
20 ns
2.0 V
22336B-12
-
8/10/2019 AM29F010B - Chip EPROM
19/33Am29F010B 19
P R E L I M I N A R Y
DC CHARACTERISTICS
TTL/NMOS Compatible
Notes:
1. The I CCcurrent listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICCspecifications are tested with VCC=VCCmax.
3. ICCactive while Embedded Program or Embedded Erase Algorithm is in progress.
4. Not 100% tested.
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
ILI Input Load Current VIN= VSS to VCC, VCC = VCC Max 1.0 A
ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 A
ILO Output Leakage Current VOUT= VSS to VCC, VCC = VCC Max 1.0 A
ICC1VCC Active Read Current
(Notes 1,2)CE# = VIL, OE# = VIH 12 30 mA
ICC2VCC Active Write Current
(Notes 2,3, 4)CE# =VIL, OE# =VIH 30 40 mA
ICC3 VCC Standby Current CE# and OE# = VIH 0.4 1.0 mA
VIL Input Low Voltage 0.5 0.8 V
VIH Input High Voltage 2.0 VCC + 0.5 V
VIDVoltage for Autoselect and Sector
ProtectVCC = 5.0 V 10.5 12.5 V
VOL Output Low Voltage IOL= 12 mA, VCC = VCC Min 0.45 V
VOH Output High Voltage IOH=2.5 mA, VCC = VCC Min 2.4 V
VLKO Low VCCLock-out Voltage 3.2 4.2 V
-
8/10/2019 AM29F010B - Chip EPROM
20/3320 Am29F010B
P R E L I M I N A R Y
DC CHARACTERISTICS (Continued)
CMOS Compatible
Notes:
1. The I CCcurrent listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICCspecifications are tested with VCC=VCCmax.
3. ICCactive while Embedded Program or Embedded Erase Algorithm is in progress.
4. Not 100% tested.
5. ICC3 = 20 A max at extended temperatures (> +85C).
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
ILI Input Load Current VIN= VSS to VCC, VCC = VCC Max 1.0 A
ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 A
ILO Output Leakage Current VOUT= VSS to VCC, VCC = VCC Max 1.0 A
ICC1 VCC Active Current (Notes 1,2) CE# = VIL, OE# = VIH 12 30 mA
ICC2VCC Active Current
(Notes 2, 3,4)CE# = VIL, OE# = VIH 30 40 mA
ICC3 VCC Standby Current (Note 5) CE# =VCC 0.5 V,OE# = VIH 1 5 A
VIL Input Low Voltage 0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VIDVoltage for Autoselect and
Sector ProtectVCC = 5.25 V 10.5 12.5 V
VOL Output Low Voltage IOL= 12 mA, VCC = VCC Min 0.45 V
VOH1Output High Voltage
IOH=2.5 mA, VCC = VCC Min 0.85 VCC V
VOH2 IOH=100 A, VCC = VCC Min VCC0.4 V
VLKO Low VCC Lock-out Voltage 3.2 4.2 V
-
8/10/2019 AM29F010B - Chip EPROM
21/33Am29F010B 21
P R E L I M I N A R Y
TEST CONDITIONS
Table 6. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 k
CL 6.2 k
5.0 V
DeviceUnderTest
22336B-13
Figure 7. Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition -45 All others Unit
Output Load 1 TTL gate
Output Load Capacitance, CL(including jig capacitance)
30 100 pF
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.03.0 0.452.4 V
Input timing measurement
reference levels1.5 0.8 V
Output timing measurement
reference levels1.5 2.0 V
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Dont Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
-
8/10/2019 AM29F010B - Chip EPROM
22/3322 Am29F010B
P R E L I M I N A R Y
AC CHARACTERISTICS
Read-only Operations Characteristics
Notes:
1. Not 100% tested.
2. See Figure 7 and Table 6for test specifications.
Parameter
Symbol
Parameter Description Test Setup
Speed Options
UnitJEDEC Std -45 -55 -70 -90 -120
tAVAV tRC Read Cycle Time (Note 1) Min 45 55 70 90 120 ns
tAVQV tACC Address to Output DelayCE# = VILOE# = VIL
Max 45 55 70 90 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 45 55 70 90 120 ns
tGLQV tOE Output Enable to Output Delay Max 25 30 30 35 50 ns
tEHQZ tDFChip Enable to Output High Z
(Note 1)Max 10 15 20 20 30 ns
tGHQZ tDFOutput Enable to Output High Z
(Note 1)Max 10 15 20 20 30 ns
tOEHOutput Enable Hold Time
(Note 1)
Read Min 0 ns
Toggle and Data
Polling Min 10 ns
tAXQX tOH
Output Hold Time From
Addresses CE# orOE#,
Whichever Occurs First
Min 0 ns
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH ZOutput Valid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOEtDF
tOH
22336B-14
Figure 8. Read Operations Timings
-
8/10/2019 AM29F010B - Chip EPROM
23/33Am29F010B 23
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performancesection for more informaiton.
Parameter Symbol
Parameter Description
Speed Options
UnitJEDEC Std -45 -55 -70 -90 -120
tAVAV tWC Write Cycle Time (Note 1) Min 45 55 70 90 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 35 45 45 45 50 ns
tDVWH tDS Data Setup Time Min 20 20 30 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHWL tGHWLRead Recover Time Before Write
(OE# High to WE# Low)Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH
tWP
Write Pulse Width Min 25 30 35 45 50 ns
tWHWL tWPH Write Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 s
tWHWH2 tWHWH2 Chip/Sector Erase Operation (Note 2) Typ 1.0 sec
tVCS VCCSet Up Time (Note 1) Min 50 s
-
8/10/2019 AM29F010B - Chip EPROM
24/3324 Am29F010B
P R E L I M I N A R Y
AC CHARACTERISTICS
22336B-15
Note: PA = program address, PD = program data, DOUTis the true data at the program address.
Figure 9. Program Operation Timings
22336B-16
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status).
Figure 10. Chip/Sector Erase Operation Timings
OE#
WE#
CE#
VCC
Data
Addresses
tDS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
555h PA PA
Read Status Data (last two cycles)
A0h
tCS
Status DOUT
Program Command Sequence (last two cycles)
tCH
PA
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
InProgress Complete
tWHWH2
VAVA
Erase Command Sequence (last two cycles) Read Status Data
-
8/10/2019 AM29F010B - Chip EPROM
25/33Am29F010B 25
P R E L I M I N A R Y
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0DQ6
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note:VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
22336B-17
Figure 11. Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
tOE
DQ6
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
tACC
tRC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note:VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
22336B-18
Figure 12. Toggle Bit Timings (During Embedded Algorithms)
-
8/10/2019 AM29F010B - Chip EPROM
26/3326 Am29F010B
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performancesection for more information.
Parameter Symbol
Parameter Description
Speed Options
UnitJEDEC Standard -45 -55 -70 -90 -120
tAVAV tWC Write Cycle Time (Note 1) Min 45 55 70 90 120 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 35 45 45 45 50 ns
tDVEH tDS Data Setup Time Min 20 20 30 45 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time (Note 1) Min 0 ns
tGHEL tGHEL Read Recover Time Before Write Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 25 30 35 45 50 ns
tEHEL tCPH CE# Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 s
tWHWH2 tWHWH2 Chip/Sector Erase Operation (Note 2) Typ 1.0 sec
-
8/10/2019 AM29F010B - Chip EPROM
27/33Am29F010B 27
P R E L I M I N A R Y
AC CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25C, 5.0 V VCC
, 1 million cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90C, VCC= 4.5 V (4.75 V for -45), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
6. The device has a minimum guaranteed erase cycle endurance of 1 million cycles.
tGHEL
tWS
OE#
CE#
WE#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# DOUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program55 for erase
tWHWH1 or 2
tWH
PD for program30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase555 for chip erase
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT= Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
22336B-19
Figure 13. Alternate CE# Controlled Write Operation Timings
Parameter
Limits
CommentsTyp (Note 1) Max (Note 2) Unit
Chip/Sector Erase Time 1.0 15 secExcludes 00h programming prior to
erasure (Note 4)
Byte Programming Time 7 300 s Excludes system-level overhead
(Note 5)Chip Programming Time (Note 3) 0.9 6.25 sec
-
8/10/2019 AM29F010B - Chip EPROM
28/3328 Am29F010B
P R E L I M I N A R Y
LATCHUP CHARACTERISTIC
Note:Includes all pins except VCC. Test conditions: VCC= 5.0 Volt, one pin at a time.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA= 25C, f = 1.0 MHz.
PLCC AND PDIP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA= 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Description Min Max
Input Voltage with respect to VSSon I/O pins 1.0 V VCC+ 1.0 V
VCCCurrent 100 mA +100 mA
Parameter
Symbol Parameter Description Test Conditions Typ Max Unit
CIN Input Capacitance VIN= 0 6 7.5 pF
COUT Output Capacitance VOUT= 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN= 0 7.5 9 pF
Parameter
Symbol Parameter Description Test Conditions Typ Max Unit
CIN Input Capacitance VIN= 0 4 6 pF
COUT Output Capacitance VOUT= 0 8 12 pF
CIN2 Control Pin Capacitance VPP= 0 8 12 pF
Parameter Description Test Conditions Min Unit
Minimum Pattern Data Retention Time150C 10 Years
125C 20 Years
-
8/10/2019 AM29F010B - Chip EPROM
29/33Am29F010B 29
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
PD 03232-Pin Plastic DIP (measured in inches)
Dwg rev AD; 10/99
-
8/10/2019 AM29F010B - Chip EPROM
30/3330 Am29F010B
P R E L I M I N A R Y
PHYSICAL DIMENSIONS* (continued)
PL 03232-Pin Plastic Leaded Chip Carrier (measured in inches)
Dwg rev AH; 10/99
-
8/10/2019 AM29F010B - Chip EPROM
31/33Am29F010B 31
P R E L I M I N A R Y
PHYSICAL DIMENSIONS* (continued)
TS 03232-Pin Standard Thin Small Outline Package (measured in millimeters)
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
-
8/10/2019 AM29F010B - Chip EPROM
32/3332 Am29F010B
P R E L I M I N A R Y
PHYSICAL DIMENSIONS* (continued)
TSR 03232-Pin Standard Thin Small Outline Package (measured in millimeters)
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
-
8/10/2019 AM29F010B - Chip EPROM
33/33
P R E L I M I N A R Y
REVISION SUMMARY
Revision A (August 12, 1999)
Ini t ia l release. The Am29F010B replaces theAm29F010A data sheet (22181B+1).
Revision A+1 (September 22, 1999)
Device Bus Operations
Sector Protection/Unprotection:Corrected the publica-tion number for the programming supplement.
Revision A+2 (September 27, 1999)
Erase and Programming Performance table
In Notes 1 and 6, corrected the erase cycle endurance
to 1 million cycles.
Revision B (November 12, 1999)
AC CharacteristicsFigure 9. Program OperationsTiming and Figure 10. Chip/Sector Erase
Operations
Deleted tGHWLand changed OE# waveform to start at
high.
Physical Dimensions
Replaced figures with more detailed illustrations.
Trademarks
Copyright 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies