Altium DesignerPrinted Electronics

Sr. Product Marketing Manager

David Marrakchi

Printed Electronics Challenges

§ Layer-less design concept

§ Tracks & Dielectrics are printed/deposited

§ Need to isolate “only” crossover tracks

§ Selecting the right material for the application

§ Net connectivity & Design Rules Check

§ 2D to true 3D visualization Source: www.chromaline.com/printed-electronics/

Printed Electronics Support

§ Non-standard stackup layer order, representing material deposition order

§ Consideration of strict layers printing order with specified type (conductive vs. non- conductive)

§ Ability to create custom geometry within the isolation layer (Crossover tracks Dielectric)

Layer-less design conceptSwitching board mode to Printed Electronics in LSM

Crossover generated dielectric

Printed Electronics Support

§ Predefined Printed Electronics material in Materials Library:

§ Functionally driven materials (inks): conductive, non-conductive, stretchable, adhesive, etc…

§ User Defined Materials

Material Library

Printed Electronics Support

§ Touching tracks from different layers are considered shorts

§ Dielectric isolation layer only needed in crossover areas

Nets connectivity & Design Rules Checks

Short-Circuit

Short Circuit Constraint: Track on layer “Base (Layer 1)” and Track on layer “Additional (Layer 3)”

Dielectric

Clearance

Antenna

Unrouted Net

Dielectric shape drawn on non-conductive layer prevents from short-circuit

Clearance Constraint: Track on layer “Base (Layer 1)” and Track on layer “Additional (Layer3)”

Antenna is made with the several tracks printed on top of each other in order to gain desired height of the material

Unrouted Net Constraint:Net N1 Between Track on layer “Base (Layer 1)” and Track on layer “Additional (Layer3)”

Bad connection

Ok connection

Printed Electronics Support

§ Automatically or manually generates dielectric shapes for the

crossover tracks from different layers with defined expansion size

§ Ability to fill gaps between dielectric shapes

Dielectric shapes generation

Before shape generation: No dielectrics -> Short-Circuits violation

After shape generation : Dielectric are created -> No Short Circuits violation

Printed Electronics Support

§ Visualization does support the absence

of the top/bottom layers concept

2D to 3D visualization

2D

3D

Courtesy of Tactotek

Printed Electronics Support

Thank you!!

Q&A