alliance as7c256-20tc 256k sram circuit analysis · blpc ry rwl rdb/~ wl 2.1.2 redundant memory...

F1.0

July 16, 1998

Table of Contents

List of Figures ..................................................................................Introduction......................................................................................Page 3Device Summary Sheet ...................................................................Page 4Chip Description ..............................................................................Page 6Top Level Diagram............................................................................. Tab 1Data Path ............................................................................................ Tab 2Address Path...................................................................................... Tab 3Clocks................................................................................................. Tab 4Symbol and Signal Naming Conventions ........................................ Tab 5Signal Cross-Reference .................................................................... Tab 6

AllianceAS7C256-20TC256K SRAM

Circuit Analysis

For questions, comments, or more information about this report, or for anyadditional technical needs concerning semiconductor technology, pleasecall a Sales Representative at Chipworks.

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Rev 1.0 - May 29, 1998 12:26x:\sr\alliance\256_sram\pdfs\images\packmark.vsd

Alliance AS7C256-20TCDevice Type: 32Kx8 SRAMDie Markings: ASR1808NU

© (M) 1995Date Code: 9739

0.1.1 Package Markings

Rev 1.0 - Jul 14, 1998 10:14x:\sr\alliance\256_sram\pdfs\images\xray.vsd


© (M) 1995Date Code: 9739

0.1.2 Package X-Ray

PackagePin #

BondPads

{OE~} 22

23{A11}

21 {A10}

24

25

26

27

28

1

2

3

4

5

6

7

{A9}

{A8}

{A13}

{WE~}

{VCC}

{A14}

{A12}

{A7}

{A6}

{A5}

{A4}

{A3}

20

19

18

17

16

15

14

13

12

11

10

9

8

{CE~}

{I/O7}

{I/O6}

{I/O5}

{I/O4}

{I/O3}

{GND}

{I/O2}

{I/O1}

{I/O0}

{A0}

{A1}

{A2}

Rev 1.0 - May 29, 1998 12:28x:\sr\alliance\256_sram\pdfs\images\pconfig.vsd


© (M) 1995Date Code: 9739

0.1.3 Pin Configuration

Rev 1.0 - May 29, 1998 12:21x:\sr\alliance\256_sram\pdfs\images\diemark.vsd


© (M) 1995Date Code: 9739

0.1.4 Die Markings

Rev 1.0 - Jul 15, 1998 04:21x:\sr\alliance\256_sram\pdfs\images\diephoto.vsd


© (M) 1995Date Code: 9739

0.2.0 Die Photograph Die Size: 5.07mm x 2.15mm = 10.90mm2 — (seal)

1.0.0 Top Level DiagramAlliance AS7C256-20TCDevice Type:

ASR1808NU

Date Code:

File:

3-Jul-1998 11:42:35

Reference:

Revision: JS

Die Markings: 32Kx8 SRAM

9739Note: Device sizes are in microns (as measured from photographs) +/- 0.25 µm

Template: A40.DOTX:\SR\ALLIANCE\256_SRAM\PDFS\PROTEL\TOPLEVEL.SCH

© (M) 1995

{I/O[7:0]}{CE~}

{WE~}

{OE~}

{I/O[7:0]}

READ~

WRITE~

CE1~

OE1

BLPC[15:0]

Y<256>

DLPC

WL<2048>

RY[15:0]<2>

RWL[15:0]

DBW[15:0][7:0]

DBR[15:0][7:0]~

DBOE[7:0][7:0]/~

DBPC[15:0]~

RDBSAEN[3:0]

RDBPC[7:0]~

RDBSEL[7:0]~

RDWR[7:0]

RDLS[7:0][7:0]

0ATD

2.0.0 Data PathDATAPATH.SCH

{A[14:0]}

{CE~}

{WE~}

{OE~}

READ~

WRITE~

CE1~

OE1

DLPC

0ATDOUT1

0ATDOUT2~

0ATDOUT3~

DBR[15:0][7:0]~

RDLS[7:0][7:0]

DBPC[15:0]~

DBOE[7:0][7:0]/~

DBW[15:0][7:0]

RDBSAEN[3:0]

RDBPC[7:0]~

RDBSEL[7:0]~

RDWR[7:0]

BS[15:0]~

ABD[7:0]

RYH[7:0]~

RYH[7:0]

CE1

0ATD

4.0.0 ClocksCLOCKS.SCH

{A[14:0]}

CE1~

CE1

0ATDOUT1

0ATDOUT2~

0ATDOUT3/~

Y<256>

WL<2048>

RWL[15:0]

BLPC[15:0]

ABD[7:0]

RYH[7:0]

RYH[7:0]~

RY[15:0]<2>

BS[15:0]~

3.0.0 Address PathADDPATH.SCH

2.0.0 Data PathAlliance AS7C256-20TCDevice Type:Die Markings:

Date Code:

3-Jul-1998 11:42:40

X:\SR\ALLIANCE\256_SRAM\PDFS\PROTEL\DATAPATH.SCHFile: Reference:

Revision: JS

32Kx8 SRAMASR1808NU


Template: B40.DOT

© (M) 1995

READ~

DL[7:0]/~ DOUT[7:0]/~

2.4.0 Data Line Sense AmplifierDLSNSAMP.SCH

{I/O[7:0]}

OE1

DOUT[7:0]/~

2.5.0 Data Output BufferDOUTBUFF.SCH

DIN[7:0]{I/O[7:0]}

CE1~

2.6.0 Data Input BufferDINBUFF.SCH

{I/O[7:0]}

RDB[L]/~ RDB[R]/~

RDBSAEN

DL[7:0]/~

RDBSEL<2>~RDWR<2>

RDBPC<2>~

0ATD

RDLS<2>[7:0]

2.3.0 Redundant Column AccessREDACCES.SCH

READ~WRITE~CE1~ OE1

1 of 4

BLPC[i+7]

Y[i+7]<16>

WL[i+7]<128>

RY[i+7]<2>

RWL[i+7]

BLPC[15:0]

Y<256>

BLPC[i+8]

Y[i+8]<16>

WL[i+8]<128>

RY[i+8]<2>

RWL[i+8]

BLPC[i]

Y[i]<16>

WL[i]<128>

RY[i]<2>

RWL[i]

BLPC[i+1]

Y[i+1]<16>

WL[i+1]<128>

RY[i+1]<2>

RWL[i+1]

DB[R][7:0]/~DB[L][7:0]/~

DL[7:0]/~

DBR<2>[7:0]~DBOE<1>[7:0]/~

DBW<2>[7:0]

DBPC<2>~

2.2.0 Databus AccessDBACCESS.SCH

DB[R][7:0]/~DB[L][7:0]/~

DL[7:0]/~

DBR<2>[7:0]~DBOE<1>[7:0]/~

DBW<2>[7:0]

DBPC<2>~

2.2.0 Databus AccessDBACCESS.SCH

DIN[7:0] DL[7:0]/~

WRITE~DLPC

2.7.0 Data Line Write DriverDLWDRIVR.SCH

DLPC

DB[7:0]/~

RDB/~

BLPC

RY<2>

RWL<1>

WL<128>

Y<16>

2.1.0 Memory BlockMEMBLOCK.SCH

DB[7:0]/~

RDB/~BLPC

RY<2>

RWL<1>

WL<128>

Y<16>


DB[7:0]/~

RDB/~

BLPC

RY<2>

RWL<1>

WL<128>

Y<16>


DB[7:0]/~

RDB/~

BLPC

RY<2>

RWL<1>

WL<128>

Y<16>


WL<2048>

RY[15:0]<2>

RWL[15:0]DBW[i+7,i]][7:0]DBR[i+7,i][7:0]~DBOE[j][7:0]/~DBPC[i+7,i]

DBW[i+8,i+1]][7:0]DBR[i+8,i+1][7:0]~DBOE[j+1][7:0]/~DBPC[i+8,i+1]

DBW[15:0][7:0]DBR[15:0][7:0]~DBOE[7:0][7:0]/~DBPC[15:0]~

RDBSAEN[3:0]RDBPC[7:0]~

RDBSEL[7:0]~RDWR[7:0]

RDLS[7:0][7:0]0ATD 0ATD

RDWR[m+1,m]RDBSEL[m+1,m]~RDBSAEN[m]RDBPC[m+1,m]~

RDLS[j+1,j][7:0]0ATD

RDWR[m+1,m]RDBSEL[m+1,m]~RDBSAEN[m]RDBPC[m+1,m]~

RDLS[j+1,j][7:0]

DBW[15:0][7:0]DBR[15:0][7:0]DBOE[7:0][7:0]/~DBPC[15:0]~

2.1.0 Memory BlockAlliance AS7C256-20TCDevice Type:Die Markings:

Date Code:

3-Jul-1998 11:42:46

X:\SR\ALLIANCE\256_SRAM\PDFS\PROTEL\MEMBLOCK.SCHFile: Reference:

Revision: HY

32Kx8 SRAMASR1808NU


Template: B40.DOT

© (M) 1995

C

DB[7:0]/~DB7/~

DB6/~

DB5/~

DB4/~

DB3/~

DB2/~

DB1/~

DB0/~

32 Total Blocks

BLPCRY<2>

RWL<1>

WL<128>

Y<16>

RDB/~RDB/~

BLPCY<16>

DB/~RWL<1>WL<128>

2.1.1 Memory SectorMEMSECTR.SCH

BLPCY<16>

DB/~RWL<1>WL<128>


BLPCY<16>

DB/~RWL<1>WL<128>


BLPCY<16>

DB/~RWL<1>WL<128>


BLPCY<16>

DB/~RWL<1>WL<128>


BLPCY<16>

DB/~RWL<1>WL<128>


BLPCY<16>

DB/~RWL<1>WL<128>


BLPCY<16>

DB/~RWL<1>WL<128>


BLPCRY<2>RWL<1> RDB/~WL<128>

2.1.2 Redundant Memory SectorRMEMSECT.SCH

2.1.1 Memory SectorAlliance AS7C256-20TCDevice Type:

ASR1808NU

Date Code:

File:

3-Jul-1998 11:42:50

Reference: JS32, JS33

Revision: JS



Template: A40.DOTX:\SR\ALLIANCE\256_SRAM\PDFS\PROTEL\MEMSECTR.SCH

© (M) 1995

C

3.5/.5

4.5/.5 4.5/.5

VCC VCC

.6/1 .6/1

VCC VCC

WL

BL BL~Cell

WL

BL BL~Cell

WL

BL BL~Cell

4/.54/.5

BLPC

Y<16>

3.5/.5

4.5/.5 4.5/.5

VCC VCC

.6/1 .6/1

VCC VCC

WL

BL BL~Cell

WL

BL BL~Cell

WL

BL BL~Cell

4/.54/.5

3.5/.5

4.5/.5

VCC VCC

.6/1 .6/1

VCC VCC

WL

BL BL~Cell

WL

BL BL~Cell

WL

BL BL~Cell

4/.54/.5

Y15Y1Y0

DB/~DB

DB~

RWL<1>

WL<128> WL127

WL0

8 sectors per block

16 total blocks

4.5/.5

WL

BL BL~Cell

VCCVCC

BL~

WL

BL

2.1.2 Redundant Memory SectorAlliance AS7C256-20TCDevice Type:

ASR1808NU

Date Code:

File:

3-Jul-1998 11:42:54

Reference:

Revision: JS



Template: A40.DOTX:\SR\ALLIANCE\256_SRAM\PDFS\PROTEL\RMEMSECT.SCH

© (M) 1995

3.5/.5

4.5/.5 4.5/.5

VCC VCC

.6/1 .6/1

VCC VCC

WL

BL BL~Cell

WL

BL BL~Cell

WL

BL BL~Cell

4/.54/.5

BLPC

RY<2>

3.5/.5

4.5/.5

VCC VCC

.6/1 .6/1

VCC VCC

WL

BL BL~Cell

WL

BL BL~Cell

WL

BL BL~Cell

4/.54/.5

RY1RY0

RWL<1>

WL<128> WL127

WL0

WL

BL BL~Cell

VCCVCC

BL~

WL

BL

RDB/~RDB

RDB~

4.5/.5

2.2.0 Databus AccessAlliance AS7C256-20TCDevice Type:

ASR1808NU

Date Code:

File:

3-Jul-1998 11:42:58

Reference: JS27

Revision: JS



Template: A40.DOTX:\SR\ALLIANCE\256_SRAM\PDFS\PROTEL\DBACCESS.SCH

© (M) 1995

DBR<2>[7:0]~DBOE<1>[7:0]/~

DB[L][7:0]/~ DB[R][7:0]/~

DL[7:0]/~

2.2.1 Data Bus Sense AmplifiersDBSNSAMP.SCH

DB[R][7:0]/~DB[L][7:0]/~

9/.5

9/.5

DL[7:0]/~

DBR<2>[7:0]~DBOE<1>[7:0]/~

DBW<2>[7:0] DBW[i+7][7:0]

DBW[i][7:0]

4/.5

4/.5

4/.5

VCC VCC

DBPC<2>~ 4/.5

4/.5

4/.5

VCC VCC

JT23 JT24

(1 of 16)

(1 of 16)

(1 of 8) (1 of 8)

DBPC[i+7]~ DBPC[i]~

2.2.1 Data Bus Sense AmplifiersAlliance AS7C256-20TCDevice Type:

ASR1808NU

Date Code:

File:

3-Jul-1998 11:43:01

Reference: JS27

Revision: JS



Template: A40.DOTX:\SR\ALLIANCE\256_SRAM\PDFS\PROTEL\DBSNSAMP.SCH

© (M) 1995

C

9/.59/.5

VCC VCC

6.25/.5 2.25/.5 6.25/.5 2.25/.5

9/.59/.5

VCC VCC

6.25/.5 2.25/.5 6.25/.5 2.25/.5

6.25/.5 6.25/.54.5/.5 4.5/.5

4.5/.5

18.25/.5

37.25/.5

18.25/.5

37.25/.5

DB[L][7:0]

DB[L][7:0]~

DBOE[j][7:0]~

DBOE[j][7:0]

DB[R][7:0]~

DB[R][7:0]

1 of 8 per block pair

8 block pairs per chip

1 of 64 total

DBR<2>[7:0]~ DBREAD[i+7][7:0]~ DBR[i][7:0]~

DL[7:0]

DL[7:0]~

DBOE<1>[7:0]/~

DB[L][7:0]/~

DL[7:0]/~

DB[R][7:0]/~

DBOE[j][7:0]~

DBOE[j][7:0]

DBOE[j][7:0]~

2.3.0 Redundant Column AccessAlliance AS7C256-20TCDevice Type:Die Markings:

Date Code:

3-Jul-1998 11:43:04

X:\SR\ALLIANCE\256_SRAM\PDFS\PROTEL\REDACCES.SCHFile: Reference: JT36

Revision: JS

32Kx8 SRAMASR1808NU


Template: B40.DOT

© (M) 1995

9/.5

3/.5

VCC

3/.53/.5

VCC VCC

RDBPCm+1~

RDB[L]/~ RDB[L]/~

9/.5

3/.5

VCC

3/.53/.5

VCC VCC

RDBPCm~

RDB[R]/~RDB[R]/~

RDBSEL<2>~

RDWR<2>

RDBSAEN

JT49A

JT49

RDL/~

RDB[L]/~ RDB[R]/~

RDBSEL<2>~RDBSAEN

2.3.1 Redundant Data Bus Sense AmplifierREDDBSA.SCH

DL[7:0]/~

28/.5DL0/~

(3 of 8)

(1 of 2)

28/.5DL1/~

(1 of 2)

28/.5DL7/~

(1 of 2)

RDLS[j+1][0]

RDLS[j+1][7]

RDLS[j+1][1]

28/.5DL0/~

(3 of 8)

(1 of 2)

28/.5DL1/~

(1 of 2)

28/.5DL7/~

(1 of 2)

RDLS[j][0]

RDLS[j][7]

RDLS[j][1]

(1 of 2)

(1 of 2)

RDL/~

JT47A

JT47RDBPC<2>~

7.5/.57.5/.5

7.5/.5

7.5/.6

4/.5

VCC VCC

0ATD

RDLS<2>[7:0]

RDWRm+1

RDWRm

( 1 of 4) for whole chip

(to upper blocks)

(to lower blocks)

JT13

2.3.1 Redundant Data Bus Sense AmplifierAlliance AS7C256-20TCDevice Type:

ASR1808NU

Date Code:

File:

3-Jul-1998 11:43:08

Reference: JT36

Revision: JS



Template: A40.DOTX:\SR\ALLIANCE\256_SRAM\PDFS\PROTEL\REDDBSA.SCH

© (M) 1995

9/.59/.5

VCC VCC

6.25/.5 2.25/.5 6.25/.5 2.25/.5

9/.59/.5

VCC VCC

6.25/.5 2.25/.5 6.25/.5 2.25/.5

6.25/.5 6.25/.54.5/.5 4.5/.5

4.5/.5

18.25/.5

37.25/.5

18.25/.5

37.25/.5

RDB[L]

RDB[L]~

.B

.A

.C

.D

.A.A

.A

RDB[R]~

RDB[R]

RDBSEL<2>~

7/.5

3.5/.5

7/.5

3.5/.5

7/.5

3.5/.5

7/.5

3.5/.5

RDBSAENJT44

.B

.C

.D

JT48AJT48

RDL/~

RDB[L]/~ RDB[R]/~

RDL

RDL~

.A

RDBSELm+1~ RDBSELm~

2.4.0 Data Line Sense AmplifierAlliance AS7C256-20TCDevice Type:

ASR1808NU

Date Code:

File:

3-Jul-1998 11:43:12

Reference: JS10, JS11

Revision: JS



Template: A40.DOTX:\SR\ALLIANCE\256_SRAM\PDFS\PROTEL\DLSNSAMP.SCH

© (M) 1995

8.5/.5 3/.5 8.5/.5 3/.5

11.5/.5

VCC VCC

8.5/.5

9/.59/.55.75/.5 5.75/.5

11.5/.5READ~

1.5/7.5

1.5/7.5

9/.6

9/.6

VCC

VCC

VCC

VCC

DL[7:0]/~

DL[7:0]~

DL[7:0]

READ~

DOUT[7:0]/~DOUT[7:0]

DOUT[7:0]~

JT2

JT3

(1 of 8)

JT6

alliance as7c256-20tc 256k sram circuit analysis · blpc ry rwl rdb/~ wl 2.1.2 redundant memory...

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