alicia klinefelter ece 7332 spring 2011 digitally controlled oscillators (dco)
TRANSCRIPT
![Page 1: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/1.jpg)
Alicia KlinefelterECE 7332Spring 2011
DIGITALLY CONTROLLED
OSCILLATORS (DCO)
![Page 2: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/2.jpg)
2
Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in?
Early Architectures Oscillator Background Current Research
Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency
synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator
for SoC Applications Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
OUTLINE
![Page 3: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/3.jpg)
3
Problems with analog implementationDesign and verificationSettling time
20 – 30 ms in CPPLLs 10 ms in the ADPLL
Implementation cost Custom blocks
Loop Filter High Leakage current Large capacitor (2) area
Charge Pump Low output resistance Mismatch between charging current and discharging current
Phase offset and reference spurs
WHY ARE ADPLLS USEFUL?
![Page 4: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/4.jpg)
4
ALL-DIGITAL PLL (ADPLL) TOPOLOGY
Time-to-DigitalConverter (TDC)
Digital Loop Filter
Divider
ref(t)
DCO
out(t)
![Page 5: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/5.jpg)
5
Architectures
Delay chain structure sets resolution Mismatch causes linearity issues Resolution: want low quantization noise
ADPLL: TIME-TO-DIGITAL CONVERTER
Time-to-DigitalConverter (TDC)
Digital Loop Filter
Divider
ref(t)
DCO
out(t)
div(t) D
QD
QD
Q
ref(t)
div(t)
+
...
...
e[n]
[1, Perrott]
![Page 6: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/6.jpg)
6
Compact area Insensitive to leakage
ADPLL: DIGITAL LOOP FILTER
Time-to-DigitalConverter (TDC)
Digital Loop Filter
Divider
ref(t)
DCO
out(t)
![Page 7: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/7.jpg)
7
ADPLL: DCO
Time-to-DigitalConverter (TDC)
Digital Loop Filter
Divider
ref(t)
DCO
out(t)
Replaces the VCO from analog implementations Consumes 50-70% of overall ADPLL power Generally consists of a digital controller implementing
frequency acquisition algorithm and oscillator.
![Page 8: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/8.jpg)
8
Power Consumption @ Frequency Phase Noise
Measured with respect to a frequency offset from the carrier
The units, dBm/Hz, define noise power contained in a 1 Hz bandwidth
JitterLSB Resolution (ps)Tuning rangeNote: bit resolution is rarely mentioned
Does not seem to have drastic impact on tuning range
METRICS
![Page 9: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/9.jpg)
Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in?
Early Architectures Oscillator Background Current Research
Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency
synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator
for SoC Applications Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
OUTLINE
9
![Page 10: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/10.jpg)
10
Straightforward approach DAC + VCO
Varactors used initially
Problem with varactors: Capacitance not
very linear with input voltage.
For digital tuning, need flat regions.
EARLY ARCHITECTURES: ANALOG TUNING
DAC
[3, Xu]
![Page 11: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/11.jpg)
Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in?
Early Architectures Oscillator Background Current Research
Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency
synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator
for SoC Applications Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
OUTLINE
11
![Page 12: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/12.jpg)
12
Frequency determined by delay of the inverters Each stage provides phase shift where Supply voltage
Easy to integrateHigh phase noise → Not good for RF applicationsCurrent starved → high resolution, high static
power due to current source
OSCILLATORS: RING OSCILLATOR
...1 2 n
𝑛2∉𝑍
![Page 13: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/13.jpg)
Low phase noisedissipates only of the total energy stored during one cycle.
Complicated layout
High area
OSCILLATORS: LC OSCILLATOR
13
240um
[4, Thiel]
![Page 14: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/14.jpg)
Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in?
Early Architectures Oscillator Background Current Research
Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency
synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator
for SoC Applications Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
OUTLINE
14
![Page 15: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/15.jpg)
15
Weighted capacitor networks replaced varactorsConcept of fine and coarse tuning introduced
Coarse (binary weighted) lacks monotonicity Fine (unit weighted) has monotonicity but complex control
NOVELTY: FULLY DIGITAL TUNING
...
bn b1 b0
...
bn b1 b0
1x1x1x
...
bn b1 b0
1x2x2nx
![Page 16: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/16.jpg)
16
To increase resolution, many systems use ΣΔ modulators for dithering the input to the unit caps. Unit cap determines
gain of DCO Recall, ΣΔ modulators
are oversampling converters and produces output pulses proportional to signal changes. Quantization noise
effects Phase noise goes down
as frequency increases
TECHNIQUE : DITHERING
[1, Perrott]
![Page 17: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/17.jpg)
17
If you have an LTI system, the energy spectral density of the output is similar to an eigenvalue of the system.
Since we go from discrete time to continuous time, this relationship can be expressed as:
NOISE ANALYSIS: DITHERING
H(s)x[n] y(t)
[1, Perrott]
![Page 18: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/18.jpg)
Recall:
18
NOISE ANALYSIS: DITHERING
[1, Perrott]
![Page 19: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/19.jpg)
Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in?
Early Architectures Oscillator Background Current Research
Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency
synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator
for SoC Applications Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
OUTLINE
19
![Page 20: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/20.jpg)
20
Many traditional delay lines are simple inverters
Chain of tri-state inverters in parallel
Driving capability modulation (DCM)Changes the driving
current of each delay cell by controlling number of enabled tri-state buffers/inverters
Bad power, linearity
DELAY CELLS: DCM
...
en0
en1
enn
...
...
...R0
↔
R1
R2
Rn
![Page 21: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/21.jpg)
21
Hysteresis delay cells (HDC) are relatively new in low power (2007 - ). Trade off power and delay resolution.
Fewer needed to acquire the delay of a many traditional delay cells. HDCs have wider operating range
Control of driving current to obtain diff erent propagation delay
DELAY CELLS: HYSTERESIS
[2]
![Page 22: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/22.jpg)
22
Application: Wireless body area networksRelaxes phase noise requirement
Oscillator structure based on a power-of-2 delay stage DCO (P2-DCO) architectureEach delay stages is ½ delay of previous
80um x 80um in 90nm CMOS5.4uW @ 3.4MHz, 1V supplyPresents two novel HDC topologies
Improves power-to-delay and area-to-delay ratios
IMPLEMENTATION
![Page 23: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/23.jpg)
Uses different hysteresis cells for different tuning stagesNeed for decoder removed due to power of two delay
Header and footer rarely turned on at same timeLeads to voltage scaling of the cell with hysteresis
23
IMPLEMENTATION: DELAY CELLS
[9][9]
![Page 24: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/24.jpg)
Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in?
Early Architectures Oscillator Background Current Research
Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency
synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator
for SoC Applications Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
OUTLINE
24
![Page 25: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/25.jpg)
As technology migrates, push towards standard cell implementations for portability.
Goal: implement DCO in HDL
Ring oscillators always used for synthesizeable DCO
Limits implementation options Most delay cells inverters and
NANDs Controllers simply digital logic
ARCHITECTURE: STANDARD CELL
25
![Page 26: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/26.jpg)
26
Segmented delay line, hysteresis delay cells, and uses standard cells: ultra portable!
140uW (@200 MHz) with 1.47-ps resolution Segmented delay line power gating saves ~25-75% of power
Dependent on operating frequency
PAPER HIGHLIGHTS
[2]
![Page 27: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/27.jpg)
Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in?
Early Architectures Oscillator Background Current Research
Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency
synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator
for SoC Applications Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
OUTLINE
27
![Page 28: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/28.jpg)
28
New DCO tuning word (OTW) presetting technique to reduce settling time
Three stages in ADPLL PVT calibration Frequency Acquisition Tracking (locked)
Each mode is a search algorithm, each has its own scheme
For ring oscillator, controller implemented in digital logic
For LC oscillator, controller is capacitor bank
CONTROLLER: LOCKING TIME
![Page 29: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/29.jpg)
29
Paper [4] designed a new, faster locking algorithm for frequency acquisition.Locks in 18 clock cycles
Binary search typically used
CONTROLLER: FASTER ALTERNATIVE
[4]
![Page 30: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/30.jpg)
30
1. PFD produces gain and fast/slow pulse
2. Mux selects fast/slow gain value
3. Gain value like the charge pump
1. As DCO frequency differs more from target, gain increases
4. Use previous gain with new gain to determine new guess value
CONTROLLER: FASTER ALTERNATIVE
[4]
![Page 31: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/31.jpg)
Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in?
Early Architectures Oscillator Background Current Research
Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency
synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator
for SoC Applications Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
OUTLINE
31
![Page 32: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/32.jpg)
32
1.9 GHz DCO in 0.13um technology2 x 2mm2 using 6 metal layersSupply voltage at 0.5V, 100uW power
More device transconductance (gm) is available for a given bias current
Application: frequency synthesizer in wireless transceiver
Between calibration, oscillator runs free until next tuning cycle (TX/RX) Other circuitry turned off
No external components used (even with LC oscillator)
NOVELTY: SUBTHRESHOLD
![Page 33: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/33.jpg)
33
Diff erential NMOS only for high output swing for low input voltages
Inductance Want high Q
determines overall Q of system, startup current, and power consumption
Used bondwire inductances
Want 1fF LSB from caps, but a problem when wiring parasitics on same order of magnitude
OSCILLATOR: LC BASED
[10]
![Page 34: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/34.jpg)
34
Capacitor matching a problem for small unit capacitors
Varactors could work Need flat areas of curve Testing required to find
input voltages of such areas
Switched capacitor implementation using linear capacitors proposed Routing parasitics
reduced
CHALLENGE: SMALL CAPACITORS
Change in Cin by ΔC:
[10]
![Page 35: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/35.jpg)
Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in?
Early Architectures Oscillator Background Current Research
Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency
synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9]
A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator
for SoC Applications Frequency Acquisition and Locking [4]
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning
Comparison of Results
OUTLINE
35
![Page 36: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/36.jpg)
36
Power Op. Freq Voltage
5.4uW 3.4MGHz 1 V
5.2uw 3.89MHz 1 V
8mW 12.3MHz 1.2 V
1.7mW 20MHz 1 V
166uW 163.2MHz 1 V
140uW 200MHz 1 V
110uW 200mhZ 0.8 V
75.9uW 239.2MHz 1 V
340uW 450MHz 1.8 V
1.7mW 560MHz 1.2 V
2.3mW 800MHz 0.9 V
23.3mW 1GHz 1.8 V
5.5mW 5.6GHz 0.7 V
DESIGN COMPARISONS: POWER
![Page 37: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/37.jpg)
37
DESIGN COMPARISONS: FREQ OFFSET
![Page 38: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/38.jpg)
38
DESIGN COMPARISONS: TUNING RANGE
![Page 39: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/39.jpg)
39
CPPSIM Tutorials [1, Perrot] PLL Digital Frequency Synthesizers [2, Perrot] PLL Voltage Controlled Oscillators
All papers in the bibliography section of Wiki were used for plot generation
Papers [2], [4], [9], [10], [14] addressed in presentation[3, Xu] Xu, L. (2006, May 18). Digitally controlled
oscillator. Retrieved from http://www.ecdl.tkk.fi /education/4198/pdf/dco_lxu.pdf
[4, Thiel] Thiel, B.T.; Neyer, A.; Heinen, S.; , "Design of a low noise, low power 3.05–3.45 GHz digitally controlled oscillator in 90 nm CMOS," Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D. , vol., no., pp.228-231, 12-17 July 2009.
RESOURCES
![Page 40: Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)](https://reader035.vdocuments.site/reader035/viewer/2022081717/5518a249550346b31f8b48fc/html5/thumbnails/40.jpg)
40
Move to digital PLL implementations motivated by SoC applications
New digital circuits in ADPLL: TDC, fi lter, DCORing oscillators versus LC oscillatorsCurrent Research
Initial digital tuning with sigma-delta dithering Delay cells Portability Frequency acquisition algorithm Sub-threshold operation
QUESTIONS?
OVERVIEW