akd5534-b rev.3 engilish manual - akm.com · further, the akd55x4-b 10pin headercan achieve the...

[AKD5534-B]

<KM119203> 2016/05

GENERAL DESCRIPTION

The AKD55X4-B is an evaluation board for AK55X4/X2, which is 32bit, 8k – 768kHz, 4ch/2ch ADC.

4ch ADC (AK55X4) : AK5534, AK5554, AK5574 2ch ADC (AK55X2) : AK5552, AK5572

The AKD55X4-B is includes the analog input circuit and also has a digital interface transmitter .

Further, the AKD55X4-B can achieve the interface with digital audio systems via BNC-connector.

Ordering guide

AKD55X4-B -- Evaluation board for AK55X4/X2

FUNCTION

DIT with BNC or Optical digital output.

ADC 4ch/2ch input is possible.

BNC connector for an external clock input.

AK4118A (DIT)

AIN1

AIN2

Clock Generator

+VOP

Input Buffer

AK55X4 AK55X2

-VOP

TVDD

Regulators

5V/3.3V

+15V

-15V

AVDD

3.3V

BNC_TX

(OUT)

DSP Data

10pin Header

AIN3

AIN4

Input Buffer

ｷｬﾉﾝｺﾈｸﾀ

(IN)

OPT_TX

(OUT)

1.8V

VDD18

Figure 1. AKD55X4-B Block Diagram

* Circuit diagram and PCB layout are attached at the end of this manual.

AKD55X4-B AK55X4/X2 Evaluation Board Rev.3

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[AKD5534-B]

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Evaluation Board Diagram

Board Diagram

J801

J802

J800

SW604

SW600

U4

J200

J202

J203

J201

SW603

SW601

PORT500

T1

T2

J805

J804

T3

J806

J807

J808

J809

J300

J302

J303

J301

T4

T5

SW602

J400

PORT400

PORT602

PORT601

PORT600

PORT610

J600

SW400

U1

AKD55X4-B

AK55X4/X2

-15V

VSS

+15V

VBIAS

AVDD

VCC

TVDD

VDD18

D3.3V

Figure 2. AKD55X4-B Board Diagram

Description

(1) U1 ( AK55X4/AK55X2 )

32bit,8k - 768kHz,4ch/2ch A/D Converter.

(2) J200,J201,J300,J301 ( Analog data )

Cannon connector : Differential Analog Input

(3) J202,J203,J302,J303 ( Analog data )

BNC Connector : Single-ended Analog Input.

(4) J400 / PORT400 ( Digital data )

BNC Connector / Optical Connector: Digital Output.

(5) J800, J801, J802,J804,J805,J806,J807,J808,J809 ( Power supply )

Power Supply Connector.

(6) PORT600,PORT601 ( pin header )

Pin header for evaluation (MCLK, BICK, LRCK, SDTO1, SDTO2, TDMIN).

(7) PORT602 ( pin header )

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Pin header for evaluation (DCLK, DSDOL1/R1, DSDOL2/R2).

(8) U4 ( AK4118A )

AK4118A has DIT. Transports output data from AK55X4/X2.

(9) SW600 ( Toggle switch )

Toggle type-switch PDN for AK55X4/X2.

“H” : PDN = High

“L” : PDN = Low

(10) SW601 ( Toggle switch )

Toggle type-switch PDN for AK4118A.

“H” : PDN = High

“L” : PDN = Low

(11) SW602,SW603,SW604 ( Dip switch)

DIP type-switch for AK55X4/X2.

“H” : Digital signal = High

“L” : Digital Signal = Low

(12) SW400 ( Dip switch (Dual In-line Package switch)

DIP type-switch for AK4118A.

“H” : Digital signal = High

“L” : Digital Signal = Low

(13) J600 ( MCLK external input )

BNC Connector : External Clock Input (MCLK).

(14) T1, T2, T3, T4, T5

Regulator for AK55X4/X2, AK4118A, Logic Circuit.

T1 : Regulated AVDD, VBIAS (5.0V/3.3V) from +15V.

T2 : Regulated VCC1, VCC2 (5.0V) from +15V.

T3 : Regulated TVDD (3.3V) from +5V.

T4 : Regulated TVDD, VDD18 (1.8V) from +5V

T5 : Regulated D33V (3.3V) from +5V.

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Evaluation Board Manual

Operation sequence

[1] Power supply line settings

[2] Jumped pins settings

[3] DIP switches settings

[4] Toggle switches settings

[5] Register control (Serial control)

[6] Evaluation modes

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[1] Power supply line settings

(1-1) Power supply settings : Used the regulator (T1,T2,T3,T4,T5) <Default>

Set up the power supplied lines :

* Each supply line should be distributed from the power supply unit.

Name Color Setting (Typ) Function Comments Default Settings

J800 +15V Green +15V Regulator and Op-amp

power supply

Should always be connected +15V

J801 -15V Blue -15V Regulator and Op-amp

power supply

Should always be connected -15V

J804 AVDD Red +5.0V / 3.3V AK55X4/X2 AVDD 5.0V/3.3V regulator is used,

R807=short by default.

When jack is used,

R808=short.

REG :

(R807 = short)

J805 VBIAS Red +5.0V / 3.3V Referential Voltage

source for Op-amp

5.0V/3.3V regulator is used,


When jack is used,

R810=short.

REG :

(R809 = short)

J809 VCC Red +5.0V 3.3V Regulator power

supply

5.0V regulator is used,


When jack is used,

R812=short.

REG :

(R811 = short)

J806 TVDD Orange +1.8 / +3.3V/ AK55X4/X2 TVDD,

Logic IC power supply


JP800=3.3V and JP801=REG

by default.

When 1.8V regulator is used,

JP800=1.8V and JP801=REG.

When jack is used,

JP801=JACK short.

REG (3.3V) :

(JP800=3.3V and

JP801=REG)

J807 VDD18 Orange +1.8V AK55X4/X2 VDD18 LDO of AK55X4/X2 is used,

JP802=open by default.

When 1.8V regulator is used,

JP802=REG.

When jack is used,

JP802=JACK.

Open :

(JP802=open)

J808 D3.3V Orange +3.3V AK4118A 3.3V VDD,

Logic IC power supply


JP803=REG by default.

When jack is used,

JP803=JACK.

REG :

(JP803=REG)

J802 VSS Black 0V Ground Should always be connected 0V

Table 1-1. Power supply line setting ( default : used the regulator )

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(1-2) About jumper for power supply :

The roles of the jumper or the short resistance for each power supply supplied from the regulator are as follows.

Connection of the jumper for power supply :

Name Function Comments Default Settings

R807

R808

AVDD1 Select regulator power supply

or jack for AVDD1

AVDD for AK55X4/X2:

R1007=short : 5.0V/3.3V regulator is used. (default)

R1008=short : Jack is used.

REG :

R807=short

R808=open

R809

R810

VBIAS Select regulator power supply

or jack for VBIAS

VBIAS for Op-amp Referential Voltage source:

R809=short : 5.0V/3.3V regulator is used. (default)


REG :

R809=short

R810=open

R811

R812

VCC1,

VCC2

Select regulator power supply

or jack for 5.0V Regulator

power supply

VCC1, VCC2 for 5.0V Regulator power supply:

R811=short : 5.0V regulator is used. (default)


REG :

R811=short

R812=open

JP800 TVDD-VSEL Select regulator power supply

3.3V or 1.8V for TVDD

TVDD for AK55X4/X2 and Logic IC:

JP800=3.3V : 3.3V regulator is used. (default)

JP800=1.8V : 1.8V regulator is used.

3.3V :

JP800=3.3V

JP801 TVDD-SEL Select regulator power supply

or jack for TVDD

TVDD for AK55X4/X2 and Logic IC:

JP801=REG : Regulator is used. (default)

JP801=JACK: Jack is used.

REG :

JP801=REG

JP802 VDD18-SEL Select External power supply or

LDO power supply of AK55XX

for VDD18

VDD18 selector for AK55X4/X2:

JP802=REG : External Power supply of 1.8V regulator is

used.

JP802=JACK : External Power supply of Jack is used.

JP802=open : LDO of AK55X4/X2 is used. (default)

LDO of AK55XX :

JP802=open

JP803 D33V-SEL Select regulator power supply

or jack for D33V

D33V for AK4118A and Logic IC:

JP1003=REG : 3.3V regulator is used. (default)

JP1003=JACK : Jack is used.

REG :

JP803=REG

Table 1-2. Jumper for power supply

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[2] Jumped pins settings

No Names Default Functions

1 JP400 TXDATA-SEL COAX Select COAX / Optical Connector for TX data of AK4118A.

COAX: COAX for TX data of AK4118A. (default)

OPT: Optical for TX data of AK4118A.

2 PORT605 BICK-SEL DIT Select input / output to AK55X4/X2 (U1) BICK

DIT: BICK-AK4118A-T (default)

PORT: Pin Header PORT600-BICK

GND: Connected to VSS

Open: No signal

3 PORT606 LRCK-SEL DIT Select input / output to AK55X4/X2 (U1) LRCK

DIT: LRCK-AK4118A-T (default)

PORT: Pin Header PORT600-LRCK


Open: No signal

4 PORT607 BICK-PHASE THR Select polarity (non-inverted output / inverted output) of

BICK_SEL inputs / outputs.

THR: Non-inverted output. (default)

INV: Inverted output.

5 PORT608 SDTO_SEL SDTO1 Select input to DIT:AK4118A (U4) DAUX

SDTO1: AK55X4/X2-SDTO1 is used. (default)

SDTO2: AK55X4/X2-SDTO2 is used.

open: No signal for DAUX-AK4118A-T

6 PORT609 TDMI-SEL Open Select connect to AK55X4/X2 (U1) TDMI

Open: No signal for TDMIN (default)

Short: Pin Header PORT601-TDMIN

7 PORT610 MCKI-SEL DIT Select input to AK55X4/X2 (U1) MCLK

DIT: MCLK-AK4118A-T (default)

PORT: Pin Header PORT600-MCLK

EXT: External MCLK (JACK:J600 EXT) input.


8 JP600 EXT Open Open: No input (default)

Short: External MCLK (JACK:J600 EXT) input.

9 JP700 PS-SEL1 SDA/CDTI Select input / output to AK55X4/X2 (U1) CKS0/SDA/CDTI

SDA/CDTI:

SDA/CDTI signal input / output to AK55X4/X2. (default)

CKS0:

CKS0 signal of SW803 input to AK55X4/X2.

10 JP701 PS-SEL2 CAD0-I2C/CSN Select input to AK55XX (U1) CKS1/CAD0-I2C/CSN

CAD0-I2C/CSN:

CAD0-I2C/CSN signal input to AK55XX. (default)

CKS1:

CKS1 signal of SW803 input to AK55XX.

11 JP702 PS-SEL3 CAD0-I2C Select input to JP701 CAD0-I2C/CSN

CAD0-I2C:

CAD0-I2C signal of SW602 input to JP701. (default)

CSN:

CSN signal of SW602 input to JP701.

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12 JP703 PS-SEL4 SCL/CCLK Select input to AK55X4/X2 (U1) CKS2/SCL/CCLK

SCL/CCLK:

SCL/CCLK signal input to AK55X4/X2. (default)

CKS2:

CKS2 signal of SW603 input to AK55X4/X2.

13 JP704 PS-SEL5 CAD1 Select input to AK55X4/X2 (U1) CKS3/CAD1

CAD1: CAD1 signal input to AK55X4/X2. (default)

CKS3: CKS3 signal of SW603 input to AK55X4/X2.

14 JP705 PS-SEL6 PS Select input to AK55X4/X2 (U1) PS/CAD0-SPI

PS:

PS signal input to AK55X4/X2. (default)

CAD0-SPI:

CAD0-SPI signal of SW602 input to AK55X4/X2.

15 JP800 TVDD-VSEL 3.3V Select power supply voltage of TVDD

3.3V: Regulator T3 (+5V => 3.3V) (default)

1.8V: Regulator T4 (+5V => 1.8V)

16 JP801 TVDD-SEL TVDD Select power supply to TVDD

REG: Regulator T3/T4 (default)

JACK: Power supply jack J806 “TVDD”

17 JP802 VDD18-SEL REG Select power supply to VDD18

REG: Regulator T4 (default)

JACK: Power supply jack J807 “VDD18”

18 JP803 D33V-SEL REG Select power supply to D33V

REG: Regulator T5 (+5V => 3.3V) (default)

JACK: Power supply jack J808 “D3.3V”

Table 2. Main board Jumper pin setting

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[3] DIP switches settings

(3-1). Setting for SW400 (Sets AK4118A (U4) audio format and master clock setting)

No. Switch Name Function default

1 DIF2 Set-up of DIF0 pin. H

2 DIF1 Set-up of DIF1 pin. L

3 DIF0 Set-up of DIF2 pin. H

4 OCKS1 Set-up of OCKS1 pin. H

5 OCKS0 Set-up of OCKS0 pin. L

Table 3-1. SW400 Setting (AK4118A)

Mode DIF2 pin SW400_1

DIF1 pin SW400_2

DIF0 pin SW400_3 DAUX SDTO

LRCK BICK

DIF2 bit DIF1 bit DIF0 bit I/O I/O

0 0 0 0 24bit, Left

justified

16bit, Right

justified H/L O 64fs O

1 0 0 1 24bit, Left

justified

18bit, Right


2 0 1 0 24bit, Left

justified

20bit, Right


3 0 1 1 24bit, Left

justified

24bit, Right


4 1 0 0 24bit, Left

justified

24bit, Left


5 1 0 1 24bit, I2S 24bit, I

2S L/H O 64fs O default

6 1 1 0 24bit, Left

justified

24bit, Left

justified H/L I 64-128fs I

7 1 1 1 24bit, I2S 24bit, I

2S L/H I 64-128fs I

Table 3-2. Audio format (AK4118A)

OCKS1 pin

SW400_4

OCKS0 pin

SW400_5 (X’tal) MCKO1 MCKO2 fs (max)

OCKS1 bit OCKS0 bit

0 0 256fs 256fs 256fs 96 kHz

0 1 256fs 256fs 128fs 96 kHz

1 0 512fs 512fs 256fs 48 kHz default

1 1 128fs 128fs 64fs 192 kHz

Table 3-3. Master Clock Frequency Select (AK4118A)

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(3-2). Setting for SW802 (Sets AK55X4/X2 (U1) )


1 TEST TEST Enable. L

2 PW0 ADC Power Management and Monaural / Stereo select. H



5 MSN

Master/Slave select.

L: Slave Mode

H: Master Mode

L

6 CAD0-SPI Chip Address0 Pin in 3-wire serial control mode.

(I2C pin =”L”)

L

7 CAD0-I2C Chip Address0 Pin in I2C bus serial control mode.

(I2C pin =”H”, PS pin =”L”)

L

8 CAD1

Chip Address1 Pin in I2C bus or 3-wire serial control mode.

(3-wire : I2C pin =”L”)

(I2C bus : I2C =”H”, PS pin ”L”)

L

Table 3-4. SW602 Setting



1 CKS0 Clock Mode Setting #0 L

2 CKS1 Clock Mode Setting #1 H

3 CKS2 Clock Mode Setting #2 H

4 CKS3 Clock Mode Setting #3 L

5 DIF0/DSDSEL0

DIF0 : Audio Data Format select in PCM Mode

L: MSB justified

H: I2S

DSDSEL0 : DSD Sampling Rate Control in DSD Mode

H

6 DIF1/DSDSEL1

DIF1 : Audio Data Format select in PCM Mode

L: 24-bit Mode

H: 32-bit Mode

DSDSEL1 : DSD Sampling Rate Control in DSD Mode

L

7 SLOW/DCKB SLOW : Slow Roll-OFF Digital Filter select in PCM Mode

DCLKB : Polarity of DCLK in DSD Mode

L

8 SD/PMOD SD : Short Delay Digital Filter select in PCM Mode

PMOD : DSD Phase Modulation Mode select in DSD Mode

L


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1 LDOE

LDO Enable

L: LDO Disable

H: LDO Enable

H

2 ODP Output Data Placement Select. L

3 TDM0 TDM Interface Format select #0 L

4 TDM1 TDM Interface Format select #1 L

5 PS

Control mode select (I2C pin =”H”)

L: I2C Bus serial control mode

H: Parallel control mode

L

6 I2C

Control mode select

L: 3-wire serial control mode

H: I2C Bus serial control mode

H

7 DP

DSD Mode Enable

L: PCM Mode

H: DSD Mode

L

8 HPFE/DCKS

HPFE : High Pass Filter Enable

L: HPF Disable

H: HPF Enable

DCKS : Master Clock Frequency select at DSD Mode (DSD only)

L: 512fs

H: 768fs

H


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Parallel Mode, ODP pin = “L” :

PW0 pin

SW602_2

PW1 pin

SW602_3

PW2 pin

SW602_4

Power ON/OFF Data on Slot

Ch4 Ch3 Ch2 Ch1 Slot 4 Slot 3 Slot 2 Slot 1

L L L OFF OFF OFF OFF All “0” All “0” All “0” All “0”

L L H ON ON OFF OFF (CH3+4)

/2

(CH3+4)

/2

All “0” or

TDMI

All “0” or

TDMI

L H L OFF OFF ON ON All “0” or

TDMI

All “0” or

TDMI

(CH1+2)

/2

(CH1+2)

/2

L H H ON ON ON ON (CH3+4)

/2

(CH3+4)

/2

(CH1+2)

/2

(CH1+2)

/2

H L L OFF ON ON ON All “0” CH3 CH2 CH1

H L H ON ON OFF OFF CH4 CH3 All “0” All “0”

H H L OFF OFF ON ON All “0” All “0” CH2 CH1

H H H ON ON ON ON CH4 CH3 CH2 CH1 default

Table 3-7-1-1. Channel Power & Mono Mode Select (ODP pin = “L”) (AK55X4)

Parallel Mode, ODP pin = “H” :

PW0 pin

SW602_2

PW1 pin

SW602_3

PW2 pin

SW602_4

Power ON/OFF Data on Slot

Ch4 Ch3 Ch2 Ch1 Slot 4 Slot 3 Slot 2 Slot 1

L L L OFF OFF OFF OFF All “0” All “0” All “0” All “0”

L L H ON ON ON ON All “0” or

TDMI

All “0” or

TDMI

(CH3+4)

/2

(CH1+2)

/2

L H L ON ON ON ON CH4 CH3 CH2 CH1

L H H ON ON ON ON

All “0”

or

TDMI

All “0”

or

TDMI

All “0”

or

TDMI

(CH1+2

+3+4)/4

H L L ON ON ON ON CH4 CH3 CH2 CH1

H L H ON ON ON ON All “0” or

TDMI

All “0” or

TDMI

(CH3+4)

/2

(CH1+2)

/2

H H L ON ON ON ON CH4 CH3 CH2 CH1

H H H ON ON ON ON All “0” or

TDMI

All “0” or

TDMI

All “0” or

TDMI

(CH1+2

+3+4)/4

Table 3-7-1-2. Channel Power & Mono Mode Select (ODP pin = “H”) (AK55X4)

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Parallel Mode, ODP pin = “L” :

PW0 pin

SW602_2

PW1 pin

SW602_3

PW2 pin

SW602_4

Power

ON/OFF Data on Slot

Ch2 Ch1 Slot 2 Slot 1

L L L OFF OFF All “0” All “0”

L L H ON OFF CH2 All “0”

L H L OFF ON All “0” CH1

L H H ON ON (CH2+1)

/2

(CH2+1)

/2

H L L OFF OFF All “0” All “0”

H L H ON OFF CH2 All “0”

H H L OFF ON All “0” CH1

H H H ON ON CH2 CH1 default

Table 3-7-2-1. Channel Power & Mono Mode Select (ODP pin = “L”) (AK55X2)

Parallel Mode, ODP pin = “H” :

PW0 pin

SW602_2

PW1 pin

SW602_3

PW2 pin

SW602_4

Power

ON/OFF Data on Slot

Ch2 Ch1 Slot 2 Slot 1

L L L OFF OFF All “0” All “0”

L L H ON ON (CH2+1)

/2

(CH2+1)

/2

L H L ON ON CH2 CH1

L H H ON ON All “0”

or TDMI

(CH2+1)

/2

H L L ON ON CH2 CH1

H L H ON ON (CH2+1)

/2

(CH2+1)

/2

H H L ON ON CH2 CH1

H H H ON ON All “0”

or TDMI

(CH2+1)

/2

Table 3-7-2-2. Channel Power & Mono Mode Select (ODP pin = “H”) (AK55X2)

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CKS3 pin

SW603-4

CKS2 pin

SW603-3

CKS1 pin

SW603-2

CKS0 pin

SW603-1

MSN pin

SW602-5

MCLK

Frequency fs Range

L(0) L(0) L(0) L(0) L(0) 128fs

24M

Quad Speed Mode

108kHz fs 216kHz

H(1)

L(0) L(0) L(0) H(1) L(0) 192fs

36M

Quad Speed Mode

108kHz fs 216kHz

H(1)

L(0) L(0) H(1) L(0) L(0) 256fs

12M

Normal Speed Mode

8kHz fs 54kHz

H(1)

L(0) L(0) H(1) H(1) L(0) 256fs

24M

Double Speed Mode

54kHz fs 108kHz

H(1)

L(0) H(1) L(0) L(0) L(0) 384fs

36M

Double Speed Mode

54kHz fs 108kHz

H(1)

L(0) H(1) L(0) H(1) L(0) 384fs

18M

Normal Speed Mode

8kHz fs 54kHz

H(1)

L(0) H(1) H(1) L(0) L(0) 512fs

24M

Normal Speed Mode

8kHz fs 54kHz

default

H(1)

L(0) H(1) H(1) H(1) L(0) 768fs

36M

Normal Speed Mode

8kHz fs 54kHz

H(1)

H(1) L(0) L(0) L(0) L(0) 64fs

24M

Oct Speed Mode

fs = 384kHz

H(1)

H(1) L(0) L(0) H(1) L(0) 32fs

24M

Hex Speed Mode

fs = 768kHz

H(1)

H(1) L(0) H(1) L(0) L(0) 96fs

36M

Oct Speed Mode

fs = 384kHz

H(1)

H(1) L(0) H(1) H(1) L(0) 48fs

36M

Hex Speed Mode

fs = 768kHz

H(1)

H(1) H(1) L(0) L(0) L(0) 64fs

49.1M

Hex Speed Mode

fs = 768kHz

H(1)

H(1) H(1) L(0) H(1) L(0) 1024fs

32M

Normal Speed Mode

8kHz ≤ fs ≤ 32kHz

H(1)

H(1) H(1) H(1) L(0) L(0)

NA NA

H(1)

H(1) H(1) H(1) H(1) L(0)

Auto 8kHz fs 216kHz

-

Table 3-8. MCLK Frequency Select (AK55X4/X2)

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DSDSEL1 pin

SW603-6

DSDSEL0 pin

SW603-5

Frequency Mode DSD Sampling Frequency

fs=32kHz fs=44.1kHz fs=48kHz

L(0) L(0) 64fs 2.048MHz 2.8224MHz 3.072MHz default

L(0) H(1) 128fs 4.096MHz 5.6448MHz 6.144MHz

H(1) L(0) 256fs 8.192MHz 11.2896MHz 12.288MHz

H(1) H(1) - Reserved

(8.192MHz)

Reserved

(11.2896MHz)

Reserved

(12.288MHz)

Table 3-9. DSD Sampling Frequency Select (AK55X4/X2)

No. Multiplex

Mode

Speed

Mode

TDM1

SW604-4

TDM0

SW604-3

MSN

SW602-5

DIF1

SW603-6

DIF0

SW603-5 SDTO

LRCK BICK MCLK

Pol. I/O Freq. I/O Freq. I/O

0

Normal

Normal

Double

Quad

L(0) L(0)

L(0)

L(0) L(0) 24-bit, MSB ↑ I 48-128fs I 128-1024fs I

1 L(0) H(1) 24-bit, I2S ↓ I 48-128fs I 128-1024fs I default

2 H(1) L(0) 32-bit, MSB ↑ I 64-128fs I 128-1024fs I

3 H(1) H(1) 32-bit, I2S ↓ I 64-128fs I 128-1024fs I

4

H(1)

L(0) L(0) 24-bit, MSB ↑ O 64fs O 128-1024fs I

5 L(0) H(1) 24-bit, I2S ↓ O 64fs O 128-1024fs I

6 H(1) L(0) 32-bit, MSB ↑ O 64fs O 128-1024fs I

7 H(1) H(1) 32-bit, I2S ↓ O 64fs O 128-1024fs I

8

OCT

HEX L(0) L(0)

L(0)

* L(0) 16-bit, MSB ↑ I 32fs I 32-96fs I

9 * H(1) 16-bit, I2S ↓ I 32fs I 32-96fs I

10 * L(0) 24-bit, MSB ↑ I 48fs I 32-96fs I

11 * H(1) 24-bit, I2S ↓ I 48fs I 32-96fs I

12 L(0) L(0) 24-bit, MSB ↑ O 64fs O 32-96fs I

13 L(0) H(1) 24-bit, I2S ↓ O 64fs O 32-96fs I

14 H(1) L(0) 32-bit, MSB ↑ O 64fs O 32-96fs I

15 H(1) H(1) 32-bit, I2S ↓ O 64fs O 32-96fs I

16

H(1)

* L(0) 16-bit, MSB ↑ I 32fs I 32fs I

17 * H(1) 16-bit, I2S ↓ I 32fs I 32fs I

18 * L(0) 24-bit, MSB ↑ I 48fs I 48fs I

19 * H(1) 24-bit, I2S ↓ I 48fs I 48fs I

20 L(0) L(0) 24-bit, MSB ↑ O 64fs O 64fs I

21 L(0) H(1) 24-bit, I2S ↓ O 64fs O 64fs I

22 H(1) L(0) 32-bit, MSB ↑ O 64fs O 64fs I

23 H(1) H(1) 32-bit, I2S ↓ O 64fs O 64fs I

Table 3-10. Audio Interface Format Select ( Normal mode, OCT/HEX mode) : PCM Mode (AK55X4/X2)

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No. Multiplex

Mode

Speed

Mode

TDM1

SW604-4

TDM0

SW604-3

MSN

SW602-5

DIF1

SW603-6

DIF0

SW603-5 SDTO

LRCK BICK MCLK

Edg. I/O Freq. I/O Freq. I/O

24

TDM128

Normal

Double

Quad

L(0) H(1)

L(0)

L(0) L(0) 24-bit, MSB I 128fs I 128-1024fs I

25 L(0) H(1) 24-bit, I2S I 128fs I 128-1024fs I

26 H(1) L(0) 32-bit, MSB I 128fs I 128-1024fs I

27 H(1) H(1) 32-bit, I2S I 128fs I 128-1024fs I

28

H(1)

L(0) L(0) 24-bit, MSB O 128fs O 128-1024fs I

29 L(0) H(1) 24-bit, I2S O 128fs O 128-1024fs I

30 H(1) L(0) 32-bit, MSB O 128fs O 128-1024fs I

31 H(1) H(1) 32-bit, I2S O 128fs O 128-1024fs I

32

TDM256 Normal

Double H(1) L(0)

L(0)


33 L(0) H(1) 24-bit, I2S I 256fs I 256-1024fs I


35 H(1) H(1) 32-bit, I2S I 256fs I 256-1024fs I

36

H(1)


37 L(0) H(1) 24-bit, I2S O 256fs O 256-1024fs I


39 H(1) H(1) 32-bit, I2S O 256fs O 256-1024fs I

40

TDM512 Normal H(1) H(1)

L(0)


41 L(0) H(1) 24-bit, I2S I 512fs I 512-1024fs I


43 H(1) H(1) 32-bit, I2S I 512fs I 512-1024fs I

44

H(1)


45 L(0) H(1) 24-bit, I2S O 512fs O 512-1024fs I


47 H(1) H(1) 32-bit, I2S O 512fs O 512-1024fs I

Table 3-11. Audio Interface Format Select ( TDM mode) : PCM Mode (AK55X4/X2)

SD

SW603-8

SLOW

SW603-7

Filter

L L Sharp Roll-off Filter default

L H Slow Roll-off Filter

H L Short Delay Sharp Roll-off Filter

H H Short Delay Slow Roll-off Filter

Table 3-12. Digital Filter Select : PCM Mode (AK55X4/X2)

LDOE

SW604-1

PDN

SW600 LDO VDD18 pin

TVDD pin

Power Supply

L L OFF External Power Supply 1.7~1.98V 1.7~1.98V

L H OFF External Power Supply 1.7~1.98V 1.7~1.98V

H L OFF Internal 500 Pull Down 3.0~3.6V

H H ON LDO Power Output 3.0~3.6V default

Table 3-13. LDO Select (AK55X4/X2)

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I2C pin

SW604-6

PS pin

SW604-5 Control Mode

L L 3-wire Serial

L H 3-wire Serial

H L I2C Bus default

H H Parallel

Table 3-14. Control Mode Select (AK55X4/X2)

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[4] Toggle switches settings

Up=”H”, Down=”L”

[SW600] ( Power Down (PDN) for AK55X4/X2):

Power Down (PDN) Switch for AK55X4/X2

Reset AK55X4/X2 (U1) once by brining SW600 to “L” once upon power-up.

Keep “H” when AK55X4/X2 is in use; keep “L” when AK55X4/X2 is not in use.

[SW601] ( Power Down (PDN) for AK4118A):

Power Down (PDN) Switch for AK4118A

Reset AK4118A (U4) once by brining SW601 to “L” once upon power-up.

Keep “H” when AK4118A is in use; keep “L” when AK4118A is not in use.

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[5] Register control (Serial control)

AKD55X4-A can be controlled printer port (parallel port).

Connect board to PC using 10-wire flat cable (PORT500 – serial uP-IF) included with the AKD55X4-A.

There is a mark on the no.1-pin of the 10-pin connector. See Figure 3..

The pin assignments of PORT below.

PORT700

uP I/F

1

2

9

10

GN

D

GN

D

GN

D

GN

D

GN

D

CS

N

CC

LK

/ S

CL

CD

TI /

SD

A

NC

NC

Figure 3. The pin assignments of PORT500

The control software is packed with the evaluation board. The software operation sequence is included in the

evaluation board manual.

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[6] Evaluation modes

(6-1) ADC Differential Analog Input Connector ( 4ch/2ch Mode )

ADC

Channel Ch1 Ch2 Ch3 Ch4

4ch J200 J201 J300 J301

2ch J200 J201 - -

Table 6-1. Differential Analog Input Connector

(6-1-1) 4ch mode

1ch: Cannon connector = J200, 2ch: Cannon connector = J201


(6-1-2) 2ch mode


(6-2) ADC Master / Slave Mode

(6-2-1) Slave Mode

SW602-5 = “L” ( MSN pin = “L” )

(6-2-2) Matser Mode

SW602-5 = “H” ( MSN pin = “H” )

(6-3) ADC PCM / DSD Mode

(6-3-1) PCM Mode

SW602-5 = “L” ( MSN pin = “L” ), SW604-7 = “L” ( DP pin = “L” )

(6-3-2) DSD Mode

SW602-5 = “H” ( MSN pin = “H” ) , SW604-7 = “H” ( DP pin = “H” )

(6-4) ADC (Analog Digital) : PCM Mode, Slave Mode

Toggle switch setting:

SW600 SW601

L→H L→H

AK55X4/X2(U1) : Used AK4118A(U4) : Used

Table 6-2. Toggle switch setting

Start up Control Register Setting

1: Port Reset & Write Default.

2: Set Addr: 02h = “13” to Data and Clock format on ADC. Other control register settings are default.

Mode settings : Normal Speed Mode, 24bit, I2S, MCLK=256fs

DIF1-0: Audio Data Interface Modes Select (Table 3-5, Table 3-10)

CKS3-0: Sampling Speed Mode and MCLK Frequency Select (Table 3-5, Table 3-8)

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Control 1

CKS3 CKS2 CKS1 CKS0 DIF1 DIF0 HPFE

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 1

Table 6-3. Addr 02H control register setting

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(6-5) ADC (Analog Digital) : PCM Mode, Master Mode


SW600 SW601

L→H L→H





2: Set Addr: 02h = “13” to Data and Clock format on ADC. Other control register settings are default.

3: Set SW602-5 =”H” (MSN pin=”H”) to Master Mode on ADC. Other switch settings are default.

Mode settings : Normal Speed Mode, 24bit, I2S, MCLK=256fs

DIF1-0: Audio Data Interface Modes Select (Table 3-5, Table 3-10)

CKS3-0: Sampling Speed Mode and MCLK Frequency Select (Table 3-5, Table 3-8)


02H Control 1

CKS3 CKS2 CKS1 CKS0 DIF1 DIF0 HPFE


Default 0 0 0 0 0 0 0 1


(6-6) ADC (Analog Digital) : DSD Mode


SW600 SW601

L→H L→H





2: Set Addr: 04h = “80” to DSD Mode on ADC. Other control register settings are default.

3: Set SW602-5 =”H” (MSN pin=”H”), SW604-7=”H” (DP pin=”H”) to DSD Mode on ADC.

Other switch settings are default.

DP: DSD Mode Select

0: PCM Mode (default)

1: DSD Mode


04H DSD1 DP

SD SLOW


Default 0 0 0 0 0 0 0 0


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Control Software Manual

Set-up evaluation board and control software

1. Set up AKD55X4-A evaluation board according to above instructions.

2. Connect PC with AKD55X4-A evaluation board by USB cable (included in package).

3. Insert the CD-ROM labeled “AKD55X4-A Evaluation Kit” into the CD-ROM drive.

4. Access the CD-ROM drive, double-click on “akd55x4-a.exe” and set up the control program.

5. Evaluate according to the following.

Operation flow

1. Set up control program as above and open control program.

The following operation screen will be shown. (Default setting)

Figure7-1-1. Control software window [AK5574]

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2. Click the “Write” button on right side of Addr 01H register.

Figure 7-2. Register set window

3. Input dummy command settings and click “OK” to write dummy command to AK55X4/X2.

The following No Ack error message will pop up. Click “OK”.

Figure 7-3. No ack message window

4. Input registers accordingly into dialog box to evaluate AK55X4/X2.

Button Functions

1. [Port Reset] : Set up USB interface board (AKDUSBIF-B).

2. [Write Default] : Initialize all register setting.

3. [All Write] : Write all registers currently displayed.

4. [All Read] : Read all register setting.

5. [Save] : Save the current register setting to .akr file.

6. [Load] : Load register setting from saved .akr file.

7. [All Reg Write] : Opens “All Register Write” dialog box. (see Dialog boxes below)

8. [Data R/W] : Opens “Data Read/Write” dialog box . (see Dialog boxes below)

9. [Read] : Read and display current register setting in register window (on right side of main window).

Different from [All Read] as it does not reflect to the register map.

10. [Close] : Close Control Software window.

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Dialog boxes

1. [All Register Write]: Dialog box to write register setting files

Clicking the [All Reg Write] button in the main window opens the dialog box below.

Multiple register setting files created by the [SAVE] button can be set and applied.

Figure 7-4. Window of [All Reg Write]

<Operation flow>

(1) Click [Open(left) Button.

(2) Select file (*.akr) and Click [Open] Button. Up to 10 files can be selected.

(3) Click [Write] to write each file. [Write ALL] writes all files selected.

Button Functions:

1. [Open (left)] : Select register setting file (*.akr).

2. [Write] : Write register setting file in textbox.

3. [Write ALL] : Write all register setting files selected. Write is executed in descending order.

4. [Help] : “Help” window pops up.

5. [Save] : Save the current register map setting (*.mar).

6. [Open (right)] : Load register map setting file (*.mar ).

7. [Close] : Close dialog box.

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2. [Data Read/Write]: Dialog box to manually enter register setting

Click the [Data R/W] button in the main window to open the data read/write dialog box.

Data manually entered into Data box is written to the specified address.

Figure 7-5. Window of [Data R/W]

Textbox Functions:

[Address] : Input register address in 2 hexadecimal digits.

[Data] : Input register data in 2 hexadecimal digits.

[Mask] : Input mask data in 2 hexadecimal digits. This value is AND-ed with input data.

Button Functions:

[Write] : Writes data generated from [Data] and [Mask] to register specified in [Address]

[Read] : Displays register data specified in [Address] in [Read Data] box in hexadedimal.

[Close] : Closes dialog box. To cancel a process close the dialog box without writing

※ Register map updated after [Write] and [Read] operation.

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Tab Functions

1. [REG]: Register Map

Register data is indicated on the register map. Each bit on the register map is a push-button switch.

Button DOWN and red lettering indicates “1” and button UP with blue lettering indicates “0”.

Buttons with “---“are undefined in the datasheet.

Figure 7-6. [REG] window (REG 00H-07H)

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2. [Tool]: Testing Tools

This tab screen is for the evaluation testing tool.

Click button for each testing tool.

Figure 7-8. [Tool] window

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Analog input Circuit

Analog input Circuit on AKD55X4-A

Cannon Connectors (J200,J201,J300,J301) : Differential analog input signals for AK55X4/X2

Analog input Circuit :

4.7k

-

+ -

+

10 3.3k

620

-

+

10

620

Analog In

14.9Vpp

68µ

NJM5534

VA=+5

V VP=15

V

4.7k

10µ

+ 10k

10k

0.1µ

Bias

VA+

2.8Vpp

2.8Vpp

VP+

VP- Bias

1n 3.3k

1n

Bias

15n

68µ

XLR

Vin-

Vin+

open

NJM5534

NJM5534

AK55X4/X2 AINn+

AK55X4/X2 AINn-

100p

100p

open

3

2

1

Figure 8-1. Analog Input Circuit

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Measurement Results

[Measurement condition]

・ Measurement unit : Audio Precision, SYS-2722(00069)

・ MCKI : 512fs/256fs/128fs (24.576MHz )

・ BICK : 64fs

・ fs : 48kHz / 96kHz / 192kHz

・ Bit : 24bit

・ Measurement Mode : ADC @ Slave Mode

・ Power Supply : VOP+(15V)=15V, GND

AVDD=3.3V (Regulator), DVDD=3.3V (Regulator)

・ Input Frequency : 1kHz

・ Measurement Frequency : 20 ~ 20kHz @48kHz / 20～40kHz @96kHz / 20～80kHz @192kHz

・ Temperature : Room

[Measurement Results]

1. Stereo ADC （Differential Inputs）

Result

Unit SDTO1 SDTO2

Lch Rch Lch Rch

Stereo ADC : AINL/R => ADC => SDTO1/2

S/(N+D)

fs = 48kHz (-1dBFS) 105.6 107.0 107.3 107.9 dB

fs = 96kHz (-1dBFS) 101.2 102.6 103.1 104.3 dB

fs = 192kHz (-1dBFS) 104.5 103.1 103.5 103.6 dB

DR fs = 48kHz (-60dBFS, A-Weighted) 113.5 113.3 113.1 113.1 dB

S/N fs = 48kHz (A-weighted) 113.6 113.4 113.3 113.1 dB

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[Plots] [ SDTO1 ] : Stereo Mode

fs = 48 kHz

AK5534 FFT (-1dBFS Input)

AVDD=3.3V, DVDD=3.3V, MCLK=512fs, fin=1kHz

Figure 9-1. FFT (-1dBFS Input)

AK5534 FFT ( -60dBFS Input)



20 20k 50 100 200 500 1k 2k 5k 10k

Hz

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

20 20k 50 100 200 500 1k 2k 5k 10k

Hz

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

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fs = 48 kHz

AK5534 FFT ( No Signal Input)


Figure 9-3. FFT (No Signal Input)

AK5534 THD+N vs. Input Level


Figure 9-4. THD+N vs. Input Level

20 20k 50 100 200 500 1k 2k 5k 10k

Hz

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

-140 +0 -120 -100 -80 -60 -40 -20

dBr

-150

-70

-140

-130

-120

-110

-100

-90

-80

d

B

F

S

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fs = 48 kHz

AK5534 THD+N vs. Input Frequency

AVDD=3.3V, DVDD=3.3V, MCLK=512fs, -1dBFS Input

Figure 9-5. THD+N vs. Input Frequency

AK5534 Linearity


Figure 9-6. Linearity

20 20k 50 100 200 500 1k 2k 5k 10k

Hz

-150

-70

-140

-130

-120

-110

-100

-90

-80

d

B

F

S

-160 +0 -140 -120 -100 -80 -60 -40 -20

dBr

-160

+0

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

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fs = 48 kHz

AK5534 Frequency Response

AVDD=3.3V, DVDD=3.3V, MCLK=512fs, -1dBFS input

Figure 9-7. Frequency Response

20 20k 50 100 200 500 1k 2k 5k 10k

Hz

-2

+0

-1.8

-1.6

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

d

B

F

S

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fs = 96 kHz







20 40k 50 100 200 500 1k 2k 5k 10k 20k

Hz

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

20 40k 50 100 200 500 1k 2k 5k 10k 20k

Hz

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

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fs =96 kHz







20 40k 50 100 200 500 1k 2k 5k 10k 20k

Hz

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

-140 +0 -120 -100 -80 -60 -40 -20

dBr

-150

-70

-140

-130

-120

-110

-100

-90

-80

d

B

F

S

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fs = 96 kHz




AK5534 Linearity



20 40k 50 100 200 500 1k 2k 5k 10k 20k

Hz

-150

-70

-140

-130

-120

-110

-100

-90

-80

d

B

F

S

-160 +0 -140 -120 -100 -80 -60 -40 -20

dBr

-160

+0

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

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fs = 96 kHz




20 40k 50 100 200 500 1k 2k 5k 10k 20k

Hz

-2

+0

-1.8

-1.6

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

d

B

F

S

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fs = 192 kHz







20 80k 50 100 200 500 1k 2k 5k 10k 20k 50k

Hz

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

20 80k 50 100 200 500 1k 2k 5k 10k 20k 50k

Hz

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

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fs =192 kHz







20 80k 50 100 200 500 1k 2k 5k 10k 20k 50k

Hz

-180

+0

-160

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

-140 +0 -120 -100 -80 -60 -40 -20

dBr

-150

-70

-140

-130

-120

-110

-100

-90

-80

d

B

F

S

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fs = 192 kHz



9


AK5534 Linearity



20 80k 50 100 200 500 1k 2k 5k 10k 20k 50k

Hz

-150

-70

-140

-130

-120

-110

-100

-90

-80

d

B

F

S

-160 +0 -140 -120 -100 -80 -60 -40 -20

dBr

-160

+0

-140

-120

-100

-80

-60

-40

-20

d

B

F

S

T

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fs = 192 kHz




20 80k 50 100 200 500 1k 2k 5k 10k 20k 50k

Hz

-2

+0

-1.8

-1.6

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

d

B

F

S

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REVISION HISTORY

Date

(YY/MM/DD)

Manual

Revision

Board

Revision

Reason Page Contents

15/02/20 KM119200 0 First edition -

15/07/10 KM119201 1 Change - Add Measurement Results

15/09/10 KM119202 2 Change - Device Revision Up

16/05/23 KM119203 3 Change - Update Measurement Results

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IMPORTANT NOTICE

0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information

contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products.

1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.

2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing.

3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption.

4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.

5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations.

6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM.

7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM.

- 47-

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

TE

ST

1

MC

LK

TV

DD

DV

SS

VD

D18

PD

N

PW

0

PW

1

PW

2

MS

N

SD/PMOD

SLOW/DCKB

CKS3/CAD1

CKS2/SCL/CCLK

CKS1/CAD0-I2C/CSN

CKS0/SDA/CDTI

OVF

SDTO2/DSDOR2

SDTO1/DSDOL2

TDMIN/DSDOR1

LRCK/DSDOL1

BICK/DCLK

TE

ST

2

LO

DE

DC

KS

/HP

FE

DP

I2C

PS

/CA

D0-S

P1

OV

FR

ST

/TD

M1

OV

FF

UN

C/T

DM

0

DIF

1/D

SD

SE

L1

DIF

0/D

SD

SE

L0

AIN

1N

VREFL1

VREFH1

AIN2N

AIN2P

AIN

1P

VREFH2

VREFL2

AVSS

AIN

4N

AIN3N

AIN3P

AVDD

AIN

4P

C114 : Cap Dip open + 1pin Socket (PDN Cap)

C109 : Cap Dip open + 1pin Socket (MCLK Cap)

VSS

VSS

VSS

VSS

VSS

VSS VSS

VSS

VSS

VSS

AVDD1

AVDD1

AVDD1

TV

DD

1

VD

D18

PD

N1

PW

0

PW

1

PW

2

MS

N

BICK/DCLK

AIN3-P0

AIN3-N0

LRCK/DSDOL1

TDMIN/DSDOR1

SDTO2/DSDOR2

SDTO1/DSDOL2

OVF

CKS0/SDA/CDTI

CKS1/CAD0-I2C/CSN

CKS2/SCL/CCLK

CKS3/CAD1

SLOW/DCKB

SD/PMOD

DIF

0/D

SD

SE

L0

DIF

1/D

SD

SE

L1

TD

M0/O

VF

FU

NC

TD

M1/O

VF

RS

T

PS

/CA

D0-S

PI

I2C

DP

HP

FE

/DC

KS

LD

OE

TE

ST

2

AIN

1-P

0

AIN

1-N

0

TE

ST

1

MC

LK

AIN2-N0

AIN2-P0

AIN

4-P

0

AIN

4-N

0

Title

Size Document Number Rev

Date: Sheet of

<AK5534> <0>

<AKD5534-B>

A2

1 8Friday, February 20, 2015

Title


Date: Sheet of

<AK5534> <0>

<AKD5534-B>

A2


Title


Date: Sheet of

<AK5534> <0>

<AKD5534-B>

A2


TP

114

R112

(short

)

R143

0

R102(open)

TP132

TP104

R141

0

TP102

R151 (open)

TP

144

R103 (short)

R113

(short

)

TP109

+C106100u

R135 0

C114

(open)

TP

134

TP

138

R139

0

TP

120

R100 (short)

R109 22

R133 51

R118

(open)

TP131

R137

0

TP107

+C10310u

R131 51

C113

0.1

u

R107 (short)

+C

110

10u

TP

143

TP

113

R101 22

C1070.1u

TP

112

R129 51

R106(open)

TP

137

TP

119

TP105

R147

(short

)

TP

117

TP106

R119

0

R105 (short)

R111(open)

R127 51

TP130

TP

142

R146

0

R121

0

R120

0

R125 51

R123

0

TP

118

TP100

R144

0

TP108

TP103

R150 (short)

TP

136

VREFL12

VREFH13

AIN2N4

AIN2P5

NC1

AVDD6

AVSS7

NC12

AIN3P8

AIN3N9

VREFH210

VREFL211

AIN

4N

13

AIN

4P

14

TE

ST

11

5

MC

LK

16

TV

DD

17

DV

SS

18

VD

D1

81

9

PD

N2

0

PW

02

1

PW

12

2

PW

22

3

MS

N2

4

BICK/DCLK25

LRCK/DSDOL126

TDMIN/DSDOR127

SDTO1/DSDOL228

SDTO2/DSDOR229

OVF30

CKS0/SDA/CDTI31

CKS1/CAD0_I2C/CSN32

CKS2/SCL/CCLK33

CKS3/CAD134

SLOW/DCKB35

SD/PMOD36

DIF

0/D

SD

SE

L0

37

DIF

1/D

SD

SE

L1

38

OV

FF

UN

C/T

DM

03

9

OV

FR

ST

/TD

M1

40

PS

/CA

D0

_S

P1

41

I2C

42

DP

43

DC

KS

/HP

FE

44

AIN

1N

48

AIN

1P

47

TE

ST

24

6

LD

OE

45

TP129

C108

0.0

15u

R154 (open)

R155

(open)

TP

116

R142

0

R116

0

TP126

R104 (short)

TP125

R136 0

TP

141

TP123

R140

0

C1020.015u

TP

135

R110 (short)

R134 0

R138

0

C111

0.1

u

R114

0

TP124

TP128

R132 51

+

C112

4.7

u

R108 (short)

R117

(open)

+C100100u

TP

110

R153 (open)

TP

140

R130 0

TP122

C1050.015u

C109

open

C1010.1u

TP133

R156

(open)

R152 (open)R128 51

TP

115

R148

(short

)

C115

0.0

15u

R122

0

TP127

C1040.1u

TP

145

R126 51

R145

0

TP

111

TP

139

TP101

TP

121

R124

0

- 48-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AIN1P

AIN1N

AIN2N

AIN2P

BIAS11

BIAS21

BIAS11

BIAS11

BIAS21

BIAS21

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VBIAS

AIN1-P0

AIN1-N0

VOP+

VOP-

VOP-

VOP-

VOP-

VOP-

VBIAS

AIN2-P0

AIN2-N0

VOP+

VOP-

Title


Date: Sheet ofAnalog Input AIN1 & AIN2

<0>

<AKD5534-B>A3


Title



<0>

<AKD5534-B>A3


Title



<0>

<AKD5534-B>A3


R231 4.7k

C217

100p

+

C205100u

R219 620

C237

100p

+C216

10u

U204

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

C2010.01u

C251100p

+C228

10u

C215

0.01u

R209 0

R213 4.7k

+

C20047u

+

C22247u

R204 3.3k

C232

0.01u

+

C225100u

R216 3.3k

+C235

10u

J200AIN1(x4)/AIN1(x2)

22

33

11

R207 10

R215

10k

R217 3.3k

R230 4.7k

R221 10

R220 10

+

C20347u

R240 open

R208 10

J202AIN-1

C234

0.01u

C236

100p

U200

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

C2111n

C218

100p

R214

10k

U205

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

R241 open

+C214

10u

J203AIN-2

R242 open

R218 620

R203 3.3k

C227

0.01u

C2400.01u

C253100p

C2410.01u

R245 open

+

C22310u

C2301n

+

C21947u

+C209

10u

C210

0.01u

U202

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

+

C224100u

U201

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

C2200.01u

R247 open

R200 4.7k

R224 0

C2020.01u

R243 open

R202

10k

+C233

10u

+C207

10u

C229

0.01u

U203

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

C250100p

R205 620

C2121n

R206 620

R210 0

R201

10k

R244 open

C252100pC221

0.01u

+

C20410u

R222 0

C208

0.01u

C213

0.01u

J201AIN2(x4)/AIN2(x2)

22

33

11

+C226

10u

C2311n

+

C206100u

R246 open

- 49-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AIN3P

AIN3N

AIN4N

AIN4P

BIAS31

BIAS41

BIAS31

BIAS31

BIAS41

BIAS41

VSS

VSS

VSSVSS

VSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VBIAS

AIN3-P0

AIN3-N0

VOP+

VOP-

VOP-

VOP-

VOP-

VOP-

VBIAS

AIN4-P0

AIN4-N0

VOP+

VOP-

Title



<0>

<AKD5534-B>A3


Title



<0>

<AKD5534-B>A3


Title



<0>

<AKD5534-B>A3


R344 open

R300 4.7k

R341 open

R304 3.3k

+C335

10u

C3111n

R347 openR343 open

R313 4.7k

C3010.01u

C3311n

J302AIN-3

C3301n

C3210.01u

R330 4.7k

C310

0.01u

R305 620

C317

100p

R310 0

C308

0.01u

+

C30347u

C3410.01u

J300AIN3(x4)/non(x2)

22

33

11

R303 3.3k

+

C30047u

R346 open

C329

0.01u

+

C325100u

R324 0

+C314

10u

C315

0.01u

C337

100p

C318

100p

R302

10k

+

C31947u

C351100p

+

C306100u

C334

0.01u

+

C305100u

+

C30410u

R321 10

+

C324100u

U302

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

C3400.01u

C3121nR301

10k

R307 10

U303

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

C313

0.01u

+C333

10u

R340 open

R342 open

C3200.01u

C327

0.01u

+

C32247u

C350100p

R316 3.3k

U301

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

C3020.01u

J303AIN-4

U300

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

R309 0

C336

100p

+C316

10u

R314

10k

U305

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

+C326

10u

R308 10

+

C32310u

R345 open

+C309

10u

+C328

10u

U304

NJM5534

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

R331 4.7k

C352100p

R317 3.3k

R319 620

R322 0R320 10J301AIN4(x4)/non(x2)

22

33

11

C353100p

R306 620

R318 620

R315

10k

+C307

10u

C332

0.01u

- 50-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

OC

KS

0H

L

DIF

2D

IF1

DIF

0O

CK

S1

X400 Frequency Check -> 12.288MHz+ 1pin Socket (AK4118 Xtal)

OPT

COAX

EXT

XTL

DAUX-4118A-T

MCLK-4118A-T

BICK-4118A-T

LRCK-4118A-T

VSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSS

OCKS0-T

OCKS0-TOCKS1-T

LRCK-4118A-T

MCLK-4118A-T

D33V

D33V

D33V

OCKS1-T

D33V

D33V

PDN20

DAUX-4118A-T

BICK-4118A-T

EXT-MCLK-T

Title


Date: Sheet of

<AK4118A-DIT> <0>

<AKD5534-B>

A3


Title


Date: Sheet of

<AK4118A-DIT> <0>

<AKD5534-B>

A3


Title


Date: Sheet of

<AK4118A-DIT> <0>

<AKD5534-B>

A3


+

C40510u

SW400

1 2 3 4 5

10

9 8 7 6

TP400TX-OPT

+

C401 10u

C4040.01u

R4

05

47

k

R406240

C408 5p

C409 5p

JP400

TXDATA-SEL

R4

04

47

k

C4100.01u

C402 0.01u

+

C40710u

J400TX-COAX

12345

C4030.47u

PORT400TX-OPT

GND1

VCC2IN3

T400DA-02F

JP401

EXTMCLK-SEL

C4000.01u

C4060.01u

U4

IPS0/RX41

NC2

DIF0/RX53

TEST24

DIF1/RX65

VSS16

DIF2/RX77

IPS1/IIC8

P/SN9

XTL010

XTL111

TV

DD

13

NC

/GP

11

4

TX

0/G

P2

15

TX

1/G

P3

16

BO

UT

/GP

41

7

CO

UT

/GP

51

8

UO

UT

/GP

61

9

VO

UT

/GP

72

0

DV

DD

21

VS

S2

22

MC

KO

12

3

BICK26

MCKO227

DAUX28

XTO29

XTI30

PDN31

CM0/CDTO/CAD132

CM1/CDTI/SDA33

OCKS1/CCLK/SCL34

OCKS0/CSN/CAD035

INT036

AV

DD

38

R3

9

VC

OM

40

VS

S3

41

RX

04

2

NC

43

RX

14

4

TE

ST

14

5

RX

24

6

VS

S4

47

RX

34

8

VIN/GP012

LR

CK

24

SDTO25

INT

13

7

R4

01

47

k

X40012.288MHz

12

R4

02

47

k

R400 10k

R4

03

47

k

R407150

- 51-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SDA/CDTI

SCL/CCLK

CSNCSNCCLK/SCLCDTI/SDA

CS

NS

CL

/CC

LK

SD

A/C

DT

I

SCL/CCLK

SDA/CDTI

CSN

SDA/CDTI-10PINSCL/CCLK-10PINCSN-10PIN

VSS

VSS

VSS

TVDD1

SCL/CCLK

SDA/CDTI

TVDD1

CSN

D33V

Title


Date: Sheet of

<PC-IF> <0>

<AKD5534-B>

A3


Title


Date: Sheet of

<PC-IF> <0>

<AKD5534-B>

A3


Title


Date: Sheet of

<PC-IF> <0>

<AKD5534-B>

A3


R510

10k

R5

02

10

k

C500 0.01u

R5

11

10

k

R506

100k

R505470

C501 0.01u

R504470

U500PCA9306DP1

GND1

VREF12

SCL13

SDA14

EN8

VREF27

SCL26

SDA25

R5

00

10

k

C5110.01u

R503470

PORT500

10pin-CTRL

1357910

8642

R509

10k

R512

10k

R507

100k

R5

01

10

k

U501PCA9306DP1

GND1

VREF12

SCL13

SDA14

EN8

VREF27

SCL26

SDA25

R508

10k

C5130.01u

- 52-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HL HL

THR

INV

DIT

PORT

GND

DIT

PORT

GND

SDTO-SELDIT

PORT

DIT

PORT

EXT

GND

MS

N

H

L

TE

ST

1P

W0

PW

1P

W2

CA

D0

-SP

IC

AD

0-I

2C

CA

D1

DIF

0/D

SD

SE

L0

H

L

CK

S0

CK

S1

CK

S2

CK

S3

DIF

1/D

SD

SE

L1

SL

OW

/DC

KB

SD

/PM

OD

PS

LD

OE

TE

ST

2T

DM

0T

DM

1

I2C

DP

HP

FE

/DC

KS

SDTO1

SDTO2

TDMIN

SDTO1

SDTO2

LRCK

BICK

MCLK

DCLK

DSDOL1

DSDOR1

DSDOL2

DSDOR2

CLKIN1 IN1/2

IN1/4

IN1/8

IN1/16

IN1/32

IN1/64

IN1/128

IN1/256

IN1/512

IN1/1024

IN1/2048

IN1/4096

IN2/256

IN2/512

IN2/1024

IN2/2048

IN2/4096

CLKIN2 IN2/2

IN2/4

IN2/8

IN2/16

IN2/32

IN2/64

IN2/128

BICK-T-THRBICK-T-INV

BICK-T-INVBICK-T-THR

PORT800-BICK

PORT800-LRCK

PORT801-SDTO1

PORT801-SDTO2

PORT801-TDMIN

PORT800-MCLK

PORT802-DSDOL1

PORT802-DSDOR1

PORT802-DSDOL2

PORT802-DSDOR2

PORT802-DCLK

MSN

PW1PW2

PW0TEST1

CAD0-SPICAD0-I2CCAD1

DIF0/DSDSEL0

CKS2CKS3

CKS1CKS0

DIF1/DSDSEL1SLOW/DCKBSD/PMOD

PS

TDM0TDM1

TEST2LDOE

I2CDPHPFE/DCKS

SW600-PDNSW600-PDN SW601-PDN

SW601-PDN

PORT801-TDMIN

PORT801-SDTO1PORT801-SDTO2

PORT800-BICKPORT800-LRCK

PORT800-MCLK

PORT802-DCLKPORT802-DSDOL1PORT802-DSDOR1PORT802-DSDOL2PORT802-DSDOR2

VSS

VSSVSS

VSS

VSS

VSS

VSS VSSVSS

VSS VSS

VSS

VSS

VSS

VSS

VSS

VSS VSS

D33VD33V

PDN10

OVF-1

D33V

BICK-4118A-TBICK-T1

LRCK-T1

SDTO1-T1SDTO2-T1

MCLK-T1

TDMIN-T1

DSDOL1-T1

DSDOR1-T1

DSDOL2-T1

DSDOR2-T1

DCLK-T1

LRCK-4118A-T

DAUX-4118A-T

MCLK-4118A-T

CAD0-I2CCAD0-SPIMSNPW2PW1PW0TEST1

TVDD1

CAD1SLOW/DCKBDIF1/DSDSEL1DIF0/DSDSEL0CKS3CKS2CKS1CKS0

TVDD1

SD/PMOD

DPI2CPSTDM1/OVFRSTTDM0/OVFFUNCTEST2LDOE

TVDD1

HPFE/DCKS

PDN20

EXT-MCLK-T

D33V D33V

Title


Date: Sheet of

<LOGIC1> <0>

<AKD5534-B>

A3


Title


Date: Sheet of

<LOGIC1> <0>

<AKD5534-B>

A3


Title


Date: Sheet of

<LOGIC1> <0>

<AKD5534-B>

A3


R6

37

47

k

R6

26

47

k

R6

20

47

k

LE600 OVF2 1

C604

0.01u

PORT600

PCM-PORT1

R6

34

47

kR

61

84

7k

R604 0

R611 0

R601 0

R617 1k

J600EXT-T

12345

U601

74HC4040

CLK10

RST11

Q19

Q27

Q36

Q45

Q53

Q62

Q74

Q813

Q912

Q1014

Q1115

Q121VD

16

DGND8

PORT605

BICK-SEL

SW602

SW DIP-8

1 2 3 4 5 6 7 8

16

15

14

13

12

11

10

9

SW603

SW DIP-8

1 2 3 4 5 6 7 8

16

15

14

13

12

11

10

9

R64351

U600

74HC14

GND7

1A1

3A5 5A

11

5Y10

3Y6

1Y2

2Y4

4Y8

6Y126A13

4A9

2A3

VCC14

J601EXT-T

12345

PORT610MCLK-SEL

SW604

SW DIP-8

1 2 3 4 5 6 7 8

16

15

14

13

12

11

10

9

R6

33

47

k

PORT614CLK2-SEL

PORT613CLK1-SEL

C6010.01u

JP602EXT-T

R600 0

R6

38

47

k

R6

32

47

k

U602

74HC4040

CLK10

RST11

Q19

Q27

Q36

Q45

Q53

Q62

Q74

Q813

Q912

Q1014

Q1115

Q121VD

16

DGND8

R6

29

47

k

R6

22

47

k

C603

0.01u

PORT606

LRCK-SEL

C6020.01u

R6

39

47

k

R61451

R6

36

47

k

R6

27

47

k

PORT612USER-CLK2

R642 0

R6

23

47

k

C6000.01u

SW600PDN1 2

13

R608 0

R6

35

47

k

JP600EXT-T

R6

21

47

k

R6

19

47

k

R609 0

R610 0

R605 0

R612 0

R603 0

PORT601TDMIN-PORT

R607 0

PORT607BICK-PHASE

R61610k

PORT609TDMIN-SEL

D600HSU119

KA

JP601EXT-T

SW601PDN2-T 2

13

R64451

D601HSU119

KA

R61510k

R6

30

47

k

PORT611USER-CLK1

R6

25

47

k

J602EXT-T

12345

R602 0

PORT608SDTO-SEL

R6

41

47

k

R6

31

47

k

R6

40

47

k

R6

28

47

k

R6

24

47

k

R613 0

PORT602

DSD-PORT1

R606 0

- 53-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TVDD -> D33V

D33V -> TVDD

TVDD -> D33V

D33V -> TVDD

for U707 74VCX14

SDA/CDTI

CKS0

CAD0-I2C/CSN

CKS1

SCL/CCLK

CKS2

TVDD -> D33V

U705 (Buffer)10pin=VSS20pin=D33V

for U705 74VCX541

D33V -> TVDD

TVDD -> D33V

CAD0-I2C

CSN

CAD1

CKS3

CAD0-SPI

PS

U708 (NAND)7pin=VSS14pin=D33V

for U708 74VCX00

U707 (INV)7pin=VSS14pin=D33V

BICK/DCLKLRCK/DSDOL1

CKS0

SDA/CDTI

CKS1

CAD0-I2C/CSN

CKS2

SCL/CCLK

MSN01DP01-P

MSN01-PDP01-NMSN01-N

SDTO2/DSDOR2SDTO1/DSDOL2

SDTO1/DSDOL2SDTO2/DSDOR2

TDMIN/DSDOR1LRCK/DSDOL1

DP01-NDP01-N

TDMIN/DSDOR1

DP01

CAD0-I2C

CSN

CKS3

CAD1

PS

CAD0-SPI

BICK/DCLK

MSN01-NDP01-NMSN01-PDP01-N

MSN-DP-PP

MSN-DP-NP

DP01-P

DP01-P

MSN-DP-PP

MSN-DP-NP

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

BICK-T1

LRCK-T1

SDTO1-T1

MCLKMCLK-T1

D33VCKS1/CAD0-I2C/CSN

CKS2/SCL/CCLK

SDTO2-T1

DSDOR1-T1DSDOL2-T1DSDOR2-T1

DSDOL1-T1

D33V

TDMIN-T1

DPMSN CKS0/SDA/CDTI

CKS3/CAD1

PS/CAD0-SPI

SDTO1/DSDOL2SDTO2/DSDOR2

LRCK/DSDOL1BICK/DCLK

TDMIN/DSDOR1

CKS0

SDA/CDTI

CKS1CAD0-I2C

CSN

CKS2

SCL/CCLK

CKS3

CAD1

PS

CAD0-SPI

LRCK/DSDOL1TDMIN/DSDOR1SDTO1/DSDOL2SDTO2/DSDOR2

OVF OVF-1

BICK/DCLKDCLK-T1PDN10 PDN1

D33V

TVDD1

D33V

TVDD1

D33V

TVDD1

D33V

Title


Date: Sheet of

<LOGIC2> <0>

<AKD5534-B>

A3


Title


Date: Sheet of

<LOGIC2> <0>

<AKD5534-B>

A3


Title


Date: Sheet of

<LOGIC2> <0>

<AKD5534-B>

A3


JP703 PS-SEL4

R700 51

R718 0

R729 51

R708 51

R711 51

R720 0

R706 0

C7030.01u

U710

NFL21SP706

IN1

OUT3

GND2

C7080.01u

R744 0

U707

74VCX14

1A1

2A3

3A5

4A9

5A11

6A13

1Y2

2Y4

3Y6

4Y8

5Y10

6Y12

R707 0

R709 0

R715 51

R741 0JP700 PS-SEL1

U706

74VCX125

A12

A25

A39

A412

1OE1

2OE4

Y13

Y26

Y38

Y411

3OE10

4OE13

VCC14

GND7

U708

74VCX00

1A1

1B2

2A4

2B5

3A9

3B10

1Y3

2Y6

3Y8

4Y11

4A12

4B13

R737 0

R723 0

R704 51

R714 51

C7000.01u

R740 51

R746 0

0

R716 0

U705

74VCX541

A12

A23

A34

A45

A56

A67

A78

A89

G11

G219

Y118

Y217

Y316

Y415

Y514

Y613

Y712

Y811

R752 (open)

U704

74VCX125

A12

A25

A39

A412

1OE1

2OE4

Y13

Y26

Y38

Y411

3OE10

4OE13

VCC14

GND7

C7060.01u

C7050.01u

R731 0

R722 0

R705 51

C7010.01u

U703

74VCX125

A12

A25

A39

A412

1OE1

2OE4

Y13

Y26

Y38

Y411

3OE10

4OE13

VCC14

GND7

R735 0

U701

74VCX125

A12

A25

A39

A412

1OE1

2OE4

Y13

Y26

Y38

Y411

3OE10

4OE13

VCC14

GND7

R702 0

JP705 PS-SEL6

R710 0

R751 (open)

C7070.01u

R727 51

R719 0

C7040.01u

R717 0

JP701 PS-SEL2

R742 51

R726 51

R713 0

U700

74VCX125

A12

A25

A39

A412

1OE1

2OE4

Y13

Y26

Y38

Y411

3OE10

4OE13

VCC14

GND7

R739 0

C7020.01u

JP704 PS-SEL5

R701 51

R728 51

R724 0

R745 0

R721 0

U702

74VCX125

A12

A25

A39

A412

1OE1

2OE4

Y13

Y26

Y38

Y411

3OE10

4OE13

VCC14

GND7

R733 0

R712 51

R750 (open)

R732 0

U709

NFL21SP706

IN1

OUT3

GND2

R747 0

R730 0

R736 0

R738 0R743 51

R703 0

R725 51

JP702 PS-SEL3

R734 0

- 54-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+5V-->+3.3V

+5V-->+1.8V

+5V-->+3.3V

3.3V

1.8V

+15V-->+5V

+15V-->+3.3V

JACK

REG

JACK

REG

JACK

REGVCC2

VCC2

VCC1

VCC1

+15V

-15V

+15V

-15V

+15V

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS

VSS

TVDD1

D33V

VDD18

VBIAS

AVDD1

VOP+

VOP-

Title


Date: Sheet of

<Power Supply> <0>

<AKD5534-B>

A3


Title


Date: Sheet of

<Power Supply> <0>

<AKD5534-B>

A3


Title


Date: Sheet of

<Power Supply> <0>

<AKD5534-B>

A3


R806 0

+C822

47u

JP800TVDD-VSEL

+C826

47u

JP802VDD18-SEL

+C809

47u

T3 LT1963AEST-3.3

IN1

GN

D2

OUT3

J804AVDD

1

R811 0

C8020.01u

L801 01 2

+C814

47u

L800 01 2

+C818

47u

R800 0

R804 0

R805 0

C8210.01u

JP803D33V-SEL

+C80347u

+C804

47u

J802

VSS

J806TVDD

1

T4 LT1963AEST-1.8

IN1

GN

D2

OUT3

+C80847u

J805VBIAS

1

R810 open

R807 0

+C80047u

TP800TVDD

R801 0

J800

+15V

+C824

47u

R812 open

C8110.01u

C815

0.01u

R802 0

J809VCC

1

C810

0.01u

T5 LT1963AEST-3.3

IN1

GN

D2

OUT3

C8160.01u

+C823

47u

C820

0.01u

+C812

47u

C8070.01u

TP802D33V

J808D3.3V

1

T2NJM78M05FA

OUT

GN

DIN

C8060.01u

TP801VDD18

JP801TVDD-SEL

R808 open

+C825

47u

J801

-15V

+C813

47u

+C817

47u

R803 0

+C819

47u

R809 0

T1BA033CC0T

OUT

GN

DIN

+C80547u

C8010.01u

J807VDD18

1

- 55-

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