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BASIC DVD MECHANISM : LDM-H109DVD PLAYER

XD-DV290

S/M Code No. 09-99C-337-5R2

K(B),EZ(B)

SERVICE MANUAL

R E V I S I O

N

D A T A

This Service Manual is the Revision Publishing and replaces Simple ManualK:(S/M Code No.09-99C-337-5T2)EZ:(S/M Code No.09-99C-337-5T3).

(6721R-0300A)

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2

TABLE OF CONTENTS

SPECIFICATIONS .................................................................................................................................. 3

ACCESSORIES/PACKAGE LIST ........................................................................................................... 3

PROTECTION OF EYES FROM LASER BEAM DURING SERVICING/

Precaution to replace Optical block......................................................................................................... 4

DISASSEMBLY INSTRUCTIONS...................................................................................................... 5-10

ELECTRICAL MAIN PARTS LIST ........................................................................................................ 11

TRANSISTOR ILLUSTRATION ............................................................................................................ 12

BLOCK DIAGRAM-1 (OVERALL) ......................................................................................................... 13

BLOCK DIAGRAM-2 (POWER) ............................................................................................................ 14

BLOCK DIAGRAM-3 (RF/DSP/SERVO)............................................................................................... 15

BLOCK DIAGRAM-4 (AUDIO) .............................................................................................................. 16

BLOCK DIAGRAM-5 (MPEG) ............................................................................................................... 17

BLOCK DIAGRAM-6 (SYSTEM CONTROL) ........................................................................................ 18

WIRING-1 (MAIN: COMPONENT SIDE) ........................................................................................ 19, 20

WIRING-2 (MAIN: CONDUCTOR SIDE) ........................................................................................ 21, 22

SCHEMATIC DIAGRAM-1 (MAIN 1/5) ............................................................................................ 23, 24





SCHEMATIC DIAGRAM-6 (JACK) ................................................................................................. 33, 34

WIRING-3 (JUNCTION/JACK) ........................................................................................................ 35, 36

SCHEMATIC DIAGRAM-7 (JUNCTION) ........................................................................................ 37, 38

WIRING-4 (TIMER/KEY/POWER) .................................................................................................. 39, 40

SCHEMATIC DIAGRAM-8 (TIMER/KEY) ....................................................................................... 41, 42

SCHEMATIC DIAGRAM-9 (POWER) ............................................................................................. 43, 44

WAVE FORM ................................................................................................................................... 45-47

TROUBLE-SHOOTING .................................................................................................................... 48-57

LCD DISPLAY ....................................................................................................................................... 58

IC DESCRIPTION ............................................................................................................................ 59-77

IC BLOCK DIAGRAM....................................................................................................................... 78-80

MECHANICAL EXPLODED VIEW 1/1 .................................................................................................. 81

MECHANICAL PARTS LIST 1/1 ........................................................................................................... 82

MECHANISM EXPLODED VIEW 1/1 ............................................................................................. 83, 84

MECHANISM PARTS LIST 1/1 ............................................................................................................. 85

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3

SPECIFICATIONS

DVD VIDEO PLAYERPower supply 100V~240V, 50HzPower consumption 20 WMass 3.5kg(7.7lbs)External dimensions 430 * 91 * 293 (W * H * D)Signal system NTSCLaser SSemiconductor laser, wavelength 655nm (DVD) /795nm (CD)Frequency range (digital audio) 2Hz to 44kHzSignal-to-noise ratio (digital audio) More than 105dB (EIAJ)

Audio dynamic range (digital audio) More than 95dB (EIAJ)Harmonic distortion(digital audio) 0.003%Wow and flutter Below measurable level (less than +0.001% (W.PEAK) (EIAJ)Operating conditions Temperature : 5C(41F) to 35C(95F),

Operation status : Horizontal

OUTPUTSVideo outputs 1.0V (p-p), 75 , negative sync., RCA jack x 1S video outputs (Y) 1.0V (p-p), 75 , negative sync., Mini DIN 4-pin * 1

(C) 0.286V (p-p), 75 Component video output (Y) 1.0V (p-p), 75 ,negative sync., RCA jack * 1

(Pb)/(Pr) 0.7V (p-p), 75 Audio output (digital audio) 0.5V(p-p), 75 , RCA jack * 1Audio output (optical audio) Optical connector * 1Audio output (analog audio) 2.0Vrms (1kHz, 0dB), 330 , RCA jack (L, R) * 2

Design and specifications are subject to change without notice. Weight and dimensions shown are approximate.

REF. NO PART NO. KANRI DESCRIPTIONNO.

ACCESSORIES/PACKAGE LIST

1 S8-35R-S00-09G INSTRUCTION ASSY 2 S8-615-20G-000 DVD-2520N CABLE ASSY 3 S7-11R-2N0-13A REMOTE CONTROLLER A 4 S5-640-17B-000 PLUG ASSY PHONE CORD 1WAY 5 S5-640-18B-000 PLUG ASSY PHONO CORD

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4

PROTECTION OF EYES FROM LASER BEAM DURING SERVICING

VAROITUS!Laiteen Kyttminen muulla kuin tss kyttohjeessa mainit-ulla tavalla saattaa altistaa kyt-tjn turvallisuusluokan 1 ylit-tvlle nkymttmlle lasersteilylle.

VARNING!Om apparaten anvnds p annat stt n vad som specificeras idenna bruksanvising, kan anvndaren utsttas fr osynlinglaserstrlning, som verskrider grnsen fr laserklass 1.

Caution: Invisible laser radiation whenopen and interlocks defeated avoid expo-sure to beam.Advarsel:Usynling laserstling ved bning,nr sikkerhedsafbrydere er ude af funktion.Undg udsttelse for strling.

CAUTIONUse of controls or adjustments or performance of proceduresother than those specified herein may result in hazardousradiation exposure.

ATTENTIONL'utilisation de commandes, rglages ou procdures autres queceux spcifis peut entraner une dangereuse exposition aux

radiations.

ADVARSEL!Usynlig laserstling ved bning, nr sikkerhedsafbrydereer udeaf funktion. Undg udsttelse for strling.

This Compact Disc player is classified as a CLASS 1 LASERproduct.The CLASS 1 LASER PRODUCT label is located on the rearexterior.

This set employs laser. Therefore, be sure to follow carefully theinstructions below when servicing.

WARNING!WHEN SERVICING, DO NOT APPROACH THE LASER EXITWITH THE EYE TOO CLOSELY. IN CASE IT IS NECESSARY TOCONFIRM LASER BEAM EMISSION. BE SURE TO OBSERVEFROM A DISTANCE OF MORE THAN 30cm FROM THE

SURFACE OF THE OBJECTIVE LENS ON THE OPTICALPICK-UP BLOCK.

CLASS 1KLASSE 1LUOKAN 1KLASS 1

LASER PRODUCTLASER PRODUKTLASER LAITELASER APPARAT

Precaution to replace Optical block(LPC-512A)

1) After the connection, remove solder shown in

the right figure.

Body or clothes electrostatic potential could ruinlaser diode in the optical block. Be sure groundbody and workbench, and use care the clothesdo not touch the diode.

Solder

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DISASSEMBLY INSTRUCTIONS

CAUTION BEFORE STARTING SERVICINGElectronic parts are susceptible to static electricity and may easily damaged, so do not forget to take a propergrounding treatment as required.Many screws are used inside the unit. To prevent missing, dropping, etc. of the screws, always use amagnetized screw driver in servicing. Several kinds of screws are used and some of them need specialcautions. That is, take care of the tapping screws securing molded parts and fine pitch screws used to secure

metal parts. If they are used improperly, the screw holes will be easily damaged and the parts can not befixed.

CABINET DISASSEMBLY1. Top Case

1) Release 7 screws (A). (See Fig-1)2) Lift the top case with holding the back of it, and remove

it in the direction of the arrow.

2. Tray Door1) Eject the disc tray.2) Lift up the tray door in the direction of the arrow.

3. Front Panel1) Eject the disc tray. (See Fig-2)2) Remove the tray door. (See Fig-2)3) Release 2 screws (B).4) Pull the front panel toward you while pressing 7

stoppers to disengage, and remove the front panel. (See

Fig-3)

Tray Door

Disc Tray

Fig-2

Fig-1

Front Panel Stopper

Stopper

(B)

(B)

(A)

Top Case(A) (A)(A)

(A)

(A)(A)

Fig-3

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CIRCUIT BOARD DISASSEMBLYNote: Before removing the main circuit board, be sure to

shortcircuit the laserdiode output land.After replacing the main circuit board, open the land afterinserting the flexible connector.(Refer to Mechanism Disassembly)

4. Main/JACK C.B

1) Remove the top case. (See Fig-1)2) Release 10 screws (C), and take out the main/JACK

C.B. (See Fig-4)3) Remove the flexible connectors and the connector from

main circuit board.4) Then, remove the main JACK C.B.

5. Power C.B1) Release 4 screws (D). (See Fig-5)

Main C.B Flexibleconnector

Flexibleconnector

JACK C.B

(C)

(C)(C)

(C)(C)

(C)(C)(C)

(C)

Power Code

Power C.B

(D) (D)

(D)

(D)

Fig-4

Fig-5

6. TIMER and Key C.B1) Remove the front panel. (See Fig-3)2) Release 5 screws (E), and remove the TIMER C.B.

(E)

(E)

(E)

(E)(E)

TIMER C.B

Key C.B

Fig-6

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DECK MECHANISM PARTS LOCATION Bottom View

Top View

Procedure

Starting No.

5

5, 6

2

2, 8

2, 8

2, 8

2, 8, 11

2, 8, 11

2, 8, 12, 13

2, 8, 12-14

2, 8, 12-14

2, 8, 12-16

2, 8, 9

2, 8, 9

2, 8, 9

2, 8, 9-20

1, 2, 8, 9

1, 2, 8, 9

2, 8, 9

2, 8, 9

2, 8

2, 8, 26

2, 8, 26, 27

2, 8, 26-28

2, 8, 26-29

1, 2, 8, 26-30

1, 2, 8, 26-31

1

23

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Parts

Junction P.C.Board

Bracket Assembly ClampBracket Clamp

Clamp Assembly Disk

Plate Clamp

Magnet Clamp

Clamp Lower

Tray Disk

Base Assembly Feed

Rubber R

Spring Skew

Shaft PU Main

Shaft PU Sub

Mechanism Assembly

PU Unit

Guide Freed PU

Spring Guide Feed

Pick up Assembly General

Motor (Mech.)

Shaft Lead Screw

Motor Assembly PU Freed

Base PU (Outsert)

Base Assembly Main

Holder Assembly Deck on

Frame Assembly Up/Down

Rubber F

Belt Loading

GearPulley

Gear Loading

Gear Emergency

Cam Loading

Motor Assembly Loading

Base Main

Fixing Type

4 Screws,

4 Locking Tabs

2 Screws

1 Locking Tab

1 Connector

1 Screw

1 Hook

1Screw

3Screws

2 Locking Tabs

1 Locking Tab

2 Locking Tabs

1 Screw

2 Screws

1 Locking Tab

Disassembly

Bottom

Bottom

Bottom

Bottom

Bottom

Figure

4-1

4-24-2

4-2

4-2

4-2

4-2

4-3

4-4

4-4

4-4

4-4

4-4

4-4

4-4

4-4

4-4

4-4

4-4

4-4

4-4

4-5

4-5

4-5

4-5

4-5

4-5

4-5

4-5

4-5

4-5

4-5

Note: When reassembling, perform the procedure in reverse order.The Bottom on Disassembly column of aboveTable indicates the part should be disassembled at theBottom side.

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DECK ASSEMBLY

BRACKET CLAMP

CLAMPASSEMBLY DISK

BRACKET CLAMP

PLATE CLAMP

(S2)

(S2)

(A)

(Fig-A)

MAGNET CLAMP

CLAMP LOWER

7. Junction C.B (Fig-7)1) Put the Deck Assembly face down. (Bottom side)2) Release 4 Screws (S1).3) Unlock 4 Locking tabs (L1).4) Lift up the Junction C.B a little to disconnect the

Connector (C1).5) Disconnect 3 Connectors (C2, C3, C4).

DECK MECHANISM ASSEMBLY

DECK ASSEMBLY

JUNCTIONC.B(C2) (C1)

(C3)(C4)

(L1)

(L1)

(L1)(L1)

(S1)(S1) (S1) (S1)

Fig-7

Fig-8

8. Bracket Assembly Clamp (Fig-8)1) Put the Deck Assembly on original position. (Top side)2) Release 2 Screws (S2).3) Lift up the Bracket Assembly Clamp.

8-1. Clamp Assembly Disk1) Place the Clamp Assembly Disk as Fig-(A).2) Lift up the Clamp Assembly Disk in direction of arrow

(A).3) Separate the Clamp Assembly Disk from the Bracket

Clamp.

8-1-1. Plate Clamp1) Turn the Plate Clamp to counterclockwise direction and

then lift up the Plate Clamp.

8-1-2. Magnet Clamp8-1-3. Clamp Lower

8-2. Bracket Clamp

9. Tray Disk (Fig-9)1) Insert and push a Driver in the emergency eject hole (A)

at the front side, or put the Driver on the Lever (B) of the Gear Emergency and pull the Lever (B) in directionof arrow (A) so that the Tray Disk is ejected about 15-20mm.

2) Pull the Tray Disk until the moving is locked by theLocking Tab (L2).

3) Unlock the Locking tab (L2) in direction of arrow (B).4) Separate the Tray Disk completely.

TRAY DISK

EMERGENCYEJECT HOLE

LEVER

BOTTOM SIDE VIEW

(A)

(B)(L2)

(B)(A)

Fig-9

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10. Base Assembly Feed (Fig-10)1) Disconnect the Connector (C5)2) Release the Screw (S3).

10-1. Rubber R10-2. Spring Skew1) Press the (A) position of the Spring Skew and unlock

the Spring Skew locking.

10-3. Shaft PU Main10-4. Shaft PU SUBNote: When reassembling, be careful not to change the

Shaft PU Main (Long) and the Shaft PU Sub (Short).

10-5. Mechanism Assembly PU Unit10-5-1. Guide Feed PU1) Release the Screw (S4) and separate the Guide Feed PU

from the Pick up Assembly General.

10-5-2. Spring Guide Feed

MOTOR (MECH.)

BASE PU (OUTSERT)

PICK UPASSEMBLY GENERAL

SHAFT LEAD SCREW

MOTORASSEMBLY PUFEED

P.C. BOARD

Fig-(A)

SPRINGGUIDE FEED

(S5)(S5)

(L3)(A)

(S3)

(A)

(C5)

(S4)

BLACK

RED

RUBBER RSPRING SKEW(L4)

(A)

SHAFT PU SUB SHAFT PU MAIN

GUIDE FEED PU

BASE PU (OUTSERT)

CABLE FLEXIBLE

MOTOR ASSEMBLY PU FEED

Fig-10

10-5-3. Pick Up Assembly General

10-6. Motor (mech.)

1) Release the 3 Screws (S5) at bottom side.2) Push down the Motor (Mech.) and separate from theBase PU (Outsert).

10-7. Shaft Lead Screw1) Push the Shaft Lead Screw in direction on arrow (A) a

little and lift up the Shaft Lead Screw.

10-8. Motor Assembly PU Feed.1) Unlock the Locking tab (L3) and lift up the P.C.Board.2) Unlock two Locking Tabs (L4) and push down the

Motor Assembly PU Feed.3) Separate the Motor Assembly PU Feed from the Base

PU (Outsert).

Note: When reassembling, place the Motor Assembly PUFeed as Fig-(A) and insert the Cable Flexible to theHole (A) of the Base PU (Outsert). (See Fig-(A))

10-9. Motor (mech.)

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11. Base Assembly Main (Fig-11)

11-1. Holder Assembly Deck On1) Push the Locking tabs (L5) at bottom side of the Holder

Assembly Deck On in direction of arrow (A) andseparate to bottom side. (See Fig-(A))

11-2. Frame Assembly Up/Down.1) Push the two Locking tabs (L6) and lift up the Frame

Assembly Up/Down.

Note: When reassembling, insert the Lever (R1) of theFrame Assembly Up/Down to the Groove (R2) of theGear Emergency and lock the two Locking Tabs(L6). (See Fig-(B))

11-3. Rubber F11-4. Belt Loading11-5. Gear Pulley1) Release the Screw (S6) and lift up the Gear Pulley.

11-6. Gear Loading11-7. Gear EmergencyNote: When reassembling, confirm that the Hole (A) of the

Cam Loading is aligned to the Hole (B) of the GearEmergency as Fig-(C).For this alignment, place the Gear Emergency andCam Loading as Fig-(D), and then move the GearEmergency in direction of arrow (B) until these twogears are aligned as Fig-(C).

11-8. Cam Loading11-9. Motor Assembly Loading1) Release two Screws (S7).2) Unlock the Locking tab (L7) and separate the Motor

Assembly Loading to bottom side.

Note: When reassembling, confirm that the Connector (2Pin) is aligned as Fig-(E)

11-10.Base Main

Fig-11

(R1)

(R2)

MOTOR ASSEMBLY LOADING

Fig-(E) Fig-(A)BOTTOM SIDE VIEW

BASE MAIN

HOLDERASSEMBLYDECK ON

(L7)

(L6)

(R2)

(R1)

(S6)

(L6)

(L5)

(L5)

(A)

BELT LOADING

GEAR EMERGENCY

Fig-(B)

Fig-(D)

Fig-(C)

CAM LOADING

CONNECTOR(2 PIN)

GEAR LOADING

GEAR PULLY

FRAME ASSEMBLY UP/DOWN

RUBBER F

(S7)

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ELECTRICAL MAIN PARTS LIST

IC

SI-AM2-980-01A IC,AM29F800B-120EC SI-AL2-402-10E IC,AT24C02N-10SC-2.7

SI-AL4-981-92B IC,AT49F8192A-90TC SI-RH5-983-20A IC,BA5983FP-E2 SI-RH6-859-20A IC,BA6859AFP-E2

SI-RW8-610-00A IC,BT861 SI-HY2-580-10A IC,GDC25D801AA SI-GS7-142-60E IC,GM71C4260CJ-60 SI-HI6-417-03B IC,HD6417034AFI20 SI-SS4-310-00A IC,KA431AZ

SI-SS7-542-00A IC,KA7542Z SI-SS7-808-00H IC,KA78R08 4P SI-KE3-930-00G IC,KIA393F-EL SI-KE4-310-00A IC,KIA431 3P 87-001-196-010 IC,KIA7042P

SI-SS4-161-02F IC,KM4161020CT-G7 SI-SA8-661-12C IC,LC866112B-5N21 SI-JR3-414-00C IC,NJM3414AM-TE1,3K/REEL SI-JR4-580-00B IC,NJM4580M SI-BB1-716-00A IC,PCM1716E 28P

SI-BB1-700-00A IC,PLL1700E 20P SI-SH2-050-00A IC,PQ20WZ5U 20WZ51 SI-SH3-130-00A IC,PQ3DZ13U SI-TI7-437-40K IC,SN74AHC374PWLE SI-SK6-153-00A IC,STR-G6153T 5P

SI-TO1-254-00B IC,TA1254AF SI-TO1-254-00A IC,TA1254F SI-TO7-040-00F IC,TC7W04FU SI-MQ5-316-25A IC,V53C16256HK50 SI-CU3-000-00A IC,ZIVA3-PE0

SI-GS7-216-16C ICGM72V161621ET-7

TRANSISTOR

ST-R10-500-9AD TR,KRA105M ST-R10-300-9AE TR,KRC103M ST-R10-500-9AB TR,KRC105M ST-R11-510-0AA TR,KSB1151-Y ST-R12-670-9AC TR,KTA1267-GR

ST-R15-040-9BF TR,KTA1504S-Y ST-R15-050-9AD TR,KTA1505S-Y ST-R31-980-9AC TR,KTC3198-TP-BL ST-R13-040-9BA TR,KTD1304S ST-R10-000-9CB TR,UMX1N

ST-R10-000-9BM TR,UMZ1N 3K 87-070-334-070 ZENER,MTZ10B SM-TZ6-8CT-000 ZENER,MTZ6.8C

DIODE

SD-D19-300-9AB C-DIODE,KDS193 ST-R10-370-9BB C-TR,2SA1037K-Q ST-R10-300-9AA C-TR,KRC103S-T1 ST-R38-750-9AC C-TR,KTC3875S-GR-T1 SD-R15-402-0BA DIODE,1N5402

87-020-465-080 DIODE,1SS133 SD-R10-451-0AA DIODE,B10A45V1 SD-D01-000-9CA DIODE,EG01CW SD-R18-020-9AA DIODE,ERA18-02KFRB 87-A40-284-080 DIODE,ERA22-10

SD-D01-000-9AC DIODE,EU01W 83-NEG-677-080 DIODE,MTZ5.6B SD-R49-500-9AA DIODE,RB495D 87-017-352-010 DIODE,RU3YXLF-C1 100V2 87-070-173-010 DIODE,S1WBA60

MAIN C.B

C204 SC-H71-06C-611 C-CAP,10UF-6.3V C207 SC-H71-06C-611 C-CAP,10UF-6.3V C213 SC-H71-06C-611 C-CAP,10UF-6.3V C214 SC-H71-06C-611 C-CAP,10UF-6.3V

C215 SC-H71-06C-611 C-CAP,10UF-6.3V

C216 SC-H71-06C-611 C-CAP,10UF-6.3V C218 SC-H71-06C-611 C-CAP,10UF-6.3V C219 SC-H71-06C-611 C-CAP,10UF-6.3V C220 SC-H81-07C-621 C-CAP,100UF-6.3V C224 SC-H71-06C-611 C-CAP,10UF-6.3V

C226 SC-H71-06C-611 C-CAP,10UF-6.3V C230 SC-H71-06C-611 C-CAP,10UF-6.3V C302 SC-H81-07C-691 C-CAP,100UF-6.3V C310 SC-H71-06F-621 C-CAP,10UF-16V C311 SC-H71-06F-621 C-CAP,10UF-16V

C708 SC-H71-06C-611 C-CAP,10UF-6.3V C709 SC-H82-27D-611 C-CAP,220UF-10V C712 SC-H71-06C-611 C-CAP,10UF-6.3V C713 SC-H71-06C-611 C-CAP,10UF-6.3V C714 SC-H71-06F-621 C-CAP,10UF-16V

C718 SC-H71-06C-611 C-CAP,10UF-6.3V CE201 SC-H84-76C-611 C-CAP,47UF-6.3V CE202 SC-H84-76C-611 C-CAP,47UF-6.3V CE203 SC-H84-76C-611 C-CAP,47UF-6.3V CE205 SC-H84-76C-611 C-CAP,47UF-6.3V

CE206 SC-H84-76C-611 C-CAP,47UF-6.3V CE210 SC-H84-76C-611 C-CAP,47UF-6.3V CE211 SC-H84-76C-611 C-CAP,47UF-6.3V CE221 SC-H84-76C-611 C-CAP,47UF-6.3V CE223 SC-H84-76C-611 C-CAP,47UF-6.3V

CE228 SC-H84-76C-611 C-CAP,47UF-6.3V CE609 SC-H81-07F-611 C-CAP,100UF-16V CE610 SC-H81-07F-611 C-CAP,100UF-16V CE710 SC-H84-76C-611 C-CAP,47UF-6.3V X101 S2-12H-B20-02A CCR20.0MC6T TDK 20000000H

X301 S2-02R-427-01G C-RESO 27MHZ 20P

JUNCTION C.B

CE450 87-010-140-080 CAP,E 47-16V CE451 87-010-140-080 CAP,E 47-16V CE452 87-010-140-080 CAP,E 47-16V CE453 87-010-140-080 CAP,E 47-16V R451 SR-D01-01H-633 RES,1-1/2W

R452 SR-D01-01H-633 RES,1-1/2W

TIMER C.B

C500 SC-E22-73D-638 CAP,E 220-10V

C502 SC-E10-63F-638 CAP,E 10-16V C506 SC-E47-63J-638 CAP,E 47UF-35V C507 SC-E10-63F-638 CAP,E 10-16V C512 87-010-140-080 CAP,E 47-16V

C513 87-010-140-080 CAP,E 47-16V DIG501 S3-02H-V00-1D0 7-BT-259GK DH LED501 SD-L32-531-9AA LED SPR325MVWT31(GRN) RC501 S7-12R-083-8GA TSOP1238UQ1 TEMIC 8MM 37 RC SW501 S5-562-19B-000 SW,SKHV10910B

SW502 S5-562-19B-000 SW,SKHV10910B SW503 S5-562-19B-000 SW,SKHV10910B SW503 S5-562-19B-000 SW,SKHV10910B SW504 S5-562-19B-000 SW,SKHV10910B SW505 S5-562-19B-000 SW,SKHV10910B

SW506 S5-562-19B-000 SW,SKHV10910B SW507 S5-562-19B-000 SW,SKHV10910B SW510 S5-562-19B-000 SW,SKHV10910B SW511 S5-562-19B-000 SW,SKHV10910B SW512 S5-562-19B-000 SW,SKHV10910B

SW513 S5-562-19B-000 SW,SKHV10910B

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TRANSISTOR ILLUSTRATION

Regarding connectors, they are not stocked as they are not the initial order items.The connectors are available after they are supplied from connector manufacturers upon the order is received.

ECBKRA105MKRC105MKRC103M

ECBKSB1151

BCEKSE13005F UMX1N

UMZ1N

C2B1

E1

E2B2

C1B

E

C

2SA1037KKTA1504SKTA1505SKTC3198

KTC3875SKTC4419KTD1304S

SW514 S5-562-19B-000 SW,SKHV10910B X501 S6-160-20P-000 CSA6.00MGU MURATA 6MHZ

JACK C.B

CV1 87-010-060-080 CAP,E 100-16V CV2 SC-E22-76F-638 CAP,E 220UF-16V CV3 87-010-237-910 CAP,E 1000UF-16V CV6 87-015-681-080 CAP,E 10-16V CV8 87-010-140-080 CAP,E 47-16V

CV10 SC-E10-86F-630 CAP,E 1000-16V CV12 87-015-681-080 CAP,E 10-16V CV13 87-015-684-080 CAP,E 47-16V CV14 87-015-681-080 CAP,E 10-16V CV15 87-015-681-080 CAP,E 10-16V

CV16 87-016-577-080 CAP,E 470UF-16V CV21 87-010-060-080 CAP,E 100-16V JACK1 S6-12H-K26-02A TOTX178 TOSHIBA AN/DIP JACK2 S5-720-75A-000 BJP-202L BAEEN BLACK JACK3 S6-12R-IH0-05D JACK,PPJ6031J

JACK4 S6-12R-BH0-08A YKF51-5506 JALCO HORIZONT4P JACK8

KEY C.B

SW508 S5-562-19B-000 SW,SKHV10910B

POWER C.B

C900 87-010-408-040 CAP,E 47UF-50V C901 S6-240-88B-000 CAP,0.1UF-250V C902 S6-240-88B-000 CAP,0.1UF-250V C902 S6-240-88F-000 CAP,PCX2 275V 0.1UF,M C905 87-016-375-010 CAP,0.01UF-630V

C906 S6-240-87B-000 CAP,100P-1KV C907 SA-1B3-0KH-2M0 CAP,220PF-400V C913 87-012-379-010 CAP,3300PF-400V C916 87-010-387-010 CAP,E 470UF-25V KME C918 87-010-112-080 CAP,E 100-16V

C919 87-010-408-040 CAP,E 47UF-50V C921 SC-E22-76F-638 CAP,E 220UF-16V C923 87-010-237-910 CAP,E 1000UF-16V C924 87-010-237-910 CAP,E 1000UF-16V C925 87-010-375-080 CAP,E 330-10V

C926 87-010-408-040 CAP,E 47UF-50V C927 87-015-684-080 CAP,E 47-16V C929 87-010-112-080 CAP,E 100-16V C932 SC-E47-7CD-638 CAP,E 470UF-10V C934 SC-E47-7CD-638 CAP,E 470UF-10V

! F901 S5-850-11T-000 FUSE,1600MA 250V! IC903 S6-570-62B-000 SENSOR PC123Y! L901 S6-161-45H-000 FILTER SHT LFS2020V4-04350! L901 S6-161-45J-000 FL BUJEON V-04350 L902 S6-330-88G-000 COIL,CHOCK TP 5MM

L903 S6-330-88D-000 COIL,20UH R901 S6-140-07R-000 RES,2.7-2W R902 SR-S10-03K-619 RES,100K-2W R911 SR-S05-10K-619 RES,0.51-2W R922 SR-S12-00J-619 RES,M/F 120-1W

! T901 S6-420-23T-000 PT,SHT-023T/KSE-023T! V901 S6-560-04F-000 SVR681D10A SAMYANG 680V

8 8

A

Resistor Code

Chip Resistor Part Coding

Figure

Value of resistor

Chip resistor

Wattage Type Tolerance

1/16W1/10W

1/8W

16082125

3216

5%5%

5%

CJCJ

CJ

Form L W t

1.6 0.8 0.452 1.25 0.45

3.2 1.6

108118

128

: A : A

CHIP RESISTOR PART CODE

0.55

Resistor CodeDimensions (mm)

Symbol1/16W 1005 5% CJ 1.0 0.5 0.35 104

L

t

W

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13

BLOCK DIAGRAM-1 (OVERALL)

M

M

P O W E R C O N T R O L

R X D O / T X D O / S C K O

F_ R e g / M

_ R e g / M

_ R e s e t / M D_ S W

L O A D I N G D R I V E

S E N S , F O K

, S L D

_ F G

,

M S D A T 0 , D E F E C T , D S P

_ S E N S E

,

S Q S O

, S Q C K

, S C O R

, A O [ 0 : 5

]

X L A T , S

_ C L K

, S_ D

A T A

, D O [ 0 : 7

]

2 7 M H z

V D A T A [ 0 : 7 ]

H s y n c

V s y n c

C o m p o s i t e

, Y , C

C o m p o n e n t

D V D

_ L D Q M

, D V D

_ S D

_ C S 1

D V D

_ M A [ 0 : 1

1 ]

D V D

_ M D [ 0 : 1

5 ]

D V D

_ S D

_ C S 0 ,

D V D

_ U D Q M

D V D_ D A T A [ 0 : 7 ]

S D C L K I , Z I S E N B

R E Q Z I

3 3 . 8

6 8 8 M H z

D A_ D

A T A ,

D A_ L

R C K ,

D A_ B

C K

D A_ X

C K

D V D

_ S D_ C A S ,

D V D

_ S D_ R A S

D V D

_ S D_ C L K

D V D

_ M W E

D [ 0 0 : 0 7 ]

A [ 0 0 : 0 2 ]

S_ C

L K , S_ D

A T A

,

D P L L

_ L

I I C_ D

A T A

,

I I C_ C

L K

D A C

_ L 0 ,

S_ C

L K

S_ D

A T A

L

L

A U D I O

O U T

V I D E O O U T

R

C o m p o s i t e

C

Y

R

F I L T E R

A M P

D A

_ D A T A

,

D A

_ L R C K

,

D A

_ B C K

2 7 M H z

X - T

A L

S P I N D L E

_ F G , S

L D_ F

G

F D O , T D O

,

F M O

M O N

, S P I N D L E

_ D R V

T E B A L , F E B A L ,

D P O C T L

, E Q F , E Q B

F E , T

E , R

F R P , S B A D D

, D V D / C D R F

I C A D D R [ 0 : 8 ]

I C D A T A [ 0 0 : 1 5 ]

R F R P , R F C e n

,

T E

, V r e f

D V D : A , B , C , D

D V D : R F

C D : A , B , E , F

s p i n d l e

L o a d i n g

f o c u s , t r a c k i n g s l e d

S P I N D L E

M O T O R

D I S C

L O A D I N G

M O T O R

O P E N S / W

C L O S E S / W

L I M I T S / W

D E C K M E C H A N I S M

A C 1 0 0

~ 2 4 0 V ,

5 0 ~ 6 0 H z

- 2 2

. 5 V

- 2 7 V

- 2 1

. 8 V

+ 9 V

+ 5 V A

+ 5 V D

+ 5 V U

A G N D

, G N D

, U G N D

P I C K

U P

P b

P r

Y

F I L T E R

I C 3 0 8

P L L 1 7 0 0

C L O C K

G E N E R A T R O R

I C 4 0 0

B A 6 8 5 9 F P

S P I N D L E

M O T O R

D R I V E R

I C 4 0 1

B A 5 9 8 3

P O W E R

D R I V E R

I C 2 0 6

D V D S P - 3

3 0 1

C D / D V D D S P

D V D S E R V O

D R A M

2 5 6 K x

1 6 b i t

C o m p .

P O W E R

B O A R D

I C 8 0 0 / I C 8 0 1

B T 8 6 5 A / 8 6 1 A

N T S C / P A L

E n c o d e r

I C 7 0 3 / I C 6 0 1

~ 6 0 3

P C M 1 7 6 x 4

A U D I O

D A C

I C 1 0 8

S H 7 0 3 4

I C 3 0 1

Z i V A - 3

M P E G A / V

D e c o d e r

I C 3 0 6

G M 7 2 V 1 6 2 1

1 M

X 1 6 b i t

S D R A M

I C 3 0 7

G M 7 2 V 1 6 2 1

1 M

x 1 6 b i t

S D R A M

I C 2 0 1

T A 1 2 5 4 F

R F S I G N A L

P R O C E S S O R

I C 5 0 0

L C 8 6 6 1 1 2

F L D I S P L A Y

K E Y I N P U T

R E M O C O N

R E C E I V E R

D R A M

F L A S H

M E M O R Y

8/14/2019 Aiwa Xv-dv290 Sm

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14

BLOCK DIAGRAM-2 (POWER)

TRANS

Q901KTC4419SWITCHING IC

LINE FILTER

R E C T I F I E R ( F L D )

R E C T I F I E R ( 1 4 V )

R E C T I F I E R ( 5

. 2 V )

F E E D B

.

L P F

R E G ( 8 V )

F +

F -

- 2 4 V

1 2 V

8 V D 5 V

A 5 V

U 5 V

P W R O N / O F F

A C 1 0 0 V ~ 2 4

0 V

R E C T I F I E R ( 1 0 V )

L P F

RECTIFIER

L P F

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15

BLOCK DIAGRAM-3 (RF/DSP/SERVO)

P I C K

U P

M / D

U C O M

I / F U C O M

I / F U C O M

I / F M P E G

I / F M P E G

I / F

D V D : A , B , C , D

R F R P , R

F C e n ,

T E , V r e f

F E , T

E , R F R P , S B A D D R F

Z_ H O L D

D V D / C D R F

T E B A L , F

E B A L ,

D P O C T L , E

Q F , E Q B

5

4

M I R R , T Z C

S E N S , F

O K , S L D_ F G ,

M S D A T O , D E F E C T , D

S P_ S

E N S E

5 3 3 8 8 4 S Q S O , S

Q C K , S

C O R

X L A T , S_ C

L K , S_ D

A T A

D O [ 0 : 7 ]

A O [ 0 : 5 ]

Z O [ 0 : 7 ]

M C K

F D O , T D O , F

M O

S P I N D L E_ F G , S

L D_ F

G

l o a d i n g d r i v e

f o c u s , t r a c k i n g , l o a d i n g , s

l e d

s p i n d l e

M O N

, S P I N D L E_ D R V

I C D A T A [ 0 0 : 1 5 ]

I C A D D R [ 0 : 8 ]

1 6

9

4

2

4 4

D V D : R F

C D : A , B , E , F

I C 2 0 1

T A 1 2 5 4 A F

R F S i g n a l

P r o c e s s o r

I C 2 0 6

G D C 2 5 D 8 0 1 A A

C D / D V D D S P

I C 4 0 0

B A 6 8 5 9 A F P

S p

i n d l e

M o

t o r

D r i v e r

I C 4 0 1

B A 5 9 8 3

P o w e r

D r i v e r

D R A M

2 5 6 K x 1 6 b i t

I C 2 0 4

c o m p .

I C 2 0 5

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16

BLOCK DIAGRAM-4 (AUDIO)

- c o m

I / F

( I C 1 0 8 )

M P E G I / F

( I C 3 0 1 )

T O J A C K

B O A R D

C H 1 / 2 : D O W N M I X L t / R t

L t R t

R 0 L 0

M P E G

_ R S T

S_ D A T A

S_ C L K

D A C_ L 0

D A_ L

R C K

D A_ B

C K

D A_ X

C K

D A_ D

A T A 0

I C 7 0 3

P C M 1 7 1 6

A u

d i o D A C

I C 7 0 4

L P F

&

B u f f e r

N J M 4 5 8 0 M

O P A

M P

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17

BLOCK DIAGRAM-5 (MPEG)

D V D_ D A T A [ 0 : 7 ]

S D C L K 1 , Z

I S E N B

R E Q Z 1

A [ 0 0 : 0 2 ]

D [ 0 0 : 0 7 ]

M P E G_ E R R O R

I I C_ D

A T A , I I C

_ C L K

D V D_ M D [ 0 : 1 5 ]

D V D_ M A [ 0 : 1 1 ]

D V D_ S D

_ C A S

D V D_ S D

_ R A S

D V D_ S D

_ C L K

D V D_ M W E

D V D_ S D

_ C S 0 , D

V D_ U D O M

8

4

2 8 2 2

4

1 6

1 2

2 D V D_ L D O M ,

D V D_ S D

_ C S I

M C K S_

C L K , S_ D A T A , D P L L

_ L

D A_ D

A T A [ 0 : 3 ]

D A_ B

C K

S P D I F

H S Y N C , V S Y N C

2 8

V D A T A [ 0 : 7 ]

D A_ X

C K

M P E G

_ C L K

Y / C

C O M P O S I T E 1

P r P b Y

3

D S P

I / F

- C

O M

I / F

I C 3 0 1

Z i V A - 3

M P E G

A / V

D e c o

d e r

I C 8 0 1

B T 8 6 1 A

N T S C / P A

L

E n c o

d e r

I C 3 0 6

G M 7 2 V 1 6 2 1

1 M

x 1 6 b i t

S D R A M

I C 3 0 7

G M 7 2 V 1 6 2 1

1 M

x 1 6 b i t

S D R A M

I C 3 0 8

P L L 1 7 0 0

C L O C K

G E N E R A T R O R

2 7 M H z

X - T

A L

U C O M

I / F

V I D E O

I / F ( A / V )

A U D I O

I / F ( A / V )

S E R V O

I / F

BLOCK DIAGRAM-6 (SYSTEM CONTROL)

M P E G

I / F

A / V

I / F

S E R V O

I / F

D S P

I / F

D [ 0 0 : 0 7 ] , A [ 0 0 : 0 2 ] , I

I C_ C

L K , I

I C_ D

A T A , S C L K 0 ,

M P E G

_ I N T

E C H O , M

I C_ A , D

I S C_ A , S_ D A T A , S

/ C L K

B C A_ C O D E S P I N D L E_ F G , S

L D_ F

G ,

D [ 0 0 : 0 7 ] , A

[ 0 0 : 0 5 ] , E_ S I N , E_ C L K

L O A D F R , F

/ R , L

O C K , D

E F E C T , F O K ,

D S P_ S E N S E

8

D [ 0 0 : 0 7 ]

/ , / W R

S E N S

_ M C O M ,

M I C O M

_ W A I T 2

M P E G

_ E R R O R ,

D A C_ L 0 ,

R F_ L

A T ,

/ D S P

_ C S ,

/ M P E G

_ C S ,

/ P P_ C S

6

M P E G_ C T L ,

E_ D R ,

/ Z O O M

_ R S T ,

/ S_ X

R S T ,

X L A T ,

A C T_ M U T E ,

8

I I C_ C

L K ,

I I C_ D

A T A

2

I C 1 1 4

E E P R O M

A T 2 4 C 0 2

I C 1 0 1

I C 1 0 2

7 4 H C 3 7 4

I C 1 0 8

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2019

WIRING-1 (MAIN: COMPONENT SIDE)

14 13 12 11 10 9 8 7 6 5 4

TO/FROMPOWER C.B

CON902TO/FROM

JUNCTION C.BCN402

TO/FROMJUNCTION C.B

CN404

MAIN C.B(COMPONENT SIDE)

T O / F R O M

T I M E R C

. B

C N 5 0 7

NOTE

BE

CE

Cxxx

Rxxx

Lxxx

1 1

1 10

15

15

19

2 2 26

25

20

E

E

R801

R 3 9 9

R 3 6 4

R 3 6 6

R 3 6 5

R 3 0 7

CER714R787

156

157

2081 52

53

104

105

R309R312

R385R384

1

5253104

105

156157 208

C 2 2 7

1

1617 32

33

484964

1 5

15

12

14R184

R191

C128

1

112

85

84 57

56

29

28

1

1

1514

2

20 21

40

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21

WIRING-2 (MAIN: CONDUCTOR SIDE)

1 2 3 4 5 6 7 8 9 10

A

B

C

D

E

F

G

H

I

J

MAIN C.B(CONDUCTOR SIDE)

1

1

2425

48

4 5

8

1 4

58

1 4

58

1 4

58

R193

R188

E

E

1

1 40

20 21

1112 22

23

333444

1

1

1

2021 40

41

606180

5

1011

20

E

EE

C 2 0 2

R82

1

28

1

1

25 26

501

25 26

50

10

1120

NOTE

BE

CE

Cxxx

Rxxx

Lxxx

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2423

SCHEMATIC DIAGRAM-1 (MAIN 1/5)

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21/70

25


8/14/2019 Aiwa Xv-dv290 Sm

22/70

2827


8/14/2019 Aiwa Xv-dv290 Sm

23/70

29


8/14/2019 Aiwa Xv-dv290 Sm

24/70

3231


8/14/2019 Aiwa Xv-dv290 Sm

25/70

33

SCHEMATIC DIAGRAM-6 (JACK)

CV1210 F

CV16470 F/16V

CV24220 F/16V

RV0310K

RV31180

RV32680

RV3375

RV08820

RV051.0K

RV042.2K

L V 0 1

1

H

U ( B )

V ( G )

R 1

L 1

C O M P O 1

A A +

1 2 V

S C A R T 1 ( 1 6 : 9

)

S C A R T 2 ( D V D / A V )

DV021SS133

QV01KTA1267

QV07KTA1267

QV03

KRC103M

QV02

KRC103M

BVD01BEAD

BVD02BEAD

BVD03

BEAD

FV06

FV07

FV08

FV05

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1 2 3 4 5 6 7 8 9 10 11 1

A

B

C

D

E

F

G

H

I

J

K

3635

WIRING-3 (JUNCTION/JACK)

M3(LOADING MOTOR)

TO/FROMMAIN C.BCON201

JACK C.B

JUNCTION C.B

TO/FROMPOWER C.B

CON904

PICK UPASSY

TO/FROMMAIN C.BCON201

TO/FROMMAIN C.BCON801TO/FROMMAIN C.B

CON202

VIDEOOUT

OPTICAL COAXIAL

DIGITAL OUT

JACK04JACK03AUDIO OUT

L

R

S-VIDEOOUT

OPEN/CLOSESWITCH

NOTE

E C B

M

M2(SLED MOTOR)

M

SPINDLEMOTOR

MSW1 M1

INSIDELIMIT

SW

13

JACK01 JACK02

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37

SCHEMATIC DIAGRAM-7 (JUNCTION)

8/14/2019 Aiwa Xv-dv290 Sm

28/70

1 2 3 4 5 6 7 8 9 10 11 1

A

B

C

D

E

F

G

H

I

J

K

4039

WIRING-4 (TIMER/KEY/POWER)

8/14/2019 Aiwa Xv-dv290 Sm

29/70

41

SCHEMATIC DIAGRAM-8 (TIMER/KEY)

8/14/2019 Aiwa Xv-dv290 Sm

30/70

4443

SCHEMATIC DIAGRAM-9 (POWER)

C932470 /10V+8V REG.

A5V REG.

POWCONT

INSULATOR

AC 200-240V50Hz

POWER C.B T901

1

23

4

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45

WAVE FORM

1 IC201 Pin ( (LVL) SBADD VOLT/DIV: 500mVTIME/DIV: 2mS

IC201 Pin (FEO) Focus Error VOLT/DIV: 2.9VTIME/DIV: 2mS

2 IC201 Pin ) (TEO) VOLT/DIV: 2.2VTracking Error TIME/DIV: 2mS

3 IC201 Pin ) (TEO) VOLT/DIV: 2.27VVBR Tracking Error TIME/DIV: 500S

4 IC201 Pin (RFO) VOLT/DIV: 0.5VTIME/DIV: 0.1S

5 IC206 Pin (A OUT3) VOLT/DIV: 2.12VSLED Drive (FMO) TIME/DIV: 10mS

6 IC201 Pin (FEO) VOLT/DIV: 200mVFocus Error (In Focus search) TIME/DIV: 100mSIC206 Pin (A OUT1) VOLT/DIV: 2.14VFocus Drive (FDO) TIME/DIV: 100mS

7 IC801 Pin # -^ (P0-P3) VOLT/DIV: 280mVIC801 Pin ( - (P4-P7) TIME/DIV: 500SMPEG Data

88

83

Tek Stop : 1 00kS/s 3290 Acqs

M 500 s CH1 280/mV

RecordLength

Fit to ScreenOFF

Time BaseMain

TriggerPosition

50%

HorizScale(/div)

HorizPos

FastFrameSetup

more1 of 3

3

Ch3 1.00V

[ T ] ]

RecordLength

2500

T

2500points in

50divs

1000points in

20divs

500points in

10divs

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46

@ IC801 Pin (CLK IN) VOLT/DIV: 280mVMPEG Clock TIME/DIV: 500S

# IC801 Pin (VSYNC) VOLT/DIV: 280mVVertical SYNC TIME/DIV: 5mS

$ IC801 Pin (HSYNC) VOLT/DIV: 280mVTIME/DIV: 20S

% IC801 Pin + (DACF) VOLT/DIV: 500mVComponent Pb TIME/DIV: 20S

8 IC801 Pin (DACC) VOLT/DIV: 500mVComposite TIME/DIV: 20S

9 IC801 Pin (DACB) VOLT/DIV: 500mVChrominance TIME/DIV: 20S

0 IC801 Pin (DACA) VOLT/DIV: 500mVLuminance TIME/DIV: 20S

! IC801 Pin (SID) VOLT/DIV: 2.06VIC801 Pin (SIC) TIME/DIV: 25mSSDA/SCL

58

Tek Stop : 2.50MS/s 4 Acqs

M20.0 s 2 Apr 199914:47:27

Glitch Ch1Ch3 500mV

[T ]

T

3

59

75

76

Tek Stop : 1 00kS/s 3290 Acqs

M 500 s CH1 280/mV

Edge Slope

Type

SourceCh1

CouplingDC

Level280mV

Mode&

Holdoff

3

Ch3 1.00V

[ T ] ]

Slope

T

Tek Stop : 10.0kS/s 13 Acqs

M 5.00ms CH1 280/mV

Edge Slope

Type

SourceCh1

CouplingDC

Level280mV

Mode&

Holdoff

3

Ch3 1.00V

[ T ]

Slope

T

Tek Stop : 2.50MS/s 7 Acqs

M 20.0 s CH1 280/mV

Edge Slope

Type

SourceCh1

CouplingDC

Level280mV

Mode&

Holdoff

3

Ch3 1.00V

[ T ]

Slope

T

7157

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47

^ IC801 Pin , (DACE) VOLT/DIV: 500mVComponent Pr TIME/DIV: 20S

& IC801 Pin < (DACA) VOLT/DIV: 500mVComponent Y TIME/DIV: 20S

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48

TROUBLE-SHOOTING1. Power Circuit

Input Voltage: 120V It is possible to malfunction, if the unload condition is left for a long time when power is on.

(More than Dummy load 100mA) A Primary side is abnormal when the fuse is short, secondary side is abnormal when the IC103 oscillates intermittently. The resistor value of both terminal is measured with DVM crossing each other to check the each element is normal or abnormal.

(It is normal when the numerical value is different each other.)

START

Is F901 normal?

Is IC901 Pin 3switching normally?

Is CN903 Pin 3 5.2V?

Does oscillate continuously when the CON903 is disconnected ?

IC901 Pin 3Normal switching waveform on the

stand-by mode at the AC110V

Check the GND of C901 andIC901 Pin 3 with oscilloscope.

When IC901oscillating

Secondary sideis abnormal.

Are D908, D909,D907, D910, D906and D905 normal?

Front Circuit Board is abnormal

Is CON903 Pin 3 5.2V?

(A)

Replacedefective

parts.

Replace Q908and Q909.

ReplaceIC902.

Check Q904and ZD903.

After connectCON903Pin 1 , 3 short.

Are CON902Pin 5 , 6 and

9 5V?

Is CON904Pin 3 8V?

Is CON902

Pin 3 12V?

Are CON903Pin 5 -24V, Pin 7 -20V and

Pin 8 -16V?

To (A).

A primary side is abnormal.

In condition of DC140V.(Feedback is abnormal)

Is IC905

normal?

Check orreplaceD908.

Are R922, C927, R921and R918 normal?

Is voltage ofBD901 140V?

Are R907, D902,D903 and R902

normal?

Are D901, R904,R905 and R906

normal?

Is PC901 normal?

Replace defectiveparts.

YES

YES

YES

YES

YES

YES

YES

YES

YES

YES

YES

YES

YES

YES

YES

NO

NO

NO

NONO

NO NO

NO

NO

NO

NO

NO

NO

NO

END

END

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2. -COM Circuit

A. No Power

POWER ON

Power RED LED on?NO

NO

NO

NO

NO

NO

NO

OK

NO

NO

NO

YES

YES

YES

11

YES

YES

YES

YES

OK

YES

YES

A

A

Refer to Front Part.

Does Bar appearat FLD?

Do all five Barsappear?

Does Logo appearon the screen?

Is oscillation of X101 normal?

Check the oscillation

Are IC107 Pin $ , and normal?

Check short.

Replace IC107or IC108.

Is CON107connected normally?

Check power.(Refer to power)

If power isnormal

Is CON107 Pin 6 normal?

Reconnect it.

Thewaveform on A [00:21]and D [00:15] of IC108

normal?

Check short

Are IC101Pin 7 , 8 normal?

Replace IC101.

Replace Main B/D.

Refer to Front Part

END

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50

AUDIO ABNORMAL

Check Audio jack.

Check PLL FC ofMPEG part.

Refer to Audio part.

Refer to MPEG part.

Replace B/D.

YES (If OK)

YES (If OK)

YES (If OK)

YES (If OK)

END

B. Audio abnormal C. Video abnormal

VIDEO ABNORMAL

Check Video jack.

Refer to Video part.

Refer to Encoder part.

Refer to MPEG part.

Replace B/D.

YES (If OK)

YES (If OK)

YES (If OK)

YES (If OK)

END

YES (If OK)

YES

YESYES

OPEN/CLOSE ABNORMAL

Check Front.

NO

NO

Check theconnection of

CON107.Reconnect it.

Check IC101Pin # , $ .

Check the connection of MD.

Refer to SERVO part.

D. Open/Close abnormal

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E. Picture abnormal

F. Disc Error

PICTURE ABNORMAL

Check the disc.

Refer to Servo part

Check PLL IC of MPEG part

Check DSP

Check MPEG

If OK

YES (If OK)

YES (If OK)

YES (If OK)

Replace B/D

END

DISC ERROR

Check Disc

Refer to Servo part

Replace B/D

YES (If OK)

YES (If OK)

END

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3. MPEG Circuit

Power is on

Does aiwa Logo appearon the screen?

Does themoving picture of the DVD Disc

play on the screennormally?

Does themoving picture of the video

CD play on the screennormally?

Does theaudio sound output

normally?

END

Check power & clock.

Is MPEG datasignal normal?

Is error signal normal?

Is MPEG datasignal normal?

I OPTION

If included VCD function.

Is Clock normal?

Does the audiosound output from MPEG

decoder?

Check CD/DVD DSPoutput signal.

Check MPEG Decoderinput signal.





Check clock signal

Check clock signal

B

A

C

D

E

F

G

H

I

YES

YES

YES

YESYES

YES

YES

YES

YES

NO

NO NO

OK

OK

OK

OK

NO

NONO

NO

NO

YES

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5. RF/Servo Circuit

A.

CHECK POINT (General)

Does signal goesHigh to IC206 Pin when

the power is on?

YES

NO

NO

NO NO

NO

YES

YES YES

YES

END

Does signalpulse input to IC206 Pin ,

when the poweris on?

Does TTLpulse output to IC206

Pin , ?

Is IC206

Pin , , , voltageabout 2.2V?

Check 2. -COM Part.

Does33.8688MHz clock input

to IC206 Pin ?

Replace IC206(IC206 soldering or IC defect).

Replace IC700(IC700 soldering or IC defect).

Replace X301 or IC308(30MHz clock defect)

5 8 5 9

194

1 40 1 42 63

83 84 88 89

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B.

END

NO

NO

NO

YES

YES

YES

NO

NO

NO

YES

YES

YES

No disc

Power on

Does tray openor close?

Fig-1. SLED Driver waveform

Does the pick-upslide inner or outer

track?

Fig-2. Focus Driver waveform

Does

the pick-up lens move upand down?

Slide the pick-up toinner track.

Check loading Part.

Push Pick-up to inner trackto the end by hand.

DoesCON202 Pin & change

high to low?

Pressingthe open/close key repeatedly,

check the voltage of CON202 Pin9 change 0V to 5V

Junction BoardDoes

the voltage change atIC401 Pin%, ^ more than 2V on the

basis of 4.5V?

DECK assembly is defective.

DECK assembly is defective.(Limit sw)

check -COM Part.

Replace IC401.

Check SLED Driver output.IC206 Pin IC401 Pins * , & .

IC206 Pin no output : IC206 is defectiveIC401 Pin * no output : IC401 is defective

Check Focus Driver output.(IC206 Pin , IC401 Pins ! , @)

IC206 Pin no output : IC700 is defectiveIC401 Pin 1 , 2 no output : IC701 is defective83

88

88

83

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C.

END

YES

YES

YES

YES

YES

NO NO

NO

YES

YES

NO

NO

NO NO

NO

YES

DISC IN

OPEN/CLOSE

FOCUS ON?

Does the disc turn?

IC206 Pin is High?

Is OK the track jump.

Does the screen appear?

Check the focus error moving thelens up and down. (IC201

Pin )

Does theTTL level change at IC206

Pin and movingthe lens?

Replace -COM or IC206.

Check CON404 Pin 4 , 6 Motor turn when the Pin 4 is

less than 1.6V

Video Par is defective.Check 5.MPEG Circuit.

Check 7.OSD/Video Circuit.

Check A

Fig-3. FOCUS ERROR waveform

Check IC201 Pin , , , in DVD ModeCheck IC201 Pin , , , in CD Mode

IC201 no output: Pick-up is defective.

Replace IC206.

Check IC206 and IC403 when the Pin 4 is abnormal

Does the signal

pulse input at IC700 Pin , and ?

-COM part is

defective. Check2. -COM Circuit.

Replace IC700.

52 53 54 55

58 59 60 61

78

169

132

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D.

NO NONO

NO

YES

YES YES YES

CHECK A

Fig-5. RFwaveform

Check RF Eye-Pattern.RF: 1.0-2.1V (IC201 Pin ) No signal: Pick-up is defective

Is the eye-pattern vivid?Does the

sawtooth waveform emitat IC201 Pin ) ?

Does the 1.6V emit? Replace IC201.

Replace IC206. Check IC206 Pin .

No signal at IC206: IC206 is defective

Check IC206 Pin Check the clock at the IC206

Pin , .

END

Both are normal: IC206 is defective

Check IC201 Pin , , , in DVD Mode.Check IC201 Pin , , , in CD Mode.

52 53 54 55

58 59 60 61

84

162

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VID2-7

VDD

GND

VIDCLK

VIDVALID

VIDVACT

VIDHACT

P0-P3

GND

VDDMAX

P4-P7

BLANK

VSYNC

HSYNC

FIELD

GND

VDD

Secondary video input port. Pixel data (TTL compatible) in 8-bit YCrCb format. A

higher index corresponds to a greater bit significance. Data on the VID port is latched

by rising edge of VIDCLK. (Connected to GND.)

Digital power.

Digital ground.

2x pixel clock for secondary video input port. Synchronization circuitry exists for this

port to lock it to the primary video port. (Connected to GND.)

Video data valid qualifier. A logical 1 indicates data on VID [7:0] is valid data. The

sense of this signal is controlled by the VIDVALIDI bit of register 0x1C. (Connected

to GND.)

Vertical active display region. The sense of this signal is controlled by the VIDVACTI

bit of register 0x1C. (Connected to GND.)

Horizontal active pixel signal. A logical 1 indicates data on VID [7:0] is in the

horizontal display region. The sense of this signal is controlled by the VIDHACTI bit

of register 0x1C. (Connected to GND.)

Primary video input port. TTL compatible pixel data in 8-bit YCrCb format. A higher

index corresponds to a greater bit significance. (1) Data is latched on the rising edge of

the system clock.

Digital ground. Refer to the PC Board Considerations section of this

This pin must be tied to the maximum digital input value. Use 3.3 V if only 3.3 V

inputs are used, and 5 V if 5 V inputs are used.

Primary video input port. TTL compatible pixel data in 8-bit YCrCb format. A higher

index corresponds to a greater bit significance. (1) Data is latched on the rising edge of

the system clock.

Composite blanking control input (TTL compatible). BLANK is registered on the

rising edge of the system clock. The P [7:0] inputs are ignored while BLANK is a

logical 0. The sense of this signal is controlled by the BLANKI bit of register 0x19.

Vertical sync input/output (TTL compatible). As an output (master mode operation),

VSYNC is output following the rising edge of the system clock. As an input (slave

mode operation), VSYNC is registered on the rising edge of the system clock. The

sense of this signal is controlled by the VSYNCI bit of register 0x19.

Horizontal sync input/output (TTL compatible). As an output (master mode

operation), HSYNC is output following the rising edge of the system clock. As an

input (slave mode operation), HSYNC is registered on the rising edge of the system

clock. The sense of this signal is controlled by the HSYNCI bit of register 0x19.

Field control output (TTL compatible). FIELD transitions after the rising edge of the

system clock, two clock cycles following falling HSYNC. The sense of this signal is

controlled by the FIELDI bit of register 0x19. The state of this pin at power-up

determines the default state of the PCLK_SEL register. If not loaded, this pin will be

pulled low with an internal pull-down resistor.Digital ground.

Digital power.

I

I

I

I

I

I

I

I

I/O

I/O

O

1-6

7

8

9

10

11

12

13-16

17

18

19-22

23

24

25

26

27

28

IC, BT861

Pin No. Pin Name I/O Description

IC DESCRIPTION

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29, 30

31-36

37

38

39, 40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

Alpha blend pins. Provides for 1-, 2-, or 4-bit external blend selection between video

and graphic overlay data. Signals are latched using the system clock. (Connected to

GND.)

Dedicated graphic overlay port. Pixel data (TTL compatible) in 8-bit YCrCb format.

Signals are latched using the system clock. (Connected to GND.)

Digital ground.

Digital power.

Dedicated graphic overlay port. Pixel data (TTL compatible) in 8-bit YCrCb format.

Signals are latched using the system clock. (Connected to GND.)

Analog ground.

Component chrominance U channel, component blue, or composite video.

Component chrominance V channel, component green, or composite video.

Component luminance, component red, or optional luma-delayed composite video.

AGND; the capacitor must be as close to the device as possible to keep lead lengths to

an absolute minimum.

Analog power.

This pin to VAA. The capacitor must be as close to the device as possible to keep lead

lengths to an absolute minimum. COMP1 is used with DACs A/B/C and COMP2 is

used with DACs D/E/F.

Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these

pins and AGND controls the full-scale output current on the analog outputs. For

standard operation, use the nominal values shown under Recommended Operating

Conditions. FSADJ2 controls DACs D/E/F.

Voltage reference pin.

Not used.

Analog ground.

Analog power.

Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these

pins and AGND controls the full-scale output current on the analog outputs. For

standard operation, use the nominal values shown under Recommended Operating

Conditions. FSADJ1 controls DACs A/B/C.Compensation pin.

Analog power.

DAC bias voltage.

Composite video.

Modulated chrominance video signal or optional luma-delayed composite video.

Luminance video or optional composite video.

Analog ground.

Digital ground.

Alternate slave address input (TTL compatible). A logical 1 corresponds to write

address of 0x88 and a read address of 0x89, while a logical 0 corresponds to a write

address of 0x8A and a read address of 0x8B. See the Serial Programming Interface

section for more detail. (Connected to GND.)

ALPHA0, 1

OSD0-5

GND

VDD

OSD6 ,7

AGND

DACF

DACE

DACD

VBIAS2

VAA

COMP2

FSADJ2

VREF

N/C

AGND

VAA

FSADJ1

COMP1

VAA

VBIAS1

DACC

DACB

DACA

AGND

GND

ALTADDR

I

I

I

O

O

O

I

O

I

O

O

O

O

I

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RESET

VDD

GND

PGND

XTI

XTO

VPLL

CLKO

CLKIN

VIDFIELD

TTXREQ

TTXDAT

SID

SIC

GNDVDD

VID0, 1

Reset control input (TTL compatible). Setting to zero resets both video timing

(horizontal, vertical, subcarrier counters to the start of VSYNC of first field) and the

serial control interface, and resets the registers. RESET must be a logical 1 for normal

operation.

Digital power. Refer to the PC Board Considerations section of this

Digital ground.

Dedicated ground for PLL.

Crystal input for genlock PLL. (Not used.)

Crystal output for genlock PLL. (Not used.)

Dedicated power supply for PLL. (Connected to VDD.)

2x pixel clock for the primary video port. Generated by PLL or pass-through from

CLKIN pin. (Not used.)

2x pixel clock input (TTL compatible).

Field indicator for video input port. A logical 1 indicates data is from an odd field. The

sense of this signal is controlled by the VIDFIELDI bit of register 0x1C. (Connected to

GND.)

Teletext request output (TTL compatible). (Connected to VDD.)

Teletext bit stream input (TTL compatible). (Connected to GND.)

Serial interface data input/output (TTL compatible). Data is written to and read from

the device via this serial bus.

Serial interface clock input (TTL compatible). The maximum clock rate is 400 kHz.

Digital ground.Digital power.

Secondary video input port. Pixel data (TTL compatible) in 8-bit YCrCb format. A

higher index corresponds to a greater bit significance. Data on the VID port is latched

by rising edge of VIDCLK. (Connected to GND.)

63

64

65

66

67

68

69

70

71

72

73

74

75

76

7778

79, 80

I

I

O

O

I

I

O

I

I/O

I

I

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1

2-4

5

6

7

8-11

12

13

14

15

16

17

18

19

20

21-26

27

28

2930

31-35

36

37

38

39

40

41

42

43-46

IC, CL61330


P100

HDATA0-2

VDD_3.3

HDATA3

VSS

HDATA4-7

VDD_2.5

RESET

VSS

/WAIT

/INT

VDD

/AMWE

VSS

HDATA8-13

VDD

HDATA14

VSSHDATA15

HADDR12-16

VDD

HADDR17

VSS

HADDR18

VDD

HADDR19

VSS

HADDR20-23

Programmable I/O pins.

8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via

HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes

the decoder internal registers and local SDRAM/ROM via HDATA [7:0].

3.3-V supply voltage for I/O signals.



the decoder internal registers and local SDRAM/ROM via HDATA [7:0].

Ground for core logic and I/O signals.



the decoder internal egisters and local SDRAM/ROM via HDATA [7:0].

2.5-V supply voltage for core logic.

Hardware reset. An external device asserts RESET (activeLOW) to execute a decoder

hardware reset. To ensure proper initialization after power is stable, assert RESET

for at least 20 ms.


Transfer not complete/data acknowledge. Active LOW to indicate host initiated

transfer is not complete. WAIT is asserted after the falling edge of CS and

reassertedwhendecoderis ready to complete transfer cycle. Open drain signal, must

be pulled-up via 1kW to 3.3 volts. Driven high for 10 ns before tristate.

Host interrupt. Open drain signal, must be pulled-up via 4.7kW to 3.3 volts. Driven

high for 10 ns before tristate.


Not used.


Programmable I/O pins. Input mode after reset.


Programmable I/O pins. Input mode after reset.

Ground for core logic and I/O signals.Programmable I/O pins. Input mode after reset.

Programmable I/O pins. Output mode after reset.









I/O

I/O

I/O

I/O

I

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

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VDD

BEO

VSS

NC

P101

MDATA15, 0

VDD

MDATA14

VSS

MDATA1, 13, 2

VDD_3.3

MDATA12

VSS

MDATA3

VDD

MDATA11

VSS

MDATA4

VDD

MDATA10

VSS

MDATA5, 9, 6

VDD

MDATA8

VSS

MDATA7

LDQM

UDQM

VDD

/MWE

VSS

SD-CLK

/SD-CAS

/SD-RAS

VDD

SD-CS1

VSS

SD-CS0

VDD

NC




No Connection


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.

SDRAM LDQM.

SDRAM UDQM.


SDRAM write enable. Decoder asserts active LOW to request a write operation to the

SDRAM array.


SDRAM system clock.

Active LOW SDRAM column address.

Active LOW SDRAM row address.


Active LOW SDRAM bank select.


Active LOW SDRAM bank select.


No Connection.


47

48

49

50, 51

52

53, 54

55

56

57

58-60

61

62

63

64

65

66

67

68

69

70

71

72-74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

I/O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

O

O

O

O

O

O

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VSS

NC

VDD

MADDR9

VSS

MADDR1, 8, 10

VDD

MADDR7

VSS

MADDR0, 8, 1

VDD

MADDR5

VSS

MADDR2, 4, 3

VDD

MADDR12

VSS

MADDR13

VDD

MADDR14

VSS

MADDR15-17

VDD

MADDR18

VSS

MADDR19, 20

/ROM_CS

P102

NC

VDD

P103

VDD

VSS

VDD

P104

VDD

P105

VDATA0, 1

VDD


93

94

95

96

97

98-100

101

102

103

104-106

107

108

109

110-112

113

114

115

116

117

118

119

120-122

123

124

125

126, 127

128

129

130

131, 132

133

134, 135

136

137

138

139, 140

141

142, 143

144


No Connection


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address. (Not used.)


Memory address. (Not used.)

Open drain signal, must be pulled-up via 4.7kW to 3.3 volts.


No Connection.









Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up, the

decoder does not drive VDATA. During boot-up, the decoderuses configuration

parameters to drive or 3-state VDATA.


O

O

O

O

O

O

O

O

O

O

O

O

O

O

I/O

O

I/O

I/O

I/O

O

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VDATA2

VSS

P105

VDATA3

VDD

VDATA4

VSS

VDATA5

P107

VDATA6, 7

P108

/HSYNC

/VSYNC

DA-IEC

VDD

DA-DATA0

VSSDA-DATA1-3

DA-LRCK

DA-BCK

VDD

DA-XCK

VSS

DAI-DATA

DAI-LRCK






















Horizontal sync. The decoder begins out putting pixel data for a new horizontal line

after the falling (active) edge of HSYNC.

Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the

first HSYNC after the falling edge of VSYNC. VSYNC can accept vertical

synchronization or top/bottom field notification from an external source. (VSYNC

HIGH = bottom fie

Bitstream data in IEC-1937 or PCM data out in IEC-958 format.


PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.

Ground for core logic and I/O signals.PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.

PCM left-right clock. Identifies the channel for each audio sample. the polarity is

programmable.

PCM bit clock. Divided by 8 from DA-XCK, DA-BCK can be either 48 or 32 times

the sampling clock.


Audio master frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK

can be either 384 or 256 times the sampling frequency.


PCM input data, two channels. Serial audio samples relative to DAI-BCK clock.

PCM input left-right clock.

O

I/O

O

O

O

I/O

O

I/O

I/O

I/O

O

O

O

O

O

I/O

I

I


145

146

147

148

149

150

151

152

153

154, 155

156

157

158

159

160

161

162163-165

166

167

168

169

170

171

172

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DAI-BCK

P109

CLKSEL

A_VDD

VCLK

SYSCLK

A-VSS

DVD-DATA0/CD-

DATA

VDD

DVD-DATA1/CD-

LRCK

VSS

DVD-DATA2/CD-

BCK

DVD-DATA3/CD-

C2PO

DVD-DATA4/

CDG_SDATA

PI101

VREQUEST

VSTROBE

VDD

AREQUEST

VSS

V-DACK/ASTROBE

VDD

I

I/O

I

I

I

I

I

I

I

I

I/O

O

I

O

I

PCM input bit clock.


Clock Select: Internal = VDD, External = VSS

3.3-V analog supply voltage.

Video clock. Clocks out data on input. VDATA [7:0]. Clock is typically 27 MHz.

System clock. Decoderrequires an external 27MHz TTL oscillator. Drive with the

same 27-MHz as VCK.

Analog ground for PLL.

Serial CD data. This pin is shared with DVD compressed data DVD-DATA0. ERROR

200 I Error in input data. If ERROR signal is not available from the DSP it must be

grounded.


Programmable polarity 16-bit word synchronization to the decoder (right channel

HIGH). This pin is shared with DVD compressed data DVD-DATA1.


CD bit clock. Decoder acceptmultipleBCKrates. This pin is shared with DVD

compressed data DVD-DATA2.

Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture

on-screen until the next valid picture is decoded. This pin is shared with DVD

compressed data DVD-DATA3.

DVD parallel compressed data from DVD DSP. When DVD DSP sends 32-bit words,

it must write theDVD-DATA5/CDG_VFSY MSB first. CDG-SDATA: CD+G (Subcode) Data.

DVD-DATA6/CDG_SOSI Indicates serial subcode data input.

DVD-DATA7/CDG_SCLK CDG-VSFY: CD+G (Subcode) Frame Sync. Indicates

frame-start or composite synchronization input. CDG-S0S1: CD+G (Subcode) Block

Sync. Indicates block-start synchronization input. CDG-SCLK: CD+G (Subcode)

Clock. Indicates subcode data clock input or out-put.


Video request. Decoder asserts VREQUEST to indicate that the video input buffer has

available space. Polarity is programmable.Video strobe. Programmable dual mode pulse. Asynchronous and synchronous. In

Asynchronous mode, anexternal sourcepulses VSTROBE to indicate data is ready for

transfer. In synchronous mode VSTROBE clocks data.


Audio request. Decoder asserts AREQUEST to indicate that the audio input buffer has

available space. (Not used.)


In synchronous mode, Video data acknowledge. Asserted when DVD data is valid.

Polarity is programmable. In asynchronous mode, data strobing for audio bit streaminput.


173

174

175

176

177

178

179

180

181

182

183

184

185

186-189

190

191

192

193

194

195

196

197

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198

199

200

201

202-204

205

206

207

208

A-DACK

VSS

HOST&SEL

HADDR0-2

DTACKSEL

/CS

R/W

/RD

I

I

I

I

I

I

I

Audio data acknowledge.


Pull up.

Host address bus. 3-bit address bus selects one of eight host interface registers.

Tie HIGH to select WAIT signal, LOW to select DTACK signal (Motorola 68K

mode).

Host chip select. Host asserts CS to select the decoder for a read or write operation.

The falling edge of this signal triggers the read or write operation.

Read/write strobe in M mode. write strobe in I mode. Host asserts R/W LOW to select

write and

Read strobe in I mode. Must be held HIGH in M Mode LOW to select Read.

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1-16

17

18-21

22

23-27

28

29

30

31

32

33

34

35

36

37

38

39-45

46

47-52

53-56

57

58

59

60

61

62

63

64

65

66-68

69

70

71

72

73

74

75

76

77

78

79

IC, GDC25D801


DAT1-16

VSS

ADD1-4

VDD

ADD5-9

X2_MCK

VSS

MCK

VDD

RAS

UCAS

LCAS

WE

OE

SCAN_IN

TEST_SE

TEST_OUT12-6

T_SEL

TEST_OUT5-0

TEST_SEL0-3

TESTSERVO

E_SIN

E_CLK

E_ENB

E_DRB

VSS

SERVO CLK

E_SOUT

VDD

E_ST0-2

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

VSS

SENS

VDD

Bi-directional data to DRAM.

Digital GND.

Address output to DRAM.

Digital power supply.

Address output to DRAM.

Master clock from oscillator for 2x decoding.

Digital GND.

Master clock from oscillator.


Row address strobe to DRAM.

Column address upper byte control strobe to DRAM.

Column address lower byte control strobe to DRAM.

Write enable signal to DRAM.

Output enable signal to DRAM.

Scan data input (Not used.)

Test mode selection (low for normal) (Connected to GND.)

Test output (Not used.)

Test selection : 0 for normal.

Test output (Not used.)

Test mode output selection.

TEST PIN (NORMAL STATE = H ) (Connected to VDD.)

SERVO DSP PGM. DOWNLOADING DATA INPUT.

SERVO DSP PGM. DOWNLOADING CLK.

SERVO DSP DOWNLOADING ENABLE.

SERVO DSP PGM. DOWNLOADING DIRECTION.

Digital GND.

SERVO DSP CLOCK INPUT.

SERVO DSP PGM. DOWNLOADING DATA OUTPUT.


SERVO DSP DOWNLOADING STATUS 0-2.

SERVO DSP GENERAL I/O: FSON (FOCUS OK INVERTING).

SERVO DSP GENERAL I/O: PSEL.

SERVO DSP GENERAL I/O: ADADDR3 (Not used.)

SERVO DSP GENERAL I/O: FKRST (Not used.)

SERVO DSP GENERAL I/O: FKSET (Not used.)

SERVO DSP GENERAL I/O: FEL (Not used.)

SERVO DSP GENERAL I/O.

SERVO DSP GENERAL I/O: DSP_SENSE.

Digital GND.

SERVO DSP INTERNAL STATUS MONITOR.


I/O

O

I

O

I

I

O

O

O

O

O

I

I

O

I

O

I

I

I

I

I

I

I

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

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80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106-111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

Serial Command CLOCK.

Serial Command DATA.

Serial Command LATCH.

TDF.

TDF.

Analog power supply for ADC.

TDF.

Analog GND for ADC.

TDF.

TDF.

Digital GND for ADC.

TDF (Connected to VREF.)

Digital power supply for ADC.

Analog GND for ADC.

TDF.

TDF.


Analog GND for ADC.


TDF.

Analog power supply for ADC.

TDF.

TDF.

TDF.


PLL clock output.

ADC data input (Not used.)

EFMDATA INPUT SELECTION (Connected to GND.)

SUB DATA REQUEST INPUT (Not used.)

SUB Q DATA REQUEST.

5.6448 MHz (DIGITAL OUT CLOCK) (Not used.)

CD DIGITAL DATA OUTPUT (Not used.)


SUB Q DATA OUTPUT.

Digital GND.

PWM CHANNEL1 (x3 CARRIER).

PWM CHANNEL1 (x3 CARRIER).

PWM CHANNEL1 (x3 CARRIER): SLED DRIVE OUTPUT.

PWM CHANNEL1 (x1 CARRIER): PDO_CTR PWM OUTPUT.

PWM CHANNEL1 (x1 CARRIER): RF_GAIN_CTL PWM OUTPUT.

PWM CHANNEL1 (x1 CARRIER): TE_BAL_CTL PWM OUTPUT.

SCLK

SDATA

XLAT

AOUT1

AOUT2

AVDD

VCM

AGND

AOUT3

AOUT4

DGND

RFVCM

DVDD

AGND

VREFN

VREFP

INP

AGND

AIN4

AIN3

AVDD

AIN2

AIN1

AIN0

ADCVCM

SCK

EXT_AD0-5

SELEFM

EXCK

SQCK

C16M

DOTX

VDD

SQSO

VSS

PWMCH1

PWMCH2

PWMCH3

PWMCH4

PWMCH5

PWMCH6

I

I

I

O

O

I

O

O

I

I

I

I

I

I

I

I

I

I

O

I

I

I

I

O

O

O

O

O

O

O

O

O

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Interrupt request to Host.

Read strobe from HOST.

Write strobe from HOST.

Chip select from HOST.

Internal register address from HOST.

Digital GND.

Bi-directional data to HOST.


Bi-directional

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