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Advanced Methods for Steady-State Analysis and Design of Switching Power Converter Systems
by
Martin Plesnik
A thesis submitted to the Faculty of Graduate and Postdoctoral Affairs in
partial fulfillment of the requirements for the degree of
Doctor of Philosophy
in
Electrical and Computer Engineering
Ottawa-Carleton Institute for Electrical and Computer Engineering
Department of Electronics
Carleton University
Ottawa, Ontario, Canada
© 2016
Martin Plesnik
ii
Abstract
Current development trends in the area of switching power converters such as rising
integration, increasing power density, and the growing complexity of power converter
systems have indicated a strong need for a new class of simulation tools which would
allow for a complex approach to solve the problems of converter analysis and design.
Such an approach, besides being a fast and accurate simulation of the switching
waveforms of the converter, should also include an overall analysis of converter behavior
in response to changes in operating conditions, a search for extreme values of internal
variables of the converter circuit, computation of power dissipated by particular devices,
calculation of efficiency, ac analysis, sensitivity analysis, and design optimization. The
role of determining the steady-state with the resulting algorithms is crucial.
Research in the area of numerical analysis of switching power converter circuits has
been traditionally focused on the operation of a single power converter. However,
growing demand for integrated high-power-density solutions requires this analysis to
expand beyond the domain of one converter and capture the interaction of all power
converters in the network.
In order to better address the needs of development and practical design, this thesis
presents alternative simulation techniques which can be used for the analysis of networks
consisting of multiple switching converters. The focus of this work is the area of steady-
state analysis. Two new methods for the efficient determination of switching power
converter steady-state are presented. These new methods simplify the algorithm structure
by reducing the number of iteration loops and effectively address the convergence issues
iii
seen with published methods. Furthermore, the proposed algorithms are extended to
cover the area of networks with multiple switching converters. Particular focus is on the
development of general methods for the modeling and simulation of networks with
multiple switching power converters in both the time-domain and frequency-domain.
iv
Dedication
To the living memories of my father, one of the best engineers who I have ever known
and whose life has become an example and inspiration for me. I also dedicate this thesis
to my mother for her unconditional love, my wife Jana for her kindness, endless patience,
and support, and to my children Eva and Tom for being with me even when I was not at
home.
v
Acknowledgements
Foremost, I would sincerely like to express my gratitude to my supervisor, Professor
Michel Nakhla for his understanding, inspiration, and encouragement through the course
of my research work as well as for his wise guidance during the writing of my thesis.
I am sincerely grateful to professors Emad Gad, Xiaoyu Wang, Ram Achar, Ihsan Erdin,
and Gerry Moschopoulos for their comments which helped to make this thesis better.
I would like to express appreciation to my colleague Dr. Behzad Nouri for his advice and
useful comments when preparing for my thesis presentation. My thanks also belong to
Tom Plesnik for his help with editing my thesis.
Finally, I am thankful to the staff at the Department of Electronics at Carleton University
for having been so helpful, supportive, and resourceful.
Thank you very much, everyone!
vi
Table of Contents
Abstract .............................................................................................................................. ii
Dedication .......................................................................................................................... iv
Acknowledgements ............................................................................................................ v
Table of Contents .............................................................................................................. vi
List of Tables ...................................................................................................................... x
List of Figures ................................................................................................................... xi
List of Symbols ................................................................................................................. xv
List of Acronyms............................................................................................................. xvi
1 Introduction .................................................................................................................... 1
1.1 Motivation ................................................................................................................. 1
1.2 Contributions ............................................................................................................. 4
1.3 Organization of the Thesis......................................................................................... 5
2 Background and Preliminaries ..................................................................................... 8
2.1 Description of a Distributed Power Converter System ............................................. 8
2.2 High-Level Model of the Power Converter System .................................................. 9
2.3 Problem Formulation ............................................................................................... 10
2.4 Summary.................................................................................................................. 16
3 Modeling Networks with Switching Power Converters – Basic Concepts .............. 17
3.1 Introduction ............................................................................................................. 17
3.2 Device Model Selection .......................................................................................... 17
3.3 Formulation of the Network Equation ..................................................................... 25
3.3.1 Formulation of Network Equation Using the MNA method ............................ 25
vii
3.3.2 Formulation of a Piecewise Linear Network Equation Using the MNA
Method ....................................................................................................................... 27
3.3.3 Formulation of a Piecewise Linear Network Equation Using Oriented
Graphs........................................................................................................................ 30
3.4 Solution of the Network Equation ........................................................................... 32
3.4.1 Solution of a Non-Linear Network Equation ................................................... 32
3.4.2 Solution of a Piecewise Linear Network Equation Using Numerical
Integration.................................................................................................................. 34
3.4.3 Solution of a Piecewise Linear State-Space Network Equation ....................... 39
3.5 Summary.................................................................................................................. 45
4 Steady-State Determination Methods ......................................................................... 47
4.1 Introduction ............................................................................................................. 47
4.2 Methods of Accelerated Convergence ..................................................................... 48
4.2.1 Concept ............................................................................................................. 48
4.2.2 Accelerated Convergence for MNA Formulation ............................................ 51
4.2.3 Accelerated Convergence for State-Space Formulation ................................... 52
4.3 Sampled-Data Modelling Methods.......................................................................... 55
4.3.1 Concept ............................................................................................................. 55
4.3.2 Accurate Sampled-Data Steady-State Modelling ............................................. 61
4.4 Summary.................................................................................................................. 62
5 Time-Interval Approach in Periodic System Steady-State Determination ............. 65
5.1 Introduction ............................................................................................................. 65
5.2 Concept .................................................................................................................... 66
viii
5.3. Time Vector Computation Based on the State-Space Averaging Technique ......... 73
5.3.1 Principles of the Method .................................................................................. 73
5.3.2 Computation Milestones ................................................................................... 79
5.3.3 Error Function and Jacobian Matrix Generalization ........................................ 87
5.3.4 Numerical Verification ..................................................................................... 89
5.4 Time Vector Computation Based on Generalized Constraint Conditions ............... 97
5.4.1 Principles of the Method .................................................................................. 97
5.4.2 Computation Milestones ................................................................................. 103
5.4.3 Numerical Verification ................................................................................... 109
5.5 Summary................................................................................................................ 118
6 Generalized Steady-State Method for Networks with Multiple Switching Power
Converters ...................................................................................................................... 119
6.1 Introduction ........................................................................................................... 119
6.2 Principles of the Method ....................................................................................... 120
6.2.1 Constraint Equation Derivation ...................................................................... 123
6.2.2 Error Function Definition ............................................................................... 129
6.2.3 Computation of the Jacobian Matrix .............................................................. 130
6.3 Numerical Verification .......................................................................................... 131
6.4 Summary................................................................................................................ 145
7 Steady-State Determination of Switching Power Converter Networks using
Harmonic Balance ......................................................................................................... 146
7.1 Introduction ........................................................................................................... 146
7.2 Principles of the Method ....................................................................................... 148
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7.2.1 Basic Concept ................................................................................................. 148
7.2.2 Fourier Series Expansion of the Switching Waveforms ................................. 151
7.3 Steady-State Analysis ............................................................................................ 155
7.4 Steady-State Determination for Networks with Multiple Switching Converters .. 159
7.4.1 Determination of the Steady-State for Networks with Converters Connected in
Parallel ..................................................................................................................... 159
7.4.2 Determination of the Steady-State for Networks with Converters Connected
in Series ................................................................................................................... 164
7.5 Determination of the Steady-State for Networks with Switching Converters
Operating with Unknown Switching Times ................................................................ 168
7.6 Numerical Verification .......................................................................................... 173
7.7 Summary................................................................................................................ 186
8 Conclusions and Future Work .................................................................................. 188
8.1 Summary................................................................................................................ 188
8.2 Future Work........................................................................................................... 190
References ...................................................................................................................... 192
Appendix A Matrix R in Section 7.2.2 ....................................................................... 204
Appendix B Input Vectors , , and in Section 7.3 ................................... 206
Appendix C Derivation of Operators and in Section 7.3............................ 207
Appendix D Matrices and in Section 7.3. ....................................................... 215
Appendix E Definition of Operators in Section 7.4.1 ......................................... 216
Appendix F Definition of Operators in Section 7.4.2 .......................................... 217
x
List of Tables
Table 5.1: Steady-state time intervals. .............................................................................. 90
Table 5.2: Output voltage and steady-state time determination time. ............................... 90
Table 5.3: Average output voltage vs. iteration number for DCM boost converter. ......... 93
Table 5.4: Average output voltage vs. iteration number for ACR forward converter. ...... 95
Table 5.5: ACR forward converter output voltage and state variables at steady-state...... 96
Table 5.6: Output voltage and steady-state determination time. ..................................... 110
Table 5.7: Output voltage and computation time. ........................................................... 117
Table 6.1: Network switching table. ................................................................................ 126
xi
List of Figures
Figure 2.1: High-level model of distributed power system. .............................................. 10
Figure 2.2: Voltages and currents in power converter network ........................................ 12
Figure 3.1: Transformer model with parasitic parameters. ............................................... 19
Figure 3.2: Model of output inductor with parasitic parameters. ...................................... 21
Figure 3.3: Model of a power MOS FET transistor. ......................................................... 23
Figure 3.4: Model of a capacitor with parasitic parameters. ............................................. 24
Figure 3.5: Closed-loop buck converter. ........................................................................... 26
Figure 3.6: Open-loop buck converter with ideal switches. .............................................. 27
Figure 3.7: Switching functions. ....................................................................................... 28
Figure 3.8: Buck converter topologies. ............................................................................. 28
Figure 3.9: Buck converter graphs. ................................................................................... 30
Figure 3.10: Switching time determination. ...................................................................... 37
Figure 3.11: State vector and switching function with the converter’s i-th topology. ...... 41
Figure 3.12: Waveform of inductor current during start-up transient. .............................. 43
Figure 4.1: Network sampled-data trajectory. ................................................................... 56
Figure 5.1: Transient trajectory of a closed-loop converter circuit. .................................. 67
Figure 5.2: Inductor current in a DCM buck converter circuit.......................................... 78
Figure 5.3: DCM buck converter....................................................................................... 89
Figure 5.4: DCM buck converter output voltage............................................................... 91
Figure 5.5: Inductor current in DCM buck converter........................................................ 92
Figure 5.6: DCM boost converter. ..................................................................................... 93
Figure 5.7: Error functions. ............................................................................................... 94
xii
Figure 5.8: ACR forward converter................................................................................... 95
Figure 5.9: Error as a function of initial guess. ............................................................... 107
Figure 5.10: Closed-loop DCM buck converter. ............................................................. 110
Figure 5.11: DCM buck converter output voltage trajectory. ......................................... 111
Figure 5.12: Error trajectory. ........................................................................................... 112
Figure 5.13: Error trajectory with a sampled-data method.............................................. 113
Figure 5.14: Error trajectory with the GCC method........................................................ 113
Figure 5.15: Closed-loop ZCS buck converter. ............................................................... 114
Figure 5.16: Error norm trajectory. ................................................................................. 115
Figure 5.17: Sampled-data method error trajectory. ....................................................... 116
Figure 5.18: Proposed GCC method error trajectory. ..................................................... 116
Figure 5.19: Closed-loop ZCS buck converter steady-state waveforms. ........................ 117
Figure 6.1: Network with multiple switching converters. ............................................... 121
Figure 6.2: Network state evolution at periodic steady-state. ......................................... 122
Figure 6.3: Network with two switching converters. ...................................................... 125
Figure 6.4: Switching times in network with two switching converters. ........................ 126
Figure 6.5: Network state vector evolution at periodic steady-state. .............................. 127
Figure 6.6: Experimental network with switching converters. ........................................ 132
Figure 6.7: Synchronization schemes. ............................................................................. 133
Figure 6.8: Error trajectory for a network with weak coupling between converters. ...... 137
Figure 6.9: Error trajectory for network with strong coupling between converters. ....... 137
Figure 6.10: Common node voltage ripple. ..................................................................... 139
Figure 6.11: Source current. ............................................................................................ 139
xiii
Figure 6.12: POL1 converter input current. .................................................................... 141
Figure 6.13: POL1 converter input current by commercial simulator. ........................... 141
Figure 6.14: POL2 converter input current. .................................................................... 142
Figure 6.15: POL2 converter input current by commercial simulator. ........................... 142
Figure 6.16: POL1 converter output voltage and inductor current. ................................ 143
Figure 6.17: POL1 converter output voltage and inductor current by commercial
simulator. ................................................................................................................. 143
Figure 6.18: POL2 converter output voltage and inductor current. ................................ 144
Figure 6.19: POL2 converter output voltage and inductor current by commercial
simulator. ................................................................................................................. 144
Figure 7.1: Buck converter with ideal switches. ............................................................. 148
Figure 7.2: Buck converter switching waveforms. .......................................................... 149
Figure 7.3: Buck converter model. .................................................................................. 150
Figure 7.4: Network of converters connected in parallel. ............................................... 160
Figure 7.5: Model of converters connected in parallel. ................................................... 161
Figure 7.6: Network of converters connected in series. .................................................. 164
Figure 7.7: Model of converters connected in series. ...................................................... 165
Figure 7.8: Model of a converter with unknown switching times. .................................. 169
Figure 7.9: Closed-loop CCM boost converter. .............................................................. 174
Figure 7.10: Trajectory of in the closed-loop circuit simulation. .............................. 175
Figure 7.11: Output voltage waveform of the CCM boost converter.............................. 176
Figure 7.12: Inductor current waveform in the CCM boost converter. ........................... 176
Figure 7.13: Experimental circuit for numerical verification. ......................................... 177
xiv
Figure 7.14: Model of the experimental circuit. .............................................................. 178
Figure 7.15: p1 and p2 trajectory. ..................................................................................... 179
Figure 7.16: POL1 converter input current. .................................................................... 180
Figure 7.17: POL2 converter input current. .................................................................... 180
Figure 7.18: POL1 converter output voltage. .................................................................. 181
Figure 7.19: POL2 converter output voltage. .................................................................. 181
Figure 7.20: Network of four converters connected in parallel. ...................................... 183
Figure 7.21: Error norm trajectory. ................................................................................. 184
Figure 7.22: Output voltage ripples. ................................................................................ 184
Figure 7.23: Inductor currents. ........................................................................................ 185
Figure 7.24: iC0 and iC4 currents. ..................................................................................... 185
Figure 7.25: iC0 and iC4 currents by commercial simulator. ............................................ 186
xv
List of Symbols
A characteristic matrix in circuit state-space representation
b input vector or matrix in circuit state-space and MNA representation
C capacitance and inductance matrix in circuit MNA representation
cT, d output vectors or matrices in circuit state-space representation
D, d(t) duty ratio, duty ratio function
E error function
F non-linear term in circuit MNA representation
Fsw switching frequency
G admittance matrix in circuit MNA representation
h integration step, discrete system sampling period
J Jacobian matrix
k number of harmonics
P, Q, R transformation matrices with the harmonic balance method
correlation operator with the harmonic balance method
T switching time vector
Tsw switching period
U, u(t) constant and time-varying input vector in state-space equation formulation
Vg, Vin input voltage
vo output voltage
X, x(t) state vector in state-space equation formulation, nodal vector in MNA
equation formulation
y output vector in state-space equation formulation
xvi
List of Acronyms
ACR active clamp reset
CCM continuous conduction mode
DCM discontinuous conduction mode
ESR effective series resistance
FB feedback
FD frequency domain
GCC generalized constraint condition
MNA modified nodal analysis
POL point of load switching power converter
SMPS switch-mode power supply
SR synchronous rectifier
SSA state-space averaging
TD time domain
ZCS zero-current switching
1
Chapter 1
Introduction
1.1 Motivation
Research in switching power converter circuit theory has been traditionally focussed on
the operation of a simple power converter circuit. Power converter circuits have been
represented by small networks reduced to the minimum number of components needed to
preserve the power conversion concept of a particular converter topology. The reduced
circuit can be referred to as a power converter core circuit or power train.
In practical design, the converter power train represents only a small part of the
switching power converter circuit. Typical additions are various types of controllers
ensuring that the converter output voltage meets regulation targets. Other additions to the
converter circuit are input and output low pass filters which are usually needed to obtain
acceptable ripple characteristics, protection circuits, and circuits executing specific
2
functions driven by an application or user requirements. In industrial applications, the
connection between converter output and the load device is made using various
interconnection means including PCB tracks and shapes, cables, and connectors. Most
importantly, the power supply systems in today’s applications consist of multiple
switching converters while requiring additional circuits ensuring system stability, system
protection, EMI control, and a variety of application specific features. Thus, the resulting
overall network is prohibitively large and complex.
Use of Spice-like simulators for the analysis of switching converter networks is
possible however it has several practical limitations such as long simulation times and a
narrow offer of simulation analyses. Also, several authors refer to convergence problems
when simulating switching power converter circuits ([1], [2]). Methods which are well
established in circuit theory such as the shooting method ([3] - [5]), harmonic balance
([6] - [9]) method, and envelope following method ([10] - [12]) can be used for the
simulation of networks with switching power converters as well. These methods allow for
implementation of detailed models of switching power converter components allowing
for accurate time-domain analysis including detailed modeling of switching transitions.
However, the converter behaviour at switching instants is strongly non-linear and,
consequently, the modeling of transients at switching transitions using detailed device
models becomes expensive in terms of simulation time. As the number of switching
devices in the network increases, the time needed for handling the switching transitions
grows, extending the simulation time significantly. To overcome the problem of long
simulation time caused by the strongly non-linear operation of a converter in the instants
3
of switching, the piecewise linear modeling approach can be adopted. Using this
approach, the converter switching devices are replaced by ideal switches and the non-
linear network equation of the converter is replaced by a set of linear equations. In fact,
this approach to the analysis of switching power converters has created the base for the
development of a majority of methods used in the theory of switching power converters.
Work showing the internal nodal voltages and currents of switching power converter
in networks consisting of two or more converters is rare to find. Poor visibility of general
methods for the formulation of the network equation in the area of switching power
converter theory is one of the reasons. Formulation of a network equation for a reduced
switching power converter circuit, i.e. power train, typically requires manipulation of
simple equations derived using Kirchhoff’s laws of current and voltage. This method for
the formulation of network relationships is dominant in the area of switching power
converter theory. With large networks, however, this approach will not be effective and
may even fail.
Analysis of the simultaneous operation of switching converters is usually approached
by the macro-modeling technique. However, macro-models for switching power
converters are frequently derived using approximation or averaging over the converter
switching period, which prevent them from being accurate at higher frequencies.
Consequently, detailed simulation of the power converter internal nodal voltages and
currents using these types of macro-models is practically not possible.
To address the issues which were listed above, the objective of this thesis is to
develop efficient CAD methods which are applicable to the analysis of large networks
4
with multiple switching power converters. Particular focus is on the area of steady-state
analysis and simulation of the DC/DC power converter applications.
1.2 Contributions
The main contributions of this thesis are as follows:
1. Development of a steady-state method based on the time-interval concept having
constraint equations formulated using the state-space averaging technique ([13] -
[15], section 5.3). This method simplifies the algorithm structure by reducing the
number of iteration loops. Other advantages of this method are convergence
robustness and increased simulation speed.
2. Development of a steady-state method based on the time-interval concept
deploying a generalized approach to the formulation of the constraint equations
([16], section 5.4). Similar to the first method, the number of iteration loops is
reduced. The additional advantages are in simulation accuracy and general
applicability on switching power converter topologies.
3. Development of a generic simulation method for networks with multiple
switching power converters ([17], Chapter 6). The solution for the steady-state
determination of a network with one converter is extended to the steady-state
determination of a network consisting of multiple converters. Operation of a
network with multiple switching converters is modeled using a single piecewise
linear equation. The network constraint equation is formulated using exact
5
analytical expressions for circuit variables of particular converters included in the
network. The advantages of this method are in simulation accuracy and increased
speed.
4. Development of a new method for networks with multiple switching power
converters based on harmonic balance. The converter switches are replaced by
current and voltage sources generating switching waveforms identical to those
which are present in a circuit with switches. Consequently, the switching
converter can be represented by a system consisting of small linear sub-circuits
with periodic non-sinusoidal inputs which are correlated with the voltages and
currents in adjacent sub-circuits. Advantages of this method are in substantial
simplification of the derivation of the network equation for large converter
systems.
1.3 Organization of the Thesis
This thesis is organized as follows. Chapter 2 covers background for the thesis work
using power converter system examples which can be found in telecommunication and
data storage applications. A high level diagram extracting the power subsystem from a
real system is included. Problems of practical design and the resulting problems of
numerical analysis are summarized.
6
Chapter 3 first gives an overview of the device model selection. Then, techniques which
can be used to formulate a system equation for networks with switching power converters
are presented. Methods for solving network equations are included.
Chapter 4 describes methods for the steady-state simulation of networks with one
switching converter. Frequently referred methods are described in detail.
In Chapter 5, a time-interval approach for solving the switching power converter steady-
state determination problem is presented. A new approach to the formulation of the
constraint equation is introduced. Two new methods are presented. With the first method,
the constraint equation is formulated using the state-space averaging technique. With the
second method, the constraint equation is formulated using a generalized set of switching
conditions. The convergence properties of both methods are discussed and the method for
making the initial guess is formulated.
Chapter 6 introduces a general method for the steady-state simulation of networks with
multiple switching converters. Methodology used for a network with one switching
converter is extended to networks with multiple converters.
Chapter 7 presents a new method for networks with multiple switching power converters
based on the concept of harmonic balance. The principles of this method are explained
7
using the example of a single converter. Then, this method is applied on networks of
converters operating in parallel and in series.
Finally, Chapter 8 summarises the proposed work, provides concluding remarks, and
outlines directions of future research.
8
Chapter 2
Background and Preliminaries
2.1 Description of a Distributed Power Converter System
Current trends in the power electronics application area are progressing towards the
deployment of power distribution networks consisting of a large number of switching
power converters. Many examples can be found in data processing and data storage
systems, telecommunication systems (e.g. [18], [19]), mobile devices, and in space and
automobile applications.
Analysis of telecommunication equipment provides a good example of a distributed
power system. A typical telecommunication equipment system consists of multiple
boards fulfilling a variety of system functions. Some of them operate with system data
(data processing, storage, transmitting, and receiving), and some of them provide system
support (e.g. cooling, protection). Boards are interconnected using backplane boards or
9
motherboards. Individual interconnects may be realized using a variety of connector
types and cables. Each board may accommodate several power converters. Each power
converter has its input and output connected to passive networks, usually low-pass filters.
Power converters located on the same board frequently share a common front-end circuit
consisting of a passive EMI filter and variety of power management circuits. Load to the
power converters is complex, and can include simple devices (e.g. signalling LED), fans,
heating and cooling units, high-speed microprocessors, memory circuits, FPGA devices,
phase-locked circuits, and radio-frequency power amplifiers.
2.2 High-Level Model of the Power Converter System
In principle, the distributed power system can be seen as a serial-parallel network
consisting of power converters which are interconnected using passive sub-circuits. An
example of a high-level model of a distributed power converter system is shown in Fig.
2.1. In this figure, is the system input voltage, terms stand for power
converters, designate passive low-pass filters, and are used to designate
load of individual power converters.
10
Figure 2.1: High-level model of distributed power system.
2.3 Problem Formulation
The usual approach to analyze the operation of a power converter in design practice is to
isolate the converter from the network and treat it as an independent circuit while
assuming that its input is an ideal source of voltage and its load is either a linear resistor
11
or an ideal constant current source. In a power converter network however, converter
input and output voltages and load current depend on the operation of the rest of the
network. This especially applies to a network consisting of multiple switching power
converters. In these cases, due to the switching nature of power converters, large
disturbances can be generated by a converter to its input and output, affecting its
performance. In addition, performance of the adjacent converters may be affected as well.
Therefore, to analyze a power converter operating in a large network, there is a need to
treat this converter as a part of the network and to find a solution for the entire network.
An example showing the need to treat a switching converter as an integrated part of
the network is illustrated in Fig. 2.2. The voltage in node N depends on the current
flowing from the output of the front-end converter io as well as on the input currents of all
POL converters i1 through in. Consequently, current flowing thorough the capacitor C is
periodic non-sinusoidal and its waveform depends on the operation of all converters. In
practice, it is critical to know the rms characteristics of this current, determine the worst
case, and select capacitor parameters C and Rc such that the lifetime of this capacitor is
not compromised.
Furthermore, output of the front-end converter is used to feed a power bus
distributing the Vc voltage across a large area of a board while also providing supply
voltage to local noise sensitive circuits. Consequently, the ripple voltage across the
capacitor C has to be well controlled. Steady-state analysis of the entire network is
necessary when making a design decision about additional filtering.
12
Figure 2.2: Voltages and currents in power converter network
Several types of analysis are required when designing a switching power converter
network. Usually, the first analysis in the design process is associated with the
converter’s periodic operation at steady-state. When in periodic steady-state, nodal
variables of the converter network will include dc and ac components. The dc component
is essentially equal to an average of the nodal variable over the switching period. The ac
component includes a harmonic spectrum with the fundamental frequency being identical
to the converter switching frequency. Analysis of the average values of nodal variables as
they depend on the converter input voltage and load current will be referred in this thesis
as a dc analysis.
The second type of analysis that is required in practice is associated with the
investigation of waveforms of voltages and currents inside the circuits of individual
converters. Particular examples are waveforms of voltages across switching devices and
13
currents through magnetic devices and capacitors. Essentially, these waveforms are
periodic non-sinusoidal signals having both dc and ac content. The ac content of these
waveforms is significant. This type of analysis can be referred to as switching waveform
analysis.
The third type of analysis required in practice is the analysis of voltage and current
ripples at the input and output terminals of switching converters. The input and output
terminals of switching converters are usually separated from the switching devices by
low-pass filters. It is frequently required to keep the ac content of the terminal voltages
and currents within specified limits. Consequently, compared to the dc component, the ac
content of the terminal voltages and currents is small. Analysis of the ac content of the
nodal voltages and currents at converter input and output terminals can be referred to as
ripple analysis.
The fourth type of analysis being executed in design practice is associated with the
detailed investigation of voltages and currents across switching devices at the instants of
switching. This type of analysis is frequently called switching transition analysis or
commutation analysis.
Each switching converter has dynamic properties which can be characterized in the
small-signal domain. In order to achieve a particular goal when controlling a converter
during transients, various regulation schemes can be implemented. Investigation of
dynamic properties, including stability, falls into the area of converter small-signal
analysis.
The focus of this thesis is on the dc, switching waveform, and ripple analyses.
14
So far in this section, the needs and problems of practical design were identified.
Numerical analysis providing accurate data promptly is expected to facilitate design
decisions. There are, however, several problems associated with the numerical analysis of
the switching power converter network.
First, a mathematical model capturing all elements which have impact on network
operation needs to be created. This leads to issues associated with converter device
modeling as well as to those associated with the generation of a network equation.
Selection of detailed device models leads to accurate modelling of the power converter
network. However, the device models have a significant impact on the generation of the
network equation, and also they affect simulation speed and algorithm convergence.
Therefore, selection of the most accurate detailed models might not always be the best
choice. Rather, the device model may need to be simplified such that the simulation
goals, driven by the type of analysis as listed previously in this section, are satisfied.
Methods which are well known in the circuit theory area such as the shooting
method, envelope following method and harmonic balance method allow for simple
implementation of detailed device models leading to accurate simulation. However, the
simulation accuracy of these methods may come as an unnecessary expense paid for the
simulation time with certain types of analyses. For instance, detailed models of switching
devices may not need to be included in the simulation if the goal of the analysis is
investigation of current waveforms in magnetic devices.
A large number of specialized methods were developed to model the operation of a
switching power converter. With these methods, the converter circuit is represented by a
15
piecewise linear model, and switching devices are modeled as ideal switches. Typical
problems with these methods include convergence problems and the complexity of the
simulation algorithm. Particular difficulty comes from the fact that the converter
switching devices need to be treated as internal switches, i.e. switches for which
switching times are not known a priori. Since the number of switches in networks with
multiple power converters can be significantly higher than it is with a single power
converter circuit, the switching time determination problem is even more complex.
Problems with the analysis of multiple converter networks can be approached by
adopting a small-signal macro-modeling concept. However, the accuracy of the small-
signal macro-models for frequencies above the bandwidth of the converter feedback
regulation loop is poor. Using this approach, information about power converter
switching operation is lost. Consequently, this approach is not suitable for switching
waveform and ripple analyses, as defined previously.
In switching power converter theory, the power converter is usually represented by a
small circuit consisting only of components which are necessary for a particular type of
power conversion. Consequently, formulation of the network equation typically requires
manipulation of simple expressions derived using Kirchhoff’s laws of current and
voltage. With large networks, however, this approach will be ineffective or may even fail.
16
2.4 Summary
In this chapter, examples of switching power converter systems were presented. Problems
in the analysis of power converter networks, as driven by practical applications, were
formulated. The specific types of analyses which are typically needed in engineering
practice were defined. The resulting circuit theory problems were described.
17
Chapter 3
Modeling Networks with Switching Power
Converters – Basic Concepts
3.1 Introduction
This chapter presents background information on key topics which are included when
developing algorithms for the simulation and analysis of networks with switching power
converters. Specifically, this chapter describes key criteria for device model selection,
presents options for system equation formulation, and includes options for their solution.
3.2 Device Model Selection
Switching power converters are complex circuits consisting of a variety of components
performing many different functions. The key components which carry power conversion
18
operation include energy storage devices such as transformers, inductors, capacitors, and
switching devices such as power transistors and diodes. Further, controllers which
typically include error amplifiers, compensation R-C networks, ramp generators, and
comparators are added to the power converter circuit.
The device model has a significant impact on performance of the simulation
algorithm in terms of accuracy, convergence, and simulation time. In addition, and
especially with switching power converters, the device model may also have an impact
on selection of the method for formulation of the network equation. Thus, to develop an
optimal simulation algorithm, suitable device models need to be selected.
a) Models of magnetic devices
The modeling of the magnetic devices used in switching converters is a specific area of
power electronics. Precise models of magnetic devices require material and geometry
descriptions of both the windings and the core. Parameters of these devices such as the
core flux density, magnetizing inductance, leakage inductance, winding capacitance, or
winding resistance depend on physical dimensions and device architecture and are
therefore functions of space coordinates. In addition, magnetic devices are exposed to
non-linear high-frequency waveforms of applied voltage or current during switching
operation. This introduces high-frequency effects in the windings such as the skin effect,
eddy currents, and the proximity effect, which have a reverse impact to the device
parameters.
19
For the purposes of switching power converter simulation and practical design itself,
the parameters of magnetic devices have been expressed predominantly in lumped form.
Various examples of such models can be found in many publications ([20] through [24]).
The published models vary in both the architecture and the complexity of parameters.
In general, a lumped parameter model of a transformer can include the ideal trans-
former Np/Ns, magnetizing inductance of the primary winding Lm, leakage inductance of
the primary and secondary windings Llp and Lls, resistance of the primary and secondary
windings Rwp and Rws, capacitance of the primary and secondary windings Cwp and Cws,
inter-winding capacitance Ciw, and magnetic reluctance Rm. An example of such a model
is shown in Fig.3.1.
Figure 3.1: Transformer model with parasitic parameters.
The ratio of the primary to secondary turns Np/Ns is the main parameter of a trans-
former. In order to preserve the switching converter’s dynamic properties, the
magnetizing inductance Lm should be included. The magnetizing inductance depends on
both the bias current and the frequency which introduces non-linearity to the transformer
model. The primary and secondary winding resistances Rwp and Rws model passive ohmic
20
losses of the transformer and contribute to the damping of the resonant LC circuit on the
converter’s primary and secondary sides. The magnetic reluctance Rm represents the
magnetic losses in the transformer core. This parameter used to be ignored in simulation
algorithms. With soft-switching power conversion topologies, leakage inductances Llp
and Lls may become critical to the power converter’s operation. Therefore this parameter
needs to be included in the transformer model. However, with hard-switching power
conversion topologies, a very low leakage inductance of primary and secondary
windings, Llp and Lls respectively, is required. In practice, the magnitude of this leakage
inductance is frequently well below 1% of the magnetizing inductance. Consequently, in
the case of switching transition analysis, the leakage inductance should be included in the
device model. However, in cases of switching waveform and ripple analyses, the leakage
inductance can be omitted from further consideration. Parasitic capacitances of the
windings, Cwp and Cws are typically very low, on the order of tens of pF. Therefore, as
with the leakage inductance, a similar guideline can be applied: the parasitic capacitances
of the windings should be included in the device model in the case of switching transition
analysis, however, in cases of switching waveform and ripple analyses, this need not be
considered.
The model of the output inductor (Fig.3.2.), similarly as with the transformer model,
includes a magnetizing inductance L, magnetic reluctance Rm, winding resistance RL,
leakage inductance Lk, and winding capacitance Cp.
21
Figure 3.2: Model of output inductor with parasitic parameters.
Inductance depends on both the bias current and the frequency which introduce non-
linearity to the inductor model. For the purpose of switching transition analysis, leakage
inductance and winding capacitance should be included in the inductor model. However,
in cases of switching waveform and ripple analyses, these parameters may be omitted.
b) Model of switching MOS FET transistors
The MOS FET transistor operation can be modeled using SPICE parameters ([1], [2], [25
through [27]). The SPICE parameters are based on silicon design of the device, allowing
for the creation of detailed models. An example of the detailed MOS FET model is
shown in Fig.3.3. In this example, RD and RS represent Drain and Source resistances, RDS
is a Drain-to-Source shunt resistance, Cgd, Cbd, Cgs, Cbs, and Cbg are capacitances between
the MOS FET electrodes, and Vbd and Vbs are intrinsic body diodes.
The MOS FET switching operation can be defined by the expression:
22
(3.1)
where W and L are the effective width and length of the channel respectively, Kp is a
coefficient contributing to the transistor transconductance, and VT is the gate-to-source
threshold. The MOS FET transistor channel parameters W and L are usually known from
the manufacturer. The coefficients Kp and VT can be computed using transistor SPICE
parameters (e.g. [2]).
To perform the switching transition analysis, a detailed model should be used. The
detailed model allows simulation of the MOS FET transistor off-to-on and on-to-off
transitions including high-frequency ringing caused by the presence of transistor parasitic
capacitances and leakage inductances of magnetic devices connected to this transistor.
Detailed modeling of the switching transitions, however, comes back in the form of
expenses such as long simulation time. Even the ratio between switching transitions and
the MOS FET conduction times can be higher than 1:100, most of the simulation time is
spent on detailed computation of switching transition transients. Consequently, the time-
domain transient simulation becomes significantly lengthy.
23
Figure 3.3: Model of a power MOS FET transistor.
In an effort to reduce simulation time, the detailed model of the MOS FET transistor
can be replaced by an ideal switch. Perhaps the simplest ideal switch can be represented
by a resistor which changes its resistance from zero to infinity and vice-versa in zero
time. In reality, there is a non-zero voltage drop across the transistor when it is closed,
and non-zero current through when it is open. These properties of the switching transistor
can be modeled using a time-variant “two-value resistor” which has a resistance equal to
the on-resistance of the MOS FET when it is on and a high resistance when it is off:
(3.2a)
(3.2b)
24
where toff-on and ton-off are time instants when the switch is being turned on and off
respectively.
c) Model of capacitors
The model of a capacitor, except for the capacitance C itself, can include parasitic
parameters such as an effective series resistance Rc, a series inductance Lc, and a parallel
leakage resistance Rp. For microwave capacitors, a parasitic parallel capacitance Cp can
be added to the capacitor model. An example of such a model ([28]) is shown in Fig.3.4.
Figure 3.4: Model of a capacitor with parasitic parameters.
The capacitance of a capacitor typically depends on both the voltage applied and
frequency. These properties contribute to the non-linear behavior of a capacitor. In
simulation algorithms, the capacitance is frequently linearized in the neighborhood of the
operating point ([28], [29]). The serial and parallel resonant frequencies caused by the
parasitic parameters Lc and Cp, are typically about two decades higher than the converter
switching frequency. Also, for practical consideration, the leakage current caused by the
25
parasitic resistance Rp can be more than 1000 times smaller than the capacitor ripple
current. Therefore, for the purpose of switching waveform and ripple analyses, the model
of the capacitor needs only to include a linearized capacitance C in series with a parasitic
resistance Rc.
3.3 Formulation of the Network Equation
In a prevailing number of publications in the area of switching power converter theory, a
simplified model of a power converter consisting of a small number of devices is used.
Consequently, the network equation can be formulated using simple manipulations with
expressions derived using Kirchhoff’s voltage law and Kirchhoff’s current law. However,
involving a large number of components as well as implementing complex device models
requires using general formulation methods ([30], [31]).
3.3.1 Formulation of Network Equation Using the MNA method
The MNA method is a general method for formulation of the network equation. With this
method, derivation of the network equation can be relatively easily automated using
known device stamps. Consequently, linear and non-linear device models of the
switching converter can be easily implemented into system matrices. For the purpose of
illustration, assume a closed-loop buck converter circuit providing voltage conversion
from voltage Vg to voltage Vo in Fig. 3.5.
26
Figure 3.5: Closed-loop buck converter.
Using the MNA method, the circuit of this converter can be represented by the following
network equation:
(3.3)
where vector represents circuit nodal variables, n is the number of nodal
variables, and are the modified nodal conductance and capacitance
matrices respectively, vector stands for non-linear terms, and vector
collects all independent sources in the network.
27
3.3.2 Formulation of a Piecewise Linear Network Equation Using the MNA
Method
A general approach adopted in switching power converter theory to model and analyze
switching power converter operation is to replace switching devices by ideal switches
([21], [34] through [46]). As switches periodically change their status during converter
operation, different topologies are forced on the power converter circuit. Further,
assuming linear device models, each topology can be treated as a linear circuit.
Consequently, behaviour of the switching converter circuit can be approximated using a
piecewise linear model.
Assume the buck converter circuit shown in Fig. 3.6 operating in two linear
topology changes within a switching cycle.
Figure 3.6: Open-loop buck converter with ideal switches.
Assume that switches S1 and S2 have negligible impedance when on, significantly high
impedance when off, and that switching functions s1(t) and s2(t) enforce the switch state
changes simultaneously during a negligible time interval, as shown in Fig.3.7. For
28
convenience, assume that the switch is on when the switching function is equal to 1 and
that the switch is off when the switching function is equal to 0.
Figure 3.7: Switching functions.
Given these assumptions, the two linear topologies (on-time topology and off-time
topology) which model behaviour of this converter in the time-domain, are shown in
Fig.3.8.
Figure 3.8: Buck converter topologies.
29
By applying Kirchhoff’s laws of current and voltage on circuits in Fig.3.8 and
manipulating the terms, the network equation for this converter can be found in the
following form:
for (3.4)
where stands for the vector of nodal variables, n is the number of nodal
variables, matrices , and vector are the MNA system
matrices and input vector respectively, ti0 and ti0 + di Tsw represent starting and
finishing times of the i-th topology, di is a duty ratio of the i-th topology, and index i is
equal to 1 or 2 depending on the actual topology of the converter.
Conceptually, the network equation describing the operation of the circuit from
Fig.3.6 can be formulated in the form of a linear time-variant system. Coefficients of this
equation are periodic with the period equal to the converter switching period.
Consequently, all nodal variables at steady-state will also be periodic with the period
equal to the converter switching period.
30
3.3.3 Formulation of a Piecewise Linear Network Equation Using Oriented
Graphs
Assuming a piecewise linear representation of the switching power converter circuit, each
linear sub-system can have its own representation in the form of an oriented graph ([30],
[32], [33]). Each node of a linear sub-system is assigned a graph node and each two-
terminal element of a linear sub-system is replaced by a graph edge.
Figure 3.9: Buck converter graphs.
31
An oriented graph can incorporate models of all switching converter components:
resistors, capacitors, inductors, transformers, dependent and independent sources, and
error amplifiers. As an illustrative example, two graphs which are assigned to the on-time
and off-time topology of the buck converter from Fig.3.6 are shown in Fig.3.9.
Using oriented graphs, loop set and cut set matrices ([30]) are generated for each
topology allowing formulation of the relationships among state variables in the form:
(3.5a)
(3.5b)
where , … are voltages across capacitors, , , … are currents through
inductors, the indices p and q stand for p-th capacitor voltage and q-th inductor current
respectively, and , , … are independent sources, which further lead to a generic
state-space formulation in matrix form:
(3.6a)
(3.6b)
for
32
where the state vector includes all capacitor voltages and inductor currents,
, , and are the network system matrices,
is the system output, is the input vector, ti0 and ti0 + di Tsw are the
starting and finishing times of the i-th topology, and index i is equal to 1, 2, … N
depending on the converter topology.
3.4 Solution of the Network Equation
3.4.1 Solution of a Non-Linear Network Equation
The MNA equation (3.3) represents a system of differential-algebraic equations with non-
linear terms. To determine the network response, this equation is converted to a set of
nonlinear difference equations. This step can be accomplished using linear multistep
formulae such as forward Euler, backward Euler, trapezoidal, or Gear’s formulae ([30]).
For example, the general integration formula for an algorithm based on the backward
Euler formula is:
(3.7)
where x(m+1) and x(m) are two consecutive points of the system response and h is the
integration step.
33
Next, after using (3.3) to substitute for the
in (3.7), the recursive expression
defining successive points of the system response comes in the form:
(3.8)
The expression (3.8) is essentially a system of non-linear algebraic equations. Finally, the
solution to (3.8) can be found using Newton’s method, Broyden method, or continuation
methods ([30], [31]).
The selection of an integration step h in (3.8) has a significant impact on the
stability, accuracy, and speed of simulation. Rules on setting the integration step, which
are known from circuit theory (e.g. [30]), also apply on networks with switching
converters. Particular difficulties with switching power converters are caused by the
presence of both, non-linear models of switching devices and device parasitic parameters
included in device detailed models making the system equation (3.3) stiff. Magnetizing
inductances and capacitances of the converter power train devices create poles on the left
side, close to the origin of the pole-zero plane. On the other hand, the parasitic
capacitance of switching devices and leakage inductance of magnetic devices create poles
on the left side, far from the origin. Consequently, to make the integration stable, the step
size h needs to be reduced accommodating both the transition speed of the switching
devices and the parasitic parameter pole which is farthest away from the origin. To
34
increase the simulation speed, the step size may need to be increased as the fast transient
dies out.
3.4.2 Solution of a Piecewise Linear Network Equation Using Numerical Integration
a) Solution to Piecewise Linear MNA Formulation
Similar to the network non-linear model (3.3), the network equation assigned to the
piecewise linear model (3.4) can be solved using numerical integration methods.
However, while switching between converter topologies with the non-linear equation
(3.3) is managed by the presence of detailed models of the switching devices, the
switching transitions with the piecewise linear model are arranged by switching between
sets of linear equations. Consequently, instead of solving the non-linear equation (3.3),
the simulation algorithm for the piecewise linear model includes solving the set of linear
equations (3.4). Referring to the algorithm example based on the backward Euler formula
in the previous section, the recursive relationship for computing the network response is:
(3.9)
Compared to the iteration algorithm for the non-linear network equation (3.8), the non-
linear term is not included in this case.
It should be noted that, by adopting the piecewise linear modeling strategy, the
switching power converter circuit becomes a class of circuit with internal switches ([47]
35
through [50]). With this circuit class, instants of switching are not known a priori. In fact,
the switching instants depend on circuit parameters as well as on the circuit state.
Therefore, computation of switching times becomes a necessary step of simulation
algorithms.
The switching time computation can be implemented by evaluating the switching
functions at each integration step. In the case when a diode operates as a switch, the
switching function s(t) can be defined using forward current of the diode iD and reverse
voltage of the diode vD as follows:
when diode conducts (3.10a)
when diode does not conduct (3.10b)
In the case of a MOS FET transistor switch, the switching function can be defined using
the MOS FET transistor gate-to-source voltage vGS and gate-to-source threshold voltage
VT:
(3.11)
In the case of a converter from Fig.3.5, the switching functions s1 and s2 are:
(3.12a)
(3.12b)
36
The evaluation of the switching function is identical in all cases:
then switch is ON (3.13a)
then switch is OFF (3.13b)
In simulation algorithms, at the step when the switching time is detected, the network
equation is updated and the nodal vector x in (3.9) is passed to the next topology as a
vector of initial conditions.
Frequently, the switching time is not an integer multiple of the integration step. To
determine the switching time more accurately, the simulation algorithm may need to step
back and reduce the integration step in several cycles until an exit condition is satisfied.
An example of this procedure is illustrated in Fig.3.10. The step size is reduced by half
until the exit condition is satisfied.
37
Figure 3.10: Switching time determination.
b) Solution to State-Space Formulation
The piecewise linear model of a switching converter in state-space is defined by a set of
linear differential time-invariant equations (3.6). Similar to the piecewise linear MNA
formulation, (3.6) can also be solved using numerical integration methods. Using the
example of the backward Euler formula, a recursive relationship for computing network
response is obtained after the derivative of state vector x in step m+1 from (3.7):
(3.14)
38
is substituted in the state equation (3.6a), resulting in:
(3.15)
Similar to the piecewise linear MNA formulation, the network switching times need
to be determined. With the state-space formulation, the switching functions are defined
using a linear combination of state variables. Thus, the switching function may become
part of the system output. The system output equation (3.6b) will be extended for
switching functions as follows:
(3.15a)
where ,
, and k is the number of switching instants within a
switching period.
The switching functions are evaluated after each integration step using the same approach
as shown in section a.
39
3.4.3 Solution of a Piecewise Linear State-Space Network Equation
Compared with the MNA formulation, the general form of the solution for the state-space
formulation is known a priori. Thus, instead of numerical integration, the network
response can be computed by evaluation of an explicit function at selected time points
leading to improvement in the simulation algorithm in terms of speed and accuracy.
The explicit analytical solutions to (3.6a) can be found in literature on classical
control theory (e.g. [68]) in the form:
(3.16)
where is the time at the beginning of the i-th topology and is a vector of
initial conditions at the time .
The system response (3.16) consists of two components:
The first component is a term similar to the system homogenous response. This term is
frequently referred to as the system zero-input response or natural response ([43]):
(3.16a)
40
The second component is in the form of a convolution integral representing the solution
for the input u(t) while the initial conditions are set to zero. Accordingly, this term is
called the system zero-state response or forced response ([43]):
(3.16b)
Two assumptions can be made to simplify the solution (3.16). First, the input vector
u is constant during the switching period, which can be considered to be true in the case
of DC/DC converters. Second, the time ti,0 can be set to zero since during the simulation
over many switching cycles, an extra variable is assigned to monitor time. Thus the
expression (3.16) becomes:
(3.17)
and, after the integration, the solution is:
(3.18)
or:
41
(3.19)
where are initial conditions and is the state transition matrix
for the i-th linear topology of the network.
Finally, the solution to the piecewise linear model (3.6) can be found by the
evaluating expressions (3.19) and (3.6b). For the purpose of illustration, the state vector
in the selected time points within the duration of the converter’s i-th linear topology Ti is
shown in Fig.3.11.
Figure 3.11: State vector and switching function with the converter’s i-th topology.
42
While the time points , , … are arbitrary, the network switching times
, … are not known in general and need to be determined. For the purpose of
determining the network switching times, switching functions are defined as follows:
(3.20)
where and and
are constant vectors defining the i-th switching
function, n is number of state variables, and v is number of independent inputs.
Assuming the network initial condition at the beginning of the i-th topology ,
the time to switch to the (i+1)-th topology can be found as a solutions to:
(3.21)
The equation (3.21) is frequently referred as a constraint equation ([37]).
The constraint equation (3.21) includes the matrix exponential terms. Thus, to find
the solution, the matrix exponential terms can be approximated first, and then the
constraint equation is solved for the switching time .
Various solutions for the matrix exponential approximation problem can be found in
literature. In [51], the matrix exponential was replaced using the eigenvalue-eigenvector
decomposition. A popular method is to approximate the matrix exponential by the Taylor
43
series expansion ([52], [53]). The Chebyshev polynomial expansion was used to compute
the matrix exponential in [44] and [54].
The matrix exponential elimination step leads to transferring the transcendental
equation (3.21) to a non-linear algebraic equation. To solve this non-linear algebraic
equation, Newton’s iteration method is typically used. As a necessary step with Newton’s
iteration method, the initial guess of the switching time needs to be made. Making this
initial guess may be particularly difficult in cases of large transients when the switching
converter temporarily switches between operation modes. For the purpose of illustration,
assume a converter operating in discontinuous conduction mode at steady-state. When the
converter operates in this mode, typically 3 linear topologies are periodically repeating.
During the third topology, the converter inductor current is discontinuous. During large
transients, however, the converter may skip the operation in the third topology for several
switching cycles. The inductor current can be continuous and its magnitude can be
several times greater than it is in steady-state. As shown in Fig. 3.12, the converter
achieves a steady-state after n switching cycles.
Figure 3.12: Waveform of inductor current during start-up transient.
44
At the steady-state, the inductor current is discontinuous and the proper initial guess of
the switching time is . In the area close to the steady-state, such a guess of the
switching time causes no trouble in the iteration algorithm. However, the same guess
applied in the area of transient, say at the time of the first switching cycle, may lead to a
failure of Newton’s iterations. Since the hypothetical waveform of inductor current will
fall below zero during the seventh switching cycle, a better guess for the switching time
is . As is seen from Fig 3.12, the value of a proper initial guess varies as the
transient dies out. At the beginning of the simulation, the value of proper initial guess can
be several times bigger than at steady-state and therefore, in general, may not be so
straight forward to predict.
Another example of the convergence issues caused by an improper initial guess is
the operation of the pulse-width modulator with converters with voltage-mode or current-
mode control. Similar to (3.12), the constraint equation derived using this modulator
operation can be defined using the difference between the output voltage of the error
amplifier Vea and ramp generator voltage Vr. The solution of this equation can be even
more challenging because, during large transients, the difference may not be monotonous
within the interval of a guess.
Compared to numerical integration, the algorithms based on analytical methods can
compute the network transient response at a substantially reduced number of time points.
Essentially, it is good enough to compute the network transient response only at
switching times to determine the network steady-state. Thus, the simulation time needed
45
to reach the network steady-state is shorter. Accordingly, these methods are frequently
referred to as fast time-domain methods ([44], [45], [51] through [54]).
3.5 Summary
In this chapter, models representing switching power converter devices and model
selection criteria were discussed. Also, methods for the formulation of the network
equation for a switching power converter network and techniques for their solutions were
described.
The model representing a switching power converter device has a significant impact
on simulation algorithm performance in terms of accuracy, speed, and convergence.
Different types of device models may be used for different types of converter circuit
analyses. The device model should be selected such that the goal of a particular analysis
is achieved.
Two techniques for network equation formulation, the MNA formulation and
oriented graphs, were described. The main advantages of the MNA technique are in
simplicity of generation of the network equation using device stamps and in straight-
forward implementation of detailed device models. Presence of detailed device models in
the network equation allows for accurate simulation. The MNA formulation of the
network equation leads to the use of numerical integration methods. Oriented graphs are a
suitable tool for formulation of a piecewise linear network equation in state-space. A
46
state-space network equation can be solved by numerical integration. However, the main
advantage of state-space formulation is that the general solution of the network equation
is available a priori in an analytical form. This approach introduces an opportunity for the
algorithm to shorten simulation time and increase simulation accuracy.
47
Chapter 4
Steady-State Determination Methods
4.1 Introduction
Perhaps the most intuitive method which can be used to determine network steady-
state is to carry on time-domain transient simulation until the steady-state is achieved.
However, depending on how far the starting point is from the steady-state, it may take a
considerable number of switching cycles to simulate until the transient dies out and the
steady-state is reached. Consequently, determination of the network steady-state may be
too lengthy.
Other than computing particular points of the network time-domain response, the
simulation algorithm may also need to deal with possible changes in converter operating
modes which may occur with large transients, leading to convergence challenges. It may
also be a problem to identify the steady-state itself. Thus, the simulation time,
48
convergence, and steady-state accuracy are the main problems associated with using the
time-domain transient simulation for determining switching converter network steady-
state.
Methods which are well established in circuit theory such as the shooting method,
envelope following method, and harmonic balance method can also be used to determine
the steady-state of a network with switching power converters. When applied to circuits
with switching power converters, however, the presence of detailed switching device
models in the network equation slows down the simulation unnecessarily. To increase the
simulation speed, variants of these methods using ideal switches were developed.
Concepts of these methods are discussed in this chapter in detail.
4.2 Methods of Accelerated Convergence
4.2.1 Concept
Several methods were developed in the past to shorten the time needed to determine the
network steady-state. Instead of a precise simulation of the network response in the time-
domain, particular points on the solution trajectory are computed such that the steady-
state is achieved within a small number of iteration steps. These methods are referred to
in literature as methods with accelerated convergence into steady-state ([35], [36], [47],
[55]).
49
The methods of accelerated convergence are based on the time-domain shooting
method. The fundamental assumption with the time-domain shooting method is that the
circuit operating with a period of Tsw reaches a steady-state if for any time t0 the
following applies:
(4.1)
In cases when the steady-state is not achieved, the difference between the left and right
side of (4.1) is a non-zero vector. A vector error function can be defined as:
(4.2)
The network steady state problem can be solved by finding the roots of (4.2). It should be
noted that the error function definition in (4.2) applies to any of the network equation
formulations (3.3), (3.4), and (3.6).
The roots of (4.2) can be found using Newton’s iteration method. Newton’s iteration
method requires that an initial guess x0 to be made on the circuit steady-state. A new
circuit state xn is then computed using a correction of the initial guess x. The correction
is computed using values of both the error function and the derivative of the error
function at the initial guess. Formal notation for these steps of Newton’s iteration
algorithm is:
50
(4.3)
and
(4.4)
where the matrix:
(4.5)
is the Jacobian of the error function at the point .
The value of the error function at the point (4.2) is computed using simulation in the
time-domain over the network switching period.
The computation of the Jacobian of the error function (4.5) is an essential part of the
overall algorithm of accelerated convergence and its derivation is shown in detail herein.
The error function (4.2) can be substituted into the expression for the Jacobian (4.5)
resulting in:
51
(4.6)
where I is an unit matrix, arbitrary time is set to zero, and and are vectors
of network variables at the end and beginning of the switching cycle respectively.
Assume a trajectory of the network state over a switching period of k discrete points.
Define the Jacobian matrix Jm using two consecutive states on the solution trajectory
and as follows:
(4.7)
The meaning of the Jacobian Jm definition in (4.7) is that it shows a sensitivity of the
state vector changes when moving to the next point of the solution trajectory.
After the chain rule is applied to (4.6), the Jacobian matrix is obtained in the form:
(4.8)
4.2.2 Accelerated Convergence for MNA Formulation
Assume the MNA non-linear network equation (3.3) is being solved using the backward
Euler integration method. In this case, the recursive expression relating two consecutive
52
states of the nodal vector on the solution trajectory is defined in (3.8). A value of the
term in (4.7) results from partial differentiation of equation (3.8) with respect to .
Particularly:
(4.9)
At this point, all terms for the initial guess correction (4.4) are defined. Specifically, the
error over the converter switching period (4.2) can be computed using the recursive
expression (3.8), and all terms of the Jacobian (4.8) can be computed using (4.9).
Finally, Newton’s iterations may need to be executed several times such that the
error between nodal vectors at the beginning and end of the switching cycle is tolerable.
The algorithm for accelerated convergence to steady-state for a piecewise linear
MNA network equation is analogous to the one described above. With these types of
networks, the computation of Jacobian matrix will include sensitivity matrices over each
of the linear networks as well as sensitivities across switching instants ([47]).
4.2.3 Accelerated Convergence for State-Space Formulation
The concept of methods for accelerated convergence for a network equation formulated
in state-space is similar to that developed for the MNA formulation. The difference is in
the procedure of computing individual points of the error function and that of the
53
Jacobian ([35], [55]).
Assume the piecewise linear network equation (3.6). Referring to the expression
(3.19), the recursive expression relating two consecutive states of the state vector on the
solution trajectory is:
(4.10)
where is the state vector at the exit of the i-th topology, is the state vector at the
entrance to the i-th topology, and is the state transition matrix of the i-th
topology at the exit from this topology.
The value of Ji in (4.8) results from a partial differentiation of equation (4.10) with
respect to :
(4.11)
The state transition matrix is a function of because Ti is dependent on
through the implicit relationship in (3.21). Since only the state transition matrix
depends on changes of the state vector , applying the partial derivation to (4.11)
yields:
54
(4.12)
The derivative
in (4.12) shows that the duration of the i-th topology Ti depends on a
change of state vector at the entry to the topology . This term can be derived using
the switching constraint (3.21) in two steps. First, the solution for a particular topology
in (4.10) is substituted in (3.21) giving:
(4.13)
Second, partial differentiation with respect to is applied to (4.13) resulting in:
(4.14)
At this point, all terms for the initial guess correction (4.3) are defined. The error over the
converter switching period (4.2) can be computed using a simulation over one switching
cycle, and all terms of the Jacobian (4.8) can be computed using expression (4.12) and
(4.14).
Similar to the accelerated methods for the MNA network equation, Newton iterations
may need to be executed several times such that the error between nodal vectors at the
beginning and end of the switching cycle is tolerable.
55
4.3 Sampled-Data Modelling Methods
4.3.1 Concept
Sampled-data modeling has become a popular technique supporting digital methods for
switching power converter control ([37], [38], [43], [56]). With this technique, instead of
detailed modeling in the time domain, the focus is on a search for the network response at
specific time points. These time points are equally spaced using multiples of the
switching period. Thus, the steady-state algorithm computes the network state in points
creating an envelope of the network response.
Assume a closed-loop converter operating with two topological changes within the
switching period described by (3.6). An example of a state vector trajectory in the time-
domain is shown in Fig.4.1. In this figure, is the initial value of the state vector,
stands for the continuous-time response of the state vector, and is its sampled-
data form.
Beginning at an arbitrary time iTsw, the network response in adjacent switching times on
the time response trajectory [i+D]Tsw and [i+1]Tsw is:
(4.15a)
56
(4.15b)
where the symbol D is the switching power converter duty-ratio, and vector stands for
the state vector at the time iTsw.
Figure 4.1: Network sampled-data trajectory.
57
Assume that the duty-ratio D and system input u are held constant during the
switching period. After substituting for from (4.15a) and minor
manipulation of terms, the solution at the end of the switching cycle is:
(4.16)
where, for convenience, .
Define terms and as follows:
(4.17a)
(4.17b)
Consequently, (4.16) can be written as:
(4.18)
In the next step of deriving the sampled-data model of the converter, the matrix
exponentials in (4.17a) and (4.17b) are linearized:
58
(4.19a)
(4.19b)
yielding and in the form:
(4.20a)
(4.20b)
The expression (4.18) shows the relationship between two adjacent points of the time-
domain response separated by a time interval which is equal to the switching period .
To control a switching converter, it is typically necessary to set the sampling period to
span over several switching cycles:
(4.21)
For the purpose of illustration, the sampling period in Fig.4.1 is set to 3 times the
converter switching period.
The network state in the subsequent sampling period is found by repeating solution (4.18)
in N consecutive switching periods using approximations (4.20a) and (4.20b) in the form:
59
(4.22)
The general expression showing the relationship between two adjacent points of the
sampled-data model response and is:
(4.23)
When computing the high power terms of E in (4.23), it is possible show that:
(4.24a)
(4.24b)
After substituting (4.24a) and (4.24b) in (4.23), the network sampled-data model is:
(4.25)
where:
(4.26)
60
Expression (4.25) is a non-linear algebraic equation which includes the products of
system variables. Thus, to derive relationships for the network steady-state and to obtain
a small-signal response, apply a perturbation at the operating point (Uss, Dss, Xss):
(4.27)
and apply the steady-state condition:
(4.28)
on (4.25). The resulting steady-state relationship is:
(4.29)
Ignoring the non-linear terms, the small-signal model is:
where
(4.30)
61
4.3.2 Accurate Sampled-Data Steady-State Modelling
The sampled-data small-signal representation of the switching converter network in
(4.29) and (4.30) is derived using the matrix exponential linearization (4.19a) and
(4.19b). Also, non-linear and detailed model terms are neglected multiple times. This
approximation is acceptable for purposes of feedback control loop design in the majority
of industrial applications. In order to obtain the accurate steady-state response of the
network, the number of switching cycles in the sampled-data period N is set to 1, and
instead of matrix exponential linearization step (4.19), the steady-state condition:
(4.31)
is applied on the network large-signal response (4.18). After manipulation of the terms in
(4.18), while keeping the input constant, the final expression for the steady-state is:
(4.32)
It needs to be noted that with networks with internal switches, the duty-ratio D is not
known a priori. Therefore, to determine the network steady-state, the value of the duty-
ratio needs to be found. This problem is solved by searching for a solution to the set of
equations (4.32) and (3.21).
62
4.4 Summary
The methods of accelerated convergence allow for a fast determination of converter
steady-state. Instead of computing numerous points of the circuit response in the time-
domain, the solution is computed using Newton’s method applied on the shooting
condition (4.1). The necessary intermediate step is the one-cycle time-domain simulation
which needs to be done at each of the Newton’s iteration cycles to compute a value of the
error function. As explained with the analytical time-domain methods in Section 3.4, the
one-cycle time-domain simulation requires Newton’s iteration method to determine the
circuit switching times. Consequently, the steady-state algorithm, except for the main
Newton’s iteration loop, also deploys several internal Newton’s iteration loops, each
associated with computing the corresponding switching time.
Compared to transient simulation in the time-domain, there are more opportunities
for accelerated methods to fail. The first type of failure is related to the initial guess of the
network state. This initial guess needs to be made within the main iteration loop.
Although Newton’s method can converge quickly if the initial guess is close to the
solution, the solution may not be found if the initial guess falls out of the convergence
area. The second type of failure is related to the one-cycle time-domain simulation. As
described with the transient simulation method in detail in Section 3.4, the time-domain
method may fail in the computation of switching times.
Methods based on sampled-data modeling techniques, similar to methods of
accelerated convergence, allow for a fast determination of converter steady-state. In the
63
case of the linearized model, the network’s steady-state can be computed using (4.29). In
the case when the steady-state solution needs to be computed accurately, the number of
switching cycles within the sampled-data period is set to 1, leading to the steady-state
expression definition (4.32), while the matrix exponential linearization step is not
included. To solve (4.32), the constraint equation (3.21) is included in the algorithm. The
solution to the set of equations (4.32) and (3.21) can be found using one Newton’s
iteration loop. Comparing to the methods of accelerated convergence, the internal one-
cycle time-domain simulation loop is not required.
Steady-state algorithms based on the sampled-data concept may suffer multiple
convergence problems. The main problem is caused by the error when making the initial
guess which is a necessary step with Newton’s iteration algorithm. Except for the
network state, the initial guess needs also to include a guess of switching times. Thus,
comparing to the methods of accelerated convergence, the initial guess is more
challenging to make. Depending on the initial guess, the iteration algorithm may fail to
converge or it can converge to a physically meaningless solution. An example of
convergence failure is a negative entry in the switching time vector.
The second type of convergence problem is attributed to the error amplifiers which
are present in feedback circuits of closed-loop switching power converters. The same
problems were reported with methods of accelerated convergence. In [58], authors refer
to the pulse-width modulator which saturates due to the error of the initial guess
combined with the high gain of the error amplifier, which finally causes the algorithm to
fail. Authors in [39] also refer to numerical problems resulting from the presence of the
64
error amplifier. To overcome the convergence problems caused by feedback circuit
operation, authors presented a two-loop solution which includes coordination between the
converter open-loop and closed loop circuit solutions ([39] and [58]). Specifically, in
[58], the solution for a converter operating with a fixed duty cycle is found in the first
loop, and after that, the closed loop response was found in the second iteration loop.
Similarly, in [39], the converter power stage circuit and feedback control circuit are
modeled as separate blocks, the responses of these blocks are found first, and then the
final solution is found as the intersection point between the block responses.
65
Chapter 5
Time-Interval Approach in Periodic
System Steady-State Determination
5.1 Introduction
In the previous chapter, methods which are known from circuit theory area, specifically
the shooting method and sampled-data methods, were discussed. In this chapter, the time-
interval approach for solving the switching power converter steady-state determination
problem is presented. Two new methods based on the time-interval approach are
proposed. The key step in the time-interval approach is computation of the time interval
vector using a constraint equation. The constraint equation defines boundary conditions at
the instants of switching. With the first of the proposed methods, the constraint equation
is formulated using the state-space averaging technique. With the second method, the
constraint equation is formulated using exact analytical expressions for any circuit
66
variable at the switching time or its average or rms value. Compared to the existing
methods, the main benefits of the proposed methods include improvement of
convergence, reduction of the number of iteration loops, reduction of simulation time,
and reduction of the size of the system matrices.
5.2 Concept
Assume a piecewise linear state-space model of a switching power converter (3.6). A
change either in the initial state or a change in system inputs propagates through the
switching power network resulting in a specific trajectory of the state vector. Patterns of
time intervals, which are associated with alternating topologies of the converter, change
accordingly. At a periodic steady-state, the converter states repeat periodically.
Accordingly, converter topologies and time intervals associated with the converter
topologies repeat periodically as well. Thus, there is an expectation that, at the steady-
state, a relationship between the state vector, system inputs, and vector of time intervals
associated with the converter topologies exists:
(5.1)
where the term stands for a steady-state state vector, U is a vector of system inputs,
and T is the time-interval vector collecting all time intervals through associated
67
with duration of converter topologies:
(5.2)
The superscript T in (5.2) denotes the transpose operator.
For the purpose of illustration, assume a piecewise linear model of a closed-loop
switching power converter operating with two topological changes within the switching
period from Fig. 3.5. Launching from arbitrary initial conditions , the state vector
trajectory will exhibit a transient which eventually dies out and the system settles in
steady state. The transient trajectory of the state vector is illustrated in Fig.5.1.
Figure 5.1: Transient trajectory of a closed-loop converter circuit.
68
In Fig.5.1, terms and designate time intervals which are associated with the
time span of the converter’s first and second topology at the k-th switching cycle. For
example, is a time interval associated with duration of the first topology of the
converter at the k-th switching cycle. Nevertheless, the term is the switching time
when counting from the time of transition from the previous converter topology, i.e. from
. To simplify notation, the switching time and time interval as well as the
switching time vector and the time-interval vector will refer, in following, to the same
time and the same vector respectively while the switching time will be referenced to the
time of transition from the previous topology.
The particular expression for (5.1) relating the state vector, time interval vector, and
the system input at steady-state can be found using the shooting method. Assume that the
converter operates at steady-state, the state vector at the beginning of the switching
period is , and that the first and second time intervals are and respectively. Using
(3.18), while starting from the state vector at the beginning of the switching period, the
state vector at switching time is:
(5.3)
Using (3.18) again, while assuming initial conditions , the state vector at the end of
switching period is:
(5.4)
69
Shooting condition on and states at steady-state applies:
(5.5)
After substituting for and from (5.3) and (5.4), and manipulation with terms,
the relationship between the steady-state state vector , switching times and , and
the input can be found in the form:
(5.6)
where:
(5.7a)
(5.7b)
The explicit expression relating the network steady-state to switching times and ,
and the input U can be obtained from (5.6) in the form:
(5.8)
where the subscript ss denotes the steady-state state vector.
70
A general expression for (5.8) can be found in the following form:
(5.9)
where:
(5.10)
(5.11)
Ai and bi are state matrices, n is the number of topologies in steady-state, and T stands for
vector of the time intervals.
In summary:
1. As shown in (5.9) through (5.11), periodic steady-state can be represented by an
explicit function of the input U and time intervals T:
(5.12)
2. Knowing the input U, only the vector of time intervals T needs to be found to
determine the periodic steady-state xss. If the vector of time intervals T is known, the
steady-state can be computed by evaluating (5.12) at the vectors T and U.
71
3. The expression (5.8) can also be obtained using the sampled-data modeling method
discussed in Section 4.3. In this case, the steady-state relationship can be obtained as
a steady-state solution of a sampled-data large-signal model while the sampling time
is set to be identical with the switching period and no linearization step is involved.
4. The switching time vector can be computed using constraint equations defining
transitions between converter topologies (3.21). For formal reasons, the set of
constraint equations used in the next section will be in the following form:
(5.13a)
where particular components of the function f are:
(5.13b)
and the index i stands for a switching condition between the i-th and (i+1)-th
topologies.
72
Note:
The difference between methods of accelerated convergence and methods based on the
time-interval concept, or in short, time-interval steady-state methods, can be
characterized as follows:
- With the methods of accelerated convergence, the network steady-state is computed
directly. Specifically, the steady-state state vector is guessed first and then its corrections
are computed using Newton’s iteration as follows:
(5.14)
- In the time-interval approach to the steady-state problem, a general solution is
available in analytical form a priori. This advantage allows reducing the steady-state
problem to the problem of solving a set of constraint equations (5.13a) for time intervals.
Time intervals are collected in the time-interval vector. The time-interval vector is
guessed first and then its corrections are computed using Newton’s iteration as follows:
(5.15)
Having the time-interval vector determined, the steady-state can be computed by
evaluating (5.12).
73
5.3. Time Vector Computation Based on the State-Space Averaging
Technique
In this section, the procedure for the derivation of constraint equations which are
equivalent to (5.13) using the state-space averaging technique is presented, procedures for
error function derivation, and computation of the Jacobian matrix are explained.
Numerical examples are included.
5.3.1 Principles of the Method
The method of state-space averaging was presented in [59], [60], [41] and [42], and later
discussed in many other works (e.g. [21], [43]). The main goal of this method is to derive
a switching converter small-signal model and find the frequency response of networks
with switching converters. For this purpose, a converter is modeled as piecewise linear
circuit and the network equation is formulated using the state-space approach as shown in
(3.6). The derivation procedure includes a weighted addition of state-space matrices,
perturbation, and linearization. The weight of the state matrices is determined by the
duration of the topology for which the state matrices are derived.
To show principles of the state-space averaging technique, a procedure for the
derivation of the dc solution for a converter operating with two topological changes at
steady-state will now be described.
The weighted summation of the state matrices is expressed by the equations:
74
(5.16a)
(5.16b)
where is the duty ratio, is the duty ratio complement while:
(5.16c)
(5.16d)
and and are time intervals assigned to the duration of the converter’s first and
second topologies respectively.
The system described by equations (5.16) represents the switching converter’s large-
signal model. In order to derive a small-signal model, (5.16) can be perturbed by
introducing a variation of input , where is the dc line input voltage and
is the superimposed ac perturbation. Also, the duty ratio may change from cycle to cycle
and the variations may be expressed as where is the dc duty ratio and is
the ac perturbation. The perturbations of both the input and duty ratio cause a
corresponding perturbation in the state vector , where again, is the dc
component of the state vector and is the superimposed ac perturbation. Consequently,
the output y contains a dc component and a deflection . The averaged system (5.16)
with implemented perturbation is:
75
(5.18a)
(5.18b)
The dc solution can be obtained from equations (5.18) by multiplying the terms in
parenthesis and separating the dc terms in the form:
(5.19a)
(5.19b)
After substituting for d using (5.16c) the dc solution is
(5.20a)
(5.20b)
The general form of the dc solution applicable on a converter operating with n
topological changes within a switching period at steady-state which relates the steady-
state with the time intervals is:
76
(5.21a)
(5.21b)
Is it to be noted that the last time interval can be computed as a complement to the
switching period :
(5.22)
Applying the principle of small ripple ([21]), elements of the state vector in
(5.21a) can be obtained as functions of the time intervals. Further, the converter output
voltage in (5.21b) is guaranteed by operation of the converter feedback circuit and,
therefore, is known a priori. Consequently, the general formulation of the constraint
equation can be written as:
77
(5.23a)
(5.23b)
where stands for the average of the j-th state variable, is the converter average
output voltage, and the vector selects the j-th state variable from the
state vector.
As an example showing the average of a state variable, the average inductor current
in the buck converter operating in discontinuous conduction mode will now be found. A
schematic of this converter is included in the verification section in Fig.5.3. With this
converter, the waveform of inductor current can be well represented by a triangular
waveform as shown in Fig.5.2.
78
Figure 5.2: Inductor current in a DCM buck converter circuit.
Thus, the average inductor current over the switching period is:
(5.24)
The peak inductor current can be approximated by:
(5.25)
giving a final expression for the average current of the inductor in the form:
(5.26)
79
where is the converter input voltage, L is the converter inductor, and is the
converter average output voltage.
5.3.2 Computation Milestones
Eq. (5.23) is a set of non-linear algebraic equations involving matrix inversion and high
power terms of time intervals. Consequently, the search for an explicit expression for the
solution, i.e. the time interval vector T, may be a challenging problem. The solution,
however, can be found using Newton’s iteration method. The procedure for the necessary
steps including the formulation of the error function and derivation of the Jacobian matrix
is explained in this section.
Assume a buck converter operating in the discontinuous conduction mode from the
previous section. The constraint equations for this network can be derived from (5.23) by
setting n=3. For convenience, use the following substitutions:
(5.27)
(5.28)
(5.29)
(5.30)
80
To simplify the notation, terms on the left sides of expressions (5.27) through (5.30) will
be referred to in the following without and arguments.
After substituting (5.27) through (5.30) in (5.23), the constraint equations for the buck
converter network are:
(5.31)
(5.32)
To solve the set of equations (5.31) and (5.32) for , an error function is defined as:
(5.33)
where:
(5.34)
(5.35)
and the Jacobian matrix associated with the error function is:
(5.36)
81
With reference to (5.34) and (5.26), the J(1,1) element of the Jacobian matrix is defined:
(5.37)
which, after the partial differentiation by , takes the form:
(5.38)
The term
can be found using the following procedure. First, set:
(5.39)
and then differentiate both sides of (5.39) with respect to :
(5.40)
(5.41)
resulting in:
82
(5.42)
or:
(5.43)
In the next step, (5.43) is substituted in (5.38):
(5.44)
giving:
(5.45)
Finally, substitution of:
(5.46)
in (5.45) gives the J(1,1) term in form:
83
(5.47)
An analogous procedure can be applied to obtain the J(1,2) element:
(5.48)
(5.49)
(5.50)
(5.51)
After substituting (5.51) in (5.49):
(5.52)
(5.53)
and also substituting:
(5.54)
84
in (5.53), J(1,2) is obtained in the following form:
(5.55)
The J(2,1) term of the Jacobian matrix is:
(5.56)
After consecutive differentiation by , J(2,1) is:
(5.57)
(5.58)
After substituting for
from (5.43) J(2,1) is:
(5.59)
85
(5.60)
and:
(5.61)
where term is defined in (5.46).
Finally:
(5.62)
The J(2,2) element of the Jacobian matrix is:
(5.63)
After consecutive differentiation with respect to , J(2,2) is:
86
(5.64)
(5.65)
After substituting for
from (5.51):
(5.66)
(5.67)
and:
(5.68)
where is defined in (5.54).
87
Finally:
(5.69)
5.3.3 Error Function and Jacobian Matrix Generalization
In the previous section, the error function and the Jacobian matrix were derived using an
example of DCM buck converter operating in 3 topologies in steady-state. Using this
example, general forms of the error function and the Jacobian matrix for a switching
converter operating in n topology changes in steady-state can be written by inspection:
(5.70)
(5.71)
where the elements of the error function and those of Jacobian matrix are computed as
follows:
88
For
(5.72)
(5.73)
and for
(5.74)
(5.75)
where:
is an expression defining the average state variable as a function of time intervals
is a vector selecting the i-th state variable from the state vector, and
is a column vector defining sensitivity of the state vector to the time interval :
(5.76)
89
5.3.4 Numerical Verification
The performance of the proposed steady-state method was evaluated using various
topologies including buck and boost converters operating in DCM and CCM modes,
active clamp reset (ACR) forward converter with synchronous rectifiers, and isolated
flyback converter operating in CCM mode. Selected results are included.
Example1: Buck converter operating in DCM
The circuit of the buck converter operating in the DCM mode is shown in Fig. 5.3.
Circuit parameters were set as follows: Vg=12V, V0=5V, R=5Ohm, Fsw=200kHz,
inductor inductance and winding resistance were L=4.3uH and RL=0.05Ohm
respectively, capacitor capacitance and effective serial resistance were C=100uF and
RC=0.01Ohm respectively.
Figure 5.3: DCM buck converter.
90
To evaluate accuracy, the proposed method was compared with the fast time-domain
simulation method. Table 5.1 shows the time intervals at the steady-state.
Table 5.1: Steady-state time intervals.
Time Interval
Fast TD Simulation
Method
SSA Steady-State
Method
T1 (us) 1.6188 1.6108
T2 (us) 2.2166 2.2027
T3 (us) 1.1646 1.1865
Table 5.2 shows the output voltage and steady-state determination times. Initial
conditions for both methods were set to be identical by setting time intervals to Tsw/3.
With the fast time-domain method, the algorithm carried out the simulation over a
transient which took ~3000 switching cycles. In contrast to this, the proposed method
achieved convergence in 4 iteration cycles. Computation times for the fast time-domain
method and proposed method were 18.83 sec and 0.065 sec respectively.
Table 5.2: Output voltage and steady-state time determination time.
Method
Average Output Voltage
(V)
Computation Time
(sec)
Fast TD Simulation Method 4.9982 18.830
SSA Steady-State Method 4.9817 0.065
91
Waveforms of the converter output voltage and inductor current, as computed by
proposed steady-state algorithm (label b) and using the fast steady-state method (label a),
are shown in Fig. 5.4 and Fig 5.5. As Table 5.2 shows, the converter average output
voltage error is ~ 0.0165V or ~0.33%. This error is caused by the averaging concept
which is inherent to the proposed method. Therefore, a higher number of iterations do not
necessarily lead to higher steady-state accuracy. However, the error demonstrated in this
example is acceptable in practical design. The error between the inductor current
waveforms is negligible.
Figure 5.4: DCM buck converter output voltage.
0 2 4 6 8 10 12 14 16 18 204.96
4.97
4.98
4.99
5
5.01
5.02
5.03
time (us)
vou
t (V
)
b
a
92
Figure 5.5: Inductor current in DCM buck converter.
Example2: Boost converter operating in DCM
The circuit of the boost converter operating in DCM mode is shown in Fig. 5.6. Circuit
parameters were set as follows: V0 =5V, Fsw =500kHz, inductor inductance and winding
resistance were L=1uH and RL=0.05Ohm respectively, capacitor capacitance and
effective serial resistance were C=47uF and RC =0.01Ohm respectively.
0 5 10 15 20-0.5
0
0.5
1
1.5
2
2.5
3
time (us)
iL(A
)
b
a
93
Figure 5.6: DCM boost converter.
Table 5.3 demonstrates the accuracy and number of iterations needed to achieve steady-
state at nine operating points specified by the input voltage and current through the load
resistor. In each case, the number of iteration is less than four.
Table 5.3: Average output voltage vs. iteration number for DCM boost converter.
R=25Ohm R=12.5Ohm R=8.33Ohm
Vo N Vo N Vo N
Vg=3.0V 4.9899 2 4.9930 2 4.9963 3
Vg=3.3V 4.9909 3 4.9944 3 4.9960 3
Vg=3.6V 4.9923 3 4.9948 4 4.996 4
Fig. 5.7 shows the error functions E1 and E2 calculated using a two-dimensional Jacobian
function assigned to the boost DCM converter. As can be seen in this figure, only a single
94
solution exists. Also, the risk of failure of Newton’s iterations is minimal since both sur-
faces E1(T1,T2) and E2(T1,T2) are monotonous and shallow at wide neighborhood of the
solution.
Figure 5.7: Error functions.
Example3: ACR forward circuit with synchronous rectifiers
The circuit diagram of the ACR forward converter with synchronous rectifiers is shown
in Fig. 5.8. The circuit parameters were set as follows: V0=5V, Fsw=214kHz, Np=18,
Ns=7, transformer magnetizing inductance Lm=0.8mH, primary and secondary winding
resistances Rp=0.2Ohm and Rs=0.04Ohm, inductor inductance and winding resistance
95
were L=8uH and RL=0.04Ohm respectively, Cr=22nF, C=40uF, RC=0.012Ohm and
current sensing resistor Rcs=0.1Ohm.
Figure 5.8: ACR forward converter.
Table 5.4 shows the number of iterations and converter average output voltage at nine
operating points specified by the input voltage and current through the load resistor. At
no case were more than four iterations needed to find steady-state.
Table 5.4: Average output voltage vs. iteration number for ACR forward converter.
R=5Ohm R=2.5Ohm R=1.67Ohm
Vo N Vo N Vo N
Vg=38V 4.9969 3 4.9970 3 4.9972 4
Vg=48V 4.9972 2 4.9972 3 4.9973 3
Vg=58V 4.9976 3 4.9976 3 4.9976 3
96
Table 5.5 demonstrates the accuracy of determining the steady-state at a 48V input
voltage and 2A load current. The converter output and all state variables of the ACR
forward converter at the instants of switching in four consecutive switching cycles are
shown. The steady-state was found within 4 iteration cycles.
Table 5.5: ACR forward converter output voltage and state variables at steady-state.
Time
(us)
Switching
Cycle No.
v0
(V)
Im
(A)
vcr
(V)
iL
(A)
vc
(V)
0 start time 4.9915 -0.0464 79.9608 1.2573 4.9944
2.1080 1 4.9981 0.0467 79.9608 2.7274 4.9952
5.0000 1 4.9915 -0.0464 79.9608 1.2573 4.9944
7.1080 2 4.9981 0.0467 79.9608 2.7274 4.9952
10.0000 2 4.9915 -0.0464 79.9608 1.2573 4.9944
12.1080 3 4.9981 0.0467 79.9608 2.7274 4.9952
15.0000 3 4.9915 -0.0464 79.9608 1.2573 4.9944
17.1080 4 4.9981 0.0467 79.9608 2.7274 4.9952
20.0000 4 4.9915 -0.0464 79.9608 1.2573 4.9944
97
5.4 Time Vector Computation Based on Generalized Constraint
Conditions
In the previous section, a technique based on the state-space averaging was used to define
the constraint equation. The constraint equation is solved using Newton’s iteration
method with the analytical form of the Jacobian matrix. The resulting steady-state
algorithm is simple and fast giving accurate results for hard-switching power converter
topologies. However, the error introduced by state-space averaging can have an impact
on accuracy in cases of resonant converters. In this section, a method based on a
generalized approach to the formulation of the constraint equations is presented. This
method is suitable for all switching power converter topologies, including the resonant
converters.
5.4.1 Principles of the Method
Generalized constraint conditions (GCC) are defined by replacing some of the constraints
in equation (5.13) with new constraints which are set according to design targets
bonding the switching times in a new way ([16]). The formal notation for a set of
generalized constraint equations is:
(5.80)
98
In principle, any circuit variable at the switching time and its average or rms value can be
used to define the term . Referring to the buck converter operating in
continuous operation mode in Fig.3.5, the boundary condition:
(5.81a)
can be replaced by any of the following:
(5.81b)
(5.81c)
(5.81d)
(5.81e)
(5.81f)
(5.81g)
99
where terms through are constants selected according to the design targets for the
voltage across capacitor C at the time T1, inductor current at the time T1, converter
average output voltage , inductor average current , average output current
, and rms of the converter output voltage
Using any of the constraint conditions (5.81b) through (5.81g) as a replacement for
(5.81a), a corresponding steady-state can be found. Consequently, the role of the
feedback circuit in the steady-state algorithm becomes redundant. This specifically
applies to (5.81d). By using this new constraint condition, the feedback control loop may
get open and, eventually, can be removed from the system description. Consequently,
numerical problems caused by the error amplifier reported in [39] and [58] are eliminated
and two-loop steady-state algorithms can be replaced by a single-loop solution ([16]). For
this benefit, the analytical form of the converter average output voltage will be derived.
An accurate analytical form for average output voltage of a converter can be found
using the integration of the network output equation (3.6b) over the converter switching
period Tsw:
(5.82)
100
where the network output y includes the converter output voltage vo:
(5.83)
and superscript T in (5.83) stands for the transpose operator.
Using the solution of (3.6a) and (3.6b) for i=1, 2, ..., n, (5.82) can be expressed as sum of
n integrals over the period Tsw:
(5.84)
After substituting (3.6b) for , (5.84) becomes:
(5.85)
101
Further, substituting for the term in each integral:
(5.86)
(5.85) becomes:
(5.87)
where the term stands for the state vector at the transition from the i-1-th to the i-th
topology.
Further, the sum of the integral in (5.87) can be written as:
(5.88)
102
and after computing the integral and manipulation of the terms, the output is:
(5.89)
or:
(5.90)
where:
(5.91a)
(5.91b)
and:
for i = 1 (5.91c)
for i >1 (5.91d)
where:
(5.91e)
103
Finally, the constraint equation defined using the converter average output voltage Vo
comes in the following form:
(5.92)
where the row vector =[0 0 … 1] selects the converter output voltage from the vector Y.
5.4.2 Computation Milestones
Constraint equations (5.81) are non-linear equations including matrix exponential terms.
To find the solution, Newton’s iteration method can be applied. The procedure for the
necessary steps, including formulation of the error function and derivation of the Jacobian
matrix, is included in this section.
i) Error Function
The generic form of the error function and that of the Jacobian matrix is similar to (5.70)
and (5.71) respectively. The particular entry of the error function directly results from the
definition of particular constraints:
104
(5.93a)
(5.93b)
If the average output voltage Vo is selected as a constraint, then the error function is
defined as:
(5.94)
where the vector is defined in (5.89), and is a row vector selecting the average output
voltage of the converter from vector .
ii) Jacobian Matrix
The search for an analytic form of the Jacobian matrix is a tedious process. The analytical
form of the Jacobian matrix for circuits operating with a small number of topologies can
be found using reasonable effort. However, with circuits operating with a higher number
of topologies, or in the case of a search for a general form, the effort to derive the
analytical Jacobian matrix becomes substantial. The specific difficulties are introduced by
nested differentiations of intermittent terms associated with a higher number of intervals.
For these reasons, the numerical form of the Jacobian might be preferred.
The most intuitive numeric computation of the Jacobian matrix is using small
perturbations introduced to the elements of the switching time vector and observing
105
relevant changes of the error function. Then, at each Newton’s iteration cycle k, elements
of the Jacobian matrix can be computed as follows:
(5.95)
where Tj is a perturbation in the j-th element of the switching time vector T, Td,j is a
switching time vector with perturbed j-th element, and Ei(Td,i) and Ei(T) are the values of
the i-th element of the error function in the perturbed and un-perturbed switching time
vector Td,j and T respectively.
Note:
During the development of simulation algorithms for various switching converter
topologies, it was shown that the areas of successful initial guess, especially with cases of
resonant converters, were relatively small. This conclusion applies to both the sampled-
data modeling method and proposed GCC steady-state method. To extend the area of
successful initial guess, the value of the Jacobian matrix can be modified. A method
analogous to the damping single-dimension Jacobian was used. Specifically, elements in
the main diagonal and elements outside the main diagonal were reduced by multiplying
them by numbers less then 1 as shown in (5.96):
106
(5.96)
where the subscript d stands for the damped form of Jacobian matrix.
From the results from multiple experiments, convergence was substantially improved by
setting parameter between 0.5 and 0.8, and parameter between 0.2 and 0.6.
iii) Initial Guess
The initial guess is a crucial step in the Newton’s iteration algorithm when solving the
constraint equations (5.13) and (5.80). The initial guess affects the rate of convergence or
can even cause convergence failure if made incorrectly. To solve (5.13), some authors
(e.g. [37]) suggest making the initial guess for both the switching time vector T and
steady-state state vector . However, no closer instruction on how to obtain values for
initial guess for the switching vector T, nor for the state vector were found in
literature. Guidelines on making the initial guess are formulated in this work.
In this thesis, initial guess problems were studied using various converter circuits
including hard-switching and soft-switching topologies operating in a closed loop. A
common conclusion is that the difficulty of making an initial guess of switching times T
comes from the fact that all components of the error function have an oscillatory
107
character. This specifically applies to resonant converters. Consequently, a wrong guess
for the time interval may cause the algorithm to converge into a wrong and meaningless
solution.
As an example, results from the convergence investigation using a ZCS quasi-
resonant buck converter operating in four topologies within the switching cycle, is shown
in Fig. 5.15. The error function consists of four components E1 through E4, each
associated with a corresponding instant of switching. Specifically, Fig. 5.9 shows the
third component of the error function as a function of the initial guess.
Figure 5.9: Error as a function of initial guess.
The horizontal axis represents the initial guess of T3 and the vertical axis represents the
corresponding value of the error function E3. An initial guess of T3 made within 0µs and
10µs leads to the correct solution (A). A guess made outside this area will either cause
108
the algorithm to diverge or to converge to an incorrect, physically meaningless solution
(B or C).
To overcome the convergence problems caused by the initial guess, the following
guidelines can be adopted:
i) Determine the number of non-resonant transitions p and resonant transitions q
within the switching period
ii) Make an initial guess of a time interval associated with resonant transition Tg,i
as follows:
(5.97)
Make an initial guess of a time interval associated with non-resonant transition
Tg,j as follows:
(5.98)
where i=1,2,… q, j=1,2,...p, is a period of the i-th resonant tank, and is the number
of resonant periods included in the i-th time interval
iii) Using ii), make an initial guess of time interval vector :
(5.99)
109
iv) Knowing converter inputs and having the initial guess of T identified, make
an initial guess of the state vector by evaluating (5.12).
5.4.3 Numerical Verification
The proposed method was implemented using several switching converter closed-loop
topologies including buck and boost converters operating in both continuous and
discontinuous operation mode, and resonant ZCS boost and ZCS buck converters. The
performance and advantages of the proposed method in terms of accuracy, speed, and
convergence were evaluated. Selected results are included.
Example1: Closed-loop DCM buck converter
The circuit of the buck converter operating in the DCM mode is shown in Fig. 5.10.
Circuit parameters were set as follows: Vg =12V, V0 =5V, inductor inductance and
winding resistance were L=4.3uH and RL=0.05Ohm respectively, capacitor capacitance
and effective serial resistance were C=100uF and RC =0.005Ohm respectively, load
resistor R=5Ohm, feedback circuit parameters were R1=820Ohm, R2=10kOhm,
R3=1MOhm, R4=820Ohm, C4=1500nF, C5=820nF, Vref =2.5V and switching frequency
Fsw =200kHz.
110
Figure 5.10: Closed-loop DCM buck converter.
Table 5.6 shows steady-state computation accuracy. The steady-state was computed very
accurately with both the generalized constraint conditions (GCC) steady-state method and
sampled-data method. This table shows a small error of the state-space averaging (SSA)
based steady-state method caused by the averaging step. The computation time was
negligible with all methods.
Table 5.6: Output voltage and steady-state determination time.
Method
Average Output Voltage
(V)
Computation Time
(sec)
GCC Steady-State Method 5.0000 0.101
Sampled-Data Method 4.9999 0.081
SSA Steady-State Method 4.9823 0.053
Each method in Tab.5.6 employs the Newton iteration algorithm. At each Newton
iteration cycle, the average output voltage of the converter V0 was computed. To
111
demonstrate the convergence property of each method, the trajectory of the average
output voltage of the converter as a function of the iteration number is shown in Fig.5.11.
Traces a, b, and c are assigned to the GCC method, sampled-data method, and SSA
method respectively. Fig.5.12 shows error trajectories of Newton’s iterations. Trace
assignment is the same as with Fig.5.11. Initial conditions for all methods were set to be
identical using (5.12). Errors attenuate very quickly with the GCC and SSA methods.
However, with the sampled-data method, the error does not die out. This phenomenon is
caused by defining the error function involving the feedback circuit as shown in (5.81a).
Figure 5.11: DCM buck converter output voltage trajectory.
0 2 4 6 8 10 12 14 16 18 204.975
4.98
4.985
4.99
4.995
5
Iteration Number
Vo
(V)
a
b
c
112
Figure 5.12: Error trajectory.
To illustrate the convergence problems with sampled-data modeling methods, Fig.
5.13 shows un-damped oscillation of the error trajectory and its changes with different
sets of feedback circuit parameters. The circuit parameters were set as follows: a)
parameters are listed above, b) R1=1kOhm, R2=1kOhm, R3=800kOhm, R4=10kOhm,
C4=680nF, C5=820nF, and c) R1=0.5kOhm, R2=0.5kOhm, R3=1500kOhm, R4=33kOhm,
C4=470nF, C5=820nF. Traces in Fig.5.13 are labeled with a, b, and c accordingly. The
convergence of the proposed method is demonstrated in Fig. 5.14.
113
Figure 5.13: Error trajectory with a sampled-data method.
Figure 5.14: Error trajectory with the GCC method.
114
Example 2: Closed-loop ZCS buck converter
In this example, the algorithm convergence improvement with the GCC method was
investigated using a ZCS quasi-resonant buck converter operating in four topologies
within the switching cycle. The converter circuit is captured in Fig. 5.15. Circuit
parameters were set as follows: Lr=1uH, RLr=0.01Ohm, Cr=2.2uF, Rr=0.002Ohm,
C=72uF; RC=0.007Ohm, L=100uH, RL=0.02Ohm, R=0.5Ohm, R1=1kOhm, R2=1kOhm,
R3=800kOhm, R4=4.7kOhm, C4=470nF, C5=820nF, Vref=2.5V, Vg=12V, and V0=5V.
Figure 5.15: Closed-loop ZCS buck converter.
In this example, the error function consists of four components E1 through E4. The error
norms with both the GCC method and sampled-data method are shown in Fig.5.16.
Compared to the fast error reduction with the GCC method (a), the error with the
sampled-data modeling method (b) does not die out as the number of iterations increases.
L RL
Vg
C
Rc R
Lr
Cr
S RL
R1
R2
Driver
Rr D2
Vref + -
C5
C4
R3
V/F
FB Circuit
D1 vo
R4
115
Figure 5.16: Error norm trajectory.
To investigate the convergence more closely, the initial guess was intentionally set close
to the solution. Particularly, the errors of initial time intervals E1 through E4 were set to
1%. With the sampled-data method, the Fig. 5.17 shows that the component of the error
function E4 associated with feedback circuit operation does not converge. Instead, this
error component oscillates around the solution. Experiments showed that the magnitude
of these oscillations depends on the circuit parameters, particularly on those included in
the error amplifier circuit. Contrarily, all components of the error function rapidly
decrease with the proposed GCC method (Fig.5.18).
0 2 4 6 8 10 12 14 16 18 2010
-14
10-12
10-10
10-8
10-6
10-4
10-2
100
102
104
Iteration Number
norm
(E)
b
a
116
Figure 5.17: Sampled-data method error trajectory.
Figure 5.18: Proposed GCC method error trajectory.
0 2 4 6 8 10 12 14 16 18 20-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
Iteration number
E1,
E2,
E3,
E4
E4
E1
E3
E2
0 2 4 6 8 10 12 14 16 18 20-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
Iteration number
E1,
E2,
E3,
E4
E1
E4
E3
E2
117
Fig. 5.19 captures steady-state waveforms of resonant inductor current , resonant
capacitor voltage , output inductor current , and output voltage as computed
using the GCC steady-state method. Table 5.7 shows the performance of the GCC steady-
state method and sampled-data method in terms of speed and accuracy.
Figure 5.19: Closed-loop ZCS buck converter steady-state waveforms.
Table 5.7: Output voltage and computation time.
Method
Average Output
Voltage (V)
Computation Time
(sec)
Number of
Iterations
GCC Steady-State Method 5.0000 0.771 4
Sampled-Data Method 4.9888 0.849 5
0 20 40 60 80 100-5
0
5
10
15
20
25
30
vo(
V)
iL(A
)
vCr (
V)
iLr(A
)
Time (us)
118
5.5 Summary
In this chapter, the time-interval approach to the problem of steady-state determination
was presented. With this approach, the time-interval vector corresponding to the duration
of converter topologies is computed first. The time-interval vector is found as a root of
the constraint equation describing the boundary conditions between converter topologies.
Then, the network state vector is computed by evaluating the expression which is known
a priori.
Two new steady-state methods based on the time-interval concept were presented.
These two methods are based on a new formulation of the constraint equations. With the
first method, the constraint equations are formulated using the state-space averaging
technique. With the second method, the constraint equations are formulated using exact
analytical expressions for any circuit variable at the switching time or its average or rms
value. Design targets can be used to formulate the constraint equations. Compared to the
sampled data methods and methods of accelerate convergence, the computation
algorithms with the two proposed methods involve only one iteration loop and do not
suffer from convergence issues. Special attention was paid to the initial guess problem.
Recommendations on making the initial guess were formulated. A multidimensional
damping technique was proposed as a method for expanding the initial guess area.
119
Chapter 6
Generalized Steady-State Method for
Networks with Multiple Switching Power
Converters
6.1 Introduction
In previous chapters, the focus was on methods for computing the steady-state of a
network with one switching power converter. In the next two chapters, methods for
steady-state determination of networks with multiple switching power converters are
presented.
The analysis of networks with multiple switching power converters has been
approached by several authors by using a behavioral model based on the black-box
characterization ([75] through [77]). The averaging techniques (e.g. [21], [41]-[43], [63])
120
allow for computing approximate response of the switching power converter and can be
extended to the area of networks with multiple converters. However, instead of details of
the power converter operation within the switching cycle, the focus of these papers was
on modeling the converter small-signal response while the area of dc analysis and the
area of system ripple analysis were not covered in adequate depth.
In this chapter, the method referred to as the generalized steady-state method for
networks with multiple switching power converters is presented. Milestones of this
method including the principles, derivation of the constraint equation, definition of the
error function, and computation of the Jacobian matrix are explained. Numerical
examples are included.
6.2 Principles of the Method
The key idea behind the generalized steady-state method for networks with switching
power converters is to model the whole network as a single piecewise linear system.
Assume the network consisting of multiple switching power converters shown in Fig.6.1.
Further, assume that the behaviour of each switching converter in this network can be
represented using the piecewise linear model. Also, assume that all converters included in
this network operate using the same switching period , operation of this network is
periodic, and the period of the network operation is The system equation for this
network is:
121
(6.1a)
(6.1b)
for
Figure 6.1: Network with multiple switching converters.
where the state vector includes all capacitor voltages and inductor currents in
the network, ,
, , and
are the network
system matrices, is the system output, is the input vector, and
122
represent the starting and finishing times of the i-th topology, is a duty
ratio of the i-th topology, and index i is equal to 1, 2, … depending on the network
topology.
The number of topologies within the network switching cycle depends on the
number of converters in the network, number of topologies each of them operates in, and
synchronization phases among converters. For the purpose of illustration, the number of
network topologies in case of N converters operating in two topologies is .
The network state trajectory is shown in Fig.6.2.
Figure 6.2: Network state evolution at periodic steady-state.
In Fig.6.2, vectors through represent the network state at the switching instants,
through are times corresponding to duration of the network topologies, ,
and through are phase shifts of individual converters in this network.
By applying the Newton shooting method on the network equation (6.1), while
keeping the input constant, the network periodic steady-state solution can be found
in the following form:
123
(6.2)
where T is the switching time vector consisting of time intervals through , and U is a
vector of independent inputs.
Similar to the case of networks with one switching converter presented in Chapter 5,
the constraint equation can be formulated and T can be found as a solution to this
constraint equation. After T is known, the network steady-state is computed by evaluating
(6.2).
6.2.1 Constraint Equation Derivation
The pattern of the network time intervals in Fig. 6.2 consists of intervals through .
The vector T collecting the network time intervals:
(6.3)
can be expressed as a function of network period Tsw, vector of phase-shift times Ts, and
converter internal switching times vector Tc:
(6.4)
124
or shortly:
(6.5)
where the vector of phase-shifts is:
(6.6)
the vector of converter internal switching times is:
(6.7)
Notes:
1. The phase-shift times included in Ts and switching period Tsw are known design
parameters. However, the converter internal switching times Tc are adjusted by individual
converters, e.g. by converter control loops, according to inputs and loads. Therefore the
converter internal switching times Tc are not known a priori.
2. Eq. (6.4) shows that to compute the network switching time vector T, the vector of
converter internal switching times Tc needs to be determined.
125
As an example, consider a network of two power converters POL1 and POL2 shown
in Fig. 6.3.
Figure 6.3: Network with two switching converters.
Also, assume that each of these converters operates in two topologies within
switching period Tsw and that the time shift between the beginnings of the switching
cycles of individual converters is Ts. Table 6.1 summarizes the status of switches over
one switching period. Fig. 6.4 shows the evolution of network switching times. The
intervals Ton1 and Ton2 stand for converter internal switching times and represent the
lengths of the on-time topologies of converters POL1 and POL2 respectively. In this
example, Ts is set such that the network topology changes four times within the
switching period.
126
Table 6.1: Network switching table.
Topology
Number
Ti
Switch Status
S11 S12 S21 S22
1 T1 ON OFF OFF ON
2 T2 ON OFF ON OFF
3 T3 OFF ON ON OFF
4 T4 OFF ON OFF ON
Figure 6.4: Switching times in network with two switching converters.
The transitions of the network state vector over the network switching period is
illustrated in Fig. 6.5. It is apparent that the state variables associated with the POL1
converter circuit iL1 and vC1, as elements of the network state vector, transition from state
to state through the intermittent state which is enforced to this network by
the switching operation of converter POL2. Similarly, the state variables associated with
POL2 converter circuit iL2 and vC2 transition from the state to the state through
the intermittent state which is imposed to this network by the switching operation of
converter POL1.
127
Figure 6.5: Network state vector evolution at periodic steady-state.
The relation between Ta and T can be written by inspection as follows:
(6.8)
from which T can be obtained using the matrix inversion operation as:
(6.9)
or shortly:
(6.10)
128
where Ta consists of the phase-shift Ts, converter internal switching times Tc and the
network period Tsw.
Eq. (6.9) shows that in order to determine the network switching times T, the
converter internal switching times Ton1 and Ton2 need to be found. Therefore, the
converter internal switching times Ton1 and Ton2 are used to formulate the constraint
equations.
To formulate the constraint equations, either the sampled-data method can be used
leading to:
(6.11a)
(6.11b)
or the generalized method for the formulation of constraint equations (5.81b) through
(5.81g) can be applied. If the average output voltage of a converter is used as the
constraint, the constraint equations are:
(6.12a)
(6.12b)
where terms Vo1 and Vo2 are the average output voltage of converter POL1 and POL2
respectively.
129
Similar to a network with one switching converter, the set of constraint equations (6.11)
or (6.12) creates a set of non-linear equations including matrix exponential terms.
Therefore, searching for a solution to (6.11) or (6.12) leads to the use of iterative
numerical methods such as Newton’s iteration algorithm:
(6.13)
where, beginning from an initial guess, the vector T is being corrected using Jacobian
matrix J until the error E is sufficiently small.
6.2.2 Error Function Definition
The generic form of the error function is identical to (5.70). Similar to the method for
networks with one switching converter, particular elements of the error function directly
result from the definition of particular constraint:
(6.14a)
(6.14b)
If the average output voltage of a converter is selected to define the constraint equation,
the error function is defined:
130
(6.15)
where the formal definition of the network output vector is identical to (5.82), is
the desired average output voltage of this converter, and is a row vector selecting
from .
6.2.3 Computation of the Jacobian Matrix
Analytic form of the Jacobian matrix can be found by differentiating (6.14) or (6.15)
however the derivation procedure would require substantial effort. Specifically, issues
experienced with networks with one converter originated by composed differentiations
would be magnified since the number of topologies with networks consisting of multiple
switching converters can be substantially larger. For this reason, a numerical way of
computing the Jacobian matrix can be preferred.
The generic form of the elements of the numerical Jacobian matrix is identical to the
one used for networks with one switching converter (5.95):
(6.16)
131
where Tj is a perturbation in the j-th element of the switching time vector T, Td,j is a
switching time vector with perturbed j-th element, Ei(Td,i) and Ei(T) are the values of the
i-th element of the error function in the perturbed and un-perturbed switching time
vectors Td,j and T respectively, and k is the number of the Newton’s iteration cycle.
6.3 Numerical Verification
The proposed steady-state method for networks with switching power converters was
evaluated using a network of two buck converters which were connected in parallel as
shown in Fig. 6.6. Each of these converters was set to operate in continuous conduction
mode, changing its topology twice during the switching cycle. Circuit parameters were
set as follows: Rg=0.01Ohm, C0=220uF; R0=0.08Ohm, C1=10uF; R1=0.01Ohm, L1=1uH,
RL1=0.02Ohm, C3=50uF; R3=0.01Ohm, C2=10uF; R2=0.01Ohm, L2=1uH, RL2=0.02Ohm,
C4=50uF; R4=0.01Ohm, I1=5A, I2=10A, Fsw=300kHz, Vo1=3.3V, Vo2=1.2V, and Vg=12V.
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Figure 6.6: Experimental network with switching converters.
Three synchronization schemes were evaluated: a) in-phase synchronization when both
converters enter the on-time topology at the same time, b) 1800 phase synchronization
when the beginnings of the on-time topologies are delayed by one half of the switching
period, and c) leading-trailing edge phase synchronization when the beginning of the on-
time topology of the converter POL2 is synchronized with the termination of the on-time
topology of the converter POL1. The evolution of switching times for these
synchronization schemes is captured in Fig. 6.7.
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Figure 6.7: Synchronization schemes.
a) Evaluation of Steady-State Convergence
Convergence of the proposed steady-state method was investigated using several
techniques, each depended on the way of computing the Jacobian matrix. Compared to
evaluation of the analytically-derived Jacobian, the differentiation techniques for the
Jacobian numerical computation include inherent errors which are coming from finite
perturbations of arguments of the error function. Having the goal to evaluate the impact
of the numerical Jacobian on the algorithm convergence, three algorithms were assessed
134
in this thesis. The idea behind these algorithms is to perturb the vector of network
switching times T such that it affects the minimum number of time intervals collected in
vector Ta. The relation between the perturbed vector of network switching times Td,j and
perturbed vector Tad,j directly results from (6.10):
(6.17)
1. Forward perturbation
With this algorithm, only one element of T is perturbed at a time:
(6.18)
It should be noted that, using this method, a small perturbation in one element of T can
lead to perturbation of multiple time intervals collected in Ta. For instance, using the
example of the in-phase synchronization scheme in Fig. 6.7(a), the perturbation of T1 not
only leads to the perturbation of Ton2 but it also leads to the perturbation of both Tsw and
Ton1.
2. Forward perturbation with correction
With this algorithm, one element of T is perturbed and a correction to another time
element collected in T is made such that there is no change to Tsw:
135
(6.19)
With the in-phase synchronization network shown in Fig. 6.7(a), the perturbation to T2
can be compensated by a reduction of the same magnitude to T3 such that Tsw remains
unchanged.
3. Forward perturbation with adjacent interval correction
With this algorithm, one time element of T is perturbed and a correction to the
proceeding time element of T is made. Consequently, there is no change to Tsw and the
impact of this perturbation on Ta is minimized:
(6.20)
With the network in-phase synchronization shown in Fig.6.7(a), the forward perturbation
of T1 can be compensated by a reduction of T2 of the same magnitude. This way, both
Ton1 and Tsw remain unchanged.
Two sets of component parameters in the common section of the network circuit
were used to test the convergence properties of the proposed method. The purpose of
different settings was to assess the influence of coupling between the converters on the
convergence. The part of the network affecting the coupling between the converters
includes the capacitor C0, ESR of this capacitor R0, and source output resistance R. With
136
the first parameter set, the component values were R=0.01Ohm, R0=0.08Ohm, and
C0=220uF. With the second case, the values of these parameters were set such that the
coupling between the converters POL1 and POL2 was significantly increased. The
following component parameters were used: R=1Ohm, R0=1Ohm; and C0=22uF.
Figures 6.8 and 6.9 show the norm of error trajectories obtained for all test cases.
Labels 1 to 3 in these figures refer to the method used to calculate the Jacobian matrix.
The initial conditions were identical for each test. The perturbation increment of T was
set to 1%. In all test cases, convergence was achieved in less than five iteration steps. The
influence of converter coupling on the algorithm convergence was demonstrated.
However, the impact of coupling on the number iterations is not significant. With both
types of networks, the best performance was found with the algorithm that used the
Jacobian with forward perturbation with adjacent interval correction.
137
Figure 6.8: Error trajectory for a network with weak coupling between converters.
Figure 6.9: Error trajectory for network with strong coupling between converters.
138
b) Steady-State Simulation
Simulation algorithms were implemented using Matlab. The typical simulation time
including determination of the steady-state and computation of selected waveforms was
0.46s. By contrast, the simulation time using the commercial simulator LTSpice,
beginning the simulation from initial conditions close to the solution, was 62.3s (Intel®
Core (TM) i5-3340M CPU @ 2.70GHz).
Example 1: Voltage and current ripples at the common input node
The voltage ripple across the common input node Vc (Fig. 6.10) and source current Ig
waveform (Fig. 6.11) were observed to evaluate the effectiveness of the synchronization
schemes of the converter network. Symbols a, b, and c are assigned to the in-phase
synchronization, 1800 phase synchronization and leading-trailing edge synchronization
respectively. The plots demonstrate that the worst case ripples occur with the in-phase
synchronization when both converters enter the on-time topologies simultaneously (both
S11 and S21 are turned on and S12 and S22 are turned off at the same time). Consequently,
the source current as well as the voltage ripple at the common node is the biggest. The
smallest ripple occurs with the 1800 phase synchronization.
139
Figure 6.10: Common node voltage ripple.
Figure 6.11: Source current.
140
Example 2: Network waveforms with the 1800 phase synchronization
Steady-state waveforms of the input currents of the POL converters which were obtained
by simulation using Matlab are captured in Figures 6.12 and 6.14. Sections of negative
currents in these plots show that there are small intervals within the switching cycle when
converters provide power each to other. Figures 6.13 and 6.15 show waveforms of these
currents as they were obtained by simulation using the LTSpice simulator. Minor
differences are caused by the presence of detailed models of switching devices used in
the LTSpice simulation. Plots showing the output voltages and inductor currents of both
converters POL1 and POL2 are shown in Fig. 6.16 and Fig. 6.18 respectively. To
compare, Figure 6.17 and 6.19 show these waveforms as they were simulated using the
LTSpice simulator.
141
Figure 6.12: POL1 converter input current.
Figure 6.13: POL1 converter input current by commercial simulator.
0 2 4 6 8 10-4
-2
0
2
4
6
8
10
Time (us)
Ia (A
)
142
Figure 6.14: POL2 converter input current.
Figure 6.15: POL2 converter input current by commercial simulator.
0 2 4 6 8 10-2
0
2
4
6
8
10
12
Time (us)
Ib (A
)
143
Figure 6.16: POL1 converter output voltage and inductor current.
Figure 6.17: POL1 converter output voltage and inductor current by commercial
simulator.
144
Figure 6.18: POL2 converter output voltage and inductor current.
Figure 6.19: POL2 converter output voltage and inductor current by commercial
simulator.
145
6.4 Summary
In this chapter, the time-interval concept used to determine the steady-state of networks
with one switching converter was extended to networks with multiple switching
converters. The relationship between the converter network switching times and
converter internal switching times was formulated. The constraint equation can be
generated using a generalized approach presented in Section 5.4. The constraint equations
can be solved using Newton’s iteration method with the numerical form of the Jacobian
matrix. The resulting steady-state algorithm is accurate, simple and fast, operating
without restriction on the power converter topologies.
A variant of the presented method may also be implemented using the constraint equation
formulated with the SSA technique. Similar to the network with one switching converter,
the constraint equation can be solved using Newton’s iteration method. Relationships
defining the error function and Jacobian derived for a network with one switching
converter (5.70) through (5.71) also apply.
146
Chapter 7
Steady-State Determination of Switching
Power Converter Networks using
Harmonic Balance
7.1 Introduction
In Chapter 6, a network consisting of multiple switching power converters was modeled
and analyzed as one large network. As the number of switching converters in the network
grows, the number and size of system matrices in the network equation (6.1) increases.
Consequently, formulation of the network equation becomes a tedious process.
Specifically, the number of linear topologies, i.e. the number of system matrices, can be
large. For example, the number of linear topologies in a synchronized converter network
consisting of N converters, with each operating in 2 topologies within a switching cycle,
147
can be as large as . More importantly, the procedure for identifying particular
topologies using a combination of the states of all switches in the network may be
cumbersome since, in general, the state of each internal switch is not known and needs to
be guessed.
In this chapter a new steady-state method based on harmonic balance is presented.
The converter switches are replaced by current and voltage sources generating switching
waveforms identical to those which are present in a circuit with switches. Consequently,
the switching converter can be modeled as a system consisting of small linear sub-circuits
with periodic non-sinusoidal inputs which are correlated with voltages and currents in
adjacent sub-circuits. The relationship between the voltage and current sources in all sub-
circuits is formulated in both the time-domain and frequency domain. The solution for
networks operating with known switching times is found by solving a system of linear
algebraic equations. In the case of networks with unknown switching times, the steady-
state computation includes solving the constraint equation using Newton’s iteration
algorithm.
148
7.2 Principles of the Method
7.2.1 Basic Concept
The basic concept of the proposed method can be illustrated using a simple example
of a buck converter circuit. The proposed technique, however, is general in nature and
can be applied to circuits with other converters as demonstrated in the verification section
7.6.
Consider the buck converter in Fig. 7.1 operating with two topology changes within a
switching period . Assume that the converter switching times are known. During
operation in the first topology, is on and is off. It applies that
and . During the second topology, is off and is on causing the
converter circuit to decouple into two sub-circuits while and .
Figure 7.1: Buck converter with ideal switches.
Examples of voltage and current waveforms, which are present across the converter
switches when the converter operates in a periodic point, are shown in Fig. 7.2.
149
Figure 7.2: Buck converter switching waveforms. Relations between the switching waveforms of voltages and currents can be summarized
as follows:
(7.1a)
(7.1b)
(7.2a)
(7.2b)
Replace the switching devices of this converter with current and voltage
sources generating current and voltage waveforms identical to those present in the circuit
with switches. The resulting converter model is shown in Fig. 7.3.
150
Figure 7.3: Buck converter model.
The network equations can be written in the following form:
(7.3a)
(7.3b)
where vectors and
represent nodal variables of sub-circuit1 and sub-
circuit2 respectively, m and n are the numbers of nodal variables in sub-circuit1 and sub-
circuit2 respectively, ,
and
are modified
nodal conductance and susceptance matrices, input vector includes sources
and current source , and input vector includes source .
Relations between the switching waveforms of currents and voltages (7.1) and (7.2) are
imposed to the buck converter model through correlating sources and with
voltage and current respectively in adjacent sub-circuits.
151
7.2.2 Fourier Series Expansion of the Switching Waveforms
Due to the periodic operation of switching devices and , all switching
waveforms , , and can be expressed using non-sinusoidal periodic
functions. Thus, all switching waveforms can be represented in the frequency domain
using Fourier series expansions as follows:
(7.4a)
(7.4b)
(7.4c)
(7.4d)
where
is the fundamental angular frequency, and K is the number of
harmonic components.
Denote vectors of the Fourier series coefficients assigned to , , and in (7.4)
as follows:
152
,
,
, and
(7.5)
Let , , , and be the vectors collecting the time-domain samples of the
waveforms , , and at equally spaced time points, i.e.:
(7.6a)
(7.6b)
(7.6c)
(7.6d)
where
Relationships between samples and Fourier series coefficients of switching waveforms
are as follows:
(7.7a)
(7.7b)
(7.7c)
153
(7.7d)
(7.8a)
(7.8b)
(7.8c)
(7.8d)
where is the Fourier operator that converts the time-domain samples to corresponding
Fourier series coefficients and is the inverse Fourier operator that converts Fourier
series coefficients to time-domain samples.
a) Time-Domain Representation of Switching Waveforms
Assume that switching waveforms , , and are represented by harmonic
components. Then, referring to the definition of and in (7.1) and (7.2)
respectively, the relationship between switching waveforms of current and those of
voltage can be defined in the time-domain sampled form as follows:
(7.9a)
(7.9b)
154
where is a matrix which preserves samples of falling within the
interval and eliminates samples of falling within the interval
. Analogously, preserves samples of falling within the interval and
eliminates samples of falling within the interval .
The correlation between the waveforms in (7.9) can be accomplished by defining
as a matrix having a unit sub-matrix in the main diagonal. Specifically:
1. contains a unit sub-matrix in the main diagonal and zeros everywhere else.
2. Position of the unity sub-matrix on the main diagonal depends on the position of
the time interval during which the sub-circuits are connected (by a switch) within
the switching period.
3. Size of the unity sub-matrix depends on the length of time interval during which
the sub-circuits are connected (by a switch). An integer p is used to designate the
size of the unit sub-matrix .
4. Relation between p and the associated time interval is defined as follows:
(7.10)
5. p is a constant number in circuits operating with known switching times.
An example of matrix is included in Appendix A.
155
b) Frequency-Domain Representation of Switching Waveforms
To derive a relationship between switching waveforms of currents and those of voltages
in the frequency-domain, first, substitute (7.7a) and (7.7b) in (7.89a) and (7.7c) and (7.7
d) in (7.9b) giving:
(7.11a)
(7.11b)
Then, multiplying both sides of equations (7.11) by matrix leads to:
(7.12a)
(7.12b)
7.3 Steady-State Analysis
Considering that both sources and in Fig.7.3 are periodic non-sinusoidal, a
periodic solution to (7.3) can be found using the harmonic balance approach. Following
the harmonic balance approach, the solution in the form of a finite Fourier series
156
(7.13a)
(7.13b)
can be found by solving the system of linear algebraic equations (e.g.[65] and [66]) as
follows:
(7.14a)
(7.14b)
(7.14c)
(7.14d)
(7.14e)
where and are vectors containing unknown Fourier
coefficients of and , , ,
, and are block matrices derived using sub-
circuit MNA matrices , and ([53]), includes converter input
voltage , and are vectors which contain Fourier
coefficients of input current and input voltage respectively, and
and are operators representing correlation
between vectors and
157
Examples showing the structure of vectors , , and are shown in Appendix B.
The procedure for computing operators and is included in Appendix C.
For practical purposes, (7.14a) and (7.14b) can be written in a consolidated form as:
(7.15a)
(7.15b)
where and is the sum of and , and
and respectively. Examples showing the structure of and are shown in
Appendix D.
Note:
Indices of the correlation operator indicate the coupling direction. Specifically, the
operator in (7.14d) defines the correlation between and in the direction from
sub-circuit 2 to sub-circuit 1, and the operator in (7.14e) defines the correlation
between and in the direction from sub-circuit 1 to sub-circuit 2.
Solving (7.14c) through (7.14e) for leads to:
(7.16)
158
or
(7.17)
The solution for can be found by substituting (7.17) in (7.14c) giving:
(7.18)
or:
(7.19)
In summary, the solution in matrix form is as follows:
(7.20)
or:
(7.21)
159
Finally, the Fourier series coefficients of the steady-state response can be computed by
solving the following set of linear equations:
(7.22a)
(7.22b)
7.4 Steady-State Determination for Networks with Multiple Switching
Converters
In previous sections, a new method for determining the steady-state of one switching
converter based on the concept of harmonic balance was introduced. In this section, an
extension of this concept to the area of networks with multiple switching converters is
presented. The principles of the proposed steady-state method are applied on networks
consisting of converters connected in parallel and in series.
7.4.1 Determination of the Steady-State for Networks with Converters Connected in
Parallel
A network of switching power converters connected in parallel is shown in Fig. 7.4.
In the equivalent network model shown in Fig.7.5, switches through
are replaced by sources generating switching waveforms , , … ,
160
and , , … respectively. Relations between the switching waveforms of
currents and voltages are imposed to the equivalent network model through correlating
sources and with voltage and currents
respectively in the adjacent sub-circuits. To simplify the notation, the
number of converters in this network was set intentionally to N-1.
Figure 7.4: Network of converters connected in parallel.
161
Figure 7.5: Model of converters connected in parallel.
Define the input vector of sub-circuit 1 as follows:
(7.23)
where includes converter input voltage only, and … are vectors
which contain Fourier coefficients of input currents .
Next, define the input vector of sub-circuits 2, 3, …N as follows:
162
(7.24)
where includes load current , contains Fourier coefficients of voltage , and
.
Referring to section 7.3, the steady-state solution to the network in Fig.7.5 can be found
by solving the following system of linear algebraic equations:
(7.25a)
(7.25b)
(7.25c)
(7.25d)
(7.25e)
where are vectors containing Fourier coefficients of nodal variables in the i-th sub-
circuit, are block matrices derived using sub-circuit MNA matrices and and
are operators representing correlation between input vectors, , and
.
Computation of operators and is included in Appendix E.
163
Expressions (7.25b) and (7.25c) represent a system of equations with
unknowns. To solve this system, the number of equations can be increased using (7.25d)
and (7.25e).
Using a procedure similar to the one used for a network with one switching converter in
Section 7.3, unknown vectors … can be obtained by solving:
(7.26)
Unknown vectors … can be obtained by substituting the solution from
(7.26) into (7.25c) and (7.25d). Then, can be computed using (7.25b). Finally, the
Fourier series coefficients of the network steady-state response can be computed by
solving (7.25a).
Note:
Relations (7.23) through (7.25) were derived using the example of buck topology
converters. However, using a different topology converter in this network would only
affect the formulation of matrices , , , and without having a formal
164
impact on operators . Therefore, the system of equations (7.25a) through (7.25e),
corresponding to the network model in Fig.7.5, is applicable in general.
7.4.2 Determination of the Steady-State for Networks with Converters Connected
in Series
A network of switching power converters connected in series is shown in Fig. 7.6. In this
network, the output of a preceding converter in the chain provides the input voltage to the
converter which is next in the chain. An equivalent network model, including coupling
between particular sub-circuits, is illustrated in Fig.7.7. In this model, switches
through are replaced with current sources , , … and
voltage sources , and .
Similar to networks with converters connected in parallel, the number of converters in the
network was set intentionally to N-1 to simplify sub-circuit notation.
Figure 7.6: Network of converters connected in series.
165
Figure 7.7: Model of converters connected in series.
Define the input vectors of sub-circuit 1 and sub-circuit N as follows:
(7.27a)
(7.27b)
where the vector includes only voltage , and vector includes only current .
Next, define the input vectors of sub-circuit 2, 3, … N-1 as follows:
(7.28)
where vector includes Fourier coefficients of the voltage source , vector
includes Fourier coefficients of the current source , and .
Similar to Section 7.4.1, a steady-state solution to the network in Fig.7.7 can be found by
solving the following set of linear algebraic equations:
166
(7.29a)
(7.29b)
(7.29c)
(7.29d)
(7.29e)
(7.29f)
where are vectors containing the unknown Fourier coefficients of nodal variables in
the i-th sub-circuit, are block matrices derived using sub-circuit MNA matrices
and are operators representing correlation between input vectors of adjacent sub-
circuits, , and .
Definition of operators is included in Appendix E.
Expressions (7.29b) through (7.29d) represent a system of equations with
unknowns. To solve this system, the number of equations can be increased using (7.29e)
and (7.29f).
Using a procedure similar to the one used for a network with one switching converter in
Section 7.3, unknown vectors … can be obtained by solving:
167
(7.30)
Vectors … can be obtained by substituting the solution from (7.30) to
(7.29f). Next, … can be computed using (7.29c). Finally, the Fourier series
coefficients of the network steady-state response can be computed by solving (7.29a).
Note:
Similar to a network with converters connected in parallel, relations (7.29) through (7.30)
were derived using the example of buck topology converters. However, using a different
topology converter in this network would only affect formulation of matrices , ,
, and without having a formal impact on operators . Therefore, the system
of equations (7.29) through (7.30), corresponding to the network model in Fig.7.7, is
applicable in general.
168
7.5 Determination of the Steady-State for Networks with Switching
Converters Operating with Unknown Switching Times
In previous sections, networks with switching converters were analyzed assuming that the
converter switching times were known. An extension of the proposed method to networks
with converters operating with unknown switching times is presented in this section. The
methodology for development of the steady-state algorithm is based on the time-interval
technique which was presented in chapters 5 and 6.
Recall that the key idea with the time-interval technique is the determination of time-
intervals using the constraint equations. Unlike in chapters 5 and 6, time intervals with
the proposed method are represented in a sampled form. Particularly, the time interval
will be equal to a multiple of the time sample
:
(7.31)
Consequently, determination of a time interval results in determination of the positive
integer .
For the purpose of illustration, assume a buck converter circuit operating in a closed
feedback loop in Fig. 7.8.
169
Figure 7.8: Model of a converter with unknown switching times.
Depending on changes in input voltage or load current, the feedback circuit (FB) enforces
changes to the converter switching times. The converter switching waveforms change
accordingly. As a consequence to the converter model, variable changes and matrix
becomes a function of , i.e. . Since
, solution
(7.22) becomes a function of as well:
(7.32a)
(7.32b)
170
a) Formulation of the constraint equation
The variable is adjusted according to the switching condition which is formulated
implicitly using a constraint equation in the sampled time-domain. In a general case of
multiple unknown switching times, constraint equations can be formulated as follows:
(7.33a)
where i stands for the i-th constraint, is the network solution, is a vector:
(7.33b)
is an integer representing time interval corresponding to the i-th constraint, and is
the number of unknown time intervals.
For example, the constraint equation associated with operation of an error amplifier
and ramp generator that determine the duration of the first time interval is:
(7.34a)
and the constraint equation defining the boundary between CCM and DCM operating
modes in hard-switching buck or boost converters that determines the duration of the
second time interval is:
171
(7.34b)
Also, similar to chapters 5 and 6, the set of constraints (5.13) can include an extended
constraint. For instance, converter average output voltage can be selected to define the
constraint equation as follows:
(7.34c)
b) Solution of the constraint equation
The system of constraints equations, e.g. (7.34b) and (7.34c) represents a non-linear
system of equations in a sampled form. A solution to this system can be found using
Newton’s iteration method. Referring to section 5.4.2 and 6.2, the procedure of Newton’s
iteration includes making an initial guess, formulation of the error function, and
computation of the Jacobian matrix.
1. Initial guess
The initial guess of can be made by guessing time intervals followed by a
conversion to their integer form as follows:
172
(7.35)
2. Error Function
Similar to (5.93), elements of the error function directly result from the definition of
constraints:
(7.36a)
(7.36b)
3. Jacobian Matrix
Numeric computation of the Jacobian matrix was presented in Chapter 5 and can be re-
used in the form:
(7.37)
where k stands for the number of Newton’s iteration cycle, is a perturbation in the j-
th element of , is vector with a perturbed j-th element, and and are
the values of the i-th element of the error function in the perturbed and un-perturbed
vectors and respectively.
173
4. Iterative Solution
A solution can be obtained using Newton’s iterations in the form:
(7.38)
Finally, after is known, the network steady-state can be computed by solving (7.22),
(7.25) or (7.29), as shown in the previous sections.
7.6 Numerical Verification
As a proof of concept, the proposed method was verified using circuits with a single
converter including closed-loop buck converters operating in CCM and DCM modes, and
a boost converter operating in CCM mode. The proposed method was then implemented
on networks with multiple converters.
Example 1: Closed-loop CCM boost converter
In this example, the circuit of the boost converter operating in CCM mode shown in Fig.
7.9 is considered. Circuit parameters were set as follows: Vin =5V, Vout =12V, inductor
inductance and winding resistance were L=80uH and RL=0.12Ohm respectively,
capacitor capacitance and effective serial resistance were C=470uF and RC=0.005Ohm
174
respectively, the circuit load was represented by resistor R=12Ohm, and switching
frequency was Fsw =200kHz. The number of harmonic components to represent a
switching waveform was set to 300.
Figure 7.9: Closed-loop CCM boost converter.
Constraint equation was formulated using (7.34c). The trajectory of associated
with the length of the first time interval of the converter operation is shown in Fig.7.10.
The steady-state was achieved within 5 iteration cycles.
175
Figure 7.10: Trajectory of in the closed-loop circuit simulation.
Steady-state waveforms of output voltage and inductor current of the converter are
shown in Fig. 7.11 and Fig 7.12 respectively. The waveforms a were computed using the
proposed method and waveforms b were computed using the algorithm presented in
Section 5.4. While the overall shapes of the waveforms match well, a small dc error of
~0.005V or 0.04% and 0.002A or 0.08% with results obtained using the proposed method
was observed. These errors were caused by a finite number of harmonics used in the
steady-state algorithm and can be considered negligible.
0 2 4 6 8 10300
310
320
330
340
350
360
370
Interation Number
p1
176
Figure 7.11: Output voltage waveform of the CCM boost converter.
Figure 7.12: Inductor current waveform in the CCM boost converter.
177
Example 2: Network of two converters operating in parallel
Performance of the proposed method was evaluated using the experimental network from
Chapter 6 that included two switching power converters. Circuit parameters were
identical to those used in Chapter 6. Converter network model partitioning is shown in
Fig. 7.13 and its model is included in Fig. 7.14.
Figure 7.13: Experimental circuit for numerical verification.
178
Figure 7.14: Model of the experimental circuit.
The number of harmonic components to represent a switching waveform was set to
200. The constraint equation was formulated using (7.34c). Fig.7.15 shows trajectories of
variables and which correspond with the first time intervals of the operation of
individual converters.
179
Figure 7.15: p1 and p2 trajectory.
Steady-state waveforms of input currents of the POL1 and POL2 converters are
captured in Fig. 7.16 and Fig.7.17. The waveforms a were computed using the proposed
method and waveforms b were computed using the algorithm presented in Section 5.4.
Differences can be considered negligible. Plots showing the output voltages of both
converters are shown in Fig. 7.18 and Fig.7.19. The dc error of the 3.3V and 1.2V
converter outputs was 0.0084V or 0.25% and 0.0117V or 0.98% respectively.
0 1 2 3 4 520
40
60
80
100
120
140
160
180
200
220
Iteration Number
p2
p
1
180
Figure 7.16: POL1 converter input current.
Figure 7.17: POL2 converter input current.
181
Figure 7.18: POL1 converter output voltage.
Figure 7.19: POL2 converter output voltage.
182
Example 3: Network of four converters operating in parallel
In this example, the proposed method was evaluated using the network consisting of four
converters connected in parallel as shown in Fig.7.20. Circuit parameters were set as
follows: Rg=0.01Ohm, C0=220uF; R0=0.04Ohm, C1 through C4: 10uF; R1 through R4:
0.01Ohm, L1 through L4: 2uH, RL1 through RL4: 0.02Ohm, C5 through C8: 47uF, R5
through R8: 0.01Ohm, I1 through I4: 2A, and Vout1 through Vout4: 1.00V, Fsw=500kHz.
The phase shift between converters was set to 900.
The number of harmonic components to represent a switching waveform was set to
200. The constraint equation was formulated using (7.34c). The error function consisted
of four elements. The trajectory of the error norm is shown in Fig.7.21. Ripples of output
voltage and inductor current waveforms are shown in Fig.7.22 and Fig.7.23 respectively,
where waveforms a, b, c, and d belong to converters POL1, POL2, POL3, and POL4
respectively. As expected, the waveforms of output voltages and inductors currents are
identical while being equally delayed over the network switching period. Also, the ripple
current through any of the front end capacitors C1 through C4, even having a smaller
capacitance, is bigger than the current through the bulk capacitor C0. The waveforms of
current ripples through capacitors C4 (line a) and C0 (line b) are shown in Fig.7.24. To
compare, Fig.7.25 shows these waveforms as they were simulated using the LTSpice
simulator.
183
Figure 7.20: Network of four converters connected in parallel.
184
Figure 7.21: Error norm trajectory.
Figure 7.22: Output voltage ripples.
0 1 2 3 4 50
0.2
0.4
0.6
0.8
1
1.2
1.4
Iteration Number
Nor
m (E
)
185
Figure 7.23: Inductor currents.
Figure 7.24: iC0 and iC4 currents.
186
Figure 7.25: iC0 and iC4 currents by commercial simulator.
7.7 Summary
In this chapter, a new method for the analysis of networks with multiple switching
converters based on the harmonic balance concept was proposed. Compared to the
steady-state methods presented in Chapter 6, the advantages of this new method are in the
elimination of challenges associated with the formulation of a large network equation.
The converter switches are replaced by current and voltage sources generating switching
waveforms identical to those which are present in a circuit with switches. Consequently,
187
the switching converter can be modeled as a system consisting of small linear sub-circuits
with periodic non-sinusoidal inputs which are correlated with voltages and currents in
adjacent sub-circuits. The steady-state algorithms for networks with unknown switching
times are based on the time-interval technique presented in chapters 5 and 6. The
constraint equation is formulated in the sampled time-domain and solved using Newton’s
iteration method with the numerical form of the Jacobian matrix.
188
Chapter 8
Conclusions and Future Work
8.1 Summary
In this thesis, several simulation methods for the analysis of networks with switching
power converters were presented. Compared to conventional Spice-like simulators, the
presented algorithms are faster, more robust in terms of convergence, and also accurate in
dc, switching waveform, and ripple analyses. Furthermore, these algorithms are suitable
for the development of efficient algorithms for solving problems of high level analysis
such as statistical analysis, design centering, and optimization.
The time-interval concept for the development of the steady-state algorithm was
explored. With this concept, the core of the algorithm is in computing time intervals
which are associated with the duration of topologies of the converter’s piecewise linear
model. Two new methods for determining switching power converter steady-state, based
on the time interval concept, were presented. The conventional set of switching
conditions is extended for design constraints to formulate the constraint equation. With
189
the first method, the constraint equation is formulated using the state-space averaging
technique. With the second method, the constraint equation is formulated using exact
analytical expressions for any circuit variable at the switching time or its average or rms
value. The major advantages of these methods are in the elimination of the converter
feedback circuit from the constraint equation resulting in single-loop algorithms, which
further leads to algorithm simplicity, increased speed and higher accuracy.
The time-interval concept is extended to the area of analysis of networks with
multiple switching converters. Both methods for formulation of the constraint equation,
which were developed for network with one switching converter, can be used to
formulate the constraint equation for a network with multiple switching converters.
Consequently, the resulting steady-state algorithms are simple, fast, and accurate,
operating without restrictions on the power converter topologies.
As the number of switching converters in the network grows, formulation of the
network equation becomes a tedious process. To address challenges associated with the
formulation of a large network equation, a new steady-state method based on harmonic
balance was presented. The converter switches are replaced by current and voltage
sources generating switching waveforms identical to those which are present in a circuit
with switches. Consequently, the switching converter can be represented by a system
consisting of small linear sub-circuits with periodic non-sinusoidal inputs which are
correlated with voltages and currents in adjacent sub-circuits. The time-interval concept
can be applied to compute the network steady-state faster and with less implementation
effort.
190
8.2 Future Work
As network inputs and system loads change, switching converters respond by adjusting
the length of their on-time intervals. Accordingly, switching waveforms inside the
converter circuit change. As a consequence, ripples of currents and voltages present in the
sub-circuits between converters, and those present at the system inputs, i.e. system
ripples, also change. The following research in the area of system ripples can be
anticipated:
1. Electrical Stress Analysis
To avoid catastrophic component failures in circuits specifically designed to deal
with system ripples (usually low-pass filters) as well as to satisfy a variety of
regulatory standards, knowing the system ripples at nominal and worst case
operating conditions is a critical piece of information for design practice.
Therefore, the extension of the algorithms presented in this thesis to areas of
stress analysis and the worst case analysis would be a definite asset.
2. Integration with thermal simulation tools
System ripples seen by capacitors result in thermal losses contributing to an
increase in capacitor temperature. On the other hand, capacitor temperature also
depends on system cooling. To achieve a specified capacitor lifetime, the
capacitor temperature should stay below a specific limit. Therefore a simulation
191
tool that computes system ripple, calculates capacitor thermal loss, and includes
thermal system simulation would have significant meaning for practical design.
3. Sensitivity Analysis
In design practice, it is important to understand how variations in component
parameters affect the response of a converter network. In the area of system
ripples, the characteristics of capacitors which are used in the converter front-end
filters or in power bus filters are critical. Depending on the total capacitance and
frequency characteristics of capacitors used, the peak-to-peak ripple, or the
system ripple frequency spectrum in the general case, change. Thus, algorithms
computing the sensitivity of system ripples to changes in capacitor characteristics
would be a useful tool for design practice.
192
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Appendix A Matrix R in Section 7.2.2
Matrix is a correlation matrix that correlates switching waveforms in adjacent sub-
circuits. For example, preserves samples of falling within the interval
and eliminates samples of falling within the interval . Analogously,
preserves samples of falling within the interval and eliminates samples of
falling within the interval .
(A.1)
(A.2)
where:
205
(A.3)
and vectors of current and voltage samples are:
, and
(A.4)
206
Appendix B Input Vectors , , and
in Section 7.3
Referring to (7.13), includes source , includes the Fourier coefficients
and vector includes the Fourier coefficients . Examples showing the
structure of these vectors are as follows:
(B.1)
207
Appendix C Derivation of Operators
and in Section 7.3
a) Derivation of
As a starting point, assume a solution to (7.14a) in the following form:
(C.1)
As a part of the solution, vector includes Fourier coefficients . Compute
as follows:
(C.2)
where matrix extracts only those entries from which are
relevant to . An example of matrix is included at the end of this appendix.
Next, coefficients are correlated with coefficients of as shown in (7.11 b),
i.e.:
(C.3)
208
Finally, compute using and as follows:
(C.4)
where uploads into relevant entries of . An example of
is included at the end of this appendix.
By a chain of operations (C.1) through (C.4), is found in the following form:
(C.5)
and the can be defined as:
(C.6a)
or
(C.6b)
Resulting relationship between and is as follows:
(C.7)
209
b) Derivation of
The procedure for derivation of is analogous to the one shown for . First, assume
a solution to (7.14b) in the following form:
(C.8)
Similar to , can be computed as follows:
(C.9)
where extracts only those entries from which are relevant to
. An example of is included at the end of this appendix.
Next, is correlated with as shown in (7.11a), i.e.:
(C.10)
Finally, compute using and as follows:
(C.11)
210
where uploads into relevant entries of . An example
of is included at the end of this appendix.
By a chain of operations (C.8) through (C.11), is found in the following form:
(C.12)
and the can be defined as:
(C.13a)
or
(C.13b)
The resulting relationship between and is as follows:
(C.14)
211
Matrix
According to (C.2):
(C.15)
where:
,
, and
(C.16)
212
Matrix
According to (C.9):
(C.17)
where:
,
,
(C.18)
213
Matrix
According to (C.4):
(C.19)
where:
,
, and
(C.20)
214
Matrix
According to (C.11):
(C.21)
where:
,
, and
(C.22)
215
Appendix D Matrices and in
Section 7.3.
(D.1)
(D.2)
216
Appendix E Definition of Operators
in Section 7.4.1
With reference to Appendix C, each operator in the network of switching converters
connected in parallel can be defined as:
(E.1)
where:
is a matrix to upload Fourier coefficients of to relevant entries of
is a matrix to extract those entries from which are relevant to Fourier coefficients
of
is a matrix to upload Fourier coefficients of to relevant entries of
is a matrix to extract those entries from which are relevant to Fourier coefficients
of
is a matrix to correlate samples of and to samples of and
respectively in the time-domain
and .
217
Appendix F Definition of Operators
in Section 7.4.2
With reference to Appendix C, each operator in the network of switching converters
conneted in series can be defined as:
(F.1)
where:
is a matrix to upload Fourier coefficients of to relevant entries of
is a matrix to extract those entries from which are relevant to Fourier coefficients
of
is a matrix to upload Fourier coefficients of to relevant entries of
is a matrix to extract those entries from which are relevant to Fourier coefficients
of
is a matrix to correlate samples of and to samples of and
respectively in time-domain
, and or .