advanced itc presentation
DESCRIPTION
Advanced ITC Presentation. A. Pogiel J. Rajski J. Tyszer. Motivation. Reliable test response compactor. volume reduction higher than scan chains / channels ratio high observability of scan cells for wide range of X-profiles design simplicity minimum control information. Outline. - PowerPoint PPT PresentationTRANSCRIPT
Advanced ITC Advanced ITC PresentationPresentation
A. PogielA. PogielJ. RajskiJ. RajskiJ. TyszerJ. Tyszer
2MotivationMotivation
volume reduction higher than scan volume reduction higher than scan chains / channels ratiochains / channels ratio
high high observability of scan cells for observability of scan cells for wide range of X-profileswide range of X-profiles
design simplicitydesign simplicity minimum control informationminimum control information
Reliable test response compactorReliable test response compactor
3OutlineOutline
EDT environmentEDT environment Compactor architectureCompactor architecture Unknown statesUnknown states Scan chain selectionScan chain selection Experimental resultsExperimental results Fault diagnosisFault diagnosis ConclusionsConclusions
4EDT architectureEDT architecture
CompactedCompactedresponsesresponses
CompressedCompressedpatternspatterns
X-controlX-control
Scan Scan Deterministic Deterministic
patternspatterns Embedded testEmbedded test Selective Selective
compactioncompaction Direct diagnosisDirect diagnosis
5Linear selectorLinear selector
1100 22 33 5544 66 77 9988 1010 1111
44
55
33
22
00
11
6Synthesis algorithmSynthesis algorithm
1.1. Generate randomly a polynomialGenerate randomly a polynomial
2.2. Verify sharing of mask bitsVerify sharing of mask bits
3.3. Determine rankDetermine rank
4.4. Repeat 1÷3 for several polynomialsRepeat 1÷3 for several polynomials
5.5. Accept poly with the highest rankAccept poly with the highest rank
6.6. Repeat 1÷5 for all outputs Repeat 1÷5 for all outputs
7Linear independenceLinear independence
0
10
20
30
40
50
60
70
80
90
100
16 18 20 22 24 26 28 30 32
DAC 2001DAC 2001
specified bitsspecified bits
32 mask bits32 mask bits
NewNew
8Encoding efficiencyEncoding efficiency
97
97,5
98
98,5
99
99,5
100
100,5
101
12 16 24 32 40 48 56mask bitsmask bits
128128
6464
192192
256256
Scan chains:Scan chains:
9Diagnostic resolutionDiagnostic resolution
DesignDesign Xs %Xs % No comp.No comp. X-PressX-Press DifferenceDifference Fail ratioFail ratio
D1D1 0.040.04 96.7496.74 95.6095.60 1.141.14 1.51451.5145
D2D2 0.440.44 96.0496.04 89.3289.32 6.726.72 1.96931.9693
D3D3 0.040.04 96.8796.87 95.2095.20 1.671.67 1.52881.5288
D4D4 1.411.41 94.7594.75 92.8892.88 1.871.87 1.43601.4360
D5D5 2.622.62 98.9298.92 96.8696.86 2.062.06 1.15831.1583
D6D6 0.440.44 96.1196.11 91.6791.67 4.444.44 1.74371.7437
Overdrive: 8Overdrive: 81000 single stuck-at faults selected 1000 single stuck-at faults selected randomlyrandomlyThe smallest mask register The smallest mask register
10ConclusionsConclusions
Compression higher than scan Compression higher than scan chains / channels ratiochains / channels ratio
Programmable scan selectorProgrammable scan selector High observability of scan errorsHigh observability of scan errors Immune to high X-fill ratesImmune to high X-fill rates Proven on industrial designsProven on industrial designs
Dariusz Czysz, Janusz Rajski, Jerzy Dariusz Czysz, Janusz Rajski, Jerzy TyszerTyszer
12purposepurpose
Low power scheme compatible Low power scheme compatible with test compression with test compression
reduced switching during all scan reduced switching during all scan operationsoperations
preserved test quality preserved test quality
accelerated scan shiftingaccelerated scan shifting
13outlineoutline
EDT environmentEDT environment Low power test architectureLow power test architecture Scan shift-in operations Scan shift-in operations Power aware decompressorPower aware decompressor Capture and scan shift-outCapture and scan shift-out Experimental resultsExperimental results ConclusionsConclusions
14motivationmotivation
0
100
200
300
400
500
600
700
800
900
1 11 21 31 41 51 61 71 81 91
100 scan chains100 scan chains
Scan chains observing faultsScan chains observing faults
Test patternsTest patterns 0.9M gates0.9M gates45K scan cells45K scan cells
15control data encodingcontrol data encoding
Constants provided on a per pattern basisConstants provided on a per pattern basis Asserting all variables turn off low power testAsserting all variables turn off low power test
00
11
c1 + c3 + c7 = 0
c2 + c4 + c7 = 1c3 + c5 + c6 = 0
cn cn-1 … c2 c1 c0
16clock gater control dataclock gater control data
DesignDesignSpecified Specified bits per bits per
cubecube
Gated FFs Gated FFs by one by one cubecube
FFs per FFs per specified specified
bitbit
FFs with gated FFs with gated clocks (%)clocks (%)
D1D1 7.67.6 942942 124124 6161
D2D2 7.67.6 501501 6565 7070
D3D3 15.615.6 44334433 284284 9191
D4D4 5.15.1 553553 107107 5252
AverageAverage 9.09.0 16071607 145145 6868
Specified bits refer to bits provided by scan to shut off flip-flopsSpecified bits refer to bits provided by scan to shut off flip-flops
17experimental results – filling chainsexperimental results – filling chains
0
10
20
30
40
50
60
D1D1 D2D2 D3D3 D4D4
WTM [%]WTM [%]
LoadLoadUnloadUnloadCaptureCapture
ConstantConstantShadow registerShadow register
CombinedCombined
WSA [%]WSA [%]
18filling chains & clock gatingfilling chains & clock gating
0
10
20
30
40
50
60
70
80
90
100
D1D1 D2D2 D3D3 D4D4
Reduction [%]Reduction [%]
LoadLoadUnloadUnloadCaptureCaptureCapture – only clock gatersCapture – only clock gaters
19conclusionsconclusions
EDT can deliver low power testsEDT can deliver low power tests No impact on qualityNo impact on quality Significant reduction of test power in Significant reduction of test power in
shiftshift Flexible trade-offsFlexible trade-offs
– power efficiencypower efficiency– compressioncompression– test application timetest application time