advanced digital design methodology – ece 4200 2016/ece4242... · 2018-04-18 · ece 4242-3....

Advanced Digital Design Methodology – ECE 4242/5242

1 Chap 1-2 Copyright 2012 G. Tumbush v1.5

Chap 1-2 Copyright 2012 G. Tumbush v1.5 2

My Background

B.S.E.E. from Colorado State University M.S.E.E. from Colorado State University M.B.A. from UCCS Ford Microelectronics, Inc./Visteon 1985 - 2000 Intel Corp. 2000-2006 Marvell 2006-2009 Hittite Microwave 2009-2011 Covidien 2011 - 2013 LSI/Avago/Broadcom 2013 - present UCCS Fall Semester 2013 – ECE4280/5280 UCCS Spring Semester 2014 – ECE4211/5211 UCCS Fall Semester 2014 – ECE4280/2411

Chap 1-2 Copyright 2012 G. Tumbush v1.5

Course Description

3

ECE 4242-3. Advanced Digital Design Methodology. Focuses on modern digital design practice using computer-based design tools and then considers key steps in a modern design flow, with particular attention to the use of behavioral models in hardware description languages as a stepping stone to combinational and sequential logic synthesis. The Verilog language will be presented, along with ancillary topics of functional verification, testbench generation, timing analysis, fault simulation, and design for testability. Design examples will include microcontrollers, RISC-CPUs, pipelined processors, digital filters, finite state machines for datapath control, UARTs, and typical architectures of synchronous computational units. Prereq: ECE 2411.

Chap 1-2 Copyright 2012 G. Tumbush v1.5

Assumptions

4

• Prerequisite is Logic Circuits II - 2411 • Combinatorial logic • Sequential logic • State machines

Chap 1: Intro to Digital Design Methodology

• Why move from schematic capture to HDL’s?

– Productivity

– Maintainability

– Entry into downstream tools

• Simulation

• Synthesis

• Logic equivalency checking

ABC

out

wire andTop, andBot, out; assign andTop = !(!A & !B & !C); assign andBot = !(A & B & C); assign out = !(andTop & andBot);


Digital Design Flow Design Specification (1)

Design Partition (2)

Design Entry: Verilog Model (3)

Block Level Verification (4)

Design Integration and

System Verification (5)

Pre-Synthesis Sign-Off (6)

Synthesis and

Implementation (7)

Post-Synthesis Design Validation (8)

Post-Synthesis Timing Verification (9)

Design Sign-Off (14)

Test Generation and Fault Simulation (10)

Cell Placement, scan stitching, clock tree

insertion, cell routing (11)

Verify Physical/Electrical Design Rules (12)

Extract Layout Parasitics (13)


Chap 2: Review of Combinational Logic Design

• Combinational logic forms Boolean functions of the input variables.

• A binary variable can have a value of 0 or 1.

• HDL’s expand on the logic value system to support X, Z, drive strengths, etc.

• The output(s) are solely a function of the inputs and are available immediately*.


Output is a function of inputs only (no feedback)

Combinatorial

Logic

a

bc

d

y1

y2

y3

y1 = f1(a,b,c,d) y2 = f2(a,b,c,d) y3 = f3(a,b,c,d)

M. Ciletti, Advanced Digital Design with Verilog HDL, Prentice Hall, 2002 8 Chap 1-2 Copyright 2012 G. Tumbush v1.5

Logic Gates


Logic Operators

+ denotes logical “OR” or union ex: a+b

. denotes logical “AND” or intersection ex: a b or ab

- denotes logical negation ex: a or a’

’ or

_

^ denotes logical “XOR” ex: a^b or a b

.

+or +


Logic Gates - CMOS


Logic Gate Exercise

Design a 3-input CMOS NOR gate.


Basic Definitions • Natural Numbers:

– None negative integers • Debate whether to include 0

• Set: – A collection of objects, usually having a common property

• If S is a set, and x and y are certain elements then: x ∈ S means x is a element of the set S y ∉ S means y is not an element of set S

• A set with denumerable number of elements is specified by braces: A = {1, 2, 3, 4}

• Element – Any of the distinct objects that make up a set

• Postulate/Axiom – A premise or starting point of reasoning

• Theorem – A statement that has been proven on the basis of previously established statements, such as other

theorems—and generally accepted statements, such as axioms.

• A binary operator defined on a set S of elements is a rule that assigns, to each pair of S elements, a unique element from S

– Consider: a * b = c

• * is a binary operator if it specifies a rule for finding c from the pair (a, b) and also if a, b, c ∈ S • is not a binary operator if a, b ∈ S and if c ∉ S


Boolean Algebra

M. Ciletti, Advanced Digital Design with Verilog HDL, Prentice Hall, 2002

Law Sum of Products (SOP) form

Product of Sum (POS) form

Combinations with 0 and 1

a+0=a a+1 = 1

a·1 = a a·0 = 0

Commutative a+b=b+a ab=ba

Associative (a+b)+c=a+(b+c)=a+b+c (ab)c=a(bc)=abc

Distributive a(b+c)=ab+ac a+bc=(a+b)(a+c)

Idempote a+a=a a·a = a

Involution (a’)’ = a

Complement a+a’ = a a·a’ = 0


Boolean Algebra

• Associative Law: – A binary operator * on a set S is said to be associative if:

(x * y) * z = x * (y * z) for all x, y, z, ∈ S Satisfied by: (x · y) · z = x · (y · z) (x + y) + z = x + (y + z)

• Commutative Law: – A binary operator * on a set S is said to be commutative

if: x * y = y * x for all x, y, ∈ S Satisfies by: x · y = y · x x + y = x + y


Boolean Algebra • Identity Element:

– A set S is said to have an identity element w.r.t. a binary operation * on S if there exists an element e ∈ S with the property that:

e * x = x * e = x for all x ∈ S additive identity element: denoted by 0 x + 0 = 0 + x = x for any x ∈ S multiplicative identity element: denoted by 1 x · 1 = 1 · x = 1 for any x ∈ S

– Note: The set of natural number N = {1, 2, 3, …} has no identity element since 0 does not belong to the set

• Inverse – A set S is having the identity element e w.r.t. a binary operator * is said to have

an inverse whenever, for every x ∈ S, there exists an element y ∈ S such that x * y = e Additive Inverse: For every a in S, there exists an element −a in S, such that a + (−a) = 0. Multiplication Inverse: For any a in S other than 0, there exists an element a−1 in S, such that a · a−1 = 1.


Boolean Algebra

• Distributive Law:

– If * and · are two binary operators on a set S, * is said to be distributive over · whenever

x * (y · z) = (x * y) · (x *z)

– Distributivity of multiplication over addition:

For all a, b and c in S, the following equality holds:

a · (b + c) = (a · b) + (a · c).


Axiomatic Definition of Boolean Algebra

• In this work, Shannon proved that Boolean algebra and binary arithmetic could be

used to simplify the arrangement of the electromechanical relays that were used then in telephone call routing switches. He next expanded this concept, and he also proved that it would be possible to use arrangements of relays to solve problems in Boolean algebra.


• In 1904, E.V. Huntington formulated the postulates that formally define Boolean algebra.

• In 1937, Claude Shannon founded both digital computer and digital circuit design theory when, as a 21-year-old master's degree student at the Massachusetts Institute of Technology (MIT), he wrote his thesis demonstrating that electrical applications of Boolean algebra could construct and resolve any logical, numerical relationship.

• His thesis was published in the 1938 issue of the Transactions of the American Institute of Electrical Engineers , and proved that a two-valued Boolean algebra (whose members are most commonly denoted 0 and 1, or false and true) can describe the operation of two-valued electrical switching circuits.

Claude Shannon

Axiomatic Definition of Boolean Algebra • Boolean algebra is an algebraic structure defined by a set of elements, B, together

with two binary operators + and ·, provided that the following postulates are satisfied:

1. (a) The structure is closed with respect to + i.e. for all a, b in S, both a + b are in S

(b) The structure is closed with respect to · i.e. for all a, b in S, both a · b are in S 2. (a) The element 0 is an identity element with respect to +

x + 0 = 0 + x = x

(b) The element 1 is an identity element with respect to · x · 1 = 1 · x = x

3. (a) The structure is commutative with respect to + x + y = y + x

(b) The structure is commutative with respect to · x · y = y · x 4. (a) The operator · is distributive over +

x · (y + z) = (x · y) + (x · z) (b) The operator + is distributive over · x + (y · z) = (x + y) · (x + z) 5. For every element x ∈ B, there exists an element x’ ∈ B called the complement of x such

that (a) x + x’ = 1 (b) x · x’ = 0 6. There exist at least two elements x, y ∈ B such that x ≠ y


Axiomatic Definition of Boolean Algebra • Compare Boolean Algebra with arithmetic and ordinary

algebra – The Distributive Law of + over · is valid for Boolean algebra but

not for ordinary algebra x + (y · z) = (x + y) · (x + z)

– Boolean algebra does not have additive or multiplicative inverses; therefore there are no subtraction or division operations • Subtraction Inverse: a + (−a) = 0 • Multiplicative Inverse: a · a−1 = 1

– Postulate 5 defines the complement operator which is not available in ordinary algebra

x + x’ = 1 x · x’ = 0 – Ordinary algebra operates on real numbers, which constitutes

an infinite set of elements. Boolean algebra deals with a set B comprised of only two elements, 0 and 1.


Canonical and Standard Forms

• Canonical Form: Simplest or Standard form of an expression

• minterm or standard product – A product term in which each of the variables appears

once (complemented or uncomplemented) – AND operation

• maxterm or standard sum – A sum term in which each of the variables appears once

(complemented or uncomplemented) – OR operation

• Boolean functions expressed as a sum of minterms or a product of maxterms are said to be in canonical form


Sum of Products/Products of Sums

• A sum of products (SOP) is a sum of product terms

• A product of sums (POS) is a product of sum terms

bcabcba

bcbacba )()(


a b a b

Demorgan’s Laws

For 2 variables, or

........)( cbacba

baba )(

a b

ba ba

a a

a

b b

bb

a b

ba

baba


a b a+b (a+b)’ a’ b’ a’b’

0 0 0 1 1 1 1

0 1 1 0 1 0 0

1 0 1 0 0 1 0

1 1 1 0 0 0 0

a b

Demorgan’s Laws

For 2 variables, or

........)( cbacba

baba )(

a

a

b

ba ba

a

b

b

ba

baba


a b ab (ab)’ a’ b’ a’+b’

0 0 0 1 1 1 1

0 1 0 1 1 0 1

1 0 0 1 0 1 1

1 1 1 0 0 0 0

Complement of a Function – The complement of function F is F’ and is obtained by the

interchange of 0’s with 1’s and 1’s with 0’s in the value of F – The complement of a function may be derived

algebraically using DeMorgan’s theorem (A + B)’ = A’B’ (DeMorgan’s)

– Extended to three variables (A + B + C)’ = (A + x)’ where x = B + C = A’x’ (DeMorgan’s) = A’(B + C)’ substitute B + C = x = A’(B’C’) (DeMorgan’s) = A’B’C’ (associative)

– In General (A + B + C + D + … + F)’ = A’B’C’D’ … F’ (ABCD … F)’ = A’ + B’ + C’ +D’ + … + F’


Converting between SOP and POS example Convert the following SOP expression to a POS expression DeMorgan’s: (x + y)’ = x’y’ (xy)’ = x’ + y’


f’ = (ab’c + abc’ + b)’

f’ = (ab’c)’(abc’)’(b)’

f’ = (a’+b+c’)(a’+b’+c)(b’)

f = ((a’+b+c’)(a’+b’+c)(b’))’

b abc’ cab’

Converting between SOP and POS exercise

Convert the following POS expression to a SOP expression DeMorgan’s: (x + y)’ = x’y’ (xy)’ = x’ + y’


acbaba )()(

f = (a+b)(a+b’+c’)(a’)

f’ = ((a+b)(a+b’+c’)(a’))’

f’ = (a+b)’ + (a+b’+c’)’ + (a’)’

f = ((a+b)’ + (a+b’+c’)’ + (a’)’)’

f = ((a’b’) + (a’bc) + a)’

Theorems of Boolean Algebraic Minimization

M. Ciletti, Advanced Digital Design with Verilog HDL, Prentice Hall, 2002

Theorem SOP Form POS Form

Logical Adjacency

Absorption

Multiplication and Factoring

Concensus


abaab ababa ))((

babaa

babba

aaba

ababa

abbba

abaa

)(

)(

)(

baaccaba ))(( ))(( bacacaab

caabcabcab ))((

))()((

caba

cacbba

a ab b

Logical Adjacency


abaab

ab

Representation of Combinational Logic 1. Truth table 2. Boolean equation 3. Circuit schematic


Inputs Outputs

a b c_out sum

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

baoutc

bababasum

_

a

bsum

c_out

Simplification of Boolean Expressions • Boolean manipulation using theorems

• Karnaugh maps and extended karnaugh maps


Boolean manipulation example

cbacbacbacabbcaabccbaf ),,(

Using the logical adjacency theorem

xyxxy

Can be reduced to:

cbbaabbccbaf ),,(

The equation: baab

bc cb


Reduction using Boolean manipulation Exercise

Minimize the following equation


bababaf )01(),(

f = (a + b’)(a’b’)’ where b + 0 = b, a·1 = a

f = (a + b’)(a + b) where (ab)’ = a’ + b’, (a’)’ = a

f = (a + b’)a + (a + b’)b where x(y + z) = xy + xz

f = aa + ab’ + ab + bb’

f = a + ab’ + ab where aa = a, bb’ = 0

f = a(1 + b + b’)

f = a(1 + 1) where b + b’ = 1

f = a where a·1 = a

Karnaugh Maps

• Reveal logical adjacencies to reduce number of terms

Ex:

00

01

10

11

00 01 1011abcd

1 1

1

1

1 1

X

X0

0

0 0

0

X 0

0


Karnaugh Maps – SOP reduction

00

01

10

11

00 01 1011abcd

1 1

1

1

1 1

X

X0

0

0 0

0

X 0

0

bddbdcbaf ),,,(35 Chap 1-2 Copyright 2012 G. Tumbush v1.5

{ a

}

b }

c

}

d

Karnaugh Maps – POS reduction

dbdbdcbaf ),,,(

Find minimal cover of 0’s and apply DeMorgan’s

00

01

10

11

00 01 1011abcd

1 1

1

1

1 1

X

X0

0

0 0

0

X 0

0


{ a

b }

}

c

}

d

Karnaugh Maps – POS reduction(cont.)

dbdbdcbaf ),,,(

dbdbdcbaf ),,,(

dbdbdcbaf ),,,(

)()(),,,( dbdbdcbaf


Does ? )()( dbdbbddb

0

1

0 1bd

1 0

0 1

bddbf

0

1

0 1bd

1 1

0 1

dbf 1

0

1

0 1bd

1 0

1 1

dbf 2

0

1

0 1d

1 0

0 1

))(( dbdbf

b

SOP form

POS form


Karnaugh Maps for Equation Reduction example

Reduce the equation abccbacbacbaf ),,(

0

1

00 01 1011abc

1 1

10

0 0

00

abccacbaf ),,(39 Chap 1-2 Copyright 2012 G. Tumbush v1.5

}

b

} c

Karnaugh Maps Exercise

Verify your answer to the previous exercise using a Karnaugh map


bababaf )01(),(

a b a’ b’ (a + b’) (a’b’)’ f

0 0 1 1 1 0 0

0 1 1 0 0 1 0

1 0 0 1 1 1 1

1 1 0 0 1 1 1

a b 0 1

0 0 0

1 1 1

bc

a 00 01 11 10

0

1

1 0

0 0 1 0

0 0

bc

a 00 01 11 10

0

1

1 0

0 1 1 0

0 0

ac

Uses for K-map/Boolean Reduction


if (a && b && c) out = 1 else if (!a && !b && !c) out = 1 else out = 0;

if (a && b && c) out = 1 else if (!a && !b && !c) out = 1 else if (a && !b && c) out = 1 else out = 0;

customer wanted

• ECO’s • Understanding why the synthesis tool did what it did. You implemented:

abc

out

Synthesized to:

abc

out

2.6.1 Building blocks: NAND-NOR Structures


• Nand’s, nor’s , and inverters are the basic circuit used to create combinatorial logic in CMOS. • DeMorgan’s theorem provides equivalent structures for NAND and NOR gates

y

bay

a

b

a

b

a

b

a

b

y y

y

bay

equivalent

bay bay

equivalent

Example 2.35: Implementing SOP with NAND gates


Implement equation

CDDBAEFGY

E

F

A

BD

C

D

Y

G

E

F

A

BD

C

D

Y

GE

F

A

BD

C

D

Y

G

Example 2.36: Implementing POS with NOR gates


Implement equation

))()(( GAFEACBDY

B

C

A

F

E

A

G

Y

D

B

C

A

F

E

A

G

Y

D

B

C

A

F

E

A

G

Y

D

POS Exercise Determine the POS equation and implement the following Karnaugh map using a minimal POS circuit with NOR gates only.


bc

a 00 01 11 10

0

1

0 1

1 1 0 1

0 0

2.5: Glitches and Hazards


•The output of combinatorial logic may glitch depending on: 1. Circuit structure 2. Input pattern

• A circuit that can glitch has a hazard

starts at 0

momentary

transition to 1

settles at 0

static-0 hazard

starts at 1

momentary

transition to 0

settles at 1

static-1 hazard

Static Hazards – reconvergent fanout


Static hazards are caused by real propogation delays on reconvergent fanout paths

A

C

B

F

1

A

B

C

F0

1

0101

10

10

101

F0

F1

F1

F

Static Hazard Explanation


A static-1 hazard is caused by the circuit moving from a 1-cover to another adjacent 1-cover in a Karnaugh map

A

C

B

0

1

00 01 1011ABC

0 1 1

1

1

0 0 0

AC BC

CBACf

Static Hazard Solution


A static hazard is eliminated by introducing a redundant cover to connect the 2 adjacent covers.

ABCBACf 0

1

00 01 1011ABC

0 1 1

1

1

0 0 0

AC AB

BCA

C

B

Static Hazards Concerns


•Should you be concerned with static hazards? • If the glitch doesn’t settle by the next active clock edge • If the signal is an input to asynchronous logic

•clocks •interrupts •clock domain crossings • resets

• Hazard removal requires more hardware. • Synthesis tools will not create hazard free circuits • Synthesis tools will optimize away hazard removal logic

Static Hazards – nonreconvergent fanout


c

de

z

a

b

a

x

y

b

x

c

d

e

y

z

1

2

Hazard Exercise (do as HW) Evaluate the previous exercise for hazards and if a hazard is present: 1. Is the hazard a 0-hazard or 1-hazard? 2. What is the input pattern that will reveal the hazard? 3. Eliminate the hazard. Draw the new circuit and provide the

new equation.


HW from Book

• 2.4

• 2.6

• 2.7

• 2.8a-c

• 2.9a-c

• 2.10c


advanced digital design methodology – ece 4200 2016/ece4242... · 2018-04-18 · ece 4242-3....

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