Advanced Digital CircuitsECET 146

Week 1

Professor Iskandar Hack

ET 205B, 481-5733

hack@ipfw.edu

Week’s Goals

Course Overview Overview of Embedded Digital Systems Overview of Digital Technologies Overview of Design Entry Techniques

Goals of Course

Understanding of basic concepts of programmable logic

Understand various types of programmable logic devices such as Field Programmable Gate Arrays, Masked Gate Arrays, Standard Cell, and Full Custom Chips

To be able to use an industry standard digital design package such as Altera’s Max Plus or Xilinx’s ISE Foundation

Goals of Course II

Learn to use different design entry techniques, including schematic, waveform, state machine diagrams, and text hardware design languages

Work in teams to solve complex design problems

Present written and oral reports representing solutions to design problems

Course Structure

Course is project based – 50% of your grade will be based upon successful completion of assigned projects in the laboratory.

Quizzes – there will be approximately ten quizzes that will be completed These will be open book, notes and most importantly you’ll want access to the Altera Quatrus software when you take them. The quizzes will be worth 10% of your final grade. (One point per quiz)

Course Structure II

Major projects – there will be a Midterm and Final Project that will each count 20% of your course grade.

Lab Teams – Each Lab team will consist of two members. You are free to choose your own lab partner. However, each lab must be written by one member each time and alternate between lab members. You will need to identify which lab member is writing the report. The same is true with the midterm and final projects, however writes the midterm does not write the final report. You do not have to have a lab partner, if you desire you may work alone.

Grades

Grading is simple in this course – You finish all of the assignments (ON TIME of course) and you receive an A.

Of course if you’re late, your lab reports don’t meet the standard format, or your projects don’t work then the final grade is adjusted.

Most students that take this course will receive an A, those that don’t are ones that don’t finish the projects on time or they don’t work.

The primary reason that students do poorly is they wait until the project is due before they start working on it.

Course Requirements

Digital Electronics with VHDL by William Kleitz (same book as ECET 111)

Altera Quatrus II II Design software (can be downloaded from www.altera.com or from course website)

Additional Comments

In order to transport your design files from home to the lab and to save your design files while working in the lab you will need to have either a USB-Flash drive. If you do all of your work on either a laptop that you carry back and forth or on the lab computers then you don’t need the USB-Flash drive.

NOTE – there has been some minor problems with Flash drives losing data, be sure to back up regularly.

Definition of an Embedded System

An embedded digital system is any electronic system that uses digital logic as part of the control of the system.

There are two fundamental types of embedded systems Microprocessor or Microcontroller based

(covered in ECET 205/305) Custom Digital Logic (covered in this course)

Types of Custom Digital Logic Devices Discrete Logic as covered in ECET 111 Programmable Logic

Simple Programmable Logic Devices Complex Programmable Logic Devices

(CPLD’s) Field Programmable Gate Arrays

Masked Gate Arrays Standard Cell Custom Logic Integrated

Circuits Full Custom Logic Integrated Circuits

Simple Programmable Logic Devices

These devices are also known as PAL (Programmable Array Logic) GAL (Generic Array Logic) PLA (Programmable Logic Array) PLD (Programmable Logic Device)

SPLDs are the smallest and consequently the least-expensive form of programmable logic. An SPLD is typically comprised of four to 22 macro cells and can typically replace a few 7400-series TTL devices. Each of the macro cells is typically fully connected to the others in the device. Most SPLDs use either fuses or non-volatile memory cells such as EPROM, EEPROM, or FLASH to define the functionality.

CPLD - Complex Programmable Logic Devices Also known as:

EPLD (Erasable Programmable Logic Device) PEEL EEPLD (Electrically-Erasable Programmable Logic Device) MAX (Multiple Array matriX from Altera)

CPLDs are similar to SPLDs except that they are significantly higher capacity. A typical CPLD is the equivalent of two to 64 SPLDs. A CPLD typically contains from tens to a several hundred macro cells. A group of eight to 16 macro cells is typically grouped together into a larger function block. The macrocells within a function block are usually fully connected. If a device contains multiple function blocks, then the function blocks are further interconnected.

CPLD - Complex Programmable Logic Devices II In concept, CPLD’s consist of multiple PAL-

like logic blocks interconnected together via a programmable switch matrix. Typically, each logic block contains 4 to 16 macrocells, depending on the architecture

Layout of Standard CPLD

Layout of Altera Max 7000 Family

An Altera Max 7000 Macrocell

Field Programmable Gate Arrays

Similar to a CPLD, except the macrocells are smaller with respect to the overall device.

There are far more macrocells and more interconnect inside a FPGA

FPGA’s can have several hundred thousand equivalent gates, and the number is increasing rapidly, and could be in the millions before long.

Layout of a FPGA

I/O Blocks

Masked Gate Array

These are custom devices that must be ordered from an IC manufacturer

They consist of a large number of either NAND or NOR gates that are not connected

They are often referred to as a ‘sea of gates’ The top layer mask is the interconnect that

determines the final logic Remember from Basic Digital that ANY digital

circuit (including FF’s ) can be designed using just NAND or NOR gates

Layout of a Mask Gate Array

Gate Array with Channels for interconnect

Gate Array without ChannelsI/O Blocks

Standard Cell Device

Made up of standard Digital Logic cells such as counters, adders, multipliers memory components and even microcontrollers

All mask layers are custom made Because of the need for all masks to be

custom there is a long lead time for manufacturing and high cost for the fabrication of the masks

Sample Layout of Standard Cell

Standard Celladder

Standard CellShift register

Input/Output

Gate Array With routing Chan.

Full Custom Device

These are digital systems in which all parts of the design is done by hand for maximum performance or use of space

The cost of designing such devices is extremely expensive

Rarely used except in very high production units (several million units) or which absolute performance is necessary (military or space applications)

Example of a Full Custom Device

80486 Chip from Intel

Design Cost vs. Per Unit Cost

Design Cost is the ‘one time’ cost of designing the device, usually referred to as the NRE or ‘Non-Recurring Engineering’ cost

The per unit cost is the cost of each unit AFTER the NRE has been satisfied

The Total Unit Cost (TUC) is equal to the (NRE)/(# of Units) + Per Unit cost

It is important to compare TUC using available technologies to decide the appropriate technology

There may be other reasons to use a particular technology such as security, power or size restrictions

Example of Calculating Total Unit Cost The NRE is $125,000 for this particular

design The Per Unit Cost is $1.35 The Expected Number of units to be

produced is 325,000 The Total Per Unit cost is (125000/325000) +

1.35 = 1.73 per device

Comparison of Different Technologies

Technology Per Unit Cost (per gate)

NRE Lead Time

SPLD Very High Low None

CPLD High Low None

FPGA Moderate Low None

Gate Array Low Moderate Moderate

Cell Based Low High Long

Full Custom Very Low Very High Very Long

Design Entry Techniques

Schematic – Designer draws the equivalent design using gates and other logic circuits (can include IC’s such as JK FF or 74xxx parts)

Waveform – Design draws the desired input and output waveforms for the device

State Machine Diagram – Designer enters the design using a Finite State Machine Bubble Diagram

Text Design Files – Design specifies the design using a design language such as Altera Hardware Design Language (AHDL)

Example of Schematic Design

Example of Waveform Design

Example of State Machine Bubble Graph

Example of AHDL Design File

SUBDESIGN priority( low, middle, high : INPUT; highest_level[1..0] : OUTPUT; --group,vector,bus)BEGIN IF high THEN --IF-THEN-ELSE statement highest_level[] = 3; --high -> decimal 3 = binary 11 ELSIF middle THEN highest_level[] = 2; --middle -> 10 ELSIF low THEN highest_level[] = 1; --low -> 01 ELSE highest_level[] = 0; --no input was true -> 00 END IF;END;

Summary of Week 1 Overview of the course Definition of Embedded Systems

Microprocessor/Microcontroller Custom Digital Logic

Technologies used in Custom Digital Logic Discrete Components Small Scale Programmable Logic Large Scale Programmable Logic

CPLD’s FPGA’s

Masked Gate Arrays Standard Cell Full Custom

Design Entry Methods Schematic Waveform State Machine Bubble Graphs Text Design Files