adsp-bf506f ez-kit lite evaluation system manual

a

ADSP-BF506F EZ-KIT Lite®

Evaluation System Manual

Revision 1.1, July 2012

Part Number82-000226-01

Analog Devices, Inc.One Technology WayNorwood, Mass. 02062-9106

Copyright Information© 2012 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc.

Printed in the USA.

DisclaimerAnalog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli-cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark NoticeThe Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-Extender, EZ-KIT Lite, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

Regulatory Compliance The ADSP-BF506F EZ-KIT Lite is designed to be used solely in a labora-tory environment. The board is not intended for use as a consumer end product or as a portion of a consumer end product. The board is an open system design which does not include a shielded enclosure and therefore may cause interference to other electrical devices in close proximity. This board should not be used in or near any medical equipment or RF devices.

The ADSP-BF506F EZ-KIT Lite has been certified to comply with the essential requirements of the European EMC directive 2004/108/EC and therefore carries the “CE” mark.

The ADSP-BF506F EZ-KIT Lite has been appended to Analog Devices, Inc. EMC Technical File (EMC TF) referenced DSPTOOLS1, issue 2 dated June 4, 2008 and was declared CE compliant by an appointed Noti-fied Body (No.0673) as listed below.

Notified Body Statement of Compliance: Z600ANA2.038 dated June 21 2010.

Issued by: Technology International (Europe) Limited 56 Shrivenham Hundred Business Park Shrivenham, Swindon, SN6 8TY, UK

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent dam-age may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package.

ADSP-BF506F EZ-KIT Lite Evaluation System Manual v

CONTENTS

PREFACE

Product Overview ........................................................................... xi

Purpose of This Manual ................................................................ xiii

Intended Audience ........................................................................ xiii

Manual Contents ........................................................................... xiv

What’s New in This Manual ........................................................... xiv

Technical Support ........................................................................... xv

Supported Processors ...................................................................... xvi

Product Information ...................................................................... xvi

Analog Devices Web Site .......................................................... xvi

EngineerZone .......................................................................... xvii

Related Documents ...................................................................... xviii

Notation Conventions .................................................................. xviii

Contents

vi ADSP-BF506F EZ-KIT Lite Evaluation System Manual

USING ADSP-BF506F EZ-KIT LITE

Package Contents ......................................................................... 1-2

Default Configuration .................................................................. 1-3

CCES Install and Session Startup .................................................. 1-3

Session Startup ........................................................................ 1-6

VisualDSP++ Install and Session Startup ....................................... 1-8

Session Startup ........................................................................ 1-9

CCES Evaluation License ........................................................... 1-10

VisualDSP++ Evaluation License ................................................. 1-11

Memory Map ............................................................................. 1-12

Internal Flash Memory Interface ................................................. 1-13

SPI Flash Memory Interface ........................................................ 1-13

Power-On-Self Test ..................................................................... 1-14

LEDs and Push Buttons .............................................................. 1-14

JTAG Interface ........................................................................... 1-15

Expansion Interface II ................................................................. 1-15

VDDINT Programmable Regulator ............................................ 1-16

Power Measurements .................................................................. 1-17

Example Programs ...................................................................... 1-18

Board Design Database ............................................................... 1-18

ADSP-BF506F EZ-KIT Lite Evaluation System Manual vii

Contents

ADSP-BF506F EZ-KIT LITE HARDWARE REFERENCE

System Architecture ...................................................................... 2-2

Programmable Flags ...................................................................... 2-3

Push Buttons and Switches ............................................................ 2-7

UART Setup Switch (SW1) ..................................................... 2-8

Boot Mode Select Switch (SW2) .............................................. 2-8

Push Button Enable Switch (SW3) ........................................... 2-9

ADC Enable Switch (SW4) ...................................................... 2-9

CAN Enable Switch (SW5) ...................................................... 2-9

Reset Push Button (SW6) ........................................................ 2-9

Programmable Flag Push Buttons (SW7–8) .............................. 2-9

ADC Loopback Switches (SW9–10) ....................................... 2-10

Jumpers ...................................................................................... 2-11

SPI FLASH CS Enable Jumper (JP1) ..................................... 2-11

Voltage Reference Select Jumper (JP2) ................................... 2-12

VDDEXT Power Jumper (JP3) .............................................. 2-12

VDDINT Power Jumper (JP4) .............................................. 2-12

VDDFLASH Power Jumper (JP5) .......................................... 2-12

ADC Voltage Reference (JP6) ................................................ 2-13

LEDs .......................................................................................... 2-14

Reset LED (LED1) ................................................................ 2-15

GPIO LEDs (LED2–4) ......................................................... 2-15

Power LED (LED5) ............................................................... 2-15

Contents

viii ADSP-BF506F EZ-KIT Lite Evaluation System Manual

Connectors ................................................................................. 2-16

RS-232 Connector (J1) ......................................................... 2-17

CAN Connector (J2) ............................................................ 2-17

SD Connector (J3) ................................................................ 2-17

JTAG Connector (P1) ........................................................... 2-17

Expansion Interface II Connectors (P2 and P4) ..................... 2-18

Expansion Interface II Connector (P3) .................................. 2-18

DMAX Land Grid Array Connectors (P5–6) ......................... 2-19

ADC Input Connector (P7) .................................................. 2-19

Power Connector (P9) ........................................................... 2-19

ADSP-BF506F EZ-KIT LITE BILL OF MATERIALS

ADSP-BF506F EZ-KIT LITE SCHEMATIC

INDEX

ADSP-BF506F EZ-KIT Lite Evaluation System Manual ix

PREFACE

Thank you for purchasing the ADSP-BF506F EZ-KIT Lite®, Analog Devices, Inc. evaluation system for the ADSP-BF504/BF506F Blackfin® processors.

Blackfin processors embody a type of embedded processor designed specif-ically to meet the computational demands and power constraints of today’s embedded audio, video, and communications applications. They deliver breakthrough signal-processing performance and power efficiency within a reduced instruction set computing (RISC) programming model.

Blackfin processors support a media instruction set computing (MISC) architecture. This architecture is the natural merging of RISC, media functions, and digital signal processing (DSP) characteristics. Blackfin processors deliver signal-processing performance in a microprocessor-like environment.

Based on the Micro Signal Architecture (MSA), Blackfin processors com-bine a 32-bit RISC instruction set, dual 16-bit multiply accumulate (MAC) DSP functionality, and eight-bit video processing performance that had previously been the exclusive domain of very-long instruction word (VLIW) media processors.

x ADSP-BF506F EZ-KIT Lite Evaluation System Manual

The evaluation board is designed to be used in conjunction with the CrossCore® Embedded Studio (CCES) and VisualDSP++® development environments to test capabilities of the ADSP-BF504/BF506F Blackfin processors. The development environment aids advanced application code development and debug, such as:

• Create, compile, assemble, and link application programs written in C++, C, and ADSP-BF506F assembly

• Load, run, step, halt, and set breakpoints in application programs

• Read and write data and program memory

• Read and write core and peripheral registers

• Plot memory

Access to the processor from a personal computer (PC) is achieved through a USB port or an external JTAG emulator. The USB interface provides unrestricted access to the ADSP-BF506F processor and evalua-tion board peripherals. Analog Devices JTAG emulators offer faster communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products. To learn more about Analog Devices emulators and processor development tools, go to http://www.analog.com/dsp/tools.

The ADSP-BF506F EZ-KIT Lite provides example programs to demon-strate the evaluation board capabilities.

http://www.analog.com/dsp/tools

ADSP-BF506F EZ-KIT Lite Evaluation System Manual xi

Preface

Product OverviewThe board features:

• Analog Devices ADSP-BF506F Blackfin processor

• Core performance up to 400 MHz

• External bus performance up to 80 MHz

• 120-pin LQFP package

• 25 MHz crystal

• Programmable VDDINT core power

• Analog Devices AD5258 TWI digital potentiometer

• Analog Devices ADP1715 low dropout linear regulator

• Internal parallel flash memory

• Numonyx M58WT032 – 4 MB (2M x 16 bits)

• SPI flash memory

• Numonyx M25P16 – 16 Mb

• Internal ADC

• Analog Devices AD7266 2 MSPS, 12-bit, 3-channel SAR analog-to-digital converter

• Twelve single-ended inputs

• Six differential inputs

Product Overview

xii ADSP-BF506F EZ-KIT Lite Evaluation System Manual

• Universal asynchronous receiver/transmitter (UART)

• ADM3202 RS-232 line driver/receiver

• DB9 female connector

• LEDs

• Five LEDs: one board reset (red), three general-purpose (amber), and one power (green)

• Push buttons

• Three push buttons: one reset and two programmable flags with debounce logic

• Expansion interface II

• Provides access to most of the processor signals

• Land grid array

• Easy probing of all port pins

• Other features

• JTAG ICE 14-pin header

• Processor power measurement jumpers

For information about the hardware components of the EZ-KIT Lite, refer to Chapter 2, “ADSP-BF506F EZ-KIT Lite Hardware Reference”.

ADSP-BF506F EZ-KIT Lite Evaluation System Manual xiii

Preface

Purpose of This ManualThe ADSP-BF506F EZ-KIT Lite Evaluation System Manual provides instructions for installing the product hardware (board). The text describes operation and configuration of the board components and pro-vides guidelines for running your own code on the ADSP-BF506F EZ-KIT Lite. Finally, a schematic and a bill of materials are provided for reference.

Intended AudienceThe primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set.

Programmers who are unfamiliar with Analog Devices processors can use this manual but should supplement it with other texts that describe your target architecture. For the locations of these documents, see “Related Documents”.

Programmers who are unfamiliar with CCES or VisualDSP++ should refer to the online help and user’s manuals.

Manual Contents

xiv ADSP-BF506F EZ-KIT Lite Evaluation System Manual

Manual ContentsThe manual consists of:

• Chapter 1, “Using ADSP-BF506F EZ-KIT Lite” on page 1-1.Describes EZ-KIT Lite functionality from a programmer’s perspec-tive and provides an easy-to-access memory map.

• Chapter 2, “ADSP-BF506F EZ-KIT Lite Hardware Reference” on page 2-1.Provides information on the EZ-KIT Lite hardware components.

• Appendix A, “ADSP-BF506F EZ-KIT Lite Bill Of Materials” on page A-1.Provides a list of components used to manufacture the EZ-KIT Lite board.

• Appendix B, “ADSP-BF506F EZ-KIT Lite Schematic” on page B-1.Provides the resources to allow board-level debugging or to use as a reference guide. Appendix B is part of the online help.

What’s New in This Manual This is revision 1.1 of the ADSP-BF506F EZ-KIT Lite Evaluation System Manual. The manual has been updated to include CCES information. In addition, modifications and corrections based on errata reports against the previous manual revision have been made.

For the latest version of this manual, please refer to the Analog Devices Web site.

ADSP-BF506F EZ-KIT Lite Evaluation System Manual xv

Preface

Technical SupportYou can reach Analog Devices processors and DSP technical support in the following ways:

• Post your questions in the processors and DSP support community at EngineerZone®:http://ez.analog.com/community/dsp

• Submit your questions to technical support directly at:http://www.analog.com/support

• E-mail your questions about processors, DSPs, and tools develop-ment software from CrossCore Embedded Studio or VisualDSP++:

Choose Help > Email Support. This creates an e-mail [email protected] and automatically attaches your CrossCore Embedded Studio or VisualDSP++ version infor-mation and license.dat file.

• E-mail your questions about processors and processor applications to: [email protected] [email protected] (Greater China support)

• In the USA only, call 1-800-ANALOGD (1-800-262-5643)

• Contact your Analog Devices sales office or authorized distributor. Locate one at:www.analog.com/adi-sales

http://ez.analog.com/community/dsp

http://www.analog.com/support

mailto:[email protected]



http://www.analog.com/adi-sales

Supported Processors

xvi ADSP-BF506F EZ-KIT Lite Evaluation System Manual

• Send questions by mail to:Processors and DSP Technical SupportAnalog Devices, Inc.Three Technology WayP.O. Box 9106Norwood, MA 02062-9106USA

Supported ProcessorsThis evaluation system supports Analog Devices ADSP-BF504, ADSP-BF504F, and ADSP-BF506F Blackfin embedded processors.

Product InformationProduct information can be obtained from the Analog Devices Web site and the online help system.

Analog Devices Web SiteThe Analog Devices Web site, www.analog.com, provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.

To access a complete technical library for each processor family, go to http://www.analog.com/processors/technical_library. The manuals selection opens a list of current manuals related to the product as well as a link to the previous revisions of the manuals. When locating your manual title, note a possible errata check mark next to the title that leads to the current correction report against the manual.

Also note, myAnalog is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information

http://www.analog.com

http://www.analog.com/processors/technical_library/

http://www.analog.com/MyAnalog

ADSP-BF506F EZ-KIT Lite Evaluation System Manual xvii

Preface

about products you are interested in. You can choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests, including documentation errata against all manuals. myAnalog provides access to books, application notes, data sheets, code examples, and more.

Visit myAnalog (found on the Analog Devices home page) to sign up. If you are a registered user, just log on. Your user name is your e-mail address.

EngineerZoneEngineerZone is a technical support forum from Analog Devices. It allows you direct access to ADI technical support engineers. You can search FAQs and technical information to get quick answers to your embedded processing and DSP design questions.

Use EngineerZone to connect with other DSP developers who face similar design challenges. You can also use this open forum to share knowledge and collaborate with the ADI support team and your peers. Visit http://ez.analog.com to sign up.



http://ez.analog.com

Related Documents

xviii ADSP-BF506F EZ-KIT Lite Evaluation System Manual

Related DocumentsFor additional information about the product, refer to the following publications.

Notation ConventionsText conventions used in this manual are identified and described as follows.

Table 1. Related Processor Publications

Title Description

ADSP-BF504/BF504F/BF506F Blackfin Embedded Processor Data Sheet

General functional description, pinout, and timing of the processor

ADSP-BF50x Blackfin Processor Hardware Reference

Description of the internal processor archi-tecture and all register functions

Blackfin Processor Programming Reference Description of all allowed processor assembly instructions

Example Description

Close command (File menu)

Titles in reference sections indicate the location of an item within the development environment’s menu system (for example, the Close com-mand appears on the File menu).

{this | that} Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required.

[this | that] Optional items in syntax descriptions appear within brackets and sepa-rated by vertical bars; read the example as an optional this or that.

[this,…] Optional item lists in syntax descriptions appear within brackets delim-ited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this.

ADSP-BF506F EZ-KIT Lite Evaluation System Manual xix

Preface

.SECTION Commands, directives, keywords, and feature names are in text with letter gothic font.

filename Non-keyword placeholders appear in text with italic style format.

Note: For correct operation, ...A Note provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this

symbol.

Caution: Incorrect device operation may result if ...Caution: Device damage may result if ... A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol.

Warning: Injury to device users may result if ... A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users. In the online version of this book, the word Warning appears instead of this symbol.

Example Description

Notation Conventions

xx ADSP-BF506F EZ-KIT Lite Evaluation System Manual

ADSP-BF506F EZ-KIT Lite Evaluation System Manual 1-1

1 USING ADSP-BF506F EZ-KIT LITE

This chapter provides specific information to assist you with development of programs for the ADSP-BF506F EZ-KIT Lite evaluation system.

The following topics are covered.

• “Package Contents” on page 1-2

• “Default Configuration” on page 1-3

• “CCES Install and Session Startup” on page 1-3

• “VisualDSP++ Install and Session Startup” on page 1-8

• “CCES Evaluation License” on page 1-10

• “VisualDSP++ Evaluation License” on page 1-11

• “Memory Map” on page 1-12

• “Internal Flash Memory Interface” on page 1-13

• “SPI Flash Memory Interface” on page 1-13

• “Power-On-Self Test” on page 1-14

• “LEDs and Push Buttons” on page 1-14

• “JTAG Interface” on page 1-15

• “Expansion Interface II” on page 1-15

• “VDDINT Programmable Regulator” on page 1-16

Package Contents

1-2 ADSP-BF506F EZ-KIT Lite Evaluation System Manual

• “Power Measurements” on page 1-17

• “Example Programs” on page 1-18

• “Board Design Database” on page 1-18

For information about the graphical user interface, including the boot loading, target options, and other facilities of the EZ-KIT Lite system, refer to the online help.

For more detailed information about the ADSP-BF506F Blackfin proces-sor, see documents referred to at “Related Documents”.

Package ContentsYour ADSP-BF506F EZ-KIT Lite evaluation system package contains the following items.

• ADSP-BF506F EZ-KIT Lite board

• USB cable

If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or contact Analog Devices, Inc.


Using ADSP-BF506F EZ-KIT Lite

Default Configuration

The ADSP-BF506F EZ-KIT Lite board is designed to run outside your personal computer as a standalone unit.

When removing the EZ-KIT Lite board from the package, handle the board carefully to avoid the discharge of static electricity, which can dam-age some components. Figure 1-1 shows the default jumper settings, switches, connector locations, and LEDs used in installation. Confirm that your board is in the default configuration before using the board.

CCES Install and Session StartupFor information about CCES and to download the software, go to www.analog.com/CCES. A link for the ADSP-BF506F EZ-KIT Lite Board Support Package (BSP) for CCES can be found at http://www.analog.com/Blackfin/EZKits.

Follow these instructions to ensure correct operation of the product soft-ware and hardware.

Step 1: Connect the EZ-KIT Lite board to a personal computer (PC) run-ning CCES using one of two options: an Analog Devices emulator or via the debug agent.

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precau-tions are recommended to avoid performance degradation or loss of function-ality. Store unused EZ-KIT Lite boards in the protective shipping package.

http://www.analog.com/CCES

http://www.analog.com/Blackfin/EZKits

CCES Install and Session Startup


Using an Emulator:

1. Plug one side of the USB cable into the USB connector of the emu-lator. Plug the other side into a USB port of the PC running CCES.

2. Attach the emulator to the header connector P1 (labeled JTAG) on the EZ-KIT Lite board.

Figure 1-1. EZ-KIT Lite Hardware Setup



Using the on-board Debug Agent:

1. Plug one side of the USB cable into the USB connector of the debug agent ZP1 (labeled USB).

2. Plug the other side of the cable into a USB port of the PC running CCES.

Step 2: Attach the provided cord and appropriate plug to the 5V power adaptor.

1. Plug the jack-end of the power adaptor into the power connector P9 (labeled 5V) on the EZ-KIT Lite board.

2. Plug the other side of the power adaptor into a power outlet. The power LED (labeled LED5) is lit green when power is applied to the board.

3. Power the emulator (if used). Plug the jack-end of the assembled power adaptor into the emulator and plug the other side of the power adaptor into a power outlet. The enable/power is lit green when power is applied.

Step 3 (if connected through the debug agent): Verify that the yellow USB monitor LED (labeled ZLED2) and the green power LED (labeled ZLED1) on the debug agent are both on. This signifies that the board is communicating properly with the host PC and ready to run CCES.

CCES Install and Session Startup


Session StartupIt is assumed that the CrossCore Embedded Studio software is installed and running on your PC.

Note: If you connect the board or emulator first (before installing CCES) to the PC, the Windows driver wizard may not find the board drivers.

1. Navigate to the CCES environment via the Start menu.

Note that CCES is not connected to the target board.

2. Use the system configuration utility to connect to the EZ-KIT Lite board.

If a debug configuration exists already, select the appropriate configuration and click Apply and Debug or Debug. Go to step 8.

To create a debug configuration, do one of the following:

• Click the down arrow next to the little bug icon, select Debug Configurations

• Choose Run > Debug Configurations.

The Debug Configuration dialog box appears.

3. Select CrossCore Embedded Studio Application and click (New launch configuration).

The Select Processor page of the Session Wizard appears.

4. Ensure Blackfin is selected in Processor family. In Processor type, select ADSP-BF506F. Click Next.

The Select Connection Type page of the Session Wizard appears.



5. Select one of the following:

• For standalone debug agent connections, EZ-KIT Lite and click Next.

• For emulator connections, Emulator and click Next.

The Select Platform page of the Session Wizard appears.

6. Do one of the following:

• For standalone debug agent connections, ensure that the selected platform is ADSP-BF506F EZ-KIT Lite via Debug Agent.

• For emulator connections, choose the type of emulator that is connected to the board.

7. Click Finish to close the wizard.

The new debug configuration is created and added to the pro-gram(s) to load list.

8. In the Program(s) to load section, choose the program to load when connecting to the board. If not loading any program upon connection to the target, do not make any changes.

Note that while connected to the target, there is no way to choose a program to download. To load a program once connected, termi-nate the session.

To delete a configuration, go to the Debug Configurations dialog box and select the configuration to delete. Click and choose Yes when asked if you wish to delete the selected launch configuration. Then Close the dialog box.

VisualDSP++ Install and Session Startup


To disconnect from the target board, click the terminate button (red box) or choose Run > Terminate.

To delete a session, choose Target > Session > Session List. Select the session name from the list and click Delete. Click OK.

VisualDSP++ Install and Session StartupFor information about VisualDSP++ and to download the software, go to www.analog.com/VisualDSP.

There are two options to connect the EZ-KIT Lite hardware to a personal computer (PC) running VisualDSP++: via an Analog Devices emulator or va a standalone debug module. The standalone debug agent allows a debug agent to interface to the ADSP-BF506F EZ-KIT Lite. The stand-alone debug agent is shipped with the kit.

To connect the EZ-KIT Lite to a PC via an emulator:

1. Plug the 5V adaptor into connector P9 (labeled 5V) or plug the USB cable into ZP1 (labeled USB).

2. Attach the emulator to the header connector P1 (labeled JTAG) on the EZ-KIT Lite.

To connect the EZ-KIT Lite to a PC via the debug agent:

1. Plug one side of the provided USB cable into the USB connector of the debug agent ZP1 (labeled USB). Plug the other side of the cable into a USB port of the PC running VisualDSP++.

2. Verify that the yellow USB monitor LED on the debug agent, ZLED2, is lit. This signifies that the board is communicating prop-erly with the host PC and ready to run VisualDSP++.

http://www.analog.com/VisualDSP



Session Startup1. If you are running VisualDSP++ for the first time, navigate to the

VisualDSP++ environment via the Start > Programs menu. The main window appears. Note that VisualDSP++ does not connect to any session. Skip the rest of this step to step 2.

If you have run VisualDSP++ previously, the last opened session appears on the screen. You can override the default behavior and force VisualDSP++ to start a new session by pressing and holding down the Ctrl key while starting VisualDSP++. Do not release the Ctrl key until the Session Wizard appears on the screen. Go to step 3.

2. To connect to a new EZ-KIT Lite session, start Session Wizard by selecting one of the following.

• From the Session menu, New Session.

• From the Session menu, Session List. Then click New Ses-sion from the Session List dialog box.

• From the Session menu, Connect to Target.

3. The Select Processor page of the wizard appears on the screen.Ensure Blackfin is selected in Processor family. In Choose a target processor, select ADSP-BF506F. Click Next.

4. The Select Connection Type page of the wizard appears on the screen. Select EZ-KIT Lite and click Next.

5. The Select Platform page of the wizard appears on the screen. For standalone debug agent connections, ensure that the selected platform is ADSP-BF506F EZ-KIT Lite via Debug Agent. For emulator connections, choose the type of emulator that is con-nected. Specify your own Session name for your session or accept the default name.

CCES Evaluation License


The session name can be a string of any length; although, the box displays approximately 32 characters. The session name can include space characters. If you do not specify a session name, VisualDSP++ creates a session name by combining the name of the selected platform with the selected processor. The only way to change a session name later is to delete the session and open a new session.

Click Next.

6. The Finish page of the wizard appears on the screen. The page dis-plays your selections. Check the selections. If you are not satisfied, click Back to make changes; otherwise, click Finish. VisualDSP++ creates the new session and connects to the EZ-KIT Lite. Once connected, the main window’s title is changed to include the ses-sion name set in step 5.

To disconnect from a session, click the disconnect button or select Session > Disconnect from Target.

To delete a session, select Session > Session List. Select the session name from the list and click Delete. Click OK.

CCES Evaluation LicenseThe ADSP-BF506F EZ-KIT Lite software is part of the Board Support Package (BSP) for the Blackfin ADSP-BF50x family. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for 90 days after activation. Once the evaluation period ends, the evaluation license becomes permanently disabled. If the evaluation license is installed but not activated, it allows 10 days of unrestricted use and then becomes dis-abled. The license can be re-enabled by activation.



An evaluation license can be upgraded to a full license. Licenses can be purchased from:

• Analog Devices directly. Call (800) 262-5645 or 781-937-2384 or go to: http://www.analog.com/buyonline.

• Analog Devices, Inc. local sales office or authorized distributor. To locate one, go to:http://www.analog.com/salesdir/continent.asp.

The EZ-KIT Lite hardware must be connected and powered up to use CCES with a valid evaluation or full license.

VisualDSP++ Evaluation LicenseThe ADSP-BF506F EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unre-stricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires:

• VisualDSP++ restricts a connection to the ADSP-BF506F EZ-KIT Lite via the USB debug agent interface only. Connections to simu-lators and emulation products are no longer allowed.

• The linker restricts a user program to ¼ of memory (16K bytes), which is 4K bytes for code space with no restrictions for data space.

To avoid errors when opening VisualDSP++, the EZ-KIT Lite hardware must be connected and powered up. This is true for using VisualDSP++ with a valid evaluation or full license.

http://www.analog.com/buyonline

http://www.analog.com/salesdir/continent.asp

Memory Map


Memory MapThe ADSP-BF506F processor has internal static random access memory (SRAM) used for instruction or data storage. See Table 1-1. The internal memory details can be found in the ADSP-BF50x Blackfin Processor Hard-ware Reference.

The ADSP-BF506F EZ-KIT Lite board includes external serial peripheral interconnect (SPI) flash and internal flash memories. See Table 1-2; see also the following “Internal Flash Memory Interface” and “SPI Flash Memory Interface”.

Table 1-1. EZ-KIT Lite Internal Memory Map

Start Address Content

0xFFE0 0000 CORE MEMORY MAPPED REGISTERS

0xFFC0 0000 SYSTEM MEMORY MAPPED REGISTERS

0xFFB0 1000 Reserved

0xFFB0 0000 INTERNAL SCRATCHPAD RAM (4K BYTES)

0xFFA1 4000 Reserved

0xFFA0 8000 Reserved

0xFFA0 4000 L1 INSTRUCTION SRAM/CACHE (16K BYTES)

0xFFA0 0000 L1 INSTRUCTION BANK A SRAM (16K BYTES)

0xFF80 8000 Reserved

0xFF80 4000 L1 DATA BANK A SRAM/CACHE (16K BYTES)

0xFF80 0000 L1 DATA BANK A SRAM (16K BYTES)

0xEF00 1000 Reserved



Internal Flash Memory InterfaceInternal parallel flash memory of the ADSP-BF506F EZ-KIT Lite is a 4 MB (2M x 16 bits) Numonyx M58WT032 device, which is internal to the processor. The address range for flash memory is 0x2000 0000 to 0x203F FFFF.

By default, the EZ-KIT Lite boots from SPI flash memory. The processor boots from internal parallel flash memory if the boot mode select switch (SW2) is set to position 1 or 2; see “Boot Mode Select Switch (SW2)” on page 2-8.

Flash memory code can be modified. For instructions, refer to the online help and example program included in the EZ-KIT Lite installation directory.

SPI Flash Memory InterfaceSPI flash memory of the ADSP-BF506F EZ-KIT Lite is a 16 Mb Numonyx M25P16 device. The device is selected via SPI0_SEL1.

SPI flash memory is pre-loaded with boot code for the power-on-self test (POST) program. For more information, refer to “Power-On-Self Test” on page 1-14.

Table 1-2. EZ-KIT Lite External (Interface-Accessible) Memory Map

Start Address Content

0xEF00 0000 BOOT ROM (4K BYTES)

0x2040 0000 Reserved

0x2000 0000 SYNC FLASH (32M BITS)

0x0000 0000 Reserved

Power-On-Self Test


Power-On-Self TestThe power-on-self-test program (POST) tests all EZ-KIT Lite peripherals and validates functionality as well as connectivity to the processor. Once assembled, each EZ-KIT Lite if fully tested for an extended period of time with a POST. All EZ-KIT Lite boards are shipped with a POST pre-loaded into one of their on-board flash memories. The POST is exe-cuted by resetting the board and pressing the proper push button(s). The POST also can be used for reference for a custom software design or hard-ware troubleshooting. Note that the source code for the POST program is included in the installation directory along with the readme file, which describes how the board is configured to run a POST.

The POST program is only available when using VisualDSP++.

LEDs and Push ButtonsThe EZ-KIT Lite provides two push buttons and three LEDs for gen-eral-purpose I/O.

The three LEDs, labeled LED2 through LED4, are accessed via the PF0–2 GPIO ports of the processor. For information on how to program the flag pins, refer to the ADSP-BF50x Blackfin Processor Hardware Reference Manual.

The two general-purpose push buttons are labeled PB0 and PB1. The status of each individual button can be read through programmable flag inputs PF3 and PF4. The flag reads a ‘1’ when a corresponding switch is being pressed. When the switch is released, the flag reads a ‘0’. A connection between the push buttons and processor inputs is established through a DIP switch, SW3. The switch should be turned off when another source is driving the signals.

An example program is included in the ADSP-BF506F installation direc-tory to demonstrate functionality of the LEDs and push buttons.



The LED and push button signals also are connected to the expansion interface II; see “Expansion Interface II Connectors (P2 and P4)” on page 2-18 and “Expansion Interface II Connector (P3)” on page 2-18.

JTAG InterfaceThe board contains an on-board debug agent that operates via a USB port. The ADSP-BF506F EZ-KIT Lite receives all of its power via USB; there-fore, no power supply is required.

For debugging, the JTAG connector (P1) allows an external emulator (USB-ICE or HPUSB-ICE) to connect to the board, instead of the on-board debug agent.

For more information about emulators, contact Analog Devices or go to: http://www.analog.com/processors/tools/blackfin.

Expansion Interface IIThe expansion interface II allows an Analog Devices EZ-Extender® or a custom-design daughter board to be tested across various hardware plat-forms that have the same expansion interface.

The expansion interface II implemented on the ADSP-BF506F EZ-KIT Lite consists of three connectors, which are 0.1 in. shrouded headers (P2–4). The connectors contain a majority of the ADSP-BF506F processor’s signals. For pinout information, go to “ADSP-BF506F EZ-KIT Lite Sche-matic” on page B-1. The mechanical dimensions of the expansion connectors can be obtained by contacting “Technical Support”.

For more information about daughter boards, visit the Analog Devices Web site at:http://www.analog.com/processors/tools/blackfin.

http://www.analog.com/processors/tools/blackfin

http://www.analog.com/processors/tools/blackfin

VDDINT Programmable Regulator


Limits to current and interface speed must be taken into consideration when using the expansion interface. Current for the expansion interface II is sourced from the EZ-KIT Lite; therefore, the current should be limited to 1A for 5V and 500 mA for the 3.3V planes. If more current is required, then a separate power connector and a regulator must be designed on a daughter card. Additional circuitry can add extra loading to signals, decreasing their maximum effective speed.

Analog Devices does not support and is not responsible for the effects of additional circuitry.

VDDINT Programmable RegulatorBy default, the EZ-KIT Lite runs at 1.4V. The board contains a program-mable regulator that supplies the processor’s core with a voltage between 1.1 and 1.4. The voltage is adjusted by writing to the AD5258 digital potentiometer via the 2-wire interface (TWI) signals.Table 1-3 shows the appropriate step and corresponding voltage values. For an example of writing to the AD5258 potentiometer, refer to the POST example. For more information on the acceptable voltage/frequency values, refer to the ADSP-BF504/BF504F/BF506F Blackfin Embedded Processor Data Sheet and ADSP-BF50x Blackfin Processor Hardware Reference manual. For more information about the digital potentiometer, refer to the AD5258 data sheet.



Power MeasurementsSeveral locations are provided for measuring the current draw from vari-ous power planes. Precision 0.1 ohm shunt resistors are available on the VDDINT, VDDEXT, and VDDFLASH voltage domains. For current draw, the jumper is removed, voltage across the resistor can be measured using an oscilloscope, and the value of the resistor can be measured using a precision multi-meter. Once the voltage and resistance are measured, the current can be calculated by dividing the voltage by the resistance. For the highest accuracy, a differential probe should be used for measuring the voltage across the resistor.

Table 1-3. Voltage Values

Step Value Voltage (V)

57 1.10

46 1.15

36 1.20

27 1.25

18 1.30

10 1.35

3 1.40

Example Programs


Example ProgramsExample programs are provided with the ADSP-BF506F EZ-KIT Lite to demonstrate various capabilities of the product. The programs are included in the product installation kit and can be found in the Examples folder of the installation. Refer to a readme file provided with each exam-ple for more information.

CCES users are encouraged to use the example browser to find examples included with the EZ-KIT Lite Board Support Package.

Board Design DatabaseA .zip file containing all of the electronic information required for the design, layout, fabrication and assembly of the product is available for download from the Analog Devices board design database at:http://www.analog.com/board-design-database.

http://www.analog.com/board-design-database


2 ADSP-BF506F EZ-KIT LITE HARDWARE REFERENCE

This chapter describes the hardware design of the ADSP-BF506F EZ-KIT Lite board.

The following topics are covered.

• “System Architecture” on page 2-2Describes the board’s configuration and explains how the board components interface with the processor.

• “Programmable Flags” on page 2-3Shows the locations and describes the programming flags (PFs).

• “Push Buttons and Switches” on page 2-7Shows the locations and describes the push buttons and switches.

• “Jumpers” on page 2-11Shows the locations and describes the configuration jumpers.

• “LEDs” on page 2-14Shows the locations and describes the LEDs.

• “Connectors” on page 2-16Shows the locations and provides part numbers for the on-board connectors. In addition, the manufacturer and part number infor-mation is provided for the mating parts.

System Architecture


System ArchitectureThis section describes the processor’s configuration on the EZ-KIT Lite board (Figure 2-1).

The EZ-KIT Lite is designed to demonstrate the ADSP-BF506F Blackfin processor capabilities. The processor has an I/O voltage of 3.3V. The core voltage of the processor is controlled by an Analog Devices ADP1715 low dropout regulator (LDO) and an Analog Devices AD5258 digipot, which is configurable over the 2-wire interface (TWI) signals. Refer to the

Figure 2-1. System Architecture


ADSP-BF506F EZ-KIT Lite Hardware Reference

power-on-self test (POST) example in the ADSP-BF506F installation directory for information on how to set up the TWI interface.

The core voltage and clock rate can be set up on the fly by the processor. The input clock is 25 MHz. The default boot mode for the processor is SPI flash boot. See “Boot Mode Select Switch (SW2)” for information on how to change the default boot mode.

Programmable FlagsThe processor has 35 general-purpose input/output (GPIO) signals spread across three ports (PF, PG, and PH). The pins are multi-functional and depend on the ADSP-BF506F processor setup. The following tables show how the programmable flag pins are used on the EZ-KIT Lite.

• PF programmable flag pins – Table 2-1

• PG programmable flag pins – Table 2-2

• PH programmable flag pins – Table 2-3

Table 2-1. Port F Programmable Flag Connections

Processor Pin Other Processor Function EZ-KIT Lite Function

PF0 TSCLK0/UA0_RX_ALT/TMR6/CUD0

Default: LED0Land grid array, expansion interface II

PF1 RSCLK0/UA0_TX_ALT/TMR5/CDG0

Default: LED1 Land grid array, expansion interface II

PF2 DT0PRI/PWM0_BH/PPI_D8/CZM0

Default: LED2 Land grid array, expansion interface II

PF3 TFS0/PWM0_BL/PPI_D9/CDG0

Default: PB0 Land grid array, expansion interface II

PF4 RFS0/PWM0_CH/PPI_D10/TACLK0

Default: PB1 Land grid array, expansion interface II

Programmable Flags


PF5 RFS0/PWM0_CH/PPI_D10/TACLK0

Default: not used Land grid array, expansion interface II

PF6 UA1_TX/PWM0_TRIP/PPI_D12


PF7 UA1_RX/PWM0_SYNC/PPI_D13/TACI3

Default: not usedLand grid array, expansion interface II

PF8 UA1_RTS/DT0SEC/PPI_D7 Default: not usedLand grid array, expansion interface II

PF9 UA1_CTS/DR0SEC/PPI_D6/CZM0

Default: not usedLand grid array, expansion interface II

PF10 SPI0_SCK/TMR2/PPI_D5 Default: SPI0_SCK Land grid array, expansion interface II

PF11 SPI0_MISO/PWM0_TRIP/PPI_D4/TACLK2

Default: SPI0_MISO Land grid array, expansion interface II

PF12 SPI0_MOSI/PWM0_SYNC/PPI_D3

Default: SPI0_MOSI Land grid array, expansion interface II

PF13 SPI0_SEL1/TMR3/PPI_D2/ SPI0_SS

Default: SPI0_SEL1 Land grid array, expansion interface II

PF14 SPI0_SEL2/PWM0_AH/PPI_D1


PF15 SPI0_SEL3/PWM0_AL/PPI_D0


Table 2-2. Port G Programmable Flag Connections


PG0 SPI1_SEL3/TMRCLK/PPI_CLK/ UA1_RX_ALT/TACI4

Default: CAN_ERR Land grid array, expansion interface II

PG1 SPI1_SEL2/PPI_FS3/CAN_RX/ TACI5

Default: CAN_RX Land grid array, expansion interface II

Table 2-1. Port F Programmable Flag Connections (Cont’d)




PG2 SPI1_SEL1/TMR4/CAN_TX/ SPI1_SS

Default: CAN_TX Land grid array, expansion interface II

PG3 HWAIT/SPI1_SCK/DT1SEC/ UA1_TX_ALT


PG4 SPI1_MOSI/DR1SEC_ALT/ PWM1_SYNC/TACLK6

Default: SD_WP Land grid array, expansion interface II

PG5 SPI1_MISO/TMR7/PWM1_TRIP

Default: SD_CD Land grid array, expansion interface II

PG6 PG6 ACM_SGLDIFF/SD_D3/PWM1_AH

Default: ACM_SGLDIFFSD_D3, land grid array, expansion interface II

PG7 ACM_RANGE/SD_D2/PWM1_AL Default: ACM_RANGESD_D2, land grid array, expansion interface II

PG8 DR1SEC/SD_D1/PWM1_BH Default: ADC_DOUTBSD_D1, land grid array, expansion interface II

PG9 DR1PRI/SD_D0/PWM1_BL Default: ADC_DOUTASD_D0, land grid array, expansion interface II

PG10 RFS1/SD_CMD/PWM1_CH/TACI6

Default: ADC_CSSD_CMD, land grid array, expansion interface II

PG11 RSCLK1/SD_CLK/PWM1_CL/TACLK7

Default: ADC_SCLKSD_CLK, land grid array, expansion interface II

PG12 UA0_RX/SD_D4/PPI_D15/TACI2

Default: UART0_RXDS_D4, land grid array, expansion interface II

PG13 UA0_TX/SD_D5/PPI_D14/CZM1

Default: UART0_TXDS_D5, land grid array, expansion interface II

PG14 /UA0_RTS/SD_D6/TMR0/PPI_FS1/CUD1

Default: UART0_RTSDS_D5, land grid array, expansion interface II

PG15 /UA0_CTS/SD_D7/TMR1/PPI_FS2/CDG1

Default: UART0_CTSDS_D7, land grid array, expansion interface II

Table 2-2. Port G Programmable Flag Connections (Cont’d)


Programmable Flags


Table 2-3. Port H Programmable Flag Connections


PH0 ACM_A2/DT1PRI/SPI0_SEL3/WAKEUP

Default: ACM_A2 Land grid array, expansion interface II

PH1 ACM_A1/TFS1/SPI1_SEL3_ALT/TACLK3


PH2 ACM_A0/TSCLK1/SPI1_SEL2_ALT/TACI7




Push Buttons and SwitchesThis section describes operation of the push buttons and switches. The push button and switch locations are shown in Figure 2-2.

Figure 2-2. Push Button and Switch Locations

Push Buttons and Switches


UART Setup Switch (SW1)The UART setup switch (SW1) configures the UART0 signals between the DCE connector (J1) and processor. Table 2-4 shows the switch settings.

Boot Mode Select Switch (SW2)The boot mode select switch (SW2) determines the boot mode of the pro-cessor. Table 2-5 shows the available boot mode settings. By default, the ADSP-BF506F processor boots from SPI flash memory.

Table 2-4. UART Setup Switch (SW1)

SW1 Position Function

1 and 3 Enable flow control

2 Disconnects the UART_RX signal from the processor;the UART_RX signal can be used for another function

4 Connects the RTS and CTS signals together

5 Allows the host to reset the EZ-KIT Lite via the CTS signal

6 and 7 Selects the source for the CTS signal

8 Loops the TX and RX signals together for testing

Table 2-5. Boot Mode Select Switch (SW2)

SW2 Position Processor Boot Mode

0 Idle—no boot

1 Boots from stacked parallel flash in asynchronous mode

2 Boots from stacked parallel flash in synchronous mode

3 Boots through SPI0 master from SPI memory

4 Boots through SPI0 slave from host device

5 Boots through PPI from host



Push Button Enable Switch (SW3)The push button enable switch (SW3) disconnects the associated push but-ton circuit from the general-purpose I/O (GPIO) pins of the processor and allows the signals to be used on the expansion interface.

ADC Enable Switch (SW4)The ADC enable switch (SW4) disconnects the ADC from the SPORT1 interface of the processor and allows the ADC signals to be used on the SD connector or the expansion interface.

CAN Enable Switch (SW5)The CAN enable switch (SW5) disconnects the CAN transceiver from the processor and allows the CAN signals to be used on the expansion interface.

Reset Push Button (SW6)The reset push button (SW6) resets the processor via a hardware reset. The reset push button does not reset the on-board debug agent. The only way to reset the debug agent is to cycle power.

Programmable Flag Push Buttons (SW7–8)Two momentary push buttons (SW7 and SW8) are provided for general-pur-pose user input. The buttons are connected to the PF3–4 GPIO pins of the

6 Reserved

7 Boots through UART0 slave from host device

Table 2-5. Boot Mode Select Switch (SW2) (Cont’d)

SW2 Position Processor Boot Mode

Push Buttons and Switches


processor. The push buttons are active high and, when pressed, send a high (1) to the processor. The GPIO enable switch (SW3) disconnects the push buttons from the associated push button signals (refer to “Push But-ton Enable Switch (SW3)” on page 2-9 for more information).

ADC Loopback Switches (SW9–10)The ADC loopback switches (SW9 and SW10) are used for testing only. The switches connect a test signal to the ADC inputs.



JumpersThis section describes functionality of the configuration jumpers. Figure 2-3 shows the jumper locations.

SPI FLASH CS Enable Jumper (JP1)The SPI flash CS enable jumper (JP1) connects the SPI0_SEL1 signal to SPI flash memory. By default, JP1 is installed, and SPI flash is connected.

Figure 2-3. Configuration Jumper Locations

Jumpers


Voltage Reference Select Jumper (JP2)The voltage reference select jumper (JP2) selects between a 2.5V on-chip reference and an external voltage reference. When the jumper is installed on positions 2 and 3, the on-chip 2.5V reference is used. When the jumper is installed on positions 1 and 2, an external reference can be con-nected to the ADC through the DCAPA and DCAPB signals (see “ADC Voltage Reference (JP6)” on page 2-13). By default, JP2 is installed on positions 2 and 3.

VDDEXT Power Jumper (JP3)The VDDEXT power jumper (JP3) is used to measure the processor’s I/O voltage and current. By default, JP3 is ON, and the current flows through the two-pin IDC header. To measure power, remove the jumper on JP3 and measure the voltage across the precision resistor and resistance value. For more information, refer to “Power Measurements” on page 1-17.

VDDINT Power Jumper (JP4)The VDDINT power jumper (JP4) is used to measure the processor’s core voltage and current. By default, JP4 is ON, and the current flows through the two-pin IDC header. To measure power, remove the jumper on JP4 and measure the voltage across the precision resistor and resistance value. For more information, refer to “Power Measurements” on page 1-17.

VDDFLASH Power Jumper (JP5)The VDDFLASH power jumper (JP5) is used to measure the internal par-allel flash voltage and current. By default, JP5 is ON, and the current flows through the two-pin IDC header. To measure power, remove the jumper on JP5 and measure the voltage across the precision resistor and resistance value. For more information, refer to “Power Measurements” on page 1-17.



ADC Voltage Reference (JP6)The ADC voltage reference jumper (JP6) is used to supply a reference voltage to the ADC. In order to use an external voltage reference, a jumper must be placed on positions 1 and 2 of JP2. To use the on-board AD780 precision voltage reference, install a jumpers at position 1, 2 and 3, 4. To supply your own voltage reference, remove all jumpers from JP6 and con-nect your voltage reference to pins 1 and 3. By default, no jumpers are installed on JP6.

LEDs


LEDsThis section describes the on-board LEDs. Figure 2-4 shows the LED locations.

Figure 2-4. LED Locations



Reset LED (LED1)When LED1 is lit, it indicates that the master reset of all the major ICs is active. The reset signal is controlled by the Analog Devices ADM708 supervisory reset circuit.

GPIO LEDs (LED2–4)Three LEDs connect to the three general-purpose I/O pins of the proces-sor (see Table 2-6). The LEDs are active high and lit by writing a “1” to the correct programmable flag signal.

Power LED (LED5)When LED5 is lit solid, it indicates that power is being properly supplied to the board.

Table 2-6. GPIO LEDs

LED Reference Designator Processor Programmable Flag Pin

LED2 PF0

LED3 PF1

LED4 PF2

Connectors


ConnectorsThis section describes connector functionality and provides information about mating connectors. The connector locations are shown in Figure 2-5.

Figure 2-5. Connector Locations



RS-232 Connector (J1)

CAN Connector (J2)

SD Connector (J3)

JTAG Connector (P1)The JTAG header (P1) is the connecting point between the JTAG inter-face and ADSP-BF506F processor.

Pin 3 is missing to provide keying. Pin 3 in the mating connector should have a plug.

Part Description Manufacturer Part Number

DB9, female, vertical mount NORCOMP 191-009-213-L-571

Mating Cable

2m female-to-female cable DIGI-KEY AE1020-ND


RJ11 modular jack AMP 5558872-1

Mating Cable

4-conductor modular jack cable L-COM TSP3044


SD 8-bit MORETHANALL MHC-W21-601-LF

Memory Card

256 MB SANDISK-STACK SDSDB-256-A10

Connectors


When an emulator is used with the EZ-KIT Lite, the on-board debug agent is bypassed.

Expansion Interface II Connectors (P2 and P4)P2 and P4 are board-to-board connectors providing signals for the SPI, TWI, UART, SPORT, and GPIO signals of the processor. The connec-tors are located on the upper edge of the board (one connector is on the top and one is on the bottom). For more information, see “Expansion Interface II” on page 1-15.

Expansion Interface II Connector (P3)P3 is a board-to-board connector providing signals for the PPI and GPIO signals of the processor. The connector is located on the upper edge of the board. For more information, see “Expansion Interface II” on page 1-15.


50-position 0.1’’, SMT header SAMTEC TSSH-125-01-L-DV-A

Mating Connector

50-position 0.1’’, SMT socket SAMTEC SSW-125-22-F-D-VS


70-position 0.1’’, SMT header SAMTEC TSSH-135-01-L-DV-A

Mating Connector

70-position 0.1’’, SMT socket SAMTEC SSW-135-22-F-D-VS



DMAX Land Grid Array Connectors (P5–6)The DMAX land grid array areas (P5 and P6) are intended for the probing of the processor signals. The pads are exposed and designed to attach a Tektronix logic analyzer to the connectors listed in the following table. For more information about the land grid array, consult the Tektronix web site.

ADC Input Connector (P7)

Power Connector (P9)


Primary retention Tektronix 020290800

Alternate retention Tektronix 020291000


24-position 0.1’’, TH header SAMTEC TSSH-112-01-L-D


0.65 mm power jack CUI 045-0883R

Mating Connector

[email protected] power supply GLOBETEK GS-1750(R)

Connectors


ADSP-BF506F EZ-KIT Lite Evaluation System Manual A-1

A ADSP-BF506F EZ-KIT LITE BILL OF MATERIALS

The bill of materials corresponds to “ADSP-BF506F EZ-KIT Lite Sche-matic” on page B-1.

Ref. Qty. Description Reference Designator Manufacturer Part Number

1 1 74LVC14A SOIC14

U1 TI 74LVC14AD

2 1 IDT74FCT3244APY SSOP20

U5 IDT IDT74FCT3244APYG

3 1 25MHZ OSC003 U15 EPSON SG-8002CA MP

4 2 SN74LVC1G08 SOT23-5

U18,U20 TI SN74LVC1G08DBVR

5 1 TJA1041 SOIC14

U19 PHILIPS TJA1041T/N1

6 1 SI4411DY SO-8 U3 VISHAY Si4411DY-T1-E3

7 1 BF506F M25P16 U4

U4 ST MICRO M25P16-VMW6G

8 1 MIC94042 MLF4

U6 MICREL MIC94042YFL

9 1 ADM708SARZ SOIC8

U17 ANALOG DEVICES

ADM708SARZ

10 1 ADM3202ARNZ SOIC16

U16 ANALOG DEVICES

ADM3202ARNZ

11 1 ADSP-BF506F LQFP120

U7 ANALOG DEVICES

ADSPBF506FBSWZ-ENG

12 1 ADP1864AUJZ SOT23-6

VR1 ANALOG DEVICES

ADP1864AUJZ-R7

A-2 ADSP-BF506F EZ-KIT Lite Evaluation System Manual

13 1 ADP1715 MSOP8

VR3 ANALOG ADP1715ARMZ-R7

14 1 AD5258 MSOP10

U2 ANALOG DEVICES

AD5258BRMZ10

15 1 ADP1715 MSOP8

VR4 ANALOG DEVICES

ADP1715ARMZ-1.8-R7

16 6 AD8022 MSOP8 U9-14 ANALOG DEVICES

AD8022ARMZ

17 1 ADP1613 MSOP8

VR2 ANALOG DEVICES

ADP1613ARMZ-R7

18 1 DIP8 SWT016 SW1 C&K TDA08H0SB1

19 2 DIP6 SWT017 SW9-10 CTS 218-6LPST

20 2 DIP4 SWT018 SW4-5 ITT TDA04HOSB1

21 1 DB9 9PIN CON038

J1 NORCOMP 191-009-213-L-571

22 1 RJ11 4PIN CON039

J2 TYCO 5558872-1

23 1 DIP2 SWT020 SW3 C&K CKN9064-ND

24 4 IDC 2X1 IDC2X1

JP1,JP3-5 FCI 90726-402HLF

25 1 IDC 3X1 IDC3X1

JP2 FCI 90726-403HLF

26 1 IDC 7X2 IDC7X2

P1 SAMTEC TSW-107-07-T-D

27 1 IDC 12X2 IDC12X2

P7 SAMTEC SSW-112-01-T-D

28 1 3A RESETABLE FUS004

F1 TYCO SMD300F-2

29 6 IDC 2PIN_JUMPER_SHORT

SJ1-6 DIGI-KEY S9001-ND



ADSP-BF506F EZ-KIT Lite Bill Of Materials

30 1 PWR .65MM CON045

P9 DIG CP1-023-ND

31 3 MOMENTARY SWT024

SW6-8 PANASONIC EVQ-Q2K03W

32 1 ROTARY SWT027

SW2 COPAL S-8110

33 1 SD_CONN 8-BIT CON067

J3 MORETHA-NALL

MHC-W21-601-LF

34 3 YELLOW LED001

LED2-4 PANASONIC LN1461C

35 2 100 1/10W 5% 0805

R92,R94 VISHAY CRCW0805100RJNEA

36 2 600 100MHZ 500MA 1206

FER2-3 STEWARD HZ1206B601R-10

37 2 0 1/10W 5% 0805

R71,C101 VISHAY CRCW08050000Z0EA

38 1 190 100MHZ 5A FER002

FER4 MURATA DLW5BSN191SQ2

39 2 0.47UF 16V 10% 0805

C76-77 AVX 0805YC474KAT2A

40 2 1UF 10V 10% 0805

C87-88 AVX 0805ZC105KAT2A

41 8 10UF 6.3V 10% 0805

C7,C13,C21,C33,C71,C73-74,C121

AVX 08056D106KAT2A

42 1 4.7UF 6.3V 10% 0805

C113 AVX 08056D475KAT2A

43 34 0.1UF 10V 10% 0402

C4-6,C9-12,C20,C22-24,C31-32,C37-48,C70,C72,C75,C89-92,C109,C118

AVX 0402ZD104KAT2A

44 24 0.01UF 16V 10% 0402

C2-3,C8,C14-19,C25-30,C81-86,C93,C108,C122

AVX 0402YC103KAT2A



45 42 10K 1/16W 5% 0402

R3-6,R9,R11,R14,R19,R27-38,R69-70,R72-73,R79,R81-83,R88-91,R95,R98-101,R108,R128,R133-134,R137

VISHAY CRCW040210K0FKED

46 3 4.7K 1/16W 5% 0402

R15-17 VISHAY CRCW04024K70JNED

47 25 0 1/16W 5% 0402

R21-22,R25-26,R39-40,R42-43,R45-46,R49-50,R52-53,R55-56,R58-61,R63-64,R66-67,R130

PANASONIC ERJ-2GE0R00X

48 11 33 1/16W 5% 0402

R7-8,R18,R20,R135-136,R138-142

VISHAY CRCW040233R0JNEA

49 2 2.2UF 10V 10% 0805

C119-120 AVX 0805ZD225KAT2A

50 2 1A SK12 DO-214AA

D8,D10 DIODES INC

B120B-13-F

51 24 10PF 50V 5% 0805

C34-36,C49-69 AVX 08055A100JAT2A

52 1 1UF 16V 10% 0603

C96 PANASONIC ECJ-1VB1C105K

53 1 68PF 50V 5% 0603

C112 AVX 06035A680JAT2A

54 3 4.7UF 6.3V 20% 0603

C106-107,C110 PANASONIC ECJ-1VB0J475M

55 1 470PF 50V 5% 0603

C111 AVX 06033A471JAT2A

56 1 220UF 6.3V 20% D2E

CT1 SANYO 10TPE220ML

57 5 330 1/10W 5% 0603

R80,R84-87 VISHAY CRCW0603330RJNEA

58 1 0 1/10W 5% 0603

R111 PHYCOMP 232270296001L




59 15 10 1/10W 5% 0603

R23-24,R41,R44,R47-48,R51,R54,R57,R62,R65,R68,R75,R77,R113

VISHAY CRCW060310R0JNEA

60 1 4700PF 16V 10% 0603

C79 DIGI-KEY 311-1083-2-ND

61 2 100PF 50V 5% 0603

C78,C80 AVX 06035A101JAT2A

62 1 1000PF 50V 5% 0603

C104 PANASONIC ECJ-1VC1H102J

63 2 62.0 1/10W 1% 0603

R74,R76 DIGI-KEY 311-62.0HRTR-ND

64 1 4.99K 1/16W 1% 0603

R112 VISHAY CRCW06034K99FKEA

65 1 24.9K 1/10W 1% 0603

R123 DIGI-KEY 311-24.9KHTR-ND

66 5 0.05 1/2W 1% 1206

R121-122,R125-126,R131

SEI CSF 1/2 0.05 1%R

67 7 10UF 16V 10% 1210

C97-100,C102,C114,C117

AVX 1210YD106KAT2A

68 1 GREEN LED001 LED5 PANASONIC LN1361CTR

69 1 RED LED001 LED1 PANASONIC LN1261CTR

70 2 1000PF 50V 5% 1206

C115-116 AVX 12065A102JAT2A

71 1 255.0K 1/10W 1% 0603

R127 VISHAY CRCW06032553FK

72 1 80.6K 1/10W 1% 0603

R124 DIGI-KEY 311-80.6KHRCT-ND

73 1 22000PF 25V 10% 0402

C94 DIGI-KEY 490-3252-1-ND



74 2 5A MBRS540T3G SMC

D6-7 ON SEMI MBRS540T3G

75 1 2.5UH 30% IND013

L3 COILCRAFT MSS1038-252NLB

76 1 33.0K 1/16W 1% 0402

R2 ROHM MCR01MZPF3302

77 1 1.0K 1/16W 1% 0402

R120 PANASONIC ERJ-2RKF1001X

78 1 220PF 50V 10% 0402

C1 DIGI-KEY 311-1035-2-ND

79 2 100K 1/16W 5% 0402

R1,R114 DIGI-KEY 541-100KJTR-ND

80 1 2.2UF 25V 10% 0805

C103 DIGI-KEY 490-3331-1-ND

81 2 1A MBR130LSFT1G SOD-123FL

D4-5 ON SEMI MBR130LSFT1G

82 2 1UH 20% IND019

L1-2 COILCRAFT ME3220-102MLB

83 2 33 1/16W 5% RNS003

RN1-2 PANASONIC EXB-2HV330JV

84 3 1.2K 1/16W 1% 0402

R12-13,R117 VISHAY CRCW04021K20FKED

85 2 4.3 1/4W 5% 1206

R116,R119 PANASONIC ERJ-8GEYJ4R3V

86 1 2.67K 1/16W 1% 0402

R118 PANASONIC ERJ-2RKF2671X

87 1 22UH 20% IND024

L4 COILCRAFT MSD7342-223MLC

88 1 330 100MHZ 1.5A 0805

FER1 MURATA BLM21PG331SN1D




89 1 3300PF 50V 5% 0603

C95 PANASONIC ECJ-1VB1H332K

90 1 27.4K 1/10W 1% 0603

R115 PANASONIC ERJ-3EKF2742V

91 1 20.0K 1/16W 1% 0402

R109 VISHAY CRCW040220K0FKED

92 1 30A GSOT05 SOT23-3

D2 VISHAY GSOT05-GS08

93 1 30A GSOT03 SOT23-3

D3 VISHAY GSOT03-GS08

94 1 40A ESD5Z2.5T1 SOD-523

D9 ON SEMI ESD5Z2.5T1G

95 1 7A VESD01-02V-GS08 SOD-52

D1 VISHAY VESD01-02V-GS08

96 1 IDC 25x2 IDC25x2_SMTA

P2 SAMTEC TSSH-125-01-L-DV-A

97 1 35x2 IDC35x2_SMTA

P3 SAMTEC TSSH-135-01-L-DV-A


TITLE

17-12-2009_16:20 1 10

D

4

3

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A B C

20 Cotton Road

Nashua, NH 03063

A B C D

4

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PH: 1-800-ANALOGD

C

Title

Size Board No.

Date Sheet of

DEVICESANALOG

RevA0226-2009

ADSP-BF506F EZ-KIT LITE

1.0

SCHEMATICADSP-BF506F EZ-KIT LITE

DA_5V

3.3V

0402R139 33

R131.2K0402

3.3V

R1110K0402

DEFAULT=INSTALLED

SJ1

JUMPERSHORTING

R510K0402

C20.01UF0402

3.3V

C30.01UF0402

3.3V

10K0402

R19

R154.7K0402

R164.7K0402

R174.7K0402

R1410K0402

R233.0K0402

C1220PF0402

R1100K0402

TP1

3.3V

R121.2K0402

3.3V

R310K0402 0402

10KR4

3.3V

R910K0402

DSP + SPI FLASH

1017-12-2009_16:20 2

D

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A B C

20 Cotton Road

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Title

Size Board No.

Date Sheet of

DEVICESANALOG

RevA0226-2009


1.0

25MHZOSC003

U15 4

31

2GND

OE OUT

VDD

P1

IDC7X2

14

12

10

8

6

4

2

13

11

9

7

5

3

1

040210KR6

SW2

ROTARYSWT027

4

2

1 C

0

12

3

4

56

7

IDC2X1

JP121

SO8WM25P16

U4

3

7

1

8

25

6

4GND

SCK

SI SO

VCC

CS

HOLD

WP

3.3V

R20330402

RNS00333

RN2

98

107

116

125

134

143

152

161R1A R1B

R2A R2B

R3A R3B

R4A R4B

R5A R5B

R6A R6B

R7A R7B

R8A R8B

R7 330402

040233R138

R8 330402

R140 330402

040233R18

EXT_PS

DA_5V

DSP_TCK

DSP_TDI

DSP_TDO

DSP_TMS

GN

D

JTAG_CONN_TCK

JTAG_CONN_TDI

JTAG_CONN_TMS

DA_USB_PWR

DA_SOFT_RESET

DSP_EMU

DSP_TRSTJTAG_CONN_EMU

JTAG_CONN_SELECT

JTAG_CONN_TRST

JTAG_CONN_TDO

DEBUG_AGENT

U7

ADSP-BF506FLQFP120_EP

56

71

111

110

68

34

37

114

33

35

54

36

55

115

113

44

43

40

39

38

32

31

29

50

49

48

47

46

45

28

27

10

9

8

7

5

3

4

2

22

21

19

18

16

14

119

118

57

58

11

12

70

120EXTCLK

EXT_WAKE

RESET

NMI

BMODE0

BMODE1

PF0/TSCLK0/UA0_RX/TMR6/CUD0

PF1/RSCLK0/UA0_TX/TMR5/CDG0

PF10/SPI0_SCK/TMR2/PPI_D5

PF11/SPI0_MISO/PWM0_TRIP/PPI_D4/TACLK2

PF12/SPI0_MOSI/PWM0_SYNC/PPI_D3

PF13/SPI0_SEL1/TMR3/PPI_D2/SPI0_SS

PF14/SPI0_SEL2/PWM0_AH/PPI_D1

PF15/SPI0_SEL3/PWM0_AL/PPI_D0

PF2/DT0PRI/PWM0_BH/PPI_D8/CZM0

PF3/TFS0/PWM0_BL/PPI_D9/CDG0

PF4/RFS0/PWM0_CH/PPI_D10/TACLK0

PF5/DR0PRI/PWM0_CL/PPI_D11/TACLK1

PF6/UA1_TX/PWM0_TRIP/PPI_D12

PF7/UA1_RX/PWM0_SYNC/PPI_D13/TACI3

PF8/UA1_RTS/DT0SEC/PPI_D7

PF9/UA1_CTS/DR0SEC/PPI_D6/CZM0

PG0/SPI1_SEL3/TMRCLK/PPI_CLK/UA1_RX/TACI4

PG1/SPI1_SEL2/PPI_FS3/CAN_RX/TACI5

PG10/RFS1/SD_CMD/PWM1_CH/TACI6

PG11/RSCLK1/SD_CLK/PWM1_CL/TACLK7

PG12/UA0_RX/SD_D4/PPI_D15/TACI2

PG13/UA0_TX/SD_D5/PPI_D14/CZM1

PG14/UA0_RTS/SD_D6/TMR0/PPI_FS1/CUD1

PG15/UA0_CTS/SD_D7/TMR1/PPI_FS2/CDG1

PG2/SPI1_SEL1/TMR4/CAN_TX/SPI1_SS

PG3/HWAIT/SPI1_SCK/DT1SEC/UA1_TX

PG4/SPI1_MOSI/DR1SEC/PWM1_SYNC/TACLK6

PG5/SPI1_MISO/TMR7/PWM1_TRIP

PG6/ACM_SGLDIFF/SD_D3/PWM1_AH

PG7/ACM_RANGE/SD_D2/PWM1_AL

PG8/DR1SEC/SD_D1/PWM1_BH

PG9/DR1PRI/SD_D0/PWM1_BL

PH0/ACM_A2/DT1PRI/SPI0_SEL3/WAKEUP

PH1/ACM_A1/TFS1/SPI1_SEL3/TACLK3

SCL

TDO

SDA

TMS

TDI

PH2/ACM_A0/TSCLK1/SPI1_SEL2/TACI7

TRST

TCK

EMU

CLKIN

XTAL

PG

BMODE2

SDA

SCL

EXT_WAKE

DA_USB_PWREXT_PS

UART0_CTS/SD_D7

UART0_RTS/SD_D6

UART0_TX/SD_D5

UART0_RX/SD_D4

ACM_SGLDIFF/SD_D3

ACM_RANGE/SD_D2

ADC_DOUTB/SD_D1

ADC_DOUTA/SD_D0

LED0

LED1

LED2

PB0

PB1

PF5

PF6

PF7

PF8

PF9

SPI0_MISO

SPI0_MISO

SPI0_MOSI

SPI0_MOSI

SPI0_SEL1

SPI0_SEL1

PF14

PF15

RESET

ACM_A0

ACM_A1

ACM_A2

ADC_SCLK/SD_CLK

ADC_CS/SD_CMD

SD_CD

SD_WP

PG3

CAN_TX

CAN_RX

CAN_ERR

DSP_TMS

DSP_TMS

DSP_TDI

DSP_TDI

DSP_TCK

DSP_TCK

DSP_TDO

DSP_TDO

DSP_EMU

DSP_EMU

DSP_TRST

DSP_TRST

DA_SOFT_RESET

SPI0_SCK

SPI0_SCK

PG

PG

http://www.analog.com

Engineer to Engineer Note EE-68 which can be found at

When designing your JTAG interface please refer to the

All USB interface circuitry is considered proprietary and has

been omitted from this schematic.

"JTAG"

16 Mb SPI FLASHBOOT MODEPOSITION

2

3

4

5

6

7

1

0 Idle-No Boot

Boot through SPI0 master from SPI memory

Boot through SPI0 slave from host device

Boot through PPI from host

Reserved

Boot thorugh UART0 slave from host device

Default

"BOOT MODE"

"SPI FLASH CS ENABLE"

SW2: Boot Mode Select Switch

Boot from internal parallel flash in async mode

Boot from internal parallel flash in sync mode

080510UFC33 C25

0.01UF0402 0402

0.01UFC26 C27

0.01UF0402

C280.01UF0402 0402

0.01UFC29

04020.01UFC30

04020.1UFC31

04020.1UFC32

10UF0805

C21

04020.1UFC22

04020.1UFC23

04020.1UFC24

080510UFC7

080510UFC13

C60.1UF0402

C50.1UF0402

C40.1UF0402

C200.1UF0402 0402

0.01UFC14

04020.01UFC16C15

0.01UF04020402

0.01UFC8

C120.1UF0402

C110.1UF0402

C100.1UF0402

C90.1UF0402 0402

0.01UFC18 C17

0.01UF0402 0402

0.01UFC19

DSP POWER, BYPASS CAPS

10317-12-2009_16:20

D

4

3

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1

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Title

Size Board No.

Date Sheet of

DEVICESANALOG

RevA0226-2009


1.0

U7


69

62

59

117

65

61

53

52

42

24

63

25

51

41

30

26

23

20

15

6

1

121

109

108

17

13

64

66

67

112

116VDDEXT16

VDDEXT15

VDDEXT14

VDDEXT13

VDDEXT12

GND1

GND2

GND3

GND4

GND5

VDDEXT1

VDDEXT2

VDDEXT3

VDDEXT4

VDDEXT5

VDDEXT6

VDDEXT7

VDDEXT8

VDDEXT9

VDDFLASH1

VDDFLASH2

VDDINT1

VDDINT2

VDDINT3

VDDINT4

VDDINT5

VDDINT6

VDDINT7

VDDEXT10

VDDEXT11

VDDFLASH3

VDDFLASH

VDDFLASH

VDDEXT

VDDEXT

VDDEXT

VDDINTVDDINT

U14

AD8022MSOP8

5

7

6

04020.1UFC43 C44

0.1UF0402 0402

0.1UFC45 C46

0.1UF04020402

0.1UFC47C48

0.1UF04020402

0.1UFC40 C41

0.1UF0402

C390.1UF04020402

0.1UFC38

AGND

060310R24

04020R25

R2600402

04020R21

R2200402

R23100603

AGND

080510PFC68

060310R68

AGNDAGND

R54100603

C5910PF0805

R5500402

04020R56

AGND

060310R57

080510PFC61

04020R58

R5900402

04020R60

R6100402

C6410PF0805

R62100603

AGND

04020R64

080510PFC66

060310R65

AGND

R48100603

C5510PF0805

R4900402

AGND

060310R51

080510PFC57

04020R52

R5300402

R4600402

C5410PF0805

R47100603

AGND

04020R43

080510PFC52

060310R44

AGND

AGND

R41100603

C4910PF0805

R3900402

04020R40

080510PFC51

C5310PF0805

C6010PF0805

080510PFC62

C5610PF0805

080510PFC58

080510PFC65

C6310PF0805

C5010PF0805

080510PFC67

C6910PF0805

080510PFC36

C370.1UF0402

U10

AD8022MSOP8

5

7

6

MSOP8AD8022

U113

1

2

U11

AD8022MSOP8

5

7

6

U12

AD8022MSOP8

5

7

6

MSOP8AD8022

U133

1

2

U13

AD8022MSOP8

5

7

6

MSOP8AD8022

U123

1

2

AGND

080510PFC35

C3410PF0805

04020R67

AGND AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

R4200402

04020.1UFC42

04020R45

04020R50

R6300402

R6600402

R2710K0402

R2810K0402

R2910K0402

R3010K0402

R3410K0402

R3310K0402

R3210K0402

R3110K0402

R3610K0402

R3510K0402

R3810K0402

R3710K0402

AGND

ADC BUFFERS

4 1017-12-2009_16:20

D

4

3

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A B C

20 Cotton Road

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Title

Size Board No.

Date Sheet of

DEVICESANALOG

RevA0226-2009


1.0

U9

AD8022MSOP8

3

1

2

MSOP8AD8022

U95

7

6

MSOP8AD8022

U143

1

2

MSOP8AD8022

U103

1

2

IN_VB1

IN_VB2

VA1

IN_VA1

VB1

VB2

VA2

IN_VA2

VA6

VB6

VB3

VB4

VB5

+AVCC -AVCC

VA5

IN_VA3

IN_VB3

IN_VB4

IN_VA4

IN_VA5

IN_VA6

IN_VB6

IN_VB5

VA3

VA4

SJ8

JUMPERSHORTING

R7100805

AGND

3.3V

040210KR70

SW9

DIP6SWT017

9

8

76

5

4

3

2

12

11

10

1 12

45

6

ON

3

3.3V

C760.47UF0805

AGND

08050.47UFC77

3300805

FER1

C700.1UF0402

C7110UF08050402

0.1UFC72

080510UFC73C74

10UF0805

AGND

C750.1UF0402

SW10

DIP6SWT017

9

8

76

5

4

3

2

12

11

10

1 12

45

6

ON

3

040210KR69

AGND

SWT018DIP4

SW48

7

6

54

1

3

2

ON1

23

4

3.3V

3.3VAGND

ADC

D

4

3

2

1

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Title

Size Board No.

Date Sheet of

DEVICESANALOG

RevA0226-2009


1.0

JP2

IDC3X1

3

2

1

3.3V

DEFAULT=2 & 3

SJ2

JUMPERSHORTING

U7


9910

610

7

87

88

89

90

91

92

86

85

84

83

81

80

96

102

75

95

103

105

10474

94

77

101

76

1229382797873

97

98

100A0

A1

A2

AG

ND

1A

GN

D2

AG

ND

3A

GN

D4

AG

ND

5

AG

ND

7

AV

DD

CS

DCAPA

DCAPB

DG

ND

1D

GN

D2

DOUTA

DOUTB

RANGE

REF_SELECT

SCLK

SGL/DIFF

VA1

VA2

VA3

VA4

VA5

VA6

VB1

VB2

VB3

VB4

VB5

VB6

VD

DV

DR

IVE

AG

ND

6

P7

IDC12X2

9

87

65

43

2423

2221

20

2

19

1817

1615

1413

1211

10

1

VR5

AD780SOIC8

5

62

4

8 3TEMPOP_SEL

GND

VIN VOUT

TRIM

C1230.1UF0402

C12410UF0805

AGND

04020.1UFC125

JP6

IDC3X2_SMT

65

43

21

SJ7

JUMPERSHORTING

PS_5V

PS_5V

PS_5V

ACM_SGLDIFF/SD_D3

ACM_RANGE/SD_D2

ADC_DOUTB/SD_D1

ADC_DOUTA/SD_D0

ACM_A0

ACM_A1

ACM_A2

ADC_SCLK/SD_CLK

ADC_CS/SD_CMD

IN_VB1

IN_VB1 IN_VB2

IN_VB2

VA1

IN_VA1

IN_VA1

VB1

VB2

VA2

IN_VA2

IN_VA2

VA6

VB6

VB3

VB4

VB5

VA5

IN_VA3

IN_VA3

IN_VB3

IN_VB3 IN_VB4

IN_VB4

IN_VA4

IN_VA4

IN_VA5

IN_VA5 IN_VA6

IN_VA6

IN_VB6

IN_VB6

IN_VB5

IN_VB5 VA3

VA4

AVDD_ADC

"ADC INPUTS"

"VOLTAGE REFERENCE SELECT"

SW4 disconnects the DSP from the ADC

"ADC ENABLE"

"EXT VREF"

"ADC LOOPBACK"

SW9 & 10 are only used for POST

DEFAULT=NOT INSTALLED

DEFAULT=NOT INSTALLED

17-12-2009_16:20 5 10

3.3V

3.3V

3.3V

R7210K0402

R73

040210K

C78100PF0603 0603

62.0R74 R75

100603

06034700PFC79

R7662.00603 0603

10R77

C80100PF0603

J2

CON039

4

3

2

1

04020.01UFC81 C82

0.01UF0402

060310KR78

DNP

U19

SOIC14TJA1041

14 9

5 3 10

1

114

7

2

8

6

12

13CANH

CANL

EN

ERR

GN

D

INH

RXD SPLIT

TXD

VB

AT

VD

D

VIO

WAKESTB

CAN

D

4

3

2

1

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Title

Size Board No.

Date Sheet of

DEVICESANALOG

RevA0226-2009


1.0

SW5

SWT018DIP4

8

7

6

54

1

3

2

ON1

23

4

PS_5V

PS_5V

CAN_TX

CAN_RX

CAN_ERR

"CAN"

SW5 disconnects the DSP from the CAN IC

"CAN ENABLE"

17-12-2009_16:20 6 10

C1220.01UF0402

3.3V

3.3V

040210KR98R99

10K0402

3.3V

04020.1UFC89

04020.1UFC90

U16

SOIC16ADM3202ARNZ

6

2

710

1411

9 8

12 13

5

4

3

1C1+

C1-

C2+

C2-

R1INR1OUT

R2INR2OUT

T1IN T1OUT

T2IN T2OUT

V+

V-

3.3V

J1

CON038

9

8

7

6

5

4

3

2

1

04020.1UFC92

3.3V0805100R92

1000805

R94

MOMENTARYSWT024

SW8

0603330R84

0603330R85R86

3300603

R873300603

3.3V

04020.01UFC86

R90

040210K

GREENLED001

LED5

3.3V

C850.01UF0402

R82

040210K

3.3V

LED001REDLED1

10K0402

R79

04020.01UFC83

3.3V

R89

040210K

R88

040210K

74LVC14A

U1

SOIC14

65

R83

040210K

YELLOWLED001

LED4

LED001YELLOWLED3

YELLOWLED001

LED2

SWT024MOMENTARYSW7

SW3

DIP2SWT020

3

4

2

1 12

ON

R81

040210K

SOIC14

U1

74LVC14A

89

74LVC14A

U1

SOIC14

1011

SOIC14

U1

74LVC14A

1213

3.3V

RESET, LEDS, PUSH BUTTONS, UART, SD

7 1017-12-2009_16:20

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Title

Size Board No.

Date Sheet of

DEVICESANALOG

RevA0226-2009


1.0

3.3V

10K0402

R91

10K0402

R95

1UF0805

C87

C88

08051UF

0603330R80

C930.01UF0402 0805

10UFC121

R10110K0402 0402

10KR108

J3

CON067

14

15

194

16

24

23

22

17

20

2827211863

13

12

11

10

1

9

8

7

2

5 CLK

CMD

DAT0

DAT1

DAT2

DAT3

DAT4

DAT5

DAT6

DAT7

GN

D1

GN

D2

GN

D3

GN

D4

GN

D5

GN

D6

MINI_SD_CLK

MINI_SD_CMD

MINI_SD_DAT0

MINI_SD_DAT1

MINI_SD_DAT2

MINI_SD_DAT3

VD

D1

VD

D2

CD

WP

SSOP20

U5

IDT74FCT3244APY

19

1

3

5

7

9

17

15

13

11

12

14

16

18

8

6

4

21A1

1A2

1A3

1A4

1Y1

1Y2

1Y3

1Y4

2A1

2A2

2A3

2A4

2Y1

2Y2

2Y3

2Y4

OE1

OE2

SOIC8

U17

ADM708SARZ

7

5

1 8

4PFI

RESETMR

PFO

RESET

SWT024MOMENTARYSW6

SOIC14

U1

74LVC14A

43

SOIC14

U1

74LVC14A

21

SOT23-5

U18

SN74LVC1G08

42

1

SN74LVC1G08

U20

SOT23-5

42

1

04020.01UFC84

3.3V

SW1

DIP8SWT016

9

10

11

12

13

14

15

16

4

5

6

3

7

2

1

8 81

24

56

7

ON

3

0.1UF0402

C91

R13710K0402

040233R136

RNS00333

RN1

98

107

116

125

134

143

152

161R1A R1B

R2A R2B

R3A R3B

R4A R4B

R5A R5B

R6A R6B

R7A R7B

R8A R8B

R135 330402

040210KR134

040210KR100

R142 330402

040233R141

UART0_CTS/SD_D7

UART0_CTS/SD_D7

UART0_RTS/SD_D6

UART0_RTS/SD_D6

UART0_TX/SD_D5

UART0_TX/SD_D5

UART0_RX/SD_D4

UART0_RX/SD_D4

ACM_SGLDIFF/SD_D3

ACM_RANGE/SD_D2

ADC_DOUTB/SD_D1

ADC_DOUTA/SD_D0

LED0

LED1

LED2

PB0

PB1

RESET

ADC_SCLK/SD_CLK

ADC_CS/SD_CMD

SD_CD

SD_WP

DA_SOFT_RESET

CTS

CTS

"DCE"

"UART0 SETUP"

"PB2"

"PB1"

"POWER"

"RESET"

"PB ENABLE"

"RESET"

"SD CARD"

(UART 0)

3.3V 3.3V 3.3V

P5

DMAX_ALTDNP

B1

A27

A24

A21

A18

A15

A12

A9

B25

B22

B19

B16

B13

B10

B7

B4

A6

A3

B9

B8

B6

B5A5

A4

B27

B26

B3

A26

A25

B24

B23A23

A22

A20

A19

B18

B17

B2

A17

A16

B15

B14A14

A13

B12

B11A11

A10

A2

A1

B20

B21

A8

A7CLK1+

CLK1-

CLK2+

CLK2-

D0

D1

D10

D11 D12

D13

D14

D15 D16

D17

D18

D19

D2

D20

D21

D22

D23

D24

D25 D26

D27

D28

D29

D3

D30

D31

D4

D5 D6

D7

D8

D9

GND0

GND1

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

DMAX_ALT

P6

DNP

B1

A27

A24

A21

A18

A15

A12

A9

B25

B22

B19

B16

B13

B10

B7

B4

A6

A3

B9

B8

B6

B5A5

A4

B27

B26

B3

A26

A25

B24

B23A23

A22

A20

A19

B18

B17

B2

A17

A16

B15

B14A14

A13

B12

B11A11

A10

A2

A1

B20

B21

A8

A7CLK1+

CLK1-

CLK2+

CLK2-

D0

D1

D10

D11 D12

D13

D14

D15 D16

D17

D18

D19

D2

D20

D21

D22

D23

D24

D25 D26

D27

D28

D29

D3

D30

D31

D4

D5 D6

D7

D8

D9

GND0

GND1

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

EXPANSION INTERFACE, DMAX

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Title

Size Board No.

Date Sheet of

DEVICESANALOG

RevA0226-2009


1.0

IDC35X2_SMTA

P3

63

59

57

53

55

49

62

8

12

109

2

37

51

47

45

43

41

39

56

50

48

46

44

40

38

52

60

58

54

42

15

1413

25 26

23 24

21 22

19 20

33 34

31 32

29 30

27 28

17

16

18

6

4

7

5

3

1

3635

11

69

66

6867

64

61

65

70RSVD7

RSVD2

SDA

RSVD1

RSVD4 RSVD5

RSVD3

RSVD6

GND6

TIMER2/GPIO TIMER1/GPIO

GND1

GND2

GND3

GND4

PWR_IN2

VDDIO1

PPI0D0

PPI0CLK

PPI0D1

PPI0D10PPI0D11

PPI0D12PPI0D13

PPI0D14PPI0D15

PPI0D16PPI0D17

PPI0D2PPI0D3

PPI0D4PPI0D5

PPI0D6PPI0D7

PPI0D8PPI0D9

PPI0FS1 PPI0FS2

PPI0FS3

PPI1CLK

PPI1D10

PPI1D14

PPI1D16

PPI1D8

TIMER3/GPIO

PPI1FS2

PP1D0/PPI0D18

PPI1D2/PPI0D20

PPI1D4/PPI0D22

PPI1D6

PPI1D12

PPI1FS1

PPI1FS3

PPI1D1/PPI0D19

PPI1D3/PPI0D21

PPI1D5/PPI0D23

PPI1D9

RESET

PWR_IN1

GND5 3.3V1

3.3V2

VDDIO2

NC

PPI1D7

PPI1D13

PPI1D11

PPI1D15

PPI1D17

SCL

IDC25X2_SMTA

P2

47

45

43

41

39

37

35

33

31

29

27

25

15

17

13

24

22

49 50

8

6

4

2

32

34

28

19

26

23

21

30

48

46

44

42

18

20

36

40

38

11

9

7

5

3

1

16

14

12

103.3V1

3.3V2

DRPRI

DRSEC

GND1

GND2

GND3

GND4

GND5

GND6

GPIO2

GPIO4

NC

RFS

RSCLK

RSVD1

RSVD3

RSVD5

RSVD7

SDA

SPISEL1

SPISEL3

SPISS

TFS

TIMER

UARTCTS

UARTRX

PWR_IN1

PWR_IN2

VDDIO1

VDDIO2

RSVD9RSVD8

SPISEL2

SPICLK

DTPRI

TSCLK

DTSEC

SPIMOSI

SPIMISO

SCL

UARTTX

UARTRTS

RESET

GPIO1

GPIO3

WAKE

RSVD2

RSVD4

RSVD6

P4

IDC25X2_SMTADNP

47

45

43

41

39

37

35

33

31

29

27

25

15

17

13

24

22

49 50

8

6

4

2

32

34

28

19

26

23

21

30

48

46

44

42

18

20

36

40

38

11

9

7

5

3

1

16

14

12

103.3V1

3.3V2

DRPRI

DRSEC

GND1

GND2

GND3

GND4

GND5

GND6

GPIO2

GPIO4

NC

RFS

RSCLK

RSVD1

RSVD3

RSVD5

RSVD7

SDA

SPISEL1

SPISEL3

SPISS

TFS

TIMER

UARTCTS

UARTRX

PWR_IN1

PWR_IN2

VDDIO1

VDDIO2

RSVD9RSVD8

SPISEL2

SPICLK

DTPRI

TSCLK

DTSEC

SPIMOSI

SPIMISO

SCL

UARTTX

UARTRTS

RESET

GPIO1

GPIO3

WAKE

RSVD2

RSVD4

RSVD6

PS_5VPS_5V PS_5V

SDA

SDA

SDASDA

SCL

SCL

SCLSCL

EXT_WAKEEXT_WAKE

UART0_CTS/SD_D7

UART0_CTS/SD_D7

UART0_CTS/SD_D7

UART0_RTS/SD_D6

UART0_RTS/SD_D6

UART0_RTS/SD_D6UART0_RTS/SD_D6

UART0_RTS/SD_D6

UART0_TX/SD_D5

UART0_TX/SD_D5

UART0_TX/SD_D5

UART0_RX/SD_D4

UART0_RX/SD_D4

UART0_RX/SD_D4

ACM_SGLDIFF/SD_D3

ACM_SGLDIFF/SD_D3

ACM_RANGE/SD_D2

ACM_RANGE/SD_D2

ADC_DOUTB/SD_D1

ADC_DOUTB/SD_D1

ADC_DOUTB/SD_D1

ADC_DOUTA/SD_D0

ADC_DOUTA/SD_D0

ADC_DOUTA/SD_D0

LED0

LED0

LED0LED0

LED0

LED1

LED1

LED1

LED1

LED1

LED2

LED2

LED2

PB0

PB0

PB0

PB1

PB1

PB1

PF5

PF5

PF5

PF6

PF6

PF6

PF7

PF7

PF7

PF8

PF8

PF8

PF8

PF9

PF9

PF9

PF9

SPI0_MISO

SPI0_MISO

SPI0_MISO

SPI0_MOSI

SPI0_MOSI

SPI0_MOSI

SPI0_SEL1

SPI0_SEL1

SPI0_SEL1

SPI0_SEL1

PF14

PF14

PF14

PF15

PF15

PF15

RESET

RESET RESETRESET

ACM_A0

ACM_A0

ACM_A1

ACM_A1

ACM_A2

ACM_A2

ADC_SCLK/SD_CLK

ADC_SCLK/SD_CLK

ADC_SCLK/SD_CLK

ADC_CS/SD_CMD

ADC_CS/SD_CMD

ADC_CS/SD_CMD

SD_CD

SD_CD

SD_CD

SD_CD

SD_CD

SD_CD

SD_WP

SD_WP

SD_WP

SD_WP

SD_WP

PG3

PG3

PG3

CAN_TX

CAN_TX

CAN_TX

CAN_RX

CAN_RX

CAN_RX

CAN_ERR

CAN_ERR

CAN_ERR

SPI0_SCK

SPI0_SCK

SPI0_SCK

SPORT1

SPI0

UART1

SPORT0

SPI1

UART0

PWM1

C10100805

VR2

MSOP8ADP1613

6

3

5

8

7

4

2

1COMP

FB

GND

FREQ

SS

SW

EN

VIN

27.4K0603

R115

R114

0402100K

C104

06031000PF

SOD-123FLMBR130LSFT1GD5

00603

R111

DNP

00603

R110

22000PF0402

C9406031UFC96 C105

1UF0603DNP 20.0K

0402

R109

3300PF0603

C95

08052.2UFC103

C9810UF1210 1210

10UFC97

121010UFC100

C10210UF1210

1UHIND019

L1

DNP

L522UHIND024

43

21

R112

06034.99K

100603

R113

L422UHIND024

43

21

D4MBR130LSFT1GSOD-123FL

DUAL POWER REGULATOR

9 1017-12-2009_16:20

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Title

Size Board No.

Date Sheet of

DEVICESANALOG

RevA0226-2009


1.0

C9910UF1210

L2

IND0191UH

PS_5V

+AVCC

-AVCC

U6

MIC2025-1SOIC8

1

3

8

67

2FLG

IN1 OUT1

OUT2

GND

EN

DA_5V

IDC2X1

JP521

IDC2X1

JP421

JP3

IDC2X1

21

TP2

TP7

12060.05R131

3.3V

C1180.1UF04020805

2.2UFC119 C120

2.2UF0805

TP8

DEFAULT=INSTALLLED

SJ6

JUMPERSHORTING

D10SK12DO-214AA

D9ESD5Z2.5T1

SOD-523

MH5

0.125

MH6

0.125

MH7

0.125

1000PF1206

C116

1000PF1206

C115

SHGND

1206

FER3600

FER2

1206600

SHGND

R12324.9K0603

C111470PF0603

C11268PF0603

R12480.6K0603

R1260.051206

PGND

PGND

08054.7UFC113

D2E220UFCT1

U3

SI4411DYSO-8

5

6

7

8

1

2

3

4

IND0132.5UHL3

C11410UF1210

R127255.0K0603

VR1

ADP1864AUJZSOT23-6

2

1

3 6

4

5IN

CS

PGATEFB

COMP

GND

PGND

TP3

12060.05R121

12064.3R116

C1064.7UF0603

C1074.7UF0603

C1080.01UF0402

C1090.1UF0402

04021.2KR117

R1182.67K0402

R1194.31206

06034.7UFC110

R1201.0K0402

VR3

ADP1715MSOP8

6

5

4

3

2

1

8

7GND3

GND4

EN

IN

OUT

ADJ

GND1

GND2

FER4

FER002190

2

3

1

4

R13000402

12060.05R125

C11710UF1210D7

5AMBRS540T3G

SMC

D1VESD01-02V-GS08

SOD-523 DO-214AASK12D8

3.3V

TP5

D2GSOT05SOT23-3

R1220.051206

SJ4

DEFAULT=INSTALLLEDJUMPERSHORTING

D3GSOT03SOT23-3

D6MBRS540T3GSMC

2A

W1COPPER

10K0402

R129

DNP

R128

040210K

PGND

10K0402

R133

TP4

TP6

SJ3

DEFAULT=INSTALLEDJUMPERSHORTING

VR4

ADP1715MSOP8

4

2

5

31

6 7 8 GN

D4

GN

D3

GN

D2

EN OUT

GN

D1

IN

SS

POWER

1017-12-2009_16:20 10

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Title

Size Board No.

Date Sheet of

DEVICESANALOG

RevA0226-2009


1.0

F1

FUS0043A

DEFAULT=INSTALLLED

SJ5

JUMPERSHORTING

3.3V

P9

CON045

2

3

1

POWER

U2

MSOP10AD5258

1

6

8

4

5

7

9

3

2

10A

AD0

AD1

B

GND

SCL

SDA

VCC

VLOGIC

W

MH8

0.125

MH10.156

MH20.156

MH30.156

MH40.156

VDDFLASH

PS_5V

PS_5V

PS_5V

SDA

SCL

VDDEXT

VDDINT

EXT_WAKE

DA_USB_PWR

EXT_PS

1.8V @ 500mA"VDDFLASH"

3.3V @ 2A

"5V"

1.1 - 1.4V @ 500mA

"VDDINT"

"VDDEXT"

Remove JP3 when measuring VDDEXT

Remove JP5 when measuring VDDFLASH

Remove JP4 when measuring VDDINT

ADSP-BF506F EZ-KIT Lite Evaluation System Manual I-1

I INDEX

AADC enable switch (SW4), 2-9ADC input connector (P7), 2-19ADC loopback switches (SW9-10), 2-10ADC voltage ref (JP6), 2-13architecture, of this EZ-KIT Lite, 2-2audio

codec enable switch (SW4), 2-9input connector (P7), 2-19loopback switches (SW9-10), 2-10

Bbill of materials, A-1board design database, 1-18board schematic (ADSP-BF506F), B-1boot

modes, 2-8mode select switch (SW2), 2-8

CCAN interface

connector (J2), 2-17enable switch (SW5), 2-9

clock in (CLK IN) signal, 2-3configuration, of this EZ-KIT Lite, 1-3

connectorsdiagram of locations, 2-16J1 (RS-232), 2-17J2 (CAN), 2-17J3 (SD), 2-17P1 (JTAG), 1-8, 1-15, 2-17P2 (expansion), 2-18P3 (expansion), 2-18P4 (expansion), 2-18P5-6 (land grid array), 2-19P7 (ADC input), 2-19P9 (power), 1-8, 2-19

contents, of this EZ-KIT Lite package, 1-2

Ddefault configuration, of this EZ-KIT Lite, 1-3DIP switch (SW3), 2-9, 2-10DMAX land grid array connectors (P5-6), 2-19

Eevaluation license

CCES, 1-10example programs, 1-18expansion interface, 1-15, 2-18external memory, 1-13

Fflag pins, See programmable flags by name (PFx,

PGx, and PHx)

Index

I-2 ADSP-BF506F EZ-KIT Lite Evaluation System Manual

Ggeneral-purpose IO pins (GPIO), 1-14, 2-9,

2-15general-purpose push buttons (PB0-1), 1-14

Iinstallation, of this EZ-KIT Lite, 1-3

CCES, 1-3internal flash memory interface, 1-13IO voltage, 2-2

JJTAG

interface, 1-15connector (P1), 1-8, 1-15, 2-17

jumpersdiagram of locations, 2-11JP1 (SPI flash enable), 2-11JP2 (voltage reference select), 2-12JP3 (VDDEXT power), 2-12JP4 (VDDINT power), 2-12JP5 (VDDFLASH power), 2-12JP6 (ADC voltage ref), 2-13

LLEDs

diagram of locations, 2-14LED1 (reset), 2-15LED2-4 (PF0-2), 1-14, 2-15LED5 (power), 2-15LED8 (reset), 2-15

license restrictions, 1-11

MMedia Instruction Set Computing (MISC), ixmemory map, of this EZ-KIT Lite, 1-12Micro Signal Architecture (MSA), ix

Nnotation conventions, xviii

Ppackage contents, 1-2PF0-2 (IO) signals, 2-3, 2-15PF3-15 signals, 2-3PG0-15 signals, 2-4PH0-2 signals, 2-6power

connector (P9), 1-8, 2-19LED (LED5), 2-15measurements, 1-17

power-on-self test (POST), 1-14product information, xviprogrammable flag (PF)

inputs PF3-4, 1-14push buttons (SW7-8), 2-9

RReduced Instruction Set Computing (RISC), ixreset

LEDs (LED1), 2-15push button (SW6), 2-9

RS-232 connector (J1), 2-17

Sschematic, of ADSP-BF506F EZ-KIT Lite, B-1SD connector (J3), 2-17SPI flash memory

interface, 1-13CS enable jumper (JP1), 2-11

SRAM memory, 1-12See also memory map

startup, of this EZ-KIT LiteCCES, 1-3

SW1 (UART setup) switch, 2-8SW2 (boot mode select) switch, 2-8

ADSP-BF506F EZ-KIT Lite Evaluation System Manual I-3

Index

SW3 (push button enable) DIP switch, 1-14, 2-9, 2-10

SW4 (ADC enable) switch, 2-9SW5 (CAN enable) switch, 2-9SW6 (reset) push button, 2-9SW9-10 (ADC) loopback switches, 2-10switches, diagram of locations, 2-7system architecture, of this EZ-KIT Lite, 2-2

Ttechnical support, xv

UUART setup switch (SW1), 2-8

VVDDEXT, 1-17

pin, 1-17power jumper (JP3), 2-12

VDDFLASH, 1-17pin, 1-17power jumper (JP5), 2-12

VDDINpin, 1-17

VDDINTpower jumper (JP4), 2-12programmable regulator, 1-16

very-long instruction word (VLIW), ixVisualDSP++ environment, 1-9voltage

reference select jumper (JP2), 2-12values, 1-17

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