adns-9500

ADNS-9500LaserStream Gaming Sensor

Data Sheet

DescriptionThe ADNS-9500 LaserStream gaming sensor comprises of sensor and VCSEL in a single chip-on-board (COB) package. ADNS-9500 provides enhanced features like programmable frame rate, programmable resolution, congurable sleep and wake up time to suit various PC gamers preferences. The advanced class of VCSEL was engineered by Avago Technologies to provide a laser diode with a single longitudinal and a single transverse mode. This LaserStream gaming sensor is in 16-pin integrated chip-on-board (COB) package. It is designed to be used with ADNS-6190-002 small form factor (SFF) gaming laser lens to achieve the optimum performance featured in this document. These parts provide a complete and compact navigation system without moving part and laser calibration process is NOT required in the complete mouse form, thus facilitating high volume assembly.

Featuresx Small form factor chip-on-board package x Dual power supply selections, 3V or 5V x VDDIO range: 1.65 3.3V x 16-bits motion data registers x High speed motion detection at 150ips and acceleration up to 30g x Advanced technology 832-865nm wavelength VCSEL x Single mode lasing x No laser power calibration needed x Compliance to IEC/EN 60825-1 Eye Safety Class 1 laser power output level On-chip laser fault detect circuitry x Self-adjusting frame rate for optimum performance x Motion detect pin output x Internal oscillator no external clock input needed x Enhanced Programmability Frame rate up to 11,750 fps 1 to 5 mm lift detection Resolution up to 5000cpi with ~90cpi step X and Y axes independent resolution setting Register enabled Rest Modes Sleep and wake up times

Theory of OperationThe sensor is based on LaserStream technology, which measures changes in position by optically acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of movement. It contains an Image Acquisition System (IAS), a Digital Signal Processor (DSP), and a four wire serial port. The IAS acquires microscopic surface images via the lens and illumination system. These images are processed by the DSP to determine the direction and distance of motion. The DSP calculates the 'x and 'y relative displacement values. An external microcontroller reads the 'x and 'y information from the sensor serial port. The microcontroller then translates the data into PS2, USB, or RF signals before sending them to the host PC or game console.

Applicationsx Corded and cordless gaming laser mice x Optical trackballs x Motion input devices

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

Pinout of ADNS-9500 Optical Mouse SensorPin No1 2 3 4 5 6 7 8 9 10

Pin Name for 5V mode+VCSEL LASER_NEN NCS MISO SCLK MOSI MOTION XYLASER VDD5 PWR_OPT (GND)

Pin Name for 3V mode+VCSEL LASER_NEN NCS MISO SCLK MOSI MOTION XYLASER VDD3 PWR_OPT (VDD3)

DescriptionPositive Terminal Of VCSEL LASER Enable (Active Low Output) Chip Select (Active Low Input) Serial Data Output (Master In/Slave Out) Serial Clock Input Serial Data Input (Master Out/Slave In) Motion Detect (Active Low Output) Laser Current Output Control 5V input for 5V mode 3V Input for 3V mode Power Option: Connect to GND for 5V Mode Connect to VDD3 for 3V Mode Analog Ground 3V Regulator Output for 5V Mode 3V Input for 3V Mode 1.8V Regulator Output Digital Ground IO Voltage Input (1.65 - 3.3V) Negative Terminal Of VCSEL

11 12 13 14 15 16

GND REFB REFA DGND VDDIO -VCSEL

GND VDD3 REFA DGND VDDIO -VCSEL

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

W = Subcon Code XXYY = Date Code Z = Sensor Die Source V = VCSEL Die Source Figure 1. Package Pinout

2

15.60 0.20

Pin 1Notes: 1. Dimensions in millimeter 2. Dimension tolerance 0.1mm unless specied otherwise 3. Coplanarity of leads: 0.15mm 4. Lead pitch tolerance: 0.15mm 5. Non-cumulative lead pitch tolerance 0.15mm 6. Maximum ash +0.2mm 7. Lead width: 0.5mm 8. Bracket ( ) indicates reference dimensions

14.40 0.20

6.55

10.29

TOP VIEW

15.60 0.80

5.15 16 X 0.50

3.70

FRONT VIEW

RIGHT VIEW

(7.20) 1.78

8.00 2.95 (6.30) 2.55 3.68 (1.57) 0.70 13.45 1.23

SECTION A - A

BOTTOM VIEWFigure 2. Package outline drawing

3

Overview of Laser Mouse Sensor Assembly

A

A

TOP

FRONT

RIGHT

Bottom of lens ange to Surface 2.40 Top of PCB to Surface 7.40 SECTION A-ANote: Dimensions in millimeter and for reference only

Top of Sensor to Surface 10.75

Figure 3. 2D Assembly drawing of ADNS-9500 sensor and ADNS-6190-002 lens coupled with PCB and base plate

4

Figure 4. Isometric drawing of ADNS-9500 sensor and ADNS-6190-002 lens

5.02 12.96 0.50

Pin #1

6.30 10.90 12.60

14 X 1.78

16 X n0.80

Optical Center Figure 5. Recommended PCB mechanical cutouts and spacing

Assembly Recommendation1. Insert the COB sensor and all other electrical components into the application PCB. 2. Wave-solder the entire assembly in a no-wash soldering process utilizing a solder xture. The solder xture is needed to protect the sensor during the solder process. The xture should be designed to expose the sensor leads to solder while shielding the optical aperture from direct solder contact. 3. Place the lens onto the base plate. Care must be taken to avoid contamination on the optical surfaces. 4. Remove the protective kapton tapes from the optical aperture of the sensor and VCSEL respectively. Care must be taken to keep contaminants from entering the aperture. 5. Insert the PCB assembly over the lens onto the base plate. The sensor package should self-align to the lens. The optical position reference for the PCB is set by the base plate and lens. The alignment guide post of the lens locks the lens and integrated molded lead-frame DIP sensor together. Note that the PCB motion due to button presses must be minimized to maintain optical alignment. 6. Optional: The lens can be permanently locked to the sensor package by melting the lens guide posts over the sensor with heat staking process. 7. Install the mouse top case. There must be a feature in the top case (or other area) to press down onto the sensor to ensure the sensor and lenses are interlocked to the correct vertical height.

5

100k2

0R C9 100nF U3VDD1

Application Circuits

H16

C2 10nF C10 C7 1uF/10V 4.7uF/10V C15 470pF3 2

C8 100nF

25LC040P

3

VDD

DGND

GND

C3 20pFPWR_OPT 10 11 12 P2.7 P2.6 14

C11 20pF D1 R12 470R YELLOW D2 R13 470R YELLOW D3 R14 470R YELLOW C17 10uF/10V C18VDD2 11 VCC

2

C8051F347

GND

3

6VDD VDD2 VDD 1 VDD1

R11 R15 0R1

J22

Q2

C13 10nF

C14 1uF/10V

U2

1 VCC1 VDD

J1CS SCK SI SO VCC WP HOLD VSS

2

VCC

R2 NTA4151P

1 6 5 2

8 3 7 4

C12 100nF

VDD1VDD2

VDD2J3

R W G B

VBUS DD+ GND SHIELD

1 2 3 4 5

R3 R4 U1VCSEL+VE VCSEL-VE XYLASER VDDIO VDD3 / VDD5 1 16 8 15 9

20R 20R

EEPROM

1

HEADER 5VCC1 13 12 3

VCC1J4

VDD1VDD1 1

R5 0R

R6 0R

7 8 5 4 VREGIN VBUS DD+

C21 100nF

C20 3.3uF/16V

SCLK MISO MOSI NCS MOTION

SCLK MISO MOSI NCS MOTION

2 5 4 6 3 7 LASER_NEN SCLK MISO MOSI ADNS-9500 NCS REF A MOTION VDD3 / REF B

C16 100nF

C22 4.7uF/10V

9 10 C2CK/RST P3.0/C2D

P0.1/SCLK P0.2/MISO P0.3/MOSI P0.4/NCS P0.5 P0.6 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

1 32 31 30 29 28 26 25 24 23 22 21 20 19

ZB ZA LEFT RIGHT MIDDLE +CPI -CPI LED1

VDD

LED1 LED2 LED3 LED2

C19 100nF 100nF

C23 10uF/10V

1VCC

CON1 LED3P0.0 P0.7 2 27

R10 1k

1 3 5 7 9

2 4 6 8 10

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5

18 17 16 15 14 13

PIN HEADER 2.54MM10P/D

MCU

CPI Indication LED

Sensor Block

VDD

JTAG1CON2VDD

R1 1k +CPI 1 P1

R7 1k

+CPI -CPI VSS

LEFT 1 MIDDLE 3 ZB 5 RIGHT ZA -CPI 11

P2 P3

7

2 4 6 8

C4 1uF/10V PCB SOCKET 2MM8P/D

C5 100nF

8

1LEFT 1 MIDDLE 3 ZB 57

CON32 4 6 8

RIGHT ZA

VDD

+CPIVDD VDD VDD

PIN HEADER 2MM8P/D

8

SW4

3

1

+CPI

P4

1

+CPI

2

R8 10k LEFT SW1 C1 100nF1 2 3

R9 10k R IG H T SW21 3

R16 10k M ID D L E SW3 C6 100nF2 3

-CPI

P5

1

-CPI

VSS

P6

1

SW5

Z-EncoderC24 1 100nF2

Q1 ZB ZA3 2 1

3

1

2

COM B A

-CPI

Left Click

Right Click

Middle Click

Figure 6a. Schematic Diagram for 5V Corded Mouse

6

1

S W S LI DE-S P S TGND

1

VOUT FB VDD3 R2 820K VB AT

5 4

+

2

Note: 2 A A B attery 1.5v C onnec ted in s eries R4 0R R3 180K C 12 4.7uF/16V R6 60R41

-

B TI B AT TE R Y R5 Open VDD32

2

C6 4.7uF/16V C 13 4.7uF/16V C 14 10uF/16V

C7 4.7uF/16V

2

J102

3

MMB T 2222A C 16 100nF2

Q2 1 499R 2 J 13 1 R 11 1K R 10 1K C 15 100nF C 18 22nF C 17 100nF

R9

VDD3

VDD3 C 19 100nF C 20 100nF C 21 22onF EI ANT E NNA

L E FT C LIC K C E NTE R C LIC K S W4 2 D2 S W5 1 2 R es olution C hange P US H B UTT ON P 2_0 P 2_1 P 2_2 YE LLOW BLUE 2 10 28 29 30 DVV D DVV D DG UAR D DVV D DC OUP L D3 MOUS E _B UT TON 1 2 S W3 2 MOUS E _B UTT ON 1

R IG HT C L IC K

S W2

U4 T I C C 2510

1

1

MOUS E _B UT TON

AVDD AVDD AVDD AVDD

19 22 25 26 L4 1.2nH R F _P R F_N 23 24 C25 100pF L5 12nH 17 19 C26 1pF C 24 1.8pF C23 100pF C 22 1pF L6 1.2nH

2

1

1

2

C1 1 VDD3 J 12 J UMP E R _3 R 12 OR R 13 47K 3

C2

C 10 470pF 3 R7 27K R8 27K

2

7NO T E : R 2 = 8 20kohm V dd = 2. 8V R 2 = 910kohm Vdd = 3. 0V R 2 = 1 Mohm = 3. 3V

L E D I n d i c a ti o n T a b l e : I n di c a ti o n 1 0 0 0 c pi OFF OFF O N 3 s ec O N 3 s ec B li nkin g O n 1 s e c , Off 4 s e c B li nkin g O n 1 s e c , O F F 1 s e c OFF OFF O N 3 s ec OFF OFF 1 6 0 0 c pi( d efa ult) 3 2 0 0 c piVDD3

L E D1 ( Pl _0) O N 3 s ec

L E D 2 (P 1_1)

L1 4.7uH

6 0 0 0 c piJ4

L o w batter y ( 2 . 2 5 2. 3 5 V ) L o w batter y ( 120ns 120 Ps 15 Ps 15 Ps 10 Ps 160 Ps Soonest to read SROM_ID Figure 21. SROM Download Burst Mode SROM_Enable reg write address key data SROM_Load reg write byte 1 address enter burst mode

byte 2

byte 3070

address

18

Frame CaptureThis is a fast way to download a full array of pixel values from a single frame. This mode disables navigation and overwrites any downloaded rmware. A hardware reset is required to restore navigation, and the SROM rmware must be reloaded. To trigger the capture, write to the Frame_Capture register. The next available complete 1 frame image will be stored to memory. The data are retrieved by reading the Pixel_ Burst register once using the normal read method, after which the remaining bytes are clocked out by driving SCLK at the normal rate. If the Pixel_Burst register is read before the data is ready, it will return all zeros. Procedure of Frame Capture: 1. Reset the chip by writing 0x5a to Power_Up_Reset register (address 0x3a). 2. Enable laser by setting Forced_Disable bit (bit-0) of LASER_CTRL0 register to 0. 3. Write 0x93 to Frame_Capture register. 4. Write 0xc5 to Frame_Capture register. 5. Wait for two frames. 6. Check for rst pixel by reading bit zero of Motion register. If =1, rst pixel is available. 7. Continue read from Pixel_Burst register until all 900 pixels are transferred. 8. Continue step 3-7 to capture another frame.Note: Manual reset and SROM download are needed after frame capture to restore navigation for motion reading.

exit burst mode tBEXIT 4 Ps NCS 2 reg write to enter frame capture mode address data pixel dump reg read address enter burst mode SCLK tNCS-SCLK >120ns MISO Figure 22. Frame Capture Burst Mode Wait for 2 frames tSRAD tLOAD 15 Ps P2 soonest to begin again frame capture reg address 100 Ps

MOSI

P1

P900

19

Cable Top Xray View of Mouse

Positive Y LB RB Positive X 1 A9500 16

8

9

expanded view of the surface as viewed through the lens last output29 59 89 119 149 179 209 239 269 299 329 359 389 419 449 479 509 539 569 599 629 659 689 719 749 779 809 839 869 899 28 58 88 118 148 178 208 238 268 298 328 358 388 418 448 478 508 538 568 598 628 658 688 718 748 778 808 838 868 898 27 57 etc. 1 0 842 872

31 61 91 121 151 181 211 241 271 301 331 361 391 421 451 481 511 541 571 601 631 661 691 721 751 781 811 841 871 30 60 90 120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720 750 780 810 840 870

rst output Figure 23. Pixel Map (Surface referenced)

20

Power UpThe ADNS-9500 Sensor does not perform an internal power up self-reset; the Power_Up_Reset register must be written every time power is applied. The appropriate sequence is as follows: 1. Apply power to VDD5/VDD3 and VDDIO in any order 2. Drive NCS high, and then low to reset the SPI port. 3. Write 0x5a to Power_Up_Reset register (address 0x3a). 4. Wait for at least 50ms time. 5. Read from registers 0x02, 0x03, 0x04, 0x05 and 0x06 (or read these same 5 bytes from burst motion register) one time regardless of the motion pin state. 6. SROM download. 7. Enable laser by setting Forced_Disable bit (bit-0) of LASER_CTRL0 register (address 0x20) to 0. During power-up there will be a period of time after the power supply is high but before any clocks are available. The table below shows the state of the various pins during power-up and reset.

State of Signal Pins After VDD is ValidPinNCS MISO SCLK MOSI MOTION LASER_NEN

On Power-UpFunctional Undened Ignored Ignored Undened Undened

NCS High before ResetHi Undened Ignored Ignored Undened Undened

NCS Low before ResetLow Functional Functional Functional Undened Undened

After ResetFunctional Depends on NCS Depends on NCS Depends on NCS Functional Functional

ShutdownThe ADNS-9500 can be set in Shutdown mode by writing 0xb6 to register 0x3b. The SPI port should not be accessed when Shutdown mode is asserted, except the power-up command (writing 0x5a to register 0x3a). (Other ICs on the same SPI bus can be accessed, as long as the sensors NCS pin is not asserted.) The table below shows the state of various pins during shutdown. To deassert Shutdown mode: 1. Drive NCS high, then low to reset the SPI port. 2. Write 0x5a to Power_Up_Reset register (address 0x3a). 3. Wait for at least 50ms time. 4. Clear observation register. 5. Wait at least one frame and check observation register, Bit[5:0] must be set. 6. Read from registers 0x02, 0x03, 0x04, 0x05 and 0x06 (or read these same 5 bytes from burst motion register) one time regardless of the motion pin state. 7. SROM download. 8. Enable laser by setting Forced_Disable bit (bit-0) of LASER_CTRL0 register to 0. 9. Any register setting must then be reloaded. PinNCS MISO SCLK MOSI LASER_NEN MOTION

Status when Shutdown ModeFunctional *1 Undened *2 Ignore if NCS = 1 *3 Ignore if NCS = 1 *4 High (o ) Undened *2

*1 NCS pin must be held to 1 (high) if SPI bus is shared with other devices. It is recommended to hold to 1 (high) during Power Down unless powering up the Sensor. It must be held to 0 (low) if the sensor is to be re-powered up from shutdown (writing 0x5a to register 0x3a). *2 Depends on last state. MISO should be congured to drive LOW during shutdown to meet the low current consumption as specied in the datasheet. This can be achieved by reading Inverse_Product_ ID register (address 0x3f ) since the return value (0xcc) on MISO line ends in a 0 (low state). *3 SCLK is ignored, if NCS is 1 (high). It is functional if NCS is 0 (low). *4 MOSI is ignored, if NCS is 1 (high). If NCS is 0 (low), any command present on the MOSI pin will be ignored except power-up command (writing 0x5a to register 0x3a). Note: There are long wakeup times from shutdown and forced Rest. These features should not be used for power management during normal mouse motion.

21

RegistersThe ADNS-9500 registers are accessible via the serial port. The registers are used to read motion data and status as well as to set the device conguration. Address0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21- 0x23 0x24 0x25 0x26 0x27 - 0x29 0x2a 0x2e 0x2f 0x30 - 0x38 0x39 0x3a 0x3b 0x3c - 0x3e 0x3f 0x40 0x4f 0x50 0x62 0x64 22

RegisterProduct_ID Revision_ID Motion Delta_X_L Delta_X_H Delta_Y_L Delta_Y_H SQUAL Pixel_Sum Maximum_Pixel Minimum_Pixel Shutter_Lower Shutter_Upper Frame_Period_Lower Frame_Period_Upper Conguration_I Conguration_II Frame_Capture SROM_Enable Run_Downshift Rest1_Rate Rest1_Downshift Rest2_Rate Rest2_Downshift Rest3_Rate Frame_Period_Max_Bound_Lower Frame_Period_Max_Bound_Upper Frame_Period_Min_Bound_Lower Frame_Period_Min_Bound_Upper Shutter_Max_Bound_Lower Shutter_Max_Bound_Upper LASER_CTRL0 Reserved Observation Data_Out_Lower Data_Out_Upper Reserved SROM_ID Lift_Detection_Thr Conguration_V Reserved Conguration_IV Power_Up_Reset Shutdown Reserved Inverse_Product_ID Reserved Motion_Burst SROM_Load_Burst Pixel_Burst

Read/WriteR R R R R R R R R R R R R R R R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W W W R R W R

Default Value0x33 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20 0x4e 0xc0 0x5d 0x12 0x00 0x00 0x00 0x32 0x01 0x1f 0x09 0xbc 0x31 0xc0 0x5d 0xa0 0x0f 0x20 0x4e 0x01 0x00 Undened Undened 0x00 0x10 0x12 0x00 NA Undened 0xcc 0x00 Undened 0x00

Product_ID Access: Read Only Bit Field7 PID7 6 PID6

Address: 0x00 Reset Value: 0x335 PID5 4 PID4 3 PID3 2 PID2 1 PID1 0 PID0

Data Type: 8-bit unsigned integer. USAGE: This value is a unique identication assigned to this model only. The value in this register does not change; it can be used to verify that the serial communications link is functional.

Revision_ID Access: Read Only Bit Field7 RID7 6 RID6

Address: 0x01 Reset Value: 0x035 RID5 4 RID4 3 RID3 2 RID2 1 RID1 0 RID0

Data Type: 8-bit unsigned integer. USAGE: This register contains the current IC revision, the revision of the permanent internal rmware. It is subject to change when new IC versions are released.

23

Motion Access: Read Only Bit Field7 MOT 6 FAULT

Address: 0x02 Reset Value: 0x005 LP_Valid 4 Reserved 3 Reserved 2 OP_Mode1 1 OP_Mode2 0 FRAME_ Pix_First

Data Type: Bit eld USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If the MOT bit is set, Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H register should be read in sequence to get the accumulated motion. Read this register before reading the Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H registers as reading this register freezes the Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H register values. If Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H registers are not read before the Motion register is read for the second time, the data in Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H will be lost. Writing anything to this register clears the MOT bit, Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H registers. The written data byte is not saved. It also tells if laser fault, laser power setting status and operating mode in current frame. Field NameMOT

DescriptionMotion since last report or Shutdown 0 = No motion 1 = Motion occurred, data ready for reading in Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H registers Indicates that the XY_LASER is shorted to GND. 0 = no fault detected 1 = fault detected Laser Power Settings 0 = Laser power register values do not have complementary values 1 = laser power is valid Operating mode of the sensor 00 = Run 01 = Rest 1 10 = Rest 2 11 = Rest 3 This bit is set to indicate rst pixel in frame capture. 0 = Frame capture data not from pixel 0,0 1 = Frame capture data is from pixel 0,0

FAULT

LP_Valid

OP_Mode[1:0]

FRAME_Pix_First

24

Delta_X_L Access: Read Only Bit Field7 X7 6 X6

Address: 0x03 Reset Value: 0x005 X5 4 X4 3 X3 2 X2 1 X1 0 X0

Data Type: 16 bits 2s complement number. Lower 8 bits of Delta_X. USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading it clears the register.

Delta_X_H Access: Read Only Bit Field7 X15 6 X14

Address: 0x04 Reset Value: 0x005 X13 4 X12 3 X11 2 X10 1 X9 0 X8

Data Type: 16 bits 2s complement number. Upper 8 bits of Delta_X. USAGE: Delta_X_H must be read after Delta_X_L to have the full motion data. Reading it clears the register.

Delta_Y_L Access: Read Only Bit Field7 Y7 6 Y6

Address: 0x05 Reset Value: 0x005 Y5 4 Y4 3 Y3 2 Y2 1 Y1 0 Y0

Data Type: 16 bits 2s complement number. Lower 8 bits of Delta_Y. USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading it clears the register.

Delta_Y_H Access: Read Only Bit Field7 Y15 6 Y14

Address: 0x06 Reset Value: 0x005 Y13 4 Y12 3 Y11 2 Y10 1 Y9 0 Y8

Data Type: 16 bits 2s complement number. Upper 8 bits of Delta_Y. USAGE: Delta_Y_H must be read after Delta_Y_L to have the full motion data. Reading it clears the register.NOTES: Avago RECOMMENDS that registers 0x02, 0x03, 0x04, 0x05 and 0x06 to be read sequentially.25

SQUAL Access: Read Only Bit Field7 SQ7 6 SQ6

Address: 0x07 Reset Value: 0x005 SQ5 4 SQ4 3 SQ3 2 SQ2 1 SQ1 0 SQ0

Data Type: Upper 8-bits of a 10-bit unsigned integer. USAGE: The SQUAL (Surface quality) register is a measure of the number of valid features visible by the sensor in the current frame. Use the following formula to nd the total number of valid features. Number of Features = SQUAL Register Value * 4 The maximum SQUAL register value is 169. Since small changes in the current frame can result in changes in SQUAL, variations in SQUAL when looking at a surface are expected. The graph below shows 800 sequentially acquired SQUAL values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero if there is no surface below the sensor. SQUAL remains fairly high throughout the Z-height range which allows illumination of most pixels in the sensor.SQUAL Values (White Paper) At Z = 2.4mm, [email protected]" diameter, Speed = 6ips 200

150 SQUAL (Count)

100

50

0 1 51 101 151 201 251 301 351 401 451 501 551 601 651 701 751 Count

Figure 24. SQUAL Values at 1600cpi (White Paper) Mean SQUAL Vs. Z (White Paper) 1600cpi, [email protected]" diameter, Speed = 6ips 140 120 SQUAL (Count) 100 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 Distance from Lens Reference Plane to Navigation Surface (mm) 3.4 Avg-3sigma Avg Avg+3sigma

Figure 25. Mean SQUAL vs. Z (White Paper)

26

Pixel_Sum Access: Read Only Bit Field7 AP7 6 AP6

Address: 0x08 Reset Value: 0x005 AP5 4 AP4 3 AP3 2 AP2 1 AP1 0 AP0

Data Type: High 8-bits of an unsigned 17-bit integer. USAGE: This register is used to nd the average pixel value. It reports the upper byte of a 17-bit counter which sums all 900 pixels in the current frame. It may be described as the full sum divided by 512. To nd the average pixel value, follows the formula below. Average Pixel = Register Value * 512/900 # Register Value/1.76 The maximum register value is 223 (127 * 900/512 truncated to an integer). The minimum register value is 0. The pixel sum value can change every frame.

Maximum_Pixel Access: Read Only Bit Field7 MP7 6 MP6

Address: 0x09 Reset Value: 0x005 MP5 4 MP4 3 MP3 2 MP2 1 MP1 0 MP0

Data Type: Seven bit number. USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value can be adjusted every frame.

Minimum_Pixel Access: Read Only Bit Field7 MinP7 6 MinP6

Address: 0x0A Reset Value: 0x005 MinP5 4 MinP4 3 MinP3 2 MinP2 1 MinP1 0 MinP0

Data Type: Seven bit number. USAGE: Minimum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value can be adjusted every frame.

Shutter_Lower Access: Read Only Bit Field7 S7 6 S6

Address: 0x0B Reset Value: 0x205 S5 4 S4 3 S3 2 S2 1 S1 0 S0

27

Shutter_Upper Access: Read Only Bit Field7 S15 6 S14

Address: 0x0C Reset Value: 0x4e5 S13 4 S12 3 S11 2 S10 1 S9 0 S8

Data Type: 16-bit unsigned number. USAGE: Units are clock cycles of internal oscillator (nominally 47MHz). Read Shutter_Upper rst, then Shutter_Lower. They should be read consecutively. The shutter is adjusted to keep the average pixel values within normal operating ranges. The shutter value is checked and automatically adjusted to a new value if needed on every frame when operating in default mode. The shutter value can be set manually by disabling the AGC using the Conguration_II register and writing to the Shutter_Maximum_Bound registers. Because the automatic frame rate feature is related to shutter value it may also be appropriate to enable the xed frame rate mode using the Conguration_II register. The maximum value of the shutter is dependent upon the setting in the Shutter_ Maximum_Bound registers. Shown below is a graph of 800 sequentially acquired shutter values, while the sensor was moved slowly over white paper.Shutter Values (White Paper At Z = 2.4mm, [email protected]" diameter, Speed = 6ips) 120 100 Shutter Value 80 60 40 20 0 1 51 101 151 201 251 301 351 401 451 501 551 601 651 701 751 Count

Figure 26. Shutter Values at 5000cpi (White Paper) Mean Shutter vs Z (White Paper) 1600cpi, [email protected]" diameter, Speed = 6ips 300 250 Shutter Value 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 Distance from Lens Reference Plane to Navigation Surface, Z (mm) 3.4 Avg-3sigma Avg Avg+3sigma

Figure 27. Mean Shutter vs. Z (White Paper)

28

Frame_Period_Lower Access: Read Only Bit Field7 FP7 6 FP6

Address: 0x0D Reset Value: 0xc05 FP5 4 FP4 3 FP3 2 FP2 1 FP1 0 FP0

Frame_Period_Upper Access: Read Only Bit Field7 FP15 6 FP14

Address: 0x0E Reset Value: 0x5d5 FP13 4 FP12 3 FP11 2 FP10 1 FP9 0 FP8

Data Type: 16-bit unsigned integer. USAGE: To read from the registers, read Frame_Period_Upper rst followed by Frame_Period_Lower. If the Frame_Period_ Upper register greater the zero, these registers provide the Run mode frame rate period. Read these registers to determine the run mode frame period, or indirectly the run mode frame rate. Units are clock cycles of the internal oscillator (nominally 47MHz). The formula is: Run Mode's Frame Rate = Clock Frequency/Register Value If the Frame_Period_Upper register is zero, these register provide the Rest mode frame rate period. Read these register to determine the rest mode frame period, or indirectly the rest mode frame rate. Units are clock cycles of the internal oscillator (nominally 100Hz). The formula is: Rest Mode Frame Rate = 1 / [Register Value +1] To set the frame rate manually, disable automatic frame rate mode via the Conguration_II register and write the desired count value to the Frame_Period_Maximum_Bound registers.

Conguration_I Access: R/W Bit Field7 Reserved 6 Reserved

Address: 0x0F Reset Value: 0x125 RES5 4 RES4 3 RES3 2 RES2 1 RES1 0 RES0

Data Type: Bit Field. USAGE: This register sets the resolution on XY axes or X axis only. The approximate resolution value for each register setting can be calculated using the following formula. Each bit change is ~90cpi. The maximum write value is 0x38, which the resolution setting is approximately 5000cpi. Resolution value (counts per inch, cpi) RES [5:0] x 90 For example: Conguration_I Register Value0x01 0x12 0x24 0x38

Approximate Resolution (cpi)90 1620 3240 5040

DescriptionMinimum Default

Maximum

Note: Rpt_Mod bit in Conguration_II register is used to select CPI reporting mode either XY axes resolution setting in sync or independent setting for X-axis and Y-axis respectively. Refer to Conguration_V register for Y-axis resolution setting.

29

Conguration_II Access: R/W Bit Field7 F_Rest1 6 F_Rest0

Address: 0x10 Reset Value: 0x005 Rest_En 4 NAGC 3 Fixed_FR 2 Rpt_Mod 1 0 0 0

Data Type: Bit Field. USAGE: This register is used to change conguration of sensor. When the sensor is put into Force Rest function via F_Rest[1:0], the operation mode of sensor will change from current mode to the next desired Rest mode and stay at the desired Rest mode until the Force Rest mode is released. Once Force Rest mode is released, the sensor will resume to normal operation from the desired Rest mode and auto downshift to the next level of Rest modes if no motion or recover to Run mode if motion is detected. For example: Current modeRun

Next desired modeRest1

Force Rest mode actionForce Rest1 F_Rest[1:0] = 01 Force Rest2 F_Rest[1:0] = 10 Force Rest3 F_Rest[1:0] = 11

After Force Rest mode is released (F_Rest[1:0] = 00)Resume to normal operation from REST1, auto downshift to Rest2, then Rest3 in sequence if no motion or back to Run mode if motion detected. Resume to normal operation from REST2, auto downshift to Rest3 if no motion or back to Run mode if motion detected. Resume to normal operation from REST3, stay in Rest3 if no motion or back to Run mode if motion detected.

Run Run

Rest2 Rest3

Field NameF_Rest[1:0]

DescriptionPuts chip into Rest mode 00 = Normal operation 01 = Force Rest1 10 = Force Rest2 11 = Force Rest3 Enable Rest mode 0 = Normal operation without REST modes 1 = REST modes enabled Disable AGC. Shutter value will be set to the value in the Shutter_Maximum_Bound registers. 0 = no, AGC is active 1 = yes, AGC is disabled Fixed frame rate (disable automatic frame rate control). When this bit is set the frame rate will be set by the value in the Frame_Period_Maximum_Bound registers. 0 = automatic frame rate 1 = xed frame rate Select CPI reporting mode. 0 = XY axes CPI setting in sync 1 = CPI setting independently for X-axis and Y-axis. Conguration_I register sets X-axis resolution, while Conguration_V register sets Y-axis resolution. Must be set to 00

Rest_En

NAGC

Fixed_FR

Rpt_Mod

Bit[1:0]

30

Frame_Capture Access: R/W Bit Field7 FC7 6 FC6

Address: 0x12 Reset Value: 0x005 FC5 4 FC4 3 FC3 2 FC2 1 FC1 0 FC0

Data Type: Bit Field. USAGE: Used to capture the next available complete 1 frame of pixel values to be stored to SROM RAM. Writing to this register will cause any rmware loaded in the SROM to be overwritten and stops navigation. A hardware reset and SROM download are required to restore normal operation for motion reading. Refer to Frame Capture section for use details.

SROM_Enable Access: Write Only Bit Field7 SE7 6 SE6

Address: 0x13 Reset Value: 0x005 SE5 4 SE4 3 SE3 2 SE2 1 SE1 0 SE0

Data Type: 8 Bit number. USAGE: Write to this register to start either SROM download or SROM CRC test. See SROM Download section for details SROM download procedure. SROM CRC test can be performed to check for the successful of SROM downloading procedure. SROM CRC test is only valid after SROM downloaded. Navigation is halted and the SPI port should not be used during this SROM CRC test. Avago recommends reading the Motion register to determine the laser fault condition before performing the SROM CRC test. SROM CRC test procedure is as below: 1. Write 0x15 to SROM_Enable register to start SROM CRC test. 2. Wait for at least 10ms. 3. Read the CRC value from Data_Lower and Data_Upper registers.

Run_Downshift Access: R/W Bit Field7 RD7 6 RD6

Address: 0x14 Reset Value: 0x325 RD5 4 RD4 3 RD3 2 RD2 1 RD1 0 RD0

Data Type: 8 Bit number. USAGE: This register set the Run to Rest 1 downshift time. Default value is 500ms. Use the formula below for calculation. Run Downshift time (ms) = RD[7:0] x 10 Default = 50 x 10 = 500ms All the above values are calculated base on system clock, which expected to have 20% tolerance.

31

Rest1_Rate Access: R/W Bit Field7 R1R7 6 R1R6

Address: 0x15 Reset Value: 0x015 R1R5 4 R1R4 3 R1R3 2 R1R2 1 R1R1 0 R1R0

Data Type: 8 Bit number. USAGE: This register set the Rest 1 frame rate. Default value is 20ms. Use the formula below for calculation. Rest1 frame rate = (R1R[7:0] + 1) x 10ms. Default = (1 + 1) x 10 = 20ms All the above values are calculated base on 100Hz Hibernate clock, which expected to have 40% tolerance.

Rest1_Downshift Access: R/W Bit Field7 R1D7 6 R1D6

Address: 0x16 Reset Value: 0x1f5 R1D5 4 R1D4 3 R1D3 2 R1D2 1 R1D1 0 R1D0

Data Type: 8 Bit number. USAGE: This register set the Rest 1 to Rest 2 downshift time. Default value is 9920ms. Use the formula below for calculation. Rest1 Downshift time = R1D[7:0] x 16 x Rest1_Rate. Default = 31 x 16 x 20 = 9920ms All the above values are calculated base on 100Hz Hibernate clock, which expected to have 40% tolerance.




32

Rest2_Downshift Access: R/W Bit Field7 R2D7 6 R2D6

Address: 0x18 Reset Value: 0xbc5 R2D5 4 R2D4 3 R2D3 2 R2D2 1 R2D1 0 R2D0

Data Type: 8 Bit number. USAGE: This register set the Rest 2 to Rest 3 downshift time. Default value is 10mins. Use the formula below for calculation. Rest2 Downshift time = R2D[7:0] x 32 x Rest2_Rate. Default = 188 x 32 x 100 = 601600ms = 10mins All the above values are calculated base on 100Hz Hibernate clock, which expected to have 40% tolerance.




33

Frame_Period_Max_Bound_Lower Access: R/W Bit Field7 FBM7 6 FBM6

Address: 0x1A Reset Value: 0xc05 FBM5 4 FBM4 3 FBM3 2 FBM2 1 FBM1 0 FBM0

Frame_Period_Max_Bound_Upper Access: R/W Bit Field7 FBM15 6 FBM14

Address: 0x1B Reset Value: 0x5d5 FBM13 4 FBM12 3 FBM11 2 FBM10 1 FBM9 0 FBM8

Data Type: 16-bit unsigned integer. USAGE: This value sets the maximum frame period (the MINIMUM frame rate) which may be selected by the automatic frame rate control, or sets the actual frame period when operating in manual mode. To read from the registers, read Upper rst followed by Lower. To write to the registers, write Lower rst, followed by Upper. Units are clock cycles of the internal oscillator (nominally 47MHz). The formula is: Frame Rate (Frames/second, fps) = Clock Frequency / Register Value To set the frame rate manually, disable automatic frame rate mode via the Conguration_II register and write the desired count value to these registers. Writing to the Frame_Period_Max_Bound_Upper and Lower registers also activates any new values in the following registers: x Frame_Period_Max_Bound_Upper and Lower x Frame_Period_Min_Bound_Upper and Lower x Shutter_Max_Bound_Upper and Lower Any data written to these registers will be saved but will not take eect until the write to the Frame_Period_ Max_Bound_Upper and Lower is complete. After writing to this register, two complete frame times are required to implement the new settings. Writing to any of the above registers before the implementation is complete may put the chip into an undened state requiring a reset. The three bound registers must also follow this rule when set to non-default values. There is no protection against illegal register settings, which can impact the navigation. Frame_Period_Max_Bound Frame_Period_Min_Bound + Shutter_Max_Bound. The following table lists some Frame Period example values with a 47MHz clock. Frame Period Frame Rate1,880 1,958 7,200 11,750

Frame_Period Register Value Hex61a8 5dc0 1980 0fa0

Decimal25,000 24,000 6,528 4,000

Upper61 5d 19 0f

Lowera8 c0 80 a0

34

Frame_Period_Min_Bound_Lower Access: R/W Bit Field7 FBm7 6 FBm6

Address: 0x1C Reset Value: 0xa05 FBm5 4 FBm4 3 FBm3 2 FBm2 1 FBm1 0 FBm0

Frame_Period_Min_Bound_Upper Access: R/W Bit Field7 FBm15 6 FBm14

Address: 0x1D Reset Value: 0x0f5 FBm13 4 FBm12 3 FBm11 2 FBm10 1 FBm9 0 FBm8

Data Type: 16-bit unsigned integer. USAGE: This value sets the minimum frame period (the MAXIMUM frame rate) which may be selected by the automatic frame rate control. Units are clock cycles of the internal oscillator (nominally 47MHz). The minimum allowed write value is 0fa0, the maximum is 61a8. The Frame Rate formula is Frame Rate (Frames/second, fps) = Clock Rate / Register Value To read from the registers, read Upper rst followed by Lower. To write to the registers, write Lower rst, followed by Upper, then write anything to the Frame_Period_Max_Bound Lower and Upper registers to activate the new setting. A good practice is to read the content of the Frame_Period_Max_Bound registers and write it back. Reading this register will return the most recent value that was written to it. However, the value will take eect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_ Max_Bound_Upper, wait at least two frame times before writing to Frame_Period_Min_Bound_Upper or Lower again. Refer to Frame_Period_Max_Bound register USAGE for details. In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound Frame_Period_Min_Bound + Shutter_Max_Bound.

35

Shutter_Max_Bound_Lower Access: R/W Bit Field7 SB7 6 SB6

Address: 0x1E Reset Value: 0x205 SB5 4 SB4 3 SB3 2 SB2 1 SB1 0 SB0

Shutter_Max_Bound_Upper Access: R/W Bit Field7 SB15 6 SB14

Address: 0x1F Reset Value: 0x4e5 SB13 4 SB12 3 SB11 2 SB10 1 SB9 0 SB8

Data Type: 16-bit unsigned integer. USAGE: This value sets the maximum allowable shutter value when operating in automatic mode. Units are clock cycles of the internal oscillator (nominally 47MHz). Since the automatic frame rate function is based on shutter value, the value in these registers can limit the range of the frame rate control. To read from the registers, read Upper rst followed by Lower. To write to the registers, write Lower rst, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers to activate the new setting. A good practice is to read the content of the Frame_Period_Max_Bound registers and write it back. To set the shutter manually, disable the AGC via the Conguration_I register and write the desired value to these registers. Reading this register will return the most recent value that was written to it. However, the value will take eect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_ Max_Bound_Upper, wait at least two frame times before writing to Shutter_Max_Bound_Upper or Lower again. In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound Frame_Period_Min_Bound + Shutter_Max_Bound.

36

LASER_CTRL0 Access: R/W Bit Field7 Reserved 6 Reserved

Address: 0x20 Reset Value: 0x015 Reserved 4 Reserved 3 CW2 2 CW1 1 CW0 0 Force_ Disabled

Data Type: Bit eld USAGE: This register is used to control the laser drive mode. Field NameCW[2:0]

DescriptionLaser drive mode - Write 010b to bits [3,2,1] to set the laser to continuous ON (CW) mode. - Write 000b to exit laser continuous ON mode, all other values are not recommended. Reading the Motion register (0x02) will reset the value to 000b and exit laser continuous ON mode. LASER force disabled 0 = LASER_NEN normal 1 = LASER_NEN force disabled

Force_Disabled

Observation Access: R/W Bit Field7 OB7 6 OB6

Address: 0x24 Reset Value: 0x005 OB5 4 OB4 3 OB3 2 OB2 1 OB1 0 OB0

Data Type: Bit eld USAGE: The user must clear the register by writing 0x00, wait for one frame, and read the register. The active processes will have set their corresponding bit. This register may be used as part of a recovery scheme to detect a problem caused by EFT/B or ESD. Field NameOB6 OB[5:0]

Description0 = chip is not running SROM code 1 = chip is running SROM code Set once per frame

37

Data_Out_Lower Access: Read Only Bit Field7 DO7 6 DO6

Address: 0x25 Reset Value: Undened5 DO5 4 DO4 3 DO3 2 DO2 1 DO1 0 DO0

Data_Out_Upper Access: Read Only Bit Field7 DO15 6 DO14

Address: 0x26 Reset Value: Undened5 DO13 4 DO12 3 DO11 2 DO10 1 DO9 0 DO8

Data Type: 16-bit word. USAGE: Data in these registers come from the SROM CRC test. The data can be read out in either order. The SROM CRC test is initiated by writing 0x15 to SROM_Enable register. CRC ResultSROM CRC test

Data_Out_UpperBE

Data_Out_LowerEF

SROM_ID Access: Read Only Bit Field7 SR7 6 SR6

Address: 0x2A Reset Value: 0x005 SR5 4 SR4 3 SR3 2 SR2 1 SR1 0 SR0

Data Type: 8-bit unsigned integer. USAGE: Contains the revision of the downloaded Shadow ROM (SROM) rmware. If the rmware has been successfully downloaded and the chip is operating out of SROM, this register will contain the SROM rmware revision; otherwise it will contain 0x00.

Lift_Detection_Thr Access: R/W Bit Field7 Reserve 6 Reserve

Address: 0x2E Reset Value: 0x105 Reserve 4 LD_Thr4 3 LD_Thr3 2 LD_Thr2 1 LD_Thr1 0 LD_Thr0

Data Type: 8-bit unsigned integer. USAGE: To congure the lift detection from the nominal Z-height of 2.4mm of navigation system when ADNS-9500 sensor is coupled with ADNS-6190-002 lens. Higher value will result in higher lift detection. Dierent surfaces will have dierent lift detection values with same setting due to dierent surface characteristic.

38

Conguration_V Access: R/W Bit Field7 ResY7 6 ResY6

Address: 0x2F Reset Value: 0x125 ResY5 4 ResY4 3 ResY3 2 ResY2 1 ResY1 0 ResY0

Data Type: Bit eld. USAGE: This register allows the user to change the Y-axis resolution when the sensor is congured to have indepedent X-axis and Y-axis resolution reporting mode via Rpt_Mod bit = 1 in Conguration_II register. The setting in this register will be inactive if Rpt_Mod bit = 0. The approximate resolution value for each register setting can be calculated using the following formula. Each bit change is~90cpi. The minimum write value is 0x01 and maximum is 0x37. Resolution value (counts per inch, cpi) = RES [7:0] x 90

Conguration_IV Access: R/W Bit Field7 Reserved 6 Reserved

Address: 0x39 Reset Value: 0x005 Reserved 4 Reserved 3 Reserved 2 Reserved 1 SROM_Size 0 Reserved

Data Type: Bit eld. USAGE: The correct SROM le size must be selected before loading the SROM to sensor. The current SROM is 3K Bytes size. Field NameSROM_Size

Description= 0: 1.5K SROM download = 1: 3K SROM download

Power_Up_Reset Access: Write Only Bit Field7 PUR7 6 PUR6

Address: 0x3A Reset Value: 0xNA5 PUR5 4 PUR4 3 PUR3 2 PUR2 1 PUR1 0 PUR0

Data Type: 8-Bit integer. USAGE: Write 0x5a to this register to reset the chip. All settings will revert to default values. Reset is required after recovering from shutdown mode and restore normal operation after Frame Capture.

Shutdown Access: Write Only Bit Field7 OB7 6 OB6

Address: 0x3B Reset Value: Undened5 OB5 4 OB4 3 OB3 2 OB2 1 OB1 0 OB0

Data Type: 8-Bit integer. USAGE: Write 0xb6 to set the chip to shutdown mode, use POWER_UP_RESET register to power up the chip. Refer to Shutdown section for more details.39

Inverse_Product_ID Access: Read Only Bit Field7 PID7 6 PID6

Address: 0x3F Reset Value: 0xcc5 PID5 4 PID4 3 PID3 2 PID2 1 PID1 0 PID0

Data Type: 8-Bit unsigned integer. USAGE: This value is the inverse of the Product_ID, located at the inverse address. It is used to test the SPI port hardware.

Motion_Burst Access: Read Only Bit Field7 MB7 6 MB6

Address: 0x50 Reset Value: 0x005 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0

Data Type: 8-Bit unsigned integer. USAGE: The Motion_Burst register is used for high-speed access to the Motion, Observation, Delta_X_L, Delta_X_H, Delta_Y_L, Delta_Y_H, SQUAL, Pixel_Sum, Maximum_Pixel, Minimum_Pixel, Shutter_Upper, Shutter_Lower, Frame_Period_Upper and Frame_Period_Lower registers. See Burst Mode-Motion Read section for use details. Write any value to this register will clear all motion burst data.

SROM_Load_Burst Access: Write Only Bit Field7 SL7 6 SL6

Address: 0x62 Reset Value: Undened5 SL5 4 SL4 3 SL3 2 SL2 1 SL1 0 SL0

USAGE: The SROM_Load_Burst register is used for high-speed programming SROM from an external PROM or microcontroller. See SROM Download section for use details.

Pixel_Burst Access: Read Only Bit Field7 PB7 6 PB6

Address: 0x64 Reset Value: 0x005 PB5 4 PB4 3 PB3 2 PB2 1 PB1 0 PB0

Data Type: 8-Bit unsigned integer. USAGE: The Pixel_Burst register is used for high-speed access to all the pixel values for one complete frame capture, without writing to the register address to obtain each pixel data. The data pointer is automatically incremented after each read so all 900 pixel values may be obtained by reading this register 900 times. See Frame Capture section for use details.

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www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2005-2009 Avago Technologies. All rights reserved. AV02-1726EN - December 16, 2009

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