address&translaon& (part2)& - courses.cs.washington.edu · 2012-10-26 · page # <...
TRANSCRIPT
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Address Transla+on (part 2)
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Last Time
• Address Transla+on Concept • Flexible Address Transla+on – Base and bound – Segmenta+on
• Program = mul+ple con+guous regions of memory • Modern programs have many segments
– Code, data, per core heap, per thread stack, code/data for each separate library
• Hardware reloca+on and bound on each reference • Copy on write • Zero on reference
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Main Points
• Flexible Address Transla+on – Paged Transla+on – Segmenta+on + paged transla+on – Mul+-‐level paged transla+on – Hashing
• Efficient Address Transla+on – Transla+on Lookaside Buffers (TLBs) – Virtually addressed and physically addressed caches
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Address Transla+on Concept
ProcessorPhysicalMemory
Virtual AddressPhysical Address
Translation Box
ok?yes
no
raise exception
Instruction fetch or data read/write (untranslated)
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Segmenta+on
• Pros? – Can share code/data segments between processes – Can protect code segment from being overwriRen – Can transparently grow stack/heap as needed – Can detect if need to copy-‐on-‐write
• Cons? – Complex memory management
• Need to find chunk of a par+cular size – May need to rearrange memory from +me to +me to make room for new segment or growing segment • External fragmenta+on: wasted space between chunks
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Paged Transla+on
• Manage memory in fixed size units, or pages • Finding a free page is easy – Bitmap alloca+on: 0011111100000001100 – Each bit represents one physical page frame
• Each process has its own page table – Stored in physical memory – Hardware registers
• pointer to page table start • page table length
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Physical MemoryProcess View of Memory
page # < page table length ANDpage table[page #].access is permitted
no
raise exception
0x12
0Page Table
AccessFrame
read
0x!!!f
0x08 read
Virtual Address: page # page o!set
code
data
heap
page table[page #].framePhysical Address: page o!set
stack
0x0d rd/wr
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A B C D
E F G H
I J K L
I J K L
E F G H
A B C D
4
3
1
Page Table
Process View Physical Memory
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Paging Ques+ons
• What must be saved/restored on a process context switch? – Pointer to page table/size of page table – Page table itself is in main memory
• What if page size is very small?
• What if page size is very large? – Internal fragmenta+on: if we don’t need all of the space inside a fixed size chunk
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Paging and Copy on Write
• Can we share memory between processes? – Set entries in both page tables to point to same page frames
– Need core map of page frames to track which processes are poin+ng to which page frames
• UNIX fork with copy on write at page granularity – Copy page table entries to new process – Mark all pages as read-‐only – Trap into kernel on write (in child or parent) – Copy page and resume execu+on
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Paging and Fast Program Start
• Can I start running a program before its code is in physical memory? – Set all page table entries to invalid – When a page is referenced for first +me
• Trap to OS kernel • OS kernel brings in page • Resumes execu+on
– Remaining pages can be transferred in the background while program is running
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Sparse Address Spaces
• Might want many separate segments – Per-‐processor heaps – Per-‐thread stacks – Memory-‐mapped files – Dynamically linked libraries
• What if virtual address space is sparse? – On 32-‐bit UNIX, code starts at 0 – Stack starts at 2^31 – 4KB pages => 500K page table entries – 64-‐bits => 4 quadrillion page table entries
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Mul+-‐level Transla+on
• Tree of transla+on tables – Paged segmenta+on – Mul+-‐level page tables – Mul+-‐level paged segmenta+on
• All 3: Fixed size page as lowest level unit – Efficient memory alloca+on – Efficient disk transfers – Easier to build transla+on lookaside buffers – Efficient reverse lookup (from physical -‐> virtual) – Page granularity for protec+on/sharing
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Paged Segmenta+on
• Process memory is segmented • Segment table entry: – Pointer to page table – Page table length (# of pages in segment) – Access permissions
• Page table entry: – Page frame – Access permissions
• Share/protec+on at either page or segment-‐level
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page # < segment table[segment #].length AND segment table[segment #].access is permittedAND pageTable[page #].access is permitted
Physical Address:
length
0x0a
Segment TableaccesspageTable
read
0x5 rd/wr
Virtual Address: segment # page # page o!set
no
raise exception
0x12Page TableAccessFrame
read0x08 read
segment table[segment #].pageTable[page #] page o!set
Physical MemoryProcess View of Memory0
0x500
0x10000
0x10280
0x20000
0x20800
code
data
heap
0x10 rd/wr
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Mul+level Paging
Physical Address = pageTable[index].pageTable[index2] .pageTable[index3] | page o!set
Virtual Address: index index2 page o!set
Page TableLevel 1
index3
indexLevel 2
index2Level 3
index3
o!set
page frame
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x86 Mul+level Paged Segmenta+on
• Global Descriptor Table (segment table) – Pointer to page table for each segment – Segment length – Segment access permissions – Context switch: change global descriptor table register (GDTR, pointer to global descriptor table)
• Mul+level page table – 4KB pages; each level of page table fits in one page
• Only fill page table if needed – 32-‐bit: two level page table (per segment) – 64-‐bit: four level page table (per segment)
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Mul+level Transla+on
• Pros: – Allocate/fill only as many page tables as used
– Simple memory alloca+on – Share at segment or page level
• Cons: – Space overhead: at least one pointer per virtual page
– Two or more lookups per memory reference
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Portability
• Many opera+ng systems keep their own memory transla+on data structures – List of memory objects (segments) – Virtual -‐> physical – Physical -‐> virtual – Simplifies por+ng from x86 to ARM, 32 bit to 64 bit
• Inverted page table – Hash from virtual page -‐> physical page – Space propor+onal to # of physical pages
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Do we need mul+-‐level page tables?
• Use inverted page table in hardware instead of mul+level tree – IBM PowerPC – Hash virtual page # to inverted page table bucket – Loca+on in IPT => physical page frame
• Pros/cons?
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Efficient Address Transla+on
• Transla+on lookaside buffer (TLB) – Cache of recent virtual page -‐> physical page transla+ons
– If cache hit, use transla+on – If cache miss, walk mul+-‐level page table
• Cost of transla+on = Cost of TLB lookup + Prob(TLB miss) * cost of page table lookup
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TLB contains virtual page #?
Translation Lookaside Bu!er (TLB)
accessvirtualPage
read
rd/wr
no
do page table lookup
read
invalid
pageFrame
0x0000
0x0001
0x8
0xd
0x40! 0x12
=?
=?
=?
=?
Physical Address:
Virtual Address: virtualPage # page o!set
TLB.lookup(virtual page #).pageFrame page o!set
Process View of Memory0
0x500
0x10000
0x10280
0x20000
0x20800
code
data
heap
Physical Memory
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Soqware Loaded TLB
• Do we need a page table at all? – MIPS processor architecture
– If transla+on is in TLB, ok – If transla+on is not in TLB, trap to kernel – Kernel computes transla+on and loads TLB
– Kernel can use whatever data structures it wants • Pros/cons?
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When Do TLBs Work/Not Work?
Video Frame Bu!erpage #
0123
...
102110221023
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When Do TLBs Work/Not Work?
• Video Frame Buffer: 32 bits x 1K x 1K = 4MB
Video Frame Bu!erpage #
0123
...
102110221023
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Superpages
• TLB entry can be – A page – A superpage: a set of con+guous pages – x86: superpage is set of pages in one page table – x86 TLB entries
• 4KB • 2MB
• 1GB
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When Do TLBs Work/Not Work, part 2
• What happens on a context switch? – Reuse TLB? – Discard TLB?
• Mo+vates hardware tagged TLB – Each TLB entry has process ID – TLB hit only if process ID matches current process
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TLB contains virtual page #for the current process?
no
do page table lookup
0
1
1
0
Translation Lookaside Bu!er (TLB)
accessvirtualPage
rd/wr
read
read
pageFrame
0x0053
0x0001
0x3
0xd
0x40! 0x12
=?
=?
=?
=?
Physical Address:
Virtual Address: virtualPage # page o!set
TLB.lookup(virtual page #).pageFrame page o!set
Process 1 View of Memory0
0x500
0x10000
0x10280
0x20000
0x20800
code
data
heap
Physical Memory
0x0001 0x5
rd/wr
process ID
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When Do TLBs Work/Not Work, part 3
• What happens when the OS changes the permissions on a page? – For demand paging, copy on write, zero on reference, …
• TLB may contain old transla+on – OS must ask hardware to purge TLB entry
• On a mul+core: TLB shootdown – OS must ask each CPU to purge TLB entry
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TLB Shootdown
accessvirtualPage
rd/wr
rd/wr
read
pageFrame
0x53 0x3
0x40! 0x12
=?
=?
=?
=?
process ID
0
1
0 1 0x5
Processor 1 TLB
Processor 2 TLB
read
=?
=? 0 1 0x5Processor 3 TLB
rd/wr0x40! 0x121
rd/wr0x53 0x30
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Address Transla+on with TLB
ProcessorPhysicalMemory
Virtual Address
Physical Address
Translation Box
no
yes
no
raise exception
Instruction fetch or data read/write (untranslated)
virtual page in TLB?
valid page table entry?
yes
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Virtually Addressed Caches
ProcessorPhysicalMemory
Virtual Address
Physical Address
Translation Box
no
yes
no
raise exception
Instruction fetch or data read/write (untranslated)
virtual page in TLB?
valid page table entry?
yeslocationin virtualcache?
no
data
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Transla+on on a Modern Processor
Processor
Virtual Address
Physical Address
Translation Box
no
yes
no
raise exception
Instruction fetch or data read/write (untranslated)
virtual page in TLB?
valid page table entry?
yeslocationin virtualcache?
no
data
PhysicalMemory
location inphysicalcache?
no