adding the tse component to bansmom system and software development m5151117 yumiko kimezawa october...
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Adding the TSE component to BANSMOM system and Software
Development
m5151117Yumiko Kimezawa
October 4, 2012 1RPS
Outline
• Previous Work- Implementing a Triple-Speed Ethernet (TSE)
component (Hardware)
• Current Work- Adding the TSE component to BANSMOM
system- Software Development (unfinished)
• Future Work
October 4, 2012 2RPS
Triple-Speed Ethernet (TSE) part
• Components- Triple-Speed Ethernet- TX SDGMA- RX SGDMA
October 4, 2012 RPS 3
Stratix III
?
Transfer
Receive
Host PC
dispensable
User Interface
Optimized HW
October 4, 2012 RPS 4
: Data flow
: Control signal
Graphic LCD
Controller
Master CPU
Memory
MasterCPU
Timer
GraphicLCD
LEDJTAGUART
PPD Module Master Module
LEDControllerAvalon
Bus
FIR Filter
Timer
PPD CPU Memory
PPDCPU
ExternalMemory
SharedMemory
FPGA
Raw ECG data
EthernetPHY
TSE MAC
TXSGDMA
Ethernet
•Block diagram of optimized hardware
1: Signal Reading
Optimized HW
October 4, 2012 RPS 5
: Data flow
: Control signal
Graphic LCD
Controller
Master CPU
Memory
MasterCPU
Timer
GraphicLCD
LEDJTAGUART
PPD Module Master Module
LEDControllerAvalon
Bus
FIR Filter
Timer
PPD CPU Memory
PPDCPU
ExternalMemory
SharedMemory
FPGA
Raw ECG data
EthernetPHY
TSE MAC
TXSGDMA
Ethernet
•Block diagram of optimized hardware2: Filtering
Optimized HW
October 4, 2012 RPS 6
: Data flow
: Control signal
Graphic LCD
Controller
Master CPU
Memory
MasterCPU
Timer
GraphicLCD
LEDJTAGUART
PPD Module Master Module
LEDControllerAvalon
Bus
FIR Filter
Timer
PPD CPU Memory
PPDCPU
ExternalMemory
SharedMemory
FPGA
Raw ECG data
EthernetPHY
TSE MAC
TXSGDMA
Ethernet
•Block diagram of optimized hardware
3: Processing
Optimized HW
October 4, 2012 RPS 7
: Data flow
: Control signal
Graphic LCD
Controller
Master CPU
Memory
MasterCPU
Timer
GraphicLCD
LEDJTAGUART
PPD Module Master Module
LEDControllerAvalon
Bus
FIR Filter
Timer
PPD CPU Memory
PPDCPU
ExternalMemory
SharedMemory
FPGA
Raw ECG data
EthernetPHY
TSE MAC
TXSGDMA
Ethernet
•Block diagram of optimized hardware 4: Display & Transferring data
Software Development• Creating a NicheStack TCP/IP stack and
MicroC-OS/II
• Now, I am investigating
October 4, 2012 RPS 8
Software Architecture Model
October 4, 2012 RPS 9
Nios II Processor system hardware
Application
Application-specific system initialization
HAL API
Micro C/OS - II
NicheStack TCP/IP Stacksoftware component
Software device driver
Software
Hardware
•The onion diagram shows the architectural layers of a Nios II MicroC/OS-II software application
Future Work
• Investigating NicheStack TCP/IP stack and MicroC-OS/II to get data from shared memory and send it to the host PC
October 4, 2012 RPS 10
October 4, 2012 RPS 11
Optimized HW (Proposal)
October 4, 2012 RPS 12
: Data flow
: Control signal
Graphic LCD
Controller
Master CPU
Memory
MasterCPU
Timer
GraphicLCD
LEDJTAGUART
PPD Module Master Module
LEDControllerAvalon
Bus
FIR Filter
Timer
PPD CPU Memory
PPDCPU
ExternalMemory
SharedMemory
FPGA
Raw ECG data
EthernetPHY
TSE MAC
TXSGDMA
Ethernet
Optimized HW (Proposal)
October 4, 2012 RPS 13
: Data flow
: Control signal
Graphic LCD
Controller
Master CPU
Memory
MasterCPU
Timer
GraphicLCD
LEDJTAGUART
PPD Module Master Module
LEDControllerAvalon
Bus
FIR Filter
Timer
PPD CPU Memory
PPDCPU
ExternalMemory
SharedMemory
FPGA
Raw ECG data
EthernetPHY
TSE MAC
TXSGDMA
Ethernet
Optimized HW (Proposal)
October 4, 2012 RPS 14
: Data flow
: Control signal
Graphic LCD
Controller
Master CPU
Memory
MasterCPU
Timer
GraphicLCD
LEDJTAGUART
PPD Module Master Module
LEDControllerAvalon
Bus
FIR Filter
Timer
PPD CPU Memory
PPDCPU
ExternalMemory
SharedMemory
FPGA
Raw ECG data
EthernetPHY
TSE MAC
TXSGDMA
Ethernet
Optimized HW (Proposal)
October 4, 2012 RPS 15
: Data flow
: Control signal
Graphic LCD
Controller
Master CPU
Memory
MasterCPU
Timer
GraphicLCD
LEDJTAGUART
PPD Module Master Module
LEDControllerAvalon
Bus
FIR Filter
Timer
PPD CPU Memory
PPDCPU
ExternalMemory
SharedMemory
FPGA
Raw ECG data
EthernetPHY
TSE MAC
TXSGDMA
Ethernet
•Block diagram of optimized hardware