ad/da-converter, pll datasheet · • antenna arrays, beam forming, attitude determination. •...

Literature Number: DS-SY1017CJanuary 30, 2014

Rev. 1.5

SY1017C

AD/DA-Converter, PLL

DATASHEET

www.saphyrion.ch

DATASHEET SY1017C AD/DA-Converter, PLL

Document Team

Author Francesco Piazza Reviewers Lorenzo MoriggiaChristian IeraMariano PernaAngelo Consoli

Revision History

Rev. Date Who Description1.0 September 16, 2009 fp SPH document created, loosely derived from previous versions.1.1 November 26, 2009 fp Expanded all sections (based on customer support requests).1.2 October 4, 2011 fp Corrections to specifications, and sections 10.6 and 14.6.1.3 September 24, 2013 fp Corrected Section 4, updated Sections 5, 7, 14 and 16, corrected

typos (all sections), added application example (Section 17).1.4 November 14, 2013 fp Corrected typo for pin BEN (active low).1.5 January 30, 2014 fp Re-characterization of the VCO: updated VCO tuning curves and

phase noise specs. Added handling precautions (Section 15).

Contents

1 General Description 1

2 Features 1

3 Applications 1

4 Absolute Maximum Ratings 2

5 Electrical Characteristics 2

6 Device Marking 4

7 Typical Operating Characteristics 5

8 Pin Description 6

9 Equivalent Circuits 7

10 Circuit Description 8

11 Serial Interface 9

12 Register File 10

13 SY1007/SY1008 Interface 12

14 Application Information 12

15 Handling Precautions 15

16 Radiation Tolerance 15

17 Application Example 16

18 Layout Recommendations 19

19 PCB Recommendations 19

20 Mounting Recommendations 20

21 Package Drawing 21

ii Saphyrion Sagl Rev. 1.5, January 30, 2014

SY1017C AD/DA-Converter, PLL

DS-SY1017C Rev. 1.5 - January 30, 2014 DATASHEET

1 General Description

The SY1017C is a radiation hardened AD/DA-converter andinterface ASIC for GNSS receivers aimed at aerospace ap-plications. It is synergistically designed to operate togetherwith the SY1007 and SY1008 GNSS RF front-ends and itspurpose is to interface these two devices to a GNSS base-band processor.

The SY1017C integrates two flash AD-converters, a lowspeed DA-converter, a sampling clock PLL frequency synthe-sizer and a configuration register accessible via a serial inter-face. The two flash AD-converters are meant for quadratureconversion to digital of near base-band GNSS signals, fea-ture 3-bit resolution and a sampling frequency up to 50MHz.The sampling clock may be either generated by the on-chipPLL or supplied by an external clock generator. An 8-bit mul-tiplying low speed DA-converter is also integrated. Its pur-pose is to generate the control voltage for the gain control ofthe SY1007 and SY1008 in order to implement AGC.

Clock generation for the RF front-end and a 50MHz PLLfrequency synthesizer are provided on-chip. The PLL ismainly meant to generate the sampling clock for the 3-bit AD-converters. Since this PLL is completely independent fromthe AD-converters it can be used for any other purpose, whileits frequency does not need to be equal to an externally gen-erated sampling clock. The RF clock is always generated bythe SY1017C, even if the PLL is disabled. The reference fre-quency for the PLL and the RF front-end are typically gener-ated by a TCXO or OCXO reference via a frequency divider.Configuration of this divider is hard-wired to guarantee properclock frequencies under all conditions.

A register block allows control of configuration and powermanagement for both the SY1017C and the SY1007 orSY1008 attached to it. Power modes as well as PLL registerson both the SY1017C and the RF front-end are programmedthrough this register block. Access to the register block isthrough an interface similar to a Serial Peripheral Interface(SPI).

Since the SY1017C mainly targets the space market, avariant qualified to ESA ESCC9000 for satellite applicationsis available. This variant has demonstrated latch-up and ra-diation damage free operation. The SY1017C comes into acompact 6mm x 6mm ceramic-metal hermetic BGA packagecontaining no organic materials.

2 Features

• Interface IC between SY1007 or SY1008 and a GNSSbase-band processor.

• Direct interface to ESA AGGA-4 processor.• Signal bandwidth up to 24MHz, fs ≤50MHz.• Compact, low bill-of-materials, small PCB area.• Low voltage operation, low power consumption.• Compact 6mm x 6mm ceramic-metal BGA package.

3 Applications

• Space-borne GNSS receivers.• Precise orbit determination.• Antenna arrays, beam forming, attitude determination.• Multi-frequency precision/monitoring GNSS receivers.• Reliable GNSS receivers, safety of life.

Figure 1: SY1017C Block Diagram.

C1

C2

E5 D1 F4

C5

C6

D5

D6

E6

F5

F6

B6

A6

A5

B5 C4 D4 E4 B4 A4 B3 A2 D2 D3C3

F2E3F3

E1E2F1

A1

B1

B2

A3

Loopfilter

To bbprocessor(I/Q dataand clock)

To SPI-likeinterface

DVDD

C1

C2R1

C3

C4

C5

C6

TCXO

on off

Fro

m R

F fr

ont-

end

Fro

m R

F fr

ont-

end

IIP

IIN

IQP

IQN

VBG

AGCO

DIO

RCP

AVDDDVDD

3 D0[2:0]

D1[2:0]3

SCK

CKO

VBG

SEL[3:0]

RCP

MISO

CS_B

AVSS

DVDD

:2:16

DIO

bias

VOSC

8bit AGCDAC

:4:63

PFC

AGCO

AVDD

I0P

I1P

LF

MOSIreg

FREF

DVSS

SY1017C

BEN

I0N

I1N

ADC-3bit(flash)

ADC-0

ADC-3bit(flash)

ADC_1

Copyright c©2014 Saphyrion SAGL. All Rights Reserved. All trademarks and registered trademarks are the property of their respectiveowners. Saphyrion SAGL reserves the right to change the detail specifications as may be required to permit improvements in the designof its products. Saphyrion SAGL assumes no responsibility for this product’s use, nor for any infringement of patents or other rights fromthird parties which may result from its use. No license is implied under any patent or patent right by Saphyrion SAGL.

Saphyrion SAGL, CH-6934 Bioggio, Switzerland, http://www.saphyrion.ch 1


4 Absolute Maximum Ratings

Max. supply voltage, AVDD, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 4.0VESD susceptibility, HBM, JESD22-A114 . . . . . . . . . .Class 1B, 1KVContinuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mWCurrent on any input pin and LF . . . . . . . . . . . . . . . . . . . . . . . . . .±1mACurrent on any output and I/O pin except LF . . . . . . . . . . . . ±10mACurrent on analog supply pins (AVDD) . . . . . . . . . . . . . . . . . .±10mA

Current on digital supply pins (DVDD) . . . . . . . . . . . . . . . . . . .±50mAOperating junction temperature . . . . . . . . . . . . . . . . . −55 to +125CStorage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .−65 to +150CLead temperature (soldering, 40s) . . . . . . . . . . . . . . . . . . . . . . . . 240CVoltage on any pin . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V / xVDD+0.3

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Absolute maximum ratings areshort term stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the recommendedoperating conditions is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

ESD sensitive device: Use proper precautions when handling this device.

Pb Device contains lead: Product is not RoHS compliant and shall be handled accordingly. Do not disperse into the environment.

5 Electrical Characteristics

AVDD = 2.4V to 3.6V, DVDD = 2.2V to AVDD+0.2V, f(FREF) = 10.0MHz, f(SCK) = 50MHz, Tjunction = −40C to +125C, no load, unlessotherwise stated. All voltages are referred to their respective VSS. Typical values are at AVDD = 3.0V, DVDD = 3.0V, Tcase = +25C.

Parameter Conditions Min Typ Max Unit Notes

3-bit I/Q AD-ConvertersAnalog InputFull-scale range Differential ±600 mVppCommon-mode voltage To AVSS 570 600 630 mV 1Input resistance Differential 32 40 48 kΩInput bandwidth FS, sine, −3dB 25 60 MHz 2AccuracyResolution No missing codes 3 bitDC offset error ±50 mVGain error VBG=1.2V ±10 %FSR 3DNL 0.5 1 LSBINL 0.5 1 LSBSFDR Input: 1MHz sine −22 dBcDynamicsSampling frequency Pin SCK, CMOS levels 0 50 MHz 5Aperture time 2 nsDigital OutputsThreshold voltages 111→110 −700 −600 −500 mV

110→101 −500 −400 −300 mV101→100 −300 −200 −100 mV100→011 −100 0 +100 mV011→010 +100 +200 +300 mV010→001 +300 +400 +500 mV001→000 +500 +600 +700 mV

8-bit AGC DA-ConverterAnalog OutputOutput voltage range VBG=1.2V 0 0.2-2.1 2.2 V 3Output resistance 10 Ω

Output current −100 100 µAOutput bandwidth FS, sine, −3dB 1 kHzAccuracyResolution No missing codes 8 bitDC offset error ±10 mVGain error ±5 %FSR 3Gain error drift Over temperature ±5 %FSR 3DNL 1 4 LSBINL 1.5 4 LSB

2 Saphyrion Sagl Rev. 1.5, January 30, 2014



Reference Voltage Input

Input voltage range Pin VBG (E6) 1.1 1.2 1.3 V 4Input impedance Pin VBG (E6) 80 120 160 kΩ 4

Frequency synthesizer, VCO

VCO frequency range See note 5! 20 80 MHz 5VCO sensitivity 60 90 130 MHz/VVCO signal duty cycle 20MHz to 80MHz 40 75 %PLL main divider range 4 63PFC gain 6.7 7.96 9.55 µA/radPFC output current PLL loop filter, pin F6 40 50 60 µAPFC voltage swing Pin F6 0.2 2.0 VPFC leakage current Pin F6, at 125C 10 nAPLL SSB phase noise 100Hz offset −65 dBc/Hz 6

1kHz offset −65 dBc/Hz10kHz offset −58 dBc/Hz100kHz offset −60 dBc/Hz1MHz offset −88 dBc/Hz10MHz offset −112 dBc/Hz

PLL spurs Recommended loop filter −40 dBc

Reference Buffer and DividerInput level, sine wave Analog, AC-coupled 0.4 1.0 1.5 Vpp 7Input low level, VIL Digital, DC-coupled −0.2 0.3 DVDD V 8Input high level, VIH Digital, DC-coupled 0.7 DVDD DVDD+0.2 V 8Operating frequency 32 MHzReference divider range 2 16

Digital Interface

Input capacitance All digital pins 1.0 pFInput high level 0.7 DVDD DVDD+0.2 VInput low level −0.2 0.3 DVDD VOutput high level I(OH) = −1mA 0.9 DVDD VOutput low level I(OL) = +1mA 0.1 DVDD VSerial Interface (RCP, DIO, CS B, MOSI, MISO)Setup time RCP to DIO, CS B, MOSI 15 nsHold time RCP to DIO, CS B, MOSI 0 nsPropagation delay L→H RCP to MISO, 3.0V, 125C 2.4 6.4 ns 9Propagation delay H→L RCP to MISO, 3.0V, 125C 4.0 5.7 ns 9Output rise time 10-90%, 3.0V, 125C, Cl=5pF 3.4 4.9 ns 10Output fall time 90-10%, 3.0V, 125C, Cl=5pF 2.8 3.8 ns 10AD-Converter Output (SCK to D0[2:0]-D1[2:0])SCK cycle time 20 nsPropagation delay L→H 3.0V, 125C 0.5 2.0 4.0 ns 9Propagation delay H→L 3.0V, 125C 0.5 3.2 4.5 ns 9Output rise time 10-90%, 3.0V, 125C, Cl=5pF 3.4 4.9 ns 10Output fall time 90-10%, 3.0V, 125C, Cl=5pF 2.8 3.8 ns 10

Power Supply

Supply Voltage Analog AVDD 2.4 3.6 VDigital DVDD 2.2 AVDD+0.2 V

Supply Current Fully active AVDD 1.3 1.7 2.2 mA 11DVDD 2.0 mA 12

AD/DA active AVDD 1.1 1.6 2.1 mA 11DVDD 1.0 mA 12

PLL active AVDD 140 300 415 µA 11DVDD 1.0 mA 12

Sleep AVDD 100 nA 11DVDD 10 µA 12

Rev. 1.5, January 30, 2014 Saphyrion Sagl 3



Thermal CharacteristicsOperating temp. range Guaranteed performance −40 +125 C

No degradation −55 +125 CThermal resistance Rth Junction to case 25 C/W

Radiation CharacteristicsTotal dose (C60) 100 kRad(Si)Dose rate (C60) 12 Rad/min

LET No latch-up 84.8 MeV cm2

mg 13

Notes

Note 1: AD-converter is internally biased, do not force. These inputs shall be AC-coupled, 100nF is recommended.Note 2: Input bandwidth is limited to reduce aliased noise. AD-converter should not be used to subsample a high frequency IF signal.Note 3: DAC is inverting, gain depends from VBG. Gain error is uncritical in this application, AGC will compensate all gain errors.Note 4: Typically supplied by SY1007 or SY1008 RF front-end. Precautions shall be taken to avoid injecting noise into VBG.Note 5: VCO is tested to 80MHz. AD-converters shall however not be operated above their 50MHz maximum sampling frequency limit.Note 6: Closed PLL loop, RCP = 2MHz, with 33µF decoupling capacitors on VBG pin to reduce noise of bias circuit.Note 7: Reference buffer accepts the 1Vpp clipped sine signal of a TCXO/OCXO directly (AC-coupled).Note 8: A digital clock signal can be applied directly (DC-coupled) to reference buffer.Note 9: Measured from 50% point of RCP to 10% point of MISO and DIO, or from 50% point of SCK to 10% point of D0[2:0] and D1[2:0].Note 10: Measured between the 10% and 90% points. Load capacitance on these pins must be minimized (preferably below 5pF).Note 11: AVDD supply current increases with temperature (due to temperature compensation, see Figure 13).Note 12: On test board without load. Values depend on capacitive load and activity (VCO frequency, AD-converters activity).Note 13: DUTs have been tested at 85C and xVDD=3.6V until a cumulated fluence of 1E+7 ions/cm2 without detecting any latch-up.

6 Device Marking

The marking of the device is in accordance with the requirements of ESCC Basic Specification No. 21700. The informationto be marked on the component shall as a minimum be:

• Terminal identification.• Component number.• Traceability information.

Engineering model marking may occasionally deviate from the specification shown here. Please consult with Saphyrion incase of doubt.

SY1017CR – Engineering Model (EM) Marking

A1 dot and die part number: 17C=SY1017C.

YYWW = Year and week of sealing.

R = EM part, xxx = Unique serial number.

17CYYWW

Rxxx

SY1017CS – Flight Model (FM) Marking

A1 dot and die part number: 17C=SY1017C.

YYWW = Year and week of sealing.

S = FM part, xxx = Unique serial number.

17CYYWW

Sxxx



7 Typical Operating Characteristics

Figure 2: ADC transfer char.

Out

put C

ode

-0.4 0.2Input Voltage (V)

0.40

111

101

011

001

000

-0.8

110

100

010

0.6 0.8-0.6 -0.2

Figure 3: ADC SFDR 1.0MHz.

Am

plitu

de (

dB)

5 15Frequency (MHz)

2010

0

-20

-40

-60

-800 25

Figure 4: ADC SFDR 10MHz.

Am

plitu

de (

dB)

5 15Frequency (MHz)

2010

0

-20

-40

-60

-800 25

Figure 5: DAC output vs. code.

DA

C o

utpu

t vol

tage

(V

)

63 191DAC code

255127

2.0

1.5

1.0

0.5

0.000

2.5DAC 301DAC 311

2 devices

Figure 6: DAC INL vs. code.

DA

C IN

L (L

SB

)

63 191DAC code

255127

+0.5

0.0

-0.5

-1.0

-1.5

00

+1.0

+1.5

+2.0

-2.0

DAC 301DAC 311

2 devices

Figure 7: DAC DNL vs. code.

DA

C D

NL

(LS

B)

63 191DAC code

255127

+0.2

0.0

-0.2

-1.000

+1.0

+0.4

+0.6

+0.8

-0.4

-0.6

-0.8

DAC 301DAC 311

2 devices

Figure 8: VCO freq. vs. AVDD.

Fre

quen

cy (

MH

z)

0.5 1.5Tuning Voltage (V)

2.01.0

200

120

00.0 2.5

40

80

160

3.6V

3.0V

2.4V

Tj = 25°C

Figure 9: VCO freq. vs. temp.

Fre

quen

cy (

MH

z)

0.5 1.5Tuning Voltage (V)

2.01.0

200

120

00.0 2.5

-40°C

25°C

125°C

AVDD=3.0V

40

80

160

Figure 10: I(AVDD) vs. temp.

2.2

1.0

1.8

I

(m

A)

-60 -30 120

1.4

0 30 60 90Temperature (°C)

AV

DD

2.0

1.6

1.2

2.4V

3.6V 3.0V

ADC-ON mode

Figure 11: VCO phase noise.

Pha

se n

oise

(dB

c/H

z)

1k 100kFrequency offset (Hz)

1M10k

-50

-60

-70

-80

-90

100-100

f(VCO) = 50MHz f(RCP) = 2MHz

Figure 12: VCO phase noise.

Pha

se n

oise

(dB

c/H

z)

1k 100kFrequency offset (Hz)

1M10k

-50

-60

-70

-80

-90

100-100

f(VCO) = 50MHz f(RCP) = 5MHz

Figure 13: I(AVDD) vs. temp.

2.2

1.0

1.8

I

(m

A)

-60 -30 120

1.4

0 30 60 90Temperature (°C)

AV

DD

2.0

1.6

1.2

2.4V

3.6V

3.0V

Active mode



8 Pin Description

A

1

B

C

D

E

F

2 3 4 5 6

Figure 14: SY1017C pin-out (top view).

Name Ball Domain DescriptionMISO A1 DVDD Serial interface: master in slave out, test: scan output.SEL[0] A2 DVDD Reference divider, bit 0, test enable.FREF A3 DVDD TCXO/OCXO clock input (1Vpp clipped sine or full swing digital).SEL[2] A4 DVDD Reference divider, bit 2, test enable.RCP A5 DVDD Reference clock for SY1007/SY1008, PLL and serial interface.DIO A6 DVDD Single wire interface for SY1007/SY1008, needs a weak pull down.

MOSI B1 DVDD Serial interface: master out slave in, test: scan input.CS B B2 DVDD Serial interface: chip select, test: scan enable.

SEL[1] B3 DVDD Reference divider, bit 1, test enable.SEL[3] B4 DVDD Reference divider, bit 3, test enable.AVSS B5 - Negative analog supply voltage.AGCO B6 AVDD 8-bit AGC DA-converter output.SCK C1 DVDD Sampling clock input.CKO C2 DVDD PLL frequency synthesizer output (independent from SCK).BEN C3 - TCXO buffer enable, active low.AVSS C4 - Negative analog supply voltage.I0P C5 AVDD First AD-converter positive input.I0N C6 AVDD First AD-converter negative input.

DVDD D1 - Positive digital supply voltage. Decouple to DVSS close to the chip.DVSS D2 - Negative digital supply voltage.DVSS D3 - Negative digital supply voltage.AVSS D4 - Negative analog supply voltage.I1P D5 AVDD Second AD-converter positive input.I1N D6 AVDD Second AD-converter negative input.

D1[2] E1 DVDD Second AD-converter digital output: bit 2.D1[1] E2 DVDD Second AD-converter digital output: bit 1.D0[1] E3 DVDD First AD-converter digital output: bit 1.AVSS E4 - Negative analog supply voltage.AVDD E5 - Positive analog supply voltage. Decouple to AVSS close to the chip.VBG E6 AVDD 1.2V voltage reference input.D1[0] F1 DVDD Second AD-converter digital output: bit 0.D0[2] F2 DVDD First AD-converter digital output: bit 2.D0[0] F3 DVDD First AD-converter digital output: bit 0.DVDD F4 - Positive digital supply voltage. Decouple to DVSS close to the chip.VOSC F5 AVDD VCO control voltage input.

LF F6 AVDD PLL charge pump output.



9 Equivalent Circuits

Pin Description Equivalent circuit

A1 MISO Digital inputs and outputs DVDD

DVSS

DIO

ESD

ESDRENB, IENB,RCP, DIO

ESD

ESD

DVDD

DVSS

A2 SEL[0]A4 SEL[2]A5 RCPA6 DIOB1 MOSIB2 CS BB3 SEL[1]B4 SEL[3]C1 SCKC2 CKOC3 BENE1 D1[2]E2 D1[1]E3 D0[1]F1 D1[0]F2 D0[2]F3 D0[0]

A3 FREF TCXO/OCXO clock input

ESD

ESD

DVDD

DVSS

BEN/CKD

FREF

B6 AGCO 8-bit AGC DA-converter output AVDD

AVSS

AGCO

ESD

ESD

C5 I0P Analog inputs

I0P-I0NI1P-I1N

VBG, VOSC

ESD

ESD

AVSS

AVDD

C6 I0ND5 I1PD6 I1NE6 VBGF5 VOSC

F6 LF PLL charge pump output

LF

AVDD

UP

DN

AVSS

50µA

50µA

ESD

ESD



10 Circuit Description

The SY1017C is a radiation hardened AD/DA-converterand PLL ASIC. It serves as the interface between theSY1007 or SY1008 RF front-ends and the GNSS base-band processor (typically an AGGA-4). This device con-tains two AD-converters with 3-bit resolution (Section 10.1)meant to convert the I and Q outputs of an RF front-end todigital, an 8-bit DA converter (Section 10.2) meant to con-trol an analog AGC and a PLL (Section 10.3) frequencysynthesizer that generates the sampling clock for the 3-bitI/Q AD-converters. A clock signal buffer (Section 10.4) al-lows a TCXO or OCXO with 1Vpp clipped sine output to bedirectly AC-coupled to the SY1017C. A configuration reg-ister, accessible via an SPI-like interface (Sections 10.6and 11), is used to configure the PLL and to control thepower modes of both the SY1017C and – transparently –the SY1007/SY1008 RF front-end.

10.1 3-bit AD-Converters

These are 50MHz flash AD-converters meant to ac-quire the quadrature GNSS analog signals from the RFfront-end. The AD-converter’s input is differential highimpedance (40kΩ) with a full scale of 1.2Vpp and is avail-able on pins I0P, I0N, I1P and I1N respectively. The 3-bitoffset binary output is available on the D0[2:0] and D1[2:0]buses respectively.

The sampling clock input is on pin SCK. The sampleddata is latched on the rising edge of the sampling clock(Figure 15). Operation of the AD-converter is guaranteedfrom ≈0Hz to 50MHz. These AD-converters are enabledvia the corresponding power mode accessible through theconfiguration register.

I0 I1 I2 I3 I4

Q0 Q1 Q2 Q3 Q4

SCK

D0[2:0]

D1[2:0]

Figure 15: Timing of the AD-converter.

10.2 AGC 8-bit DA-Converter

It is an 8-bit voltage mode current steering DA-converterthat is meant to drive the AGC input of an RF front-end, inparticular the SY1007 or SY1008. The input is accessiblethrough the register file. The coding is straight binary, with0x00 corresponding to an output voltage of 2.092V and0xFF corresponding to 0V nominally.

Since this DA-converter is mainly required to gener-ate DC levels its bandwidth has been limited to about1kHz with an on-chip low-pass filter in the interest of re-ducing noise and glitch energy. The output is buffered,low impedance, and appears on pin AGCO. The AGC DA-converter is enabled together with the I/Q AD-converters,it cannot be controlled separately.

10.3 PLL Frequency Synthesizer

The sampling clock signal is generated by an on-chip VCOand an integer-N PLL. The VCO is a wide range ring os-

cillator covering a frequency range from about 20MHz to80MHz. Although the PLL is tested up to 80MHz the max-imum sampling frequency limit of 50MHz of the 3-bit AD-converters shall be respected. Its output is available on pinCKO (independent from SCK).

The integer-N PLL uses as reference the clock signalapplied to pin FREF divided by the reference divider ratioR. R can be programmed from 2 to 16 via the SEL[3:0]pins. The division ratio 1 is not available and whenSEL[3:0]=0x0 the SY1017C enters test mode. The PLLreference clock is used also by the RF front-end, the se-rial interface and the AGC DA-converter. It is output on pinRCP. The main divider of the PLL can be programmed fromM=4 to 63 via the serial interface by writing the one’s com-plement of M in register PM&PLL. The output frequency ofthe PLL, f(PLL), is (see figure 16):

• f(PLL) = M*FREF/R; 4≤M≤63, 2≤R≤16

The PLL loop filter is connected to pins LF (charge pumpoutput) and VOSC (VCO control voltage input). They arekept separated in order to allow various loop filter topolo-gies to be used. In the simplest case pins LF and VOSCare connected together to a CRC loop filter, otherwise if ahigher order loop filter is desired pin LF shall be connectedto the input of the loop filter and pin VOSC to its output.

Loop Filter

ReferenceOscillator

PLL Out(<50MHz)

SEL[3:0]

(Register)

VCO

M(4-63)

R(2-16)

Figure 16: SY1017C’s PLL configuration.

The PLL can be enabled and disabled independentlyfrom the AD and DA-converters via the power manage-ment register.

When the PLL is disabled pin CKO goes to a logic 0value. Since pins CKO and SCK are independent fromeach other a sampling frequency different from the onegenerated by the on-chip PLL can be used if desired. Iftwo SY1017C are available in an application there is noth-ing bad in using one SY1017C’s PLL to generate the sam-pling clock for both and the other to generate an unrelatedclock signal.

10.4 TCXO/OCXO Buffer

Many high quality TCXOs/OCXOs deliver a 1Vpp clippedsine signal. A buffer amplifier that converts the 1Vppclipped sine signal into a valid full swing digital signal hasbeen included in the SY1017C (pin FREF) in order to saveexternal components. Typically a TCXO or OCXO deliver-ing 1Vpp is AC-coupled to pin FREF. The buffer also ac-cepts a full swing digital clock signal, DC-coupled to FREF,if such signal is available.

The buffer amplifier is enabled by setting pin BEN tologic 0 and needs to be enabled no matter the clock sig-nal type used. With the buffer amplifier disabled its currentconsumption is reduced to a few nA but the SY1017C willnot receive any clock.



10.5 Bias and Reference

The SY1017C requires a 1.2V voltage reference on pinVBG, no on-chip voltage reference has been included. Allcircuits – except serial interface, register file and TCXObuffer – require the voltage reference, both the PLL andthe AD/DA-converters will not operate without it. TypicallyVBG is connected to the SY1007/SY1008’s band-gap volt-age reference, but any (clean) voltage around 1.2V maybe used instead.

10.6 Serial Bus and Register File

A configuration register, accessible via an SPI-like serialinterface, is implemented on the SY1017C. Its purpose isto configure the PLL and to control the power modes ofboth the SY1017C and the SY1007/SY1008 RF front-end.It is accessed through the pins MOSI, MISO and CS B.Caution: the pin MISO is always driven. If multiple slavesneed to share the same bus a tristate buffer is needed.

Although the serial interface is connected only to theSY1017C device, the physical location of the registers istransparent to the interface. If the addressed register isphysically located inside the SY1017C it is accessed di-rectly, otherwise if the register is located on the SY1007 orSY1008 RF front-end the SY1017C will forward the com-mand to it and return data back in case a read operationis requested. The register is protected against SEU with aHamming error correction mechanism.

11 Serial Interface

The SY1017C can be configured by programming its reg-ister file via a synchronous serial interface, which partlyconforms to the SPI standard. It deviates from the SPIspecification in that the clock (RCP) is always generatedby the SY1017C instead of being generated by the mas-ter device. Since the clock is the reference for all PLLs itshall also be always present and cannot be changed in fre-quency. The following can be accessed through the serialinterface:

• Power modes.• PLL main divider.• SY1007/SY1008’s register file (through the DIO

pin).

All SY1017C’s registers are read/write in order to allowreading back their contents for verification purposes. Incase an error is detected (it may only happen under a highradiation environment) the affected register needs to berewritten.

11.1 Communications Protocol

A data communication always consists of two 8-bit blocks.The SY1017C works as a slave and never initiates a com-munication. The master device (a GNSS base-band pro-cessor such as the AGGA-4) signals the start of a com-munications session by setting pin CS B to logic 0, whichneeds to be kept low until the end of the communication,and terminates it by resetting CS B to logic 1. The mas-ter device cannot abort an on-going packet. An abortedpacket may cause register corruption.

The first block, always sent by the master device, spec-ifies the kind of operation required, i.e. read or write, andthe address of the register to be accessed. A parity bit(odd parity) is required, and in case a parity error occursthe operation is aborted. The second 8-bit block containsthe data read or written to the selected register, in LSB-firstform. Communications to the SY1007/SY1008 are simplypassed transparently through pin DIO and have no effecton the SY1017C.

Back-to-back communications (no idle cycles betweentwo consecutive communications) are supported. If CS Bis kept low, the SY1017C is ready to accept a new commu-nication at the clock cycle following the last data bit (D7).That is the first bit of a new packet must immediately followthe last bit of previous packet.

11.2 Timing Diagram

The SY1017C samples CS B and MOSI on the fallingedge of RCP. If requested to return data (read operation),it will force them on the rising edge of the clock. Duringa read operation any data sent to MOSI is simply ignored.Figures 18 and 19 show a write and a read packet respec-tively.

RCP

CS_B

MOSI

MISO D7D6

tcp

tsu

T WR A0

D5

tr tf

tpd th

Figure 17: Serial interface timing diagram.

Name Parameter Min Typ Max Unittcp Clock Cycle time1 200 nstsu Setup time (CS B, MOSI) 15 nsth Hold time (CS B, MOSI) 0 nstpdLH Propagation delay L→H2 4.0 8.5 nstpdHL Propagation delay H→L2 5.5 7.6 nstr Output rise time, 10-90%2 3.6 6.1 nstf Output fall time, 90-10%2 3.3 4.8 ns

Table 1: Conditions: 2.2V, 125C, Cl=5pF.

Name Parameter Min Typ Max Unittcp Clock Cycle time1 200 nstsu Setup time (CS B, MOSI) 10 nsth Hold time (CS B, MOSI) 0 nstpdLH Propagation delay L→H2 2.4 6.4 nstpdHL Propagation delay H→L2 4.0 5.7 nstr Output rise time, 10-90%2 3.4 4.9 nstf Output fall time, 90-10%2 2.8 3.8 ns

Table 2: Conditions: 3.0V, 125C, Cl=5pF.



RCP

CS_B

MOSI

MISO

A1T WR D7A0 A2 P R R D0 D1 D2 D3 D4 D5 D6

Figure 18: SY1017C write packet.

RCP

CS_B

MOSI

MISO

A1T WR

D7

A2 P R

D1 D2 D3 D4 D5 D6

R

D0

A0

Figure 19: SY1017C read packet.

Notes:

1. Limited by the frequency range of the PLL. The ref-erence divider shall be set accordingly.

2. For MISO and RCP (outputs).

11.3 Packet Structure

Each packet performs a register access in either read orwrite mode. A packet consists of 2 bytes: a control bytefollowed by a data byte.

Field Target WR Addr P Res DataPosition 0 1 2:4 5 6:7 8:15

Table 3: Structure of the control word.

Field DescriptionTarget Determines the physical location of the register be-

ing addressed:0 : register is on SY1017C device.1 : register is on SY1007/SY1008 device.

WR Transfer direction:0 : READ operation.1 : WRITE operation.

Addr[0:2] Register address, LSB first.P Parity. It is calculated on Target, Write and Addr

fields. Parity is ODD, i.e. the number of 1’s in bits[5:0] of the control word must be odd.

Res[0:1] Reserved, currently unused.Data[0:7] Write operation: the master sends the data to be

written in register.Read operation: the SY1017C returns the registercontent.

Table 4: Description of the control word.

The control byte is always sent by the master andprovides information on register address and transfer di-rection (read/write), In a write operation the data wordis provided by the master and contains the new registervalue. In a read operation the data word is provided by

the SY1017C and contains the current register value. Thestructure of the control word is shown in table 3 and themeaning of the various fields in the control word is shownin table 4.

11.4 Parity Check

As a means to prevent registers corruption during write un-der a high radiation environment, parity check is performedon the control word. Parity is calculated on the valid fieldsof the control word, i.e. Target, WR and Addr[0:2]. TheRes[0:1] bits are not used to calculate parity. The expectedparity type is odd, i.e. the total number of 1’s in bits [0:5] ofthe control word must be odd. If a parity error is detectedduring a write operation, e.g. a SEU occurs, that operationis immediately aborted, i.e. the data is discarded and thecorresponding register is not updated.

The parity bit is ignored during a read operation,i.e. the data is returned regardless of the value of the paritybit. It is highly recommended that every write is followed bya read operation to verify that the write actually succeededand that the written value is the intended one.

12 Register File

12.1 Register Map

The register map is reported in table 5. This table includesall registers visible through the serial interface, regardlessif they are on the SY1017C, the SY1007 or the SY1008.Locations marked as Reserved are reserved for future de-velopment. To maintain compatibility with new releases ofthe SY1017C no attempt should be made to access theselocations. While in the current release an attempt to ac-cess these locations results in no operation, in future ver-sions it could results in temporary malfunctions. The con-



tent of all registers is undefined until written, there is nodefault value.

AddressTgt RW A0 A1 A2 Device Dir Register

0 0 0 0 0 - R Reserved0 0 0 0 1 SY1017C R PM & PLL0 0 0 1 0 SY1017C R AGC-DAC0 0 0 1 1 - R Reserved0 0 1 0 0 - R Reserved0 0 1 0 1 - R Reserved0 0 1 1 0 - R Reserved0 0 1 1 1 - R Reserved0 1 0 0 0 - W Reserved0 1 0 0 1 SY1017C W PM & PLL0 1 0 1 0 SY1017C W AGC-DAC0 1 0 1 1 - W Reserved0 1 1 0 0 - W Reserved0 1 1 0 1 - W Reserved0 1 1 1 0 - W Reserved0 1 1 1 1 - W Reserved1 0 0 0 0 RF R RF-PLL1 0 0 0 1 - R Reserved1 0 0 1 0 RF R Pwr Modes1 0 0 1 1 - R Reserved1 0 1 0 0 SY1007 R IF-PLL1 0 1 0 1 - R Reserved1 0 1 1 0 SY1008 R VCO-CT1 0 1 1 1 SY1008 R VCO-LF1 1 0 0 0 RF W RF-PLL1 1 0 0 1 - W Reserved1 1 0 1 0 RF W Pwr Modes1 1 0 1 1 - W Reserved1 1 1 0 0 SY1007 W IF-PLL1 1 1 0 1 - W Reserved1 1 1 1 0 SY1008 W VCO-CT1 1 1 1 1 SY1008 W VCO-LF

Table 5: Register map.

12.2 Register Fields

The meaning of the fields of all registers is shown in ta-ble 6. All registers visible from the SY1017C’s serial in-terface are shown, i.e. also those located on the SY1007and SY1008 RF front-end devices. Obviously those latterregisters are only visible if either a SY1007 or a SY1008is connected to the SY1017C. An operation to a SY1007

register when the SY1008 is used or vice-versa results inno operation and will not disturb normal operation of theSY1017C, the SY1007 or the SY1008.

Please note: the division factor of the SY1017C’s PLLmain divider is in one’s complement, i.e. bits 0 to 5 of reg-ister PM&PLL shall be inverted (PM&PLL[0:5] = M[0:5]).

12.3 Hamming Error Correction

As a means to protect the register’s content from singleevent upset (SEU) errors that may occur under high radia-tion, Hamming error correction has been implemented onall registers. This error correction mechanism is able tocorrect up to one error per register per clock cycle.

To implement Hamming error correction 12-bit regis-ters are used, as shown in figure 20. Each register holdsthe actual data value and 4 check-sum bits. During a reg-ister write cycle the new check-sum is computed by thegeneration matrix and stored in the register together withthe actual data.

Error-correction occurs on each clock cycle (exceptduring register write cycle). The correction matrix com-putes corrected data out of the data stored in the 12 bitregisters and rewrites it back at the following clock fallingedge, thus removing any single SEU error. Every registerhas its independent error correction system, thus severalsimultaneous errors will be corrected as long as they occurin different registers.

The various circuit blocks of the SY1017C receive datadirectly from the correction matrix rather than from the out-put of the registers. This ensures that in case of a SEU er-ror the correct value is available immediately within a com-binational delay and not with a clock cycle latency. Glitchsuppression logic removes the eventual error correctionglitch, as well as single event transient (SET) glitches.

During a read operation, if a SEU occurs in the sameclock cycle when data is latched by the read shift register,the incorrect value might be returned back, although thecontent of the register itself will be corrected on the nextclock cycle.

ErrorCorrection

HammingCode

Generator

HammingCode [3:0]

Data [7:0]

C[3:0]

D[7:0]

0

1

0

1

WR

RCP

DI[7:0]DO[7:0]

Figure 20: Hamming error correction register.



Register Bits Count Field Description TypeSY1017C 0:5 6 PLL Division Factor PLL division factor: RWPLL and M020

+ M121+ · · ·+ M525

Power Modes 6 1 PLL Enable Active = HIGH RW7 1 ADC/DAC Enable Active = HIGH RW

AGC-DAC 0:7 8 AGC-DAC DAC digital input: RW0 = Vref−1LSB; 255 = 0V RW

SY1007 & SY1008 0:1 2 Power Modes 00=Sleep RWPower Modes 01=Doze

11=Stand-By10=Fully active

2:7 6 (Reserved) Currently ignored, set to 0 N/ASY1007 & SY1008 0:7 8 RF-PLL Divider RF-PLL division factor: RWRF-PLL D020

+ D121+ · · ·+ D727

SY1007 0:7 8 IF-PLL Divider IF-PLL division factor: RWIF-PLL D020

+ D121+ · · ·+ D727

SY1008 VCO 0:3 4 VCO Coarse Tuning RF-VCO coarse tuning: RWCoarse Tuning 0000=highest frequency

1111=lowest frequency4:7 4 (Reserved) Currently ignored, set to 0 N/A

SY1008 PLL 0:2 3 PLL Voltage PLL loop filter voltage readout. RVoltage 3:7 5 (Reserved) Currently ignored, set to 0 N/A

Table 6: Register fields description.

13 SY1007/SY1008 Interface

Communication between SY1017C and SY1007 orSY1008 occurs through a single wire synchronous bidi-rectional interface: pin DIO. This interface – that is syn-chronous to RCP and thus with the serial interface – ismanaged in a transparent way by the SY1017C. Thismeans that SY1007/SY1008’s registers are accessed asif they were implemented into the SY1017C.

Packets are always originated by the SY1017C. Apacket consists of a start bit, followed by 6 bits (read) or7 bits (write) depending on the operation requested, thenby 8 data bits. The start of a communication is signaled bythe DIO line being pulled high. The SY1007/SY1008 sam-

ples the DIO line on the falling edge of RCP. If requested toreturn data (read operation), the SY1007/SY1008 will driveDIO and send data bits on RCP falling edge. At the end ofa communication the DIO line goes low and the interfaceremains idle as long as the DIO line is kept low.

Figure 21 shows the structure of a write and a read op-eration to the SY1007/SY1008 devices. ST is the start bitwhile the other fields have the same meaning as shown intables 3, 4, 5 and 6. The bits read back during a read op-eration are synchronized with the rising RCP edge beforebeing transmitted on the MISO line (see figure 19).

A more complete description of the serial interface ofthe SY1007 and SY1008 devices is given in their respec-tive data sheets.

RCP

DIO(W)

DIO(R) A1ST WR D7A2 P D1 D2 D3 D4 D5 D6R D0A0

A1ST WR D7A0 A2 P R R D0 D1 D2 D3 D4 D5 D6

Figure 21: SY1007 and SY1008 read and write packets.

14 Application Information

The SY1017C is an AD/DA-converter and frequency syn-thesizer ASIC meant for use in GNSS receivers for spaceapplications. Its main purpose is to serve as the inter-face between an RF front-end (typically a SY1007 or aSY1008 ASIC) and a base-band processor (typically anESA AGGA-4). It may be used also for different purposeshowever, such as e.g. as a general purpose clock genera-tor or AD/DA-converter if desired.

14.1 3-bit AD-Converters

The input buffer of the AD-converters is internally biased toVBG/2 (typically 600mV). No external circuitry is requiredto bias this circuit, but bias must be maintained to prop-erly use the converter. If the common-mode bias is forcedor otherwise not maintained the AD-converter will clip anddistort the signal heavily.

The best way to avoid any bias shift is to AC-couple theRF front-end’s output to the SY1017C’s input as shownin Fig. 22. 100nF ceramic X7R capacitors are recom-



mended. If the application requires DC-coupling then theDC bias of the driving circuit shall be set to VBG/2. A servocircuit as shown in Fig. 23 may be used.

C1100nFC2

100nFC3100nFC4

100nF

C5

1.0nF

SY1007SY1008

OIN

OIP

OQN

OQP

AGCI

I1N

I1P

I0N

I0P SY1017

AGCO

Figure 22: Typical SY1017C to front-end interface.

Rb

RbCdCc

Ra

Ra

Vcm

DifferentialBuffer

IN+

IN−

VBG

IxP

IxN

Figure 23: Common-mode servo loop.

Since the common-mode voltage range of the AD-converters is rather limited, they shall be driven with a dif-ferential signal: driving them with a single-ended signal willagain result in signal clipping and distortion. Since clippingin this case will be asymmetrical, a large DC-offset mayalso result. DC offset will always disturb GNSS receptionin near base-band I/Q architectures, in fact a DC-offset isexactly equivalent to an in-band interferer.

The sampling clock input is on pin SCK. The AD-converters support a sampling frequency up to 50MHz.When the internal clock generator is used, SCK shall beconnected to pin CKO, otherwise it may be connected to asuitable external clock source.

If an external sampling clock source is used, it shallprovide a CMOS-compatible signal swing with a duty cy-cle between 40% and 60%. An external level shifter shallbe used if the available sampling clock signal conforms toa different standard.

Please note that even if the sampling clock frequencysynthesizer is tested to 80MHz, the sampling clock of theAD-converters shall not be set above 50MHz. The opera-tion of the AD-converters is not guaranteed above 50MHz.

14.2 AGC 8-bit DA-Converter

The AGC DA-converter is a combinational current steeringdesign. It therefore requires no clock and its output is up-dated when the converter’s register (address 010) is writ-ten. Please note that the DA-converter is inverting, i.e. theoutput is reversed with respect to the input code: the code0xFF corresponds to 0V while the code 0x00 correspondsto 2.2V (see Figure 5, Section 7).

The output of the converter is a voltage, through alow impedance buffer with a compliance of ±100µA. It ismeant to drive the SY1007/SY1008 AGC input and its out-put voltage range has been taylored for this purpose. TheSY1017C’s AGCO pin can therefore be connected directlyto the SY1007/SY1008 AGCI pin as shown in Fig. 22.

In the interest of reducing noise on the AGCO output a2nd order RC active filter with about 1kHz bandwidth has

been included. A capacitor of about 1nF – ceramic COGor X7R – should be connected between pin AGCO andAVSS to further reduce high frequency noise.

Since the SY1017C has no negative supply voltageavailable, the output will be clipped near the negative railand a few codes near 0xFF will be lost. This will be ofno consequences in its application as AGC driver but mayneed to be taken into consideration if the DA-converter isused for some other purposes. Under typical conditionsthe output will be clipped to about 200mV above AVSS.

Given that the DNL of the DA-converter is specifiedas 4 LSB maximum, monotonicity is not guaranteed. If theconverter is used inside a regulation loop (AGC is a regula-tion loop indeed) an algorithm tolerant to non-monotonicityshall be used, otherwise the loop might become instable orget stuck at non-monotonic steps of the converter.

14.3 PLL Frequency Synthesizer

This frequency synthesizer is meant mainly to generatethe sampling clock of the AD-converters. Other uses arehowever possible as long as all its specifications are re-spected.

The reference divider (R, see Figure 16) can be pro-grammed via the SEL[3:0] pins. Hard programming is infact necessary to guarantee that RCP – and thus the serialinterface – is always present and has the proper frequency.Typically the reference divider should be programmed todeliver about 2 to 5MHz on RCP: if the frequency is toolow the SY1007/SY1008 front-end will not work, if the fre-quency is too high frequency plan selection will be toocoarse. Please see SY1007/SY1008 data sheets. HigherRCP frequencies will however lead to improved PLL phasenoise, which ideally improves by 3dB for every doubling ofRCP frequency (see Figures 11 and 12).

The main divider (M in Figure 16) shall be programmedvia the serial interface (see Table 6). Please note that themain divider contains a random value at power up andneeds to be programmed properly before using the PLL.This means that the PLL cannot be used as the main clocksource. Random behavior and possibly deadlocks will re-sult if this is attempted.

Although the PLL is tested up to 80MHz, it is recom-mended not to use it above 50MHz when configured assampling clock generator for the AD-converters (the AD-converters will not work above 50MHz). If used for otherpurposes attention is still required not to operate it beyondits 20MHz-80MHz limits. The VCO may in fact stop at fre-quencies above 80MHz (typically the VCO stops around120-150MHz under worst-case conditions).

Please note that the duty cycle of the VCO (pin CKO)is not 50% (see specifications, Section 5). All circuits con-nected to CKO shall be able to accept the duty cycle asspecified. A divider by 2 may however be used to achievea 50% duty cycle, should this be required.

R1

C1

C21.8kΩ

LF VOSC

8.2nF

1.0nF

Values shown are forRCP frequency = 2MHz

Figure 24: Recommended PLL loop filter.



The loop filter is external and needs to be connectedto pins LF and VOSC. A possible CRC loop filter with rec-ommended values (for RCP = 2MHz) is shown in Fig. 24.Loop filters with different time constants or higher orderconfigurations may be used as well to get a different bal-ance between phase noise and spuriae (lower time con-stants yield improved phase noise at the expense of higherpower spuriae).

14.4 Reference Clock (FREF)

The SY1017C accepts as reference clock both a 1Vpp(clipped) sine or a full swing digital signal. A TCXO orOCXO delivering 1Vpp shall be AC-coupled to pin FREFwith a ≥1nF COG ceramic capacitor. Lower quality di-electrics – such as X7R or X5R – should be avoided. PinFREF will self-bias to the bias level required for proper op-eration and shall not be forced, otherwise erratic behavioror no operation may result. If a full swing CMOS digitalclock signal is available, it shall be DC-coupled to FREF.In order to operate the SY1017C the buffer shall be turnedon (with pin BEN, active low), no matter the clock signaltype used.

In order to obtain proper performances from theSY1017C (and the associated SY1007/SY1008 RF front-end) it is important that the clock signal is clean and with-out glitches. The following recommendations should beadhered to:

• Avoid powering the analog section of the SY1017Cor the clock source (OCXO) with a digital VDD, aclean supply voltage is required.

• Avoid running reference clock and digital or highpower RF signals in parallel.

Glitches on an otherwise clean clock signal may also ap-pear due to SET. In order to reduce likelihood of SET onthe reference clock line a strong clock source, possibly ter-minated close to the SY1017C, may be used.

14.5 Reference Voltage

The SY1017C requires a 1.2V voltage reference onpin VBG. Typically the reference voltage is taken fromSY1007/SY1008’s band-gap reference, but any clean 1.2Vreference voltage already available into the applicationmay be used instead. The reference is used by both the3-bit AD-converters and the AGC DA-converter to set thegain, while all bias voltages and currents for the convert-ers and the PLL are derived from it. This means that boththe converters and the PLL will not work without a 1.2Vreference on pin VBG. On the other hand, the serial inter-face, the register file and the clock buffer operate indepen-dently from the voltage reference. The SY1017C thereforeis always accessible and may be used to enable the volt-age reference (by setting the SY1007/SY1008 into Dozeor higher modes).

Since VBG is used as reference for the converters,any noise injected into it will appear at the converter’s out-put. Since the converters are multiplicative, intermodula-tion products may be generated as well. Therefore do notinject any noise into VBG if proper performance is to beachieved. In order to reduce high frequency noise, a 10nFto 100nF capacitor is required on pin VBG. The capaci-tor already mounted on the SY1007/SY1008’s band-gap

reference is sufficient, provided that a low inductance con-nection exists between that capacitor and the SY1017C,otherwise a separate capacitor shall be mounted as closeas possible to the VBG pin.

14.6 Communications

The serial interface of the SY1017C is partly compliant tothe SPI standard (Sections 10.6 and 11). It deviates fromthe SPI specification mainly in that the clock is always gen-erated by the SY1017C instead of being generated by themaster device. This means that the SY1017C cannot beused on a standard SPI bus. This deviation was introducedas a means to both permit transparent communication tothe SY1007/SY1008 front-end and to reduce the likelihoodof self-interference.

The SY1017C samples data on the falling edge of RCP(see Fig. 17). It is therefore safest to synchronize the serialinterface (i.e. change the data) on the rising edge of RCP.During a read operation the SY1017C returns data on theMISO line; any data on MOSI during a read operation issimply ignored and has no consequence on SY1017C’soperation.

A communication, once initiated, cannot be abortedand shall be completed. An attempt at aborting a com-muncation may result in data corruption. To recover froman operation abort attempt the register file needs to beread back and possibly corrupted data rewritten. After 16clock cycles from the start of a communication (includingan aborted one) the SY1017C’s serial interface is ready fora new communication.

Under typical conditions the SY1017C is the only slaveon the serial bus. Consequently MISO is always drivenand is NOT tristate when the SY1017C is not selected. Ifother SY1017C needs to be connected to the same serialbus, tristate buffers are necessary on the MISO pin of allSY1017C. The tristate buffer needs to be enabled togetherwith the SY1017C to which is connected.

Other SPI-compliant devices may be connected to thesame bus as long as they can operate at the selectedRCP frequency and never attempt to drive RCP. The tris-tate buffer shall again be attached to the MISO pin of allSY1017C’s sharing the same bus.

Communications to the SY1007 or SY1008 RF front-ends are made via the DIO line. In order to prevent com-munication errors or the unintentional restart of a commu-nication at the end of the previous one (especially if it wasa read cycle), the DIO shall be prevented from floating. A10kΩ pull-down resistor is recommended.

14.7 Power Management

The SY1017C provides low latency power modes that canbe used to implement various power saving schemes. TheAD/DA-converters and the PLL frequency synthesizer canbe enabled independently from each other. The powermodes can be accessed through a register (address 001),please see table 6.

At power on all registers, including the power modesregister, are in a random state and need therefore to be ini-tialized. The SY1017C will however always behave prop-erly, with no high-current or abnormal states, for whateverregister contents. The OCXO buffer, the reference divider



and the register file are not affected by the power manage-ment and remain fully operational in any power mode.

14.8 Power Supply

The SY1017C requires two power supplies: analog(AVDD) and digital (DVDD). The power supplies need notbe well regulated but must be well filtered. This applies inparticular to the analog power supply AVDD.

No particular sequencing is needed while applyingpower to the SY1017C. AVDD and DVDD may be appliedsimultaneously or in any order. Increasing DVDD aboveits maximum operating level (AVDD+0.2V) is not recom-mended except during the power on transient. This will notcause any permanent damage, but the SY1017C will notoperate correctly if the condition is violated. Once DVDDis returned to the allowed range the SY1017C will resumeproper operation from itself while no data is lost if DVDD iskept above its minimum rating of 2.2V.

Signal voltages shall not be applied to the SY1017Cbefore the power supply is applied, otherwise ESD protec-tion diodes may become forward biased and possibly bedamaged. Digital signals may track DVDD during powertransients, as long as the DVDD+0.2V condition is not vio-lated.

Good power supply decoupling is always required. A100nF ceramic capacitor (X7R) mounted very close to thedevice body is recommended on each AVDD and DVDDpin. A 2.2µF (or higher) ceramic or tantalum capacitor maybe required on AVDD, especially if AVDD is not well regu-lated.

15 Handling Precautions

15.1 Hazardous Substances

The SY1017C’s solder balls contain lead (Sn60-Pb40),therefore the SY1017C is not RoHS compliant and shallbe handled accordingly. Discarded SY1017C devices shallnot be dispersed into the environment or disposed of withcommon waste.

Apart from the lead contained in the solder balls, theSY1017C does not contain any other hazardous mate-rials, in particular no mercury (Hg), cadmium (Cd) orhexavalent chromium (Cr6+), the flame retardants poly-brominated biphenyls (PBB) and polybrominated diphenylethers (PBDE), or berillium oxide (BeO) ceramic.

15.2 Storage

The SY1017C is packaged in a ceramic-metal packagethat is not sensitive to humidity, however improper stor-age may cause contamination or oxidation of the solderballs thus impacting solderability. The product shall notbe exposed to high humidity or to direct sunlight, harm-ful/corrosive gases or dust. Also avoid storing it in loca-tions where sudden temperature changes may occur.

To ensure long shelf life, the product should be storedin a controlled temperature (≈20-25C) and humidity(<60%) environment, possibly in its original shipping bag.Do not open the bag until just before product’s use. If long-term storage of several years is anticipated, the productshould be stored in a dry cabinet.

16 Radiation Tolerance

The SY1017C is a rad-hard device and several counter-measures have been taken during its design to achievea high degree of radiation tolerance. The extensive use ofguard rings and other latch-up prevention techniques – es-pecially in the I/O area – yields excellent latch-up immunity.Heavy ion tests up to a LET of 84.8MeV cm2

mg have proventhe chip’s robustness against both latch-up and SEU. Sev-eral DUTs have been tested at temperatures up to 85Cand a maximum supply voltage of 3.6V until a cumulatedfluence of 1E+7 ions/cm2 without detecting any latch-up.

All registers are protected against SEU with a Ham-ming error correction mechanism, while a parity bit pro-tects communications from the master device to theSY1017C. It is however good practice not to rely on thebuilt-in SEU protection alone. It is recommended that aftera write operation a read operation to the same register isperformed, while all registers should periodically be readback (every few seconds) to check their contents. If cor-rupted data is found then re-read the register, if the datais still wrong then rewrite the register and check it again.Checking back the registers is the first thing to do in caseof suspicion of configuration loss of the device (e.g. if thereceiver stops working suddenly).

Clock lines (FREF and RCP) may also be subjectto SET that may cause glitches. These are the effectsof SET glitches on the clock lines of the SY1017C (andSY1007/SY1008 devices):

• During programming a clock glitch may (will) corruptthe data, as the glitch is interpreted as an extra clockcycle thus the communication gets misaligned. Thiscan be guarded against by reading back the reg-isters just after programming and rewriting them incase of corruption.

• Clock glitches will disturb the PLL. Single glitcheswill however not cause any cycle skip, loss of lock orsimilar effects. At most only a small phase jump,which will disappear within a few ms, may occur.Cycle skips would only be possible if several clockglitches appear consecutively within a few ms, whichis however very unlikely to happen.

• If no communication is being made, clock glitches ofat least about 10ns will not cause registers corrup-tion, misbehavior of the interface, error correction orother parts of the chip except the PLL.

• Very short clock glitches (below about 10ns) mayoccasionally cause some data corruption due to in-ternal timing violations even if no communication isbeing made. By reading the registers back periodi-cally such data corruptions can be easily found andcorrected.

Whatever glitch of whatever length may appear on clock orsignal lines, it will not affect SY1017C’s reliability or put itinto some unstable or unrecoverable state. Should a clockglitch cause whatever trouble to the SY10xx chips it is suf-ficient to reprogram them to have them back to proper op-eration.

The SY1017C comes into a ceramic-metal hermeticpackage containing no organic materials, while eutectic –rather than epoxy – die attach has been used. This de-vice will therefore not decompose or release any substan-tial amount of organic contaminants under high radiationlevels.



17 Application Example

Figure 25: Application example: top level.



Figure 26: Application example: RF section (SY1007).



Figure 27: Application example: AD-converter section (SY1017C).



18 Layout Recommendations

The SY1017C is a mixed-signal device sharing sensitiveanalog signals and high slew-rate digital signals on thesame chip. If the PCB is not properly designed crosstalkmay easily occur and performance of both the SY1017Cand the RF front-end attached to it could be degraded sig-nificantly.

The best performance is generally achieved when theSY1017C is placed over a solid ground plane with as lit-tle interruptions as possible. Separation between analog(AVSS) and digital (DVSS) grounds is usually not neces-sary. If it is done however it is fundamental that the twoground planes are connected together with a wide, solidtrack under the SY1017C’s package. Any impedance be-tween AVSS and DVSS – such as a thin track or a connec-tion away from the SY1017C – inevitably result in substan-tial crosstalk and poor performance.

Proper PCB routing is important to avoid that switch-ing noise from digital signals interferes with the analogones. All digital signals should be routed away from sen-sitive analog/RF tracks, while analog tracks should beshielded with grounded metal. Routing analog signals onthe top layer and digital signals on the bottom layer witha ground plane in between is an effective means to avoidcrosstalk. Most sensitive to interference are the referenceclock (FREF) and the voltage reference input (VBG). TheSY1017C shall also be placed in a cavity or shield wellseparated from the RF front-end (SY1007 or other).

Capacitive loading on digital lines – especially on theoutputs of the AD-converters and the PLL – shall be mini-mized, possibly kept below 5pF. Avoid long tracks on theseoutputs, mount the SY1017C close to the base-band pro-cessor.

Decoupling capacitors shall be connected very closeto the chip using traces as wide as possible, with the otherside of the capacitor well grounded (2-3 vias). Low ESL ce-ramic capacitors are recommended, especially on DVDD,to reduce switching noise as much as possible. VBG shallalso be well decoupled to AVSS with a low ESL capacitor.

19 PCB Recommendations

To guarantee proper mounting of the IC, the PCB land pat-tern shown in Figure 28a shall be used. In particular thefollowing requirements shall be adhered to:

• Non-solder mask defined (NSMD) lands shall bepreferred.

• The width of the fan-out traces shall not exceed0.3mm and shall be symmetrical to avoid part ro-tation due to surface tension of solder.

• Vias inside PCB lands shall be plugged and metal-lized on top to prevent solder from wicking throughthe via hole. Unplugged vias inside PCB lands arenot allowed.

• If used, a solder mask with tight openings is recom-mended to ensure that some solder mask remainsbetween the PCB lands. Traces passing betweenlands shall be completely covered with solder mask,otherwise short-circuits may easily develop. Puttingthe solder mask only under the SY1017C is alsopossible if covering the whole PCB is not allowed.

• If PCB flexing is likely, the part should be placed onan unstressed area, away from the area of maxi-mum flexing, otherwise solder joints may crack.

• The PCB shall meet the solderability requirementsof IPC/JEDEC J-STD-003 and shall be flat to within0.1mm per cm. Surface finishes such as an organicsolderability preservative (OSP) coating or Sn andNi-Au finishes are fine, while hot air solder leveled(HASL) finish is not recommended.

• If a Ni-Au finish is chosen (electroplated Ni, immer-sion Au), Au thickness must be less than 0.2µm toavoid solder joint embrittlement.

PCB Gerber data is available and can be used as recom-mended layout. To request it please contact SAPHYRIONsupport team at [email protected].

a. b.

0.80

0.80

0.35

Stencil

0.80 BSC

U1-SY1017

0.80

BS

C

Solder Mask

PCB Land

o0.4

5+ −0

.05

≅0.0

5

Figure 28: PCB land pattern and stencil openings: BGA, 6mm x 6mm, 36 balls.



20 Mounting Recommendations

The SY1017C is fitted with Sn 60%-Pb 40% solder balls(melting point = 183C). The device shall be mounted tothe PCB by reflow soldering. Infra-red (IR) reflow is thepreferred method, vapor-phase reflow may also be usedhowever. Please follow these recommendations:

• Stainless steel stencils with a thickness of 100-125µm are recommended for solder paste applica-tion. For improved solder paste release the wallsof the apertures should be tapered and the cornersrounded.

• The recommended stencil apertures are shown inFig. 28b. Use laser cutting followed by electro-polishing for stencil fabrication. Etched stencils arenot recommended.

• Use Type 3 (25µm to 45µm particle size range) orfiner solder paste for printing. (Near) eutectic Sn60-Pb40, Sn63-Pb37 or Sn62-Pb36-Ag2 solder pasteswith a melting point of 183C shall be used.

• The standard JEDEC (J-STD-020) reflow tempera-ture profile shown in Fig. 29 should be used. Therecommendations given by the solder paste manu-facturer should also be followed.

Typically, the area under the profile curve, bounded bythe liquidus temperature, defines the quality of the solderjoint. Too little area leads to cold solder joints, which area reliability risk. Too much area could result in undesirablemetallurgical issues, that could also be a reliability risk.Some experimentation may be necessary. A daisy-chaindevice that can be used to validate the soldering processfor the SY1017C is available.

After assembly the board shall be cleaned to removesolder flux residue. Solder flux residue between pads oron RF components may cause high leakages which mayincrease RF losses to an unacceptable level. Ultrasoniccleaning shall not be used since many parts – especiallycrystals, SAW filters and oscillators – may be damaged.No-clean solder flux may be used to minimize cleaning re-quirements.

Profile Feature Sn-Pb Eutectic AssemblyPreheat/soak:Temperature Min (TSmin) 100CTemperature Max (TSmax) 150CTime (tSmin to tSmax) 60s to 120sReflow:Ramp-up rate (TL to Tp) 3C/s max.Liquidus temperature (TL) 183CTime (tL) maintained above TL 60s to 150sPeak temperature (Tp) 240CTime whitin 5C of actual peak temperature Tp (tp) 10s to 30sRamp-down rate (Tp to TL) 6C/s max.Time 25C to peak temperature 6 minutes max.

Table 7: Reflow profile details (JEDEC J-STD-020).

T min

T

T

t t

Time [s]

Tem

pera

ture

[C

]

t 25[ C] to Peak Temperature

LS

S

T maxS

L

p

Ramp up Ramp down

t p

Figure 29: Recommended reflow profile.


DATA

SH

EE

TS

Y1017C

AD

/DA

-Converter,P

LL

21P

ackageD

rawing

A-A

1

1

2

2

3

3

4

4

5

5

6

6

A A

B B

C C

D D

Issue

Sheet

Scale

File name

NameCustomer

Drawing no.

Designed by

Checked byCONFIDENTIAL INFORMATIONALL RIGHTS RESERVED. PASSING ON AND COPYING OF THIS DOCUMENT,

USE AND COMMUNICATION OF ITS CONTENTS NOT PERMITTEDWITHOUT WRITTEN AUTHORIZATION FROM KYOCERA.

Date

0EUROPEAN DESIGN CENTREA3

David

2007037 - 36 csp -assy.iam

16:1

36 CSPKF-2007037-REF

1/130/03

/2007

A A

6 0.155.6 0.054.7 0.08 0.85 0.1 0.72 0.07

0.845x0.8=

SOLDER LID42 ALLOY / Solder KC-003

CERAMICKYOCERA A473

NOTES :1. CERAMIC MADE BASED ON KYOCERA DRWG KD-UA4K322. SODLER LID MADE BASED ON KYOCERA DRWG KKM-30017-013. BALL ARE FOR REFERENCE ONLY

Rev.1.5,January

30,2014S

aphyrionS

agl21


Glossary

Acronym Meaning Acronym MeaningAD[C] Analog-to-Digital [Converter] HBT Heterojunction Bipolar TransistorAGC Automatic Gain Control IF Intermediate FrequencyAGGA Advanced GPS/GLONASS ASIC LET Linear Energy TransferASIC Application Specific Integrated Circuit OCXO Oven Controlled Crystal Oscillator(C)BGA (Ceramic) Ball Grid Array PCB Printed Circuit BoardDA[C] Digital-to-Analog [Converter] PLL Phase-Locked LoopEM/FM Engineering Model / Flight Model RF Radio FrequencyESA European Space Agency SEL Single Event Latch-upESCC European Space Components Coordination SET Single Event TransientESD Electro-Static Discharge SEU Single Event UpsetGLONASS GLObalnaya NAvigatsionnaya SiGe Silicon-Germanium (HBT)

Sputnikovaya Sistema SPI Serial Peripheral InterfaceGNSS Global Navigation Satellite System TCXO Temp. Compensated Crystal OscillatorGPS Global Positioning System (NAVSTAR) VCA Voltage Controlled AmplifierHBM Human Body Model (ESD) VCO Voltage Control Oscillator

Ordering Information

Part Description Package Temperature Pack RoHSSY1017CR AD/DA-converter and interface Ceramic BGA −55 to +125C Tray No

IC, rad-hard. 36 ballsSY1017CS AD/DA-converter and interface Ceramic BGA −55 to +125C Tray No

IC, space qualified, ESCC9000. 36 balls

Related ProductsPart Description CommentsSY1007 GNSS receiver RF front-end IC. Separate RF and IF local oscillators.SY1008 GNSS receiver RF front-end IC. Higher integration level, no external LO inductors.Daisy-Chain Daisy-chain CBGA package. To develop and validate the soldering process.

Via della Posta 10B6934 BioggioSwitzerland

Phone +41 91 220 1100Fax +41 91 220 1101http://www.saphyrion.ch

DISCLAIMER

SAPHYRION PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICESOR IN APPLICATIONS WHICH INVOLVE POTENTIAL RISK OF DEATH, PERSONAL INJURY OR SEVERE PROPERTYOR ENVIRONMENTAL DAMAGE IN CASE OF FAILURE OR MALFUNCTION OF THE PRODUCT.IN CASES WHERE EXTREMELY HIGH RELIABILITY IS REQUIRED (SUCH AS USE IN NUCLEAR POWER CONTROL,AEROSPACE AND AVIATION, TRAFFIC EQUIPMENT, MEDICAL EQUIPMENT, AND SAFETY EQUIPMENT), SAFETYSHOULD BE ENSURED BY USING SEMICONDUCTOR DEVICES THAT FEATURE ASSURED SAFETY OR BY MEANSOF USERS’ FAIL-SAFE PRECAUTIONS OR OTHER ARRANGEMENT. IN NO EVENT SHALL SAPHYRION BE LIABLEFOR ANY DAMAGES THAT MAY RESULT FROM AN ACCIDENT OR ANY OTHER CAUSE DURING OPERATION OF THEUSER’S UNITS ACCORDING TO THE DATASHEET(S).


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