add dnnweaver v2.0: from tensors to fpgas pl a n n e ......workflow compiler design planner pareto...
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Workflow
Compiler Design Planner
Pareto Frontier for DNN Acceleration
Real-Time Object Detection Demo with Drone
DNNWEAVER v2.0: From Tensors to FPGAsH. Sharma, Jongse Park, Balavinayagam Samynathan, Behnam Robatmill, Shahrzad Mirkani, Hadi Esmaeilzadeh
CSE, UCSD, [email protected] Bigstream, [email protected]
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layer{name: Pool,type: POOLING,params{…}}layer{name: Conv,type: CONVOLUTION,params{…}}layer{name: Inner-Product,type: INNER_PRODUCT,params{…}}
Macro Dataflow Graph
ConvPool
Inner-
Product
MultMult
Add
MultMult
Add
…
OHAI Abstraction LayerDNNWEAVER ISAHigh-level DNN
specification in Caffe
Design Weaver
×Normaliza*on
Pooling >
Ac*va*on Lookupf(x)
PEn-1PE1PE0 …
PU0
Slices are scheduled onto PUs
Flexible # PEs
Exchangeable components
HardwareSchedule
Co-optimize Hardware and
Execution Schedule
×Normaliza*on
Pooling >
Ac*va*on Lookupf(x)
PEn-1PE1PE0 …
PUm -1
×Normaliza*on
Pooling >
Ac*va*on Lookupf(x)
PEn-1PE1PE0 …
PU0…
AcceleratorCore
Memory InterfaceGenerates Memory Interface
Static Data Marshalling
ConvPool
Inner-
Product
Accelerator Configuration
State-Machines and Micro-Codes
Scheduler
Design
Planner
High-LevelDNN
Specification
Compiler
Macro Dataflow
Graph
Design
Weaver
Accelerator Core
Scheduler
Accelerator Templates
FPGA Specification
SynthesizableAccelerator
Verilog
Memory Interface
High-Level
DNN Model
FPGA
Acceleration
DNNWEAVER Bridges the Semantic Gap
Compiler
Execution Schedule
Resource Allocation
• Video source:Camera-attached flying drone
• FPGA platform:UltraScale KintexXCKU115
• Detection algorithm:Yolo-v2-tiny
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