adc0801/adc0802/adc0803/adc0804/adc0805 8-bit up
TRANSCRIPT
ADC0801,ADC0802,ADC0803,ADC0804,ADC0805
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters
Literature Number: JAJSB69
1999幎 11æ
1© National Semiconductor Corporation DS005671-07-JP
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ADC0801/ADC0802/ADC0803/ADC0804/ADC08058ãããÎŒPã³ã³ãããã« A/Dã³ã³ããŒã¿
TRI-STATE®ã¯ãã·ã§ãã«ã»ãã³ã³ãã¯ã¿ãŒç€Ÿã®ç»é²åæšã§ãã
Z-80®ã¯ã¶ã€ãã°ç€Ÿã®åæšã§ãã
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ADC0801ãADC0802ãADC0803ãADC0804ãADC0805 ã¯ãCMOS 8ãããã®é次æ¯èŒå A/Dã³ã³ããŒã¿ã§ã256R補åãšãã䌌ãå·®åå ¥åã©ããŒã䜿çšããŠããŸãããããã®ã³ã³ããŒã¿ã¯ãÎŒP/NSC800ãINS8080Aãã¡ããªã®å¶åŸ¡ãã¹ãšå®¹æã«ã€ã³ã¿ãã§ãŒã¹ã§ããTRI-STATE® åºåã©ããã¯å®¹æã«ããŒã¿ã»ãã¹ãšã€ã³ã¿ãã§ãŒã¹ã§ããããã«èšèšãããŠããŸããã€ã³ã¿ãã§ãŒã¹çšã®å€ä»ããžãã¯ãå¿ èŠãšããªãã§ããããããã€ã¯ãããã»ããµãšæ¥ç¶ããŠããã¡ã¢ãªã»ãã±ãŒã·ã§ã³ã I/OããŒãã®ããã«åäœãããããšãå¯èœã§ãã
ã¢ããã°å·®åé»å§å ¥åãªã®ã§åçžé»å§é€å»æ¯ãé«ããšããã¢ããã°å ¥åé»å§å€ããŒãã»ãªãã»ããã§ããŸãããŸãåºæºé»å§å ¥åã¯ããããªãå°ããã¢ããã°é»å§ã¹ãã³ã§ãå®å šãª 8ãããå解èœã«ãšã³ã³ãŒãã§ããããã«èª¿æŽãå¯èœã§ãã
ç¹é·â 8080ãã€ã¯ãããã»ããµã»ãã¡ããªãšãã€ã¬ã¯ãã»ã€ã³ã¿ãã§ãŒã¹ã§ããã¢ã¯ã»ã¹ã»ã¿ã€ã 㯠135ns
â ãããããã€ã¯ãããã»ããµãšã®å®¹æãªã€ã³ã¿ãã§ãŒã¹ããããã¯ã¹ã¿ã³ãã»ã¢ããŒã³ã§ã䜿çšå¯
â ã¢ããã°å·®åé»å§å ¥åâ ããžãã¯å ¥åºå㯠CMOSãTTLé»å§ã¬ãã«ãããã§ãå¯â 2.5V (LM336)ã®åºæºé»å§ã§ãåäœå¯â ã¯ããã¯ã»ãžã§ãã¬ãŒã¿å èµâ åäž 5Vé»æºã§ã®ã¢ããã°å ¥åé»å§ç¯å²ã¯ 0ïœ 5V
â 0調æŽäžèŠâ 0.3ã€ã³ãæšæºå¹ ã® 20ãã³DIPããã±ãŒãžâ 20 ãã³ã»ã¢ãŒã«ããããã»ãã£ãªã¢ããã³ã¹ã¢ãŒã«ã»ã¢ãŠãã©ã€ã³ã»ããã±ãŒãž
â ã¬ã·ãªã¡ããªãã¯åäœã5VDCã2.5VDCããããã¯ã¢ããã°ã»ã¹ãã³èª¿æŽãããåºæºé»å§ã«ããåäœã®ãããã§ãå¯
äž»ãªä»æ§â åè§£èœ 8ãããâ ããŒã¿ã«èª€å·® ± 1/4 LSBã± 1/2 LSBã± 1LSB
â å€ææé 100ÎŒs
ãã³é 眮å³ADC080X
Dual-In-Line and Small Outline (SO) Packages
See Ordering Information
補åæ å ±
TEMP RANGE 0â TO 70â 0â TO 70â ïŒ 40â TO ïŒ 85â± 1/4 Bit Adjusted ADC0801LCN
ERROR ± 1/2 Bit Unadjusted ADC0802LCWM ADC0802LCN
± 1/2 Bit Adjusted ADC0803LCN
± 1Bit Unadjusted ADC0804LCWM ADC0804LCN ADC0805LCN/ADC0804LCJ
PACKAGE OUTLINE M20Bâ Small
Outline
N20AâMolded DIP
ã泚æïŒãã®æ¥æ¬èªããŒã¿ã·ãŒãã¯åèè³æãšããŠæäŸããŠãããå 容ãããããææ°ã§ãªãå ŽåããããŸãã補åã®ãæ€èšããã³ãæ¡çšã«éããããããŠã¯ãå¿ ãææ°ã®è±æããŒã¿ã·ãŒããã確èªãã ããã
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8080 Interface
Error Specification (Includes Full-Scale,
Zero Error, and Non-Linearity)
Part Full- VREF/2ïŒ 2.500 VDC VREF/2ïŒ No Connection
Number Scale (No Adjustments) (No Adjustments)
Adjusted
ADC0801 ± 1/4 LSB
ADC0802 ±1/2 LSB
ADC0803 ± 1/2 LSB
ADC0804 ± 1 LSB
ADC0805 ± 1 LSB
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絶察æ倧å®æ Œ (Note 1ã2)
æ¬ããŒã¿ã·ãŒãã«ã¯è»çšã»èªç©ºå®å®çšã®èŠæ Œã¯èšèŒãããŠããŸãããé¢é£ããé»æ°çä¿¡é Œæ§è©Šéšæ¹æ³ã®èŠæ Œãåç §ãã ããã
åäœå®æ Œ (Note 1ã2)
é»æ°çç¹æ§ç¹èšã®ãªãéãã以äžã®ä»æ§ã¯VCCïŒ 5VDCãADC0804LCJã§ã¯ïŒ 40âïœïŒ 85âãADC0801/02/03/05LCNã§ã¯ïŒ 40âïœïŒ 85âãADC0804LCNã§ã¯ 0âïœ 70âãADC0802/04LCWNã§ã¯ 0âïœ 70âã®æž©åºŠç¯å²ã§é©çšãããfCLKïŒ 640kHzãšããŸãã
ACé»æ°çç¹æ§ç¹èšã®ãªãéãã以äžã®ä»æ§ã¯VCCïŒ 5VDCãADC0804LCJã§ã¯ïŒ 40âïœïŒ 85âãADC0801/02/03/05LCNã§ã¯ïŒ 40âïœïŒ 85âãADC0804LCNã§ã¯ 0âïœ 70âãADC0802/04LCWNã§ã¯ 0âïœ 70âã®æž©åºŠç¯å²ã§é©çšãããfCLKïŒ 640kHzãšããŸãã
é»æºé»å§ (VCC)(Note 3) 6.5V
ããžãã¯å¶åŸ¡å ¥å ïŒ 0.3VïœïŒ 18V
ä»ã®å ¥åããã³åºå ïŒ 0.3Vïœ (VCCïŒ 0.3V)
ãªãŒã枩床 (ãã³ãä»ã 10ç§ )
ãã¥ã¢ã«ã»ã€ã³ã©ã€ã³ã»ããã±ãŒãž (ãã©ã¹ãã㯠) 260âãã¥ã¢ã«ã»ã€ã³ã©ã€ã³ã»ããã±ãŒãž (ã»ã©ãã㯠) 300âè¡šé¢å®è£ ããã±ãŒãžããŒãã»ãã§ãŒãº (60ç§ ) 215âèµ€å€ç· (15ç§ ) 220â
ä¿å枩床ç¯å² ïŒ 65âïœïŒ 150âå®æ Œæ¶è²»é»å TAïŒ 25â 875 mW
ESDèæ§ (Note 10) 800V
枩床ç¯å² TMIN⊠TA⊠TMAX
ADC0804LCJ ïŒ 40â⊠TAâŠïŒ 85âADC0801/02/03/05LCN ïŒ 40â⊠TAâŠïŒ 85âADC0804LCN 0â⊠TAâŠïŒ 70âADC0802/04LCWM 0â⊠TAâŠïŒ 70â
VCCç¯å² 4.5 VDCïœ 6.3 VDC
Parameter Conditions Min Typ Max UnitsADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj. ± 1/4 LSB
(See Section 2.5.2)
ADC0802: Total Unadjusted Error (Note 8) VREF/2ïŒ 2.500 VDC ± 1/2 LSB
ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj. ± 1/2 LSB
(See Section 2.5.2)
ADC0804: Total Unadjusted Error (Note 8) VREF/2ïŒ 2.500 VDC ± 1 LSB
ADC0805: Total Unadjusted Error (Note 8) VREF/2-No Connection ± 1 LSB
VREF/2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 kΩADC0804 (Note 9) 0.75 1.1 kΩ
Analog Input Voltage Range (Note 4) V(ïŒ ) or V(ïŒ ) Gndâ0.05 VCCïŒ 0.05 VDC
DC Common-Mode Error Over Analog Input Voltage ± 1/16 ± 1/8 LSB
Range
Power Supply Sensitivity VCCïŒ 5 VDC± 10ïŒ Over ± 1/16 ± 1/8 LSB
Allowed VIN(ïŒ ) and VIN(ïŒ )
Voltage Range (Note 4)
Symbol Parameter Conditions Min Typ Max UnitsTC Conversion Time fCLKïŒ 640 kHz (Note 6) 103 114 ÎŒs
TC Conversion Time (Notes 5, 6) 66 73 1/fCLK
fCLK Clock Frequency VCCïŒ 5V, (Note 5) 100 640 1460 kHz
Clock Duty Cycle 40 60 ïŒ CR Conversion Rate in Free-Running INTR tied to WR with 8770 9708 conv/s
Mode CSïŒ 0 VDC, fCLKïŒ 640 kHz
tW(WR)L Width of WR Input (Start Pulse Width) CSïŒ 0 VDC (Note 7) 100 ns
tACC Access Time (Delay from Falling CLïŒ 100 pF 135 200 ns
Edge of RD to Output Data Valid)
t1H, t0H TRI-STATE Control (Delay CLïŒ 10 pF, RLïŒ 10k 125 200 ns
from Rising Edge of RD to (See TRI-STATE Test
Hi-Z State) Circuits)
tWI, tRI Delay from Falling Edge 300 450 ns
of WR or RD to Reset of INTR
CIN Input Capacitance of Logic 5 7.5 pF
Control Inputs
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05 ACé»æ°çç¹æ§ (ã€ã¥ã )
ç¹èšã®ãªãéãã以äžã®ä»æ§ã¯VCCïŒ 5VDCãADC0804LCJã§ã¯ïŒ 40âïœïŒ 85âãADC0801/02/03/05LCNã§ã¯ïŒ 40âïœïŒ 85âãADC0804LCNã§ã¯ 0âïœ 70âãADC0802/04LCWNã§ã¯ 0âïœ 70âã®æž©åºŠç¯å²ã§é©çšãããfCLKïŒ 640kHzãšããŸãã
Note 1: ã絶察æ倧å®æ Œããšã¯ãICã«ç Žå£ãçºçããå¯èœæ§ã®ãããªãããå€ããããŸãããã®èŠæ Œãè¶ ããŠåäœãããŠãã ICã«ã¯ãDCç¹æ§ãACç¹æ§ãããã®èŠæ Œãé©çšãããŸããã
Note 2: ç¹èšã®ãªãéãããã¹ãŠã®é»å§ã¯ GNDã«å¯ŸããŠæž¬å®ãããå€ã§ããã¢ããã°ã»ã°ã©ãŠã³ãã»ãã€ã³ãã¯ã€ãã«ããžã¿ã«ã»ã°ã©ãŠã³ãã«æ¥ç¶ãããªããã°ãªããŸããã
Note 3: VCCããã°ã©ãŠã³ãéã«ãã¬ã€ã¯ã»ããŠã³é»å§ 7VDC (ä»£è¡šå€ )ã®ãã§ããŒã»ãã€ãªãŒããå èµãããŠããŸãã
Note 4: VIN (ïŒ )⊠VIN (ïŒ )æã«ã¯ããžã¿ã«åºåã³ãŒã㯠0000 0000ã«ãªããŸãã2åã®ãªã³ãããã»ãã€ãªãŒãããåã¢ããã°å ¥åã«æ¥ç¶ãããŠããŸãã (ããããã¯å³ãåç § )ãããã¯ã°ã©ãŠã³ããã1ãã€ãªãŒãã»ããããé»å§ã ãäœãããVCCãã1ãã€ãªãŒãã»ããããé«ãã¢ããã°å ¥åé»å§ã«å¯ŸããŠé æ¹åã«å°éããŸããäœã VCCã¬ãã« (4.5V)ã§ã®ãã¹ãæã§ã¯ãç¹ã«æž©åºŠäžæäžã«é«ãã¢ããã°å ¥åã¬ãã« (5V)ããã®å ¥åãã€ãªãŒãã®å°éãåŒãèµ·ãããã»ãŒãã«ã¹ã±ãŒã«è¿ãã®ã¢ããã°å ¥åã«å¯ŸããŠãšã©ãŒãçããããã®ã§ã泚æãå¿ èŠã§ããã©ã¡ãã®ãã€ãªãŒãã50mVã®ãã©ã¯ãŒãã»ãã€ã¢ã¹ã蚱容ãããŠããŸããããã¯ã¢ããã°å ¥åé»å§ã VCCã 50mV以äžè¶ ããªãéããåºåã³ãŒãã¯æ£ããããšãæå³ããŸãããããã£ãŠã0ïœ 5VDCã®å ¥åç¯å²ãæºããã«ã¯ãåããã€ã¹ã®æž©åºŠç¯å²ãåæå ¬å·®ãè² è·ç¶æ ã§ãæå° 4.950VDCã® VCCãå¿ èŠã§ãã
Note 5: 粟床㯠fCLKïŒ 640kHzã§ä¿èšŒãããŸãããã以äžã®é«ã fCLKã§ã¯ç²ŸåºŠãäœäžããŸããfCLKãäœãå Žåã§ã¯ããã¥ãŒãã£ã»ãµã€ã¯ã«ã®ãªãããå€ã¯ã¯ããã¯ã®ãã€ã»ã¿ã€ã ããŸãã¯ããŒã»ã¿ã€ã ã®ã€ã³ã¿ãŒãã«ã 275ns (æå° )以äžãŸã§æ¡åŒµã§ããŸãã
Note 6: éåæã¹ã¿ãŒãã»ãã«ã¹ã§ã¯ãå éšã¯ããã¯ã®äœçžãå€æããã»ã¹ã®ã¹ã¿ãŒãã«é©åããããã«ãªãåã«ã8 ã¯ããã¯ã»ãµã€ã¯ã«ãå¿ èŠã§ããã¹ã¿ãŒãèŠæ±ãå éšã§ã©ãããããŸã (2.0é ã® Figure 4åç § )ã
Symbol Parameter Conditions Min Typ Max UnitsCOUT TRI-STATE Output 5 7.5 pF
Capacitance (Data Buffers)
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1) Logical â1â Input Voltage VCCïŒ 5.25 VDC 2.0 15 VDC
(Except Pin 4 CLK IN)
VIN (0) Logical â0â Input Voltage VCCïŒ 4.75 VDC 0.8 VDC
(Except Pin 4 CLK IN)
IIN (1) Logical â1â Input Current VINïŒ 5 VDC 0.005 1 ÎŒADC
(All Inputs)
IIN (0) Logical â0â Input Current VINïŒ 0 VDC ïŒ 1 ïŒ 0.005 ÎŒADC
(All Inputs)
CLOCK IN AND CLOCK RVTïŒ CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 VDC
Threshold Voltage
VTïŒ CLK IN (Pin 4) Negative 1.5 1.8 2.1 VDC
Going Threshold Voltage
VH CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 VDC
(VTïŒ )ïŒ (VTïŒ )
VOUT (0) Logical â0â CLK R Output IOïŒ 360 ÎŒA 0.4 VDC
Voltage VCCïŒ 4.75 VDC
VOUT (1) Logical â1â CLK R Output IOïŒïŒ 360 ÎŒA 2.4 VDC
Voltage VCCïŒ 4.75 VDC
DATA OUTPUTS AND INTRVOUT (0) Logical â0â Output Voltage
Data Outputs IOUTïŒ 1.6 mA, VCCïŒ 4.75 VDC 0.4 VDC
INTR Output IOUTïŒ 1.0 mA, VCCïŒ 4.75 VDC 0.4 VDC
VOUT (1) Logical â1â Output Voltage IOïŒïŒ 360 ÎŒA, VCCïŒ 4.75 VDC 2.4 VDC
VOUT (1) Logical â1â Output Voltage IOïŒïŒ 10 ÎŒA, VCCïŒ 4.75 VDC 4.5 VDC
IOUT TRI-STATE Disabled Output VOUTïŒ 0 VDC ïŒ 3 ÎŒADC
Leakage (All Data Buffers) VOUTïŒ 5 VDC 3 ÎŒADC
ISOURCE VOUT Short to Gnd, TAïŒ 25â 4.5 6 mADC
ISINK VOUT Short to VCC, TAïŒ 25â 9.0 16 mADC
POWER SUPPLYICC Supply Current (Includes fCLKïŒ 640 kHz,
Ladder Current) VREF/2ïŒNC, TAïŒ 25â
and CSïŒ 5V
ADC0801/02/03/04LCJ/05 1.1 1.8 mA
ADC0804LCN/LCWM 1.9 2.5 mA
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Note 7: CS å ¥åã¯WRã¹ãããŒãå ¥åãã€ããŒãã«ããã®ã§ãã¿ã€ãã³ã°èªäœã¯WRã®ãã«ã¹å¹ ã«äŸåããŸããä»»æã®å¹ ã®ãã«ã¹ã¯ãã®éããªã»ããã¢ãŒãã«ã³ã³ããŒã¿ãããŒã«ãããå€æéå§ã¯WRãã«ã¹ã® LowããHighãžã®é·ç§»ã«ãã£ãŠã€ãã·ã£ã©ã€ãºãããŸã (ãã¿ã€ãã³ã°å³ãåç § )ã
Note 8: ãããã®ã³ã³ããŒã¿ã¯ãŒã調æŽãå¿ èŠãšããŸãã (2.5.1åç § )ã0V以å€ã®ã¢ããã°å ¥åé»å§ã§ 0ã³ãŒããåºåããå Žåã¯ã2.5é ããã³ Figure 7ãåç §ããŠãã ããã
Note 9: VREF/2端åã¯VCCããã°ã©ãŠã³ããžæ¥ç¶ãããŠãã2ã€ã®æµæåå§åè·¯ã®äžå¿ç¹ã§ããADC0804LCJã§ã¯åæµæ㯠16kΩ(ä»£è¡šå€ )ã§ããããã以å€ã®åæµæ㯠2.2kΩ(ä»£è¡šå€ )ã§ãã
Note 10: 䜿çšããè©Šéšåè·¯ã¯ã人äœã¢ãã«ã«ããšã¥ãçŽåæµæ 1500Ωãš100pFã®ã³ã³ãã³ãµãããªãåè·¯ã䜿çšããå端åã«æŸé»ãããŸãã
代衚çãªæ§èœç¹æ§
Logic Input Threshold Voltagevs. Supply Voltage
Delay From Falling Edge ofRD to Output Data Validvs. Load Capacitance
CLK IN Schmitt Trip Levelsvs. Supply Voltage
fCLK vs. Clock Capacitor Full-Scale Error vsConversion Time
Effect of Unadjusted Offset Errorvs. VREF/2 Voltage
Output Current vsTemperature
Power Supply Currentvs Temperature (Note 9)
Linearity Error at LowVREF/2 Voltages
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05 TRI-STATEãã¹ãåè·¯ããã³æ³¢åœ¢
t1H t1H, CLïŒ 10 pF
trïŒ 20 ns
t0H t0H, CLïŒ 10 pF
trïŒ 20 ns
ã¿ã€ãã³ã°å³ (ãã¹ãŠã®ã¿ã€ãã³ã°ã¯ã50ïŒ ã®é»å§ç¹ãã枬å®ãããŠããŸãã )
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ã¿ã€ãã³ã°å³ (ãã¹ãŠã®ã¿ã€ãã³ã°ã¯ã50ïŒ ã®é»å§ç¹ãã枬å®ãããŠããŸãã )(ã€ã¥ã )
Output Enable and Reset with INTR
Note: INTRã®ãªã»ãããä¿èšŒããããã«ãå²ã蟌ã¿ã®å®è¡åŸ (INTRã®ç«ã¡äžãããšããž )ãã8ã¯ããã¯ã»ãµã€ã¯ã« (8/fCLK)ã§ãªãŒãã®ä¿¡å·ãç«ã¡äžããŠãã ããã
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6800 Interface Ratiometeric with Full-Scale Adjust
Note: VIN 端åãŸã㯠VREF/2 端åã§ã³ã³ãã³ãµã䜿ãå Žåã«ã¯ã2.3.2 é ã®ãå ¥åãã€ãã¹ã»ã³ã³ãã³ãµããåç §ããŠãã ããã
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Absolute with a 2.500V Reference
*äœæ¶è²»é»æµåºæºé»å§æºãšããŠãLM385-2.5ã®ããŒã¿ã·ãŒããåç §ããŠãã ããã
Absolute with a 5V Reference
Zero-Shift and Span Adjust: 2V⊠VIN⊠5V Span Adjust: 0V⊠VIN⊠3V
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Directly Converting a Low-Level Signal A ÎŒP Interfaced Comparator
VREF/2ïŒ 256 mV
1 mV Resolution with ÎŒP Controlled Range
VREF/2ïŒ 128 mV
1 LSBïŒ 1 mV
VDAC⊠VIN⊠(VDACïŒ 256 mV)
0⊠VDACïŒ 2.5V
For:
VIN(ïŒ )ïŒ VIN(ïŒ )
OutputïŒ FFHEX
For:
VIN(ïŒ )ïŒ VIN(ïŒ )
OutputïŒ 00HEX
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Digitizing a Current Flow
Self-Clocking Multiple A/Ds
*CLK Råºåã®è² è·ãäœæžããããã«æµæå€ã®å€§ãã Rã䜿çšããŠãã ããã
External Clocking
100 kHz⊠fCLK⊠1460 kHz
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Self-Clocking in Free-Running Mode
* é»æºæå ¥åŸãåäœãä¿èšŒããããã«ãWRå ¥åãç¬éçã«ã°ã©ãŠã³ã(Lowã¬ãã« )ã«ã¹ã€ããã³ã°ããå¿ èŠããããŸãã
ÎŒP Interface for Free-Running A/D
Operating with âAutomotiveâ Ratiometric Transducers
* VIN(ïŒ )ïŒ 0.15 VCC
15ïŒ of VCC⊠VXDR⊠85ïŒ of VCC
Ratiometric with VREF/2 Forced
ÎŒP Compatible Differential-Input Comparator with Pre-Set VOS (with or without Hysteresis)
* æµæå€ Rã®éžæ㯠Figure 5ãåç §ããŠãã ããã
DB7ïŒâ1â for VIN(ïŒ )ïŒ VIN(ïŒ )ïŒ (VREF/2)
ãã¹ããªã·ã¹ãå¿ èŠãªãå Žåã«ã¯ãç¹ç·å ã®åè·¯ã¯çç¥ããŠãã ããã
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Handling ± 10V Analog Inputs
*Beckman Instruments #694-3-R10K resistor array
Low-Cost, ÎŒP Interfaced, Temperature-to-Digital Converter
ÎŒP Interfaced Temperature-to-Digital Converter
*åè·¯äžã®å€ã¯ 0â⊠TAâŠïŒ 128âã«å¯ŸããŠã®ãã®ã瀺ãããŠããŸãã
**ããããã®ã»ã³ãµãèŒæ£ããã°å®¹æã«çœ®ãæããå¯èœã«ãªããA/Dã³ã³ããŒã¿ã¯ããããããèšå®ãããå ¥åé»å§ã§èŒæ£ãããŸãã
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Handling ± 5V Analog Inputs Read-Only Interface
*Beckman Instruments #694-3-R10K resistor array
ÎŒP Interfaced Comparator with Hysteresis Protecting the Input
Diodes are 1N914
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Analog Self-Test for a System
A Low-Cost, 3-Decade Logarithmic Converter
*LM389 transistors
A, B, C, DïŒLM324A quad op amp
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3-Decade Logarithmic A/D Converter
Noise Filtering the Analog Input
fCïŒ 20 Hz
æ¥å³»ãªæžè¡°åž¯åç¹æ§ãæãããããã«ãã§ãã·ã§ãåã®ãŠããã£ã»ã²ã€ã³ 2 次ã®ããŒãã¹ã»ãã£ã«ã¿ã䜿çšããŠããŸãã
ã¢ããã°ã»ãã«ããã¬ã¯ãµã䜿çšããå Žåã«ã¯ãããããã®ãã£ãã«ã«å¥ã ã®ãã£ã«ã¿ãå ãããšã·ã¹ãã å šäœãšããŠã®å¿çæ§ãåäžããŸãã
Multiplexing Differential Inputs
Output Buffers with A/D Data Enabled
* A/D ã®åºåããŒã¿ã¯ INTR ãã¢ãµãŒãããã 1ã¯ããã¯ã»ãµã€ã¯ã«åã«ã¢ããããŒããããŸãã
Increasing Bus Drive and/or Reducing Time on Bus
*åºåããŒã¿ã¯ãCSã®ç«ã¡äžãããšããžã§ã»ããã¢ãããããŸãã
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Sampling an AC Input Signal
Note 11: å ¥ååšæ³¢æ°ã®æãè¿ã (ãšãªã¢ã·ã³ã° )ã®é²æ¢ããã³ãã£ã«ã¿ã®æžè¡°åž¯åã®å¿çæ§ãååã«ç¢ºä¿ããããã«ãfSïŒ 2f (ïŒ 60dB)ãåžžã«æºããããã«ãªãŒããŒã»ãµã³ããªã³ã°ããŠãã ããã fSã¯ãµã³ããªã³ã°åšæ³¢æ°ãfã¯å ¥åä¿¡å·åšæ³¢æ°ã
Note 12: ãã£ã«ã¿ã®éé垯åå ã§çããæ¯å¹ 誀差ã«æ³šæããŠãã ããã
70ïŒ Power Savings by Clock Gating
(å®å šãªã·ã£ããããŠã³ã«ã¯çŽ 30ç§ããããŸã )
Power Savings by A/D and VREF Shutdown
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Note: A/Dã®é»æºã 0Vã«ããããã«ãããžãã¯å ¥åã«ããVCCããã©ã€ãããããšãå¯èœã§ãã
ã·ã£ããããŠã³ã»ã¢ãŒãã«ããå Žåã«ã¯ãããŒã¿ã»ãã¹ã A/Dã®åºåããªãŒããŒã»ãã©ã€ãããªãããã«ãããã¡ãèšããŠãã ããã
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1.0 A/Då€æ誀差ã®ç¹æ§
Figure 1ã«çæ³çãªA/Då€æç¹æ§ (é段ç¹æ§ )ã瀺ããŸãã暪軞ã¯ã¢ããã°å ¥åé»å§ã§åãã€ã³ã㯠1LSB (VREF/2端åã« 2.5V
ãå ããããŠããå Žå㯠19.53mV)ã¹ãããã«ãªã£ãŠããŸãããããã®å ¥åã«å¯Ÿå¿ããããžã¿ã«åºåã³ãŒãã¯ãããã DïŒ 1ãDãD
ïŒ 1ãšããŠè¡šããããã¢ããã°å ¥åã®ã»ã³ã¿å€ (AïŒ 1ãAãAïŒ1ã»ã»ã»ã»ã»ã»)ãæ£ããããžã¿ã«ã³ãŒããåºåããã ãã§ãªããåäžæç¹ ( é£æ¥åºåã³ãŒãéã®é·ç§»ç¹ ) ã¯åã»ã³ã¿å€ãã± 1/2
LSBé¢ããå Žæã«äœçœ®ããŠããŸããå³ã«ç€ºãããã«ãäžæç¹ã¯çæ³çã§å¹ ãæã¡ãŸãããæ£ããããžã¿ã«åºåã³ãŒããçæ³ã®ã»ã³ã¿å€ãã± 1/2 LSBãŸã§ã®ã¢ããã°å ¥åé»å§ç¯å²ã§åºåãããŸãããããã£ãŠåãã¬ãã ( åãããžã¿ã«ã³ãŒããåºåããã¢ããã°å ¥åé»å§ã®ç¯å² )㯠1LSBã®å¹ ãæã£ãŠããŸãã
Figure 2㯠ADC0801ã®ææªæã®èª€å·®ã瀺ããŠããŸãããã¹ãŠã®ã»ã³ã¿å ¥åå€ã¯æ£ããã³ãŒãã®åºåãä¿èšŒããé£æ¥ããäžæç¹ã¯ã»ã³ã¿ãã€ã³ããžÂ±1/4 LSB以äžè¿ã¥ããªãããšãä¿èšŒãããŠããŸããèšãããããšãã»ã³ã¿å€Â± 1/4 LSB ã«çããã¢ããã°å ¥åãå ããã°ãA/D ã³ã³ããŒã¿ã¯æ£ããããžã¿ã«ã³ãŒããåºåããã
ãšãä¿èšŒãããŸããã³ãŒããé·ç§»ããããžã·ã§ã³ã®æ倧ç¯å²ãæ°Žå¹³ã®ç¢å°ã§ç€ºãããŠããŸããããã㯠1/2 LSBãã倧ãããªããªãããšãä¿èšŒãããŠããŸãã
Figure 3ã®èª€å·®ã«ãŒã㯠ADC0802ã®ææªã®ã±ãŒã¹ã瀺ããŠããŸãããã®å Žåã¯ãLSBã¢ããã°é»å§ã®ã»ã³ã¿å€ã«çããã¢ããã°å ¥åãå ããã°ãA/Dã³ã³ããŒã¿ã¯æ£ããããžã¿ã«ã³ãŒããåºåããããšãä¿èšŒãããŸãã
åå€æç¹æ§ã®å³åŽã«å¯Ÿå¿ãã誀差ç¹æ§ã瀺ãããŠããŸããå€ãã®äººã«ãšã£ãŠå€æç¹æ§ãã誀差ç¹æ§ã®ã»ãã解ãããããããããŸãããA/Dã³ã³ããŒã¿ãžã®ã¢ããã°å ¥åé»å§ã¯ããªãã¢ãªåŸæå ¥åãããã¯é«åè§£èœ DACã®ååºåã¹ãããã«ãã£ãŠäŸçµŠãããŸãã誀差ã¯é£ç¶çã«è¡šããããA/Dã³ã³ããŒã¿ã®éååäžç¢ºå®æ§ãå«ãããšã«æ³šæãå¿ èŠã§ããäŸãã°ãFigure 1ã®ãã€ã³ã1ã§ã®èª€å·®ã¯ãããžã¿ã«ã³ãŒãããã¬ããã®ã»ã³ã¿å€ãã1/2 LSBæ©ãåŸãããã®ã§ã1/2 LSBã«ãªããŸãã誀差ç¹æ§ã¯åžžã«äžå®ã®è² ã®åŸæãæã¡ãäžæ¹ãžã®ç«ã¡äžããã¯åžžã« 1LSB ã®å€ãæã¡ãŸãã
Transfer Function Error Plot
FIGURE 1. Clarifying the Error Specs of an A/D ConverterAccuracyïŒÂ± 0 LSB: A Perfect A/D
Transfer Function Error Plot
FIGURE 2. Clarifying the Error Specs of an A/D ConverterAccuracyïŒÂ± 1/4 LSB
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Transfer Function Error Plot
FIGURE 3. Clarifying the Error Specs of an A/D ConverterAccuracyïŒÂ± 1/2 LSB
2.0 æ©èœèª¬æ
ADC0801 ã·ãªãŒãºã¯ 256R ãããã¯ãŒã¯ãšç䟡åè·¯ãå«ãã§ããŸããã¢ããã°ã»ã¹ã€ããã¯é次æ¯èŒããžãã¯ã«ãã£ãŠãå·®åã¢ããã°å ¥åé»å§ [VIN (ïŒ )ïŒVIN (ïŒ )]ã Rãããã¯ãŒã¯ã®çžå¿ããã¿ããã«äžèŽããããã«å¶åŸ¡ãããŸãããŸãæäžäœãããããã¹ããã 8åã®æ¯èŒ (64ã¯ããã¯ã»ãµã€ã¯ã« )ã®åŸãããžã¿ã« 8ããã2é²ã³ãŒã (1111 1111ïŒãã«ã¹ã±ãŒã« )ãåºåã©ãããžäŒéãããŠããã®åŸå²ã蟌ã¿ãã©ã°ããã¡ãŸã (INTR㯠Highãã Lowã«ãªããŸã )ãå€æéçšã¯æ°ããªã¹ã¿ãŒãã³ãã³ãã«ãã£ãŠå²ã蟌ãŸããŸããCSïŒ 0ãšã㊠INTRãWRå ¥åãžæ¥ç¶ãããšããªãŒã»ã©ã³ãã³ã°ã»ã¢ãŒãã§åäœã§ããŸããããããæ¡ä»¶äžã§ã¹ã¿ãŒãã¢ããã確å®ã«ãããããæåã®ãã¯ãŒã¢ããã»ãµã€ã¯ã«æã«å€éš WRãã«ã¹ãå¿ èŠã§ãã
WRå ¥åã HighããLowã«ãªãæãå éš SARã©ãããšã·ããã¬ãžã¹ã¿æ®µããªã»ãããããŸããCS å ¥åãšWR å ¥åã Low ã§ããéããA/Dã³ã³ããŒã¿ã¯ãªã»ããç¶æ ã«ä¿æãããŸããå€æã¯ãããå ¥åã®å°ãªããšã 1ã€ã LowããHighã«é·ç§»ããåŸã1ïœ 8
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ã³ã³ããŒã¿ã¯ CSãšWRãåæã« Lowã«ããŠã¹ã¿ãŒãããŸããããã¯ã¹ã¿ãŒãã»ããªãããããã (F/F)ãã»ãããããã®åºåã®ã¬ãã«â1â㯠8ãããã»ã·ããã¬ãžã¹ã¿ããªã»ããããŠã€ã³ã¿ã©ãã (INTR) F/Fããªã»ããããDããªãããããã F/F1ã« 1ãå ¥åããŸããF/F1㯠8ãããã»ã·ããã¬ãžã¹ã¿ã®å ¥å端ã«äœçœ®ããŠããŸããå éšã¯ããã¯ã¯ãã®â1âã F/F1 ã® Q åºåã«äŒéããŸããAND ã²ãŒãG1 ã¯ãã®â1âåºåãã¯ããã¯ä¿¡å·ãšçµã¿åãããŠã¹ã¿ãŒãF/F ãžãªã»ããä¿¡å·ãäŸçµŠããŸããã»ããä¿¡å·ããã§ã«ãªã (WRã CS ã®äžæ¹ãâ1â ) å Žåãã¹ã¿ãŒãF/Fã¯ãªã»ããããã8ãããã»ã·ããã¬ãžã¹ã¿ãžâ1âãã¯ããã¯ã€ã³ãããŸãããããŠå€æéçšãã¹ã¿ãŒãããŸããã»ããä¿¡å·ããŸã æ®ã£ãŠãããããã®ãªã»ãããã«ã¹ã¯å¹æãããã (ã¹ã¿ãŒãF/Fã®äž¡åºåã¯ç¬æã«â1âã¬ãã«ã«ãªã)ã8ãããã»ã·ããã¬ãžã¹ã¿ã¯ãªã»ããã¢ãŒãã«ä¿æãããŸãããããã£ãŠãã®ããžãã¯ã¯ CSãšWRä¿¡å·ã®éã§æãç«ã¡ãã³ã³ããŒã¿ã¯ãããä¿¡å·ã®å°ãªããšã1ã€ã Highã«ãªã£ãåŸã¹ã¿ãŒãããå éšã¯ããã¯ã¯åã³ã¹ã¿ãŒãF/Fã«ãªã»ããä¿¡å·ãäŸçµŠããŸãã
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FIGURE 4. Block Diagram
â1â㯠(SARåäœãå®æããã ) 8ãããã»ã·ããã¬ãžã¹ã¿ãã¯ããã¯åäœã«ããééããåŸãDã¿ã€ãã©ãã LATCH 1ãžå ¥åãããŸãããã®â1âãã·ããã¬ãžã¹ã¿ããåºåããããšãANDã²ãŒãG2
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FIGURE 5. Analog Input Impedance
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2.4 åºæºé»å§
2.4.1 ã¹ãã³èª¿æŽ
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FIGURE 6. The VREFERENCE Design on the IC
IC ã®åºæºé»å§ã¯ VCC é»æºç«¯åãžå ããããé»å§ã® 1/2ããããã¯å€éšçã«VREF/2端åã«å ããããé»å§ã«çãããªããŸãããã㯠VCC é»å§ãçšããã¬ã·ãªã¡ããªãã¯ãªåºæºé»å§åäœã®å Žåã5VDC åºæºé»å§ã VCC é»æºã«äœ¿çšããããããã«å¿çšäžã®èªç±åºŠã®ããã«VREF/2å ¥åãž 2.5VDC以äžã®é»å§ãå ãããããããšãå¯èœã«ããŸããVREF/2 å ¥åã¯å éšçã« 2 åã®ã²ã€ã³ãæã£ãŠããã®ã§ããã«ã¹ã±ãŒã«å·®åå ¥åé»å§ã¯ 9ãã³ã®é»å§ã® 2 åã«ãªããŸãã
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ãšããå Žåãã¹ãã³ã¯ Figure 7ã«ç€ºãããã« 3Vã«ãªããŸãããªãã»ãããåžåãããã VIN (ïŒ )端åã« 0.5VDCãå ãããšãåºæºé»å§ã¯ 3Vã¹ãã³ã® 1/2ã€ãŸã1.5VDCã«ãªããŸããA/Dã³ã³ããŒã¿ã¯ 0.5V ïœ 3.5V ã® VIN ( ïŒ ) ä¿¡å·ã 0.5Vãå ¥åããŒãã«ã3.5VDCå ¥åããã«ã¹ã±ãŒã«ãšããŠå€æããŸãããããã£ãŠå解èœã®å š 8ãããã¯ãã®ãã°ããããã¢ããã°å ¥åé»å§ç¯å²ã«å¯Ÿå¿ããŸãã
2.4.2 åºæºé»å§ã®ç²ŸåºŠ
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a) Analog Input Signal Example
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b) Accommodating an Analog Input from0.5V (Digital OutïŒ 00HEX) to 3.5V
(Digital OutïŒ FFHEX)
FIGURE 7. Adapting the A/D Analog Input Voltages to Match an Arbitrary Input Signal Range
2.5 誀差ãšåºæºé»å§èª¿æŽ
2.5.1 ãŒã誀差
ãã® A/Dã³ã³ããŒã¿ã¯ãŒã調æŽãå¿ èŠãšããŸãããæå°ã¢ããã°å ¥åé»å§å€ãVIN (MIN) ãã°ã©ãŠã³ãã§ãªãå ŽåããŒããªãã»ãããå¯èœã§ããA/Dã® VIN (ïŒ )å ¥åã«ãã® VIN (MIN)å€ããã€ã¢ã¹ããã°ããã®æå°å ¥åé»å§ã«å¯Ÿã 0000 0000ããžã¿ã«ã³ãŒããåºåããããã«ã³ã³ããŒã¿ãèšå®ã§ããŸã (ãå¿çšãã®é åç § )
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2.5.3 ä»»æã®ã¢ããã°å ¥åé»å§ç¯å²èª¿æŽ
A/Dã³ã³ããŒã¿ã®ã¢ããã°ãŒãé»å§ãã°ã©ãŠã³ãããé¢ããå Žå( äŸãã°ã°ã©ãŠã³ãã»ã¬ãã«ãŸã§äžãããªãã¢ããã°å ¥åä¿¡å·ã«å¯Ÿ
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2.6 ã»ã«ãã¯ããã¯
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2.9 ããŒã¿ã»ãã¹ã®é§å
ãã® MOS A/Dã³ã³ããŒã¿ã¯ MOS ãã€ã¯ãããã»ããµãã¡ã¢ãªåæ§ãããŒã¿ã»ãã¹ã®ããŒã¿ã«å®¹éã倧ãããªãå Žåã¯ããã¹ã»ãã©ã€ããå¿ èŠãšããŸããããŒã¿ã»ãã¹ãžæ¥ç¶ãããä»ã®å路㯠TRI-
STATE (ãã€ã»ã€ã³ããŒãã³ã¹ã»ã¢ãŒã )ã§ãã£ãŠãããŒã¿ã«å®¹éè² è·ãå¢å€§ãããŸããããã¯ãã¬ãŒã³ã»ãã¹ããŸãããŒã¿ã»ãã¹ã®æµ®é容éã倧ããå¢å€§ãããŸãã
èšèšè ã«ãšã£ãŠããã®åé¡ãåé¿ããããã€ãã®æ段ããããŸããåºæ¬çã«ããŒã¿ã»ãã¹ã®å®¹éæ§è² è·ã¯ DC ç¹æ§ãæºè¶³ããŠãå¿çæéãã¹ããŒããŠã³ãããŸããæ¯èŒçé ã CPUã¯ããã¯åšæ³¢æ°ã§åäœããŠããã·ã¹ãã ã®å Žåããã¹äžã§é©åãªããžãã¯ã»ã¬ãã«ã«éããã®ã«ååãªæéãåŸãããã®ã§ãæ¯èŒç倧ãã容éæ§è² è·ããã©ã€ãã§ããŸã (ã代衚çãªæ§èœç¹æ§ãåç § )ã
ããéã CPUã¯ããã¯åšæ³¢æ°ã®å Žåã¯ããŠãšã€ãã»ã¹ããŒãã䜿çš(8080)ããããã¯ã¯ããã¯äŒžåŒµåè·¯ãäœ¿çš (6800)ããã°ãI/OãªãŒã (ãããã¯ã©ã€ã)ã«å¯ŸããŠæéã延é·ã§ããŸãã
æéãçã容éæ§è² è·ã倧ããå Žåã¯ãå€éšãã¹ã»ãã©ã€ããçšããªããã°ãªããŸããããããã¯ãTRI-STATEãããã¡(DM74LS240
ã·ãªãŒãºã®ãããªäœé»åã·ã§ããããŒãæšå¥šãããŸã ) ããã¹ã»ãã©ã€ããšããŠèšèšãããç¹å¥ã®é«é§åé»æµè£œåã§ããPNPå ¥åãæã£ãé«é»æµãã€ããŒã©ã»ãã¹ã»ãã©ã€ããæšå¥šãããŸãã
2.10 é»æº
VCC é»æºã©ã€ã³ã®ã¹ãã€ã¯ã»ãã€ãºã¯ãã³ã³ãã¬ãŒã¿ããã®ãã€ãºã«å¿çããŠå€æ誀差ãåŒãèµ·ãããŸãããã£ã«ã¿ãšããŠã³ã³ããŒã¿ã®VCC端åã®è¿ãã« 1ÎŒF以äžã®äœã€ã³ãã¯ã¿ã³ã¹ã®ã¿ã³ã¿ã«ã»ã³ã³ãã³ãµãä»ããŠãã ãããã·ã¹ãã ã«å®å®åãããŠããªãé»å§ãäŸçµŠããå Žåã¯ã³ã³ããŒã¿ (ãããŠä»ã®ã¢ããã°åè·¯ )ã«åå¥ã®ã¬ã®ã¥ã¬ãŒã¿ãšã㊠LM340LAZ-5.0ãTO-92 ããã±ãŒãžã® 5V é»å§ã¬ã®ã¥ã¬ãŒã¿ã䜿çšããã°ãVCCé»æºäžã®ããžã¿ã«ã»ãã€ãºãå€§å¹ ã«åæžã§ããŸãã
2.11 ç·æãšé»æºã®ãã€ãã¹ã«ããã泚æäºé
ã¹ã¿ã³ããŒãã»ããžã¿ã«é ç·ã©ãããœã±ããã¯ããã® A/D ã³ã³ããŒã¿ã®ãã¬ããããŒãçšã«ã¯é©ããŸãããããªã³ãåºæ¿äžã®ãœã±ãããçšãããã¹ãŠã®ããžãã¯ä¿¡å·é ç·ãšç·æãéäžããŠã¢ããã°ä¿¡å·ç·ããã§ããã ãé ãã«é¢ããŸããã¢ããã°å ¥åãžã®åç·ã¯äžèŠãªããžã¿ã«ã»ãã€ãºããã èªå°ã®åå ãšãªãã®ã§ãå€ãã®å Žåã·ãŒã«ãç·ãå¿ èŠã«ãªããŸãã
ããžãã¯ã»ã°ã©ãŠã³ãç¹ãšã¯å¥ã«äžç¹ã¢ããã°ã»ã°ã©ãŠã³ãã䜿çšãããªããã°ãªããŸãããé»æºé»å§ãã€ãã¹ã»ã³ã³ãã³ãµãšã»ã«ãã¯ããã¯ã»ã³ã³ãã³ãµ (䜿çšãããŠããã° )ã¯ããšãã«ããžã¿ã«ã»ã°ã©ãŠã³ãã«åž°ããªããŠã¯ãªããŸãããVREF/2ãã€ãã¹ã»ã³ã³ãã³ãµãã¢ããã°å ¥åãã£ã«ã¿ã»ã³ã³ãã³ãµããŸãã¯å ¥åä¿¡å·ã·ãŒã«ãã£ã³ã°( é®ãžã ) ã¯ããããã¢ããã°ã»ã°ã©ãŠã³ãç¹ã«åž°ããªããŠã¯ãªããŸãããé©åãªã°ã©ãŠã³ãã®ããã®è©Šéšæ³ã¯ A/Dã³ã³ããŒã¿ã®ãŒã誀差ã枬å®ããããšã§ãã1/4 LSBãè¶ ãããŒã誀差ã¯ãéåžžäžé©åãªããŒãã¬ã€ã¢ãŠã ( é 眮 )ãšé ç·ã«ãããã®ã§ã (2.5.1 é ã®ããŒã誀差ã®æž¬å®æ³ããåç §ããŠãã ãã )ã
3.0 A/Dã³ã³ããŒã¿ã®è©Šéšæ³
A/D ã³ã³ããŒã¿ã®è©Šéšæ³ã¯è€éã«é¢é£ããå€ãã®æ®µéããããŸããæãç°¡åãªè©Šéšæ³ã® 1ã€ã¯ã³ã³ããŒã¿ã«æ¢ç¥ã®ã¢ããã°å ¥åé»å§ãäžããFigure 9 ã§ç€ºãããã«ããžã¿ã«åºåã³ãŒãã®çµæãLEDã䜿ã£ãŠè¡šç€ºãããããšã§ãã
è©Šéšã容æã«ããããã«ã2.560VDCã® VREF/2 (ãã³ 9) é»å§ãš5.12VDCã® VCC é»æºé»å§ã䜿çšããªããã°ãªããŸãããããã§20mVã® LSBå€ãäœããŸãã
ãã«ã¹ã±ãŒã«èª¿æŽãããã®ã§ããã°ã5.090VDC (5.120 ïŒ 1.5LSB)
ã®ã¢ããã°å ¥åé»å§ãVIN (ïŒ )端åãã°ã©ãŠã³ãã«ããŠãVIN (ïŒ )
端åã«äŸçµŠããŠãã ãããVREF/2å ¥åé»å§ã®å€ããããžã¿ã«åºåã³ãŒããã¡ããã© 1111 1110ãã1111 1111ã«å€åãããŸã§èª¿æŽããŠãã ãããVREF/2ã®ãã®å€ã¯ãã®åŸã®ãã¹ãŠã®è©Šéšçšã«äœ¿çšãããªããŠã¯ãªããŸããã
ãã®ããžã¿ã«åºå LED衚瀺㯠2ã€ã® 16é²æ³ãã€ãŸã4ã€ã®æäžäœ (MS)ããããš 4ã€ã®æäžäœ (LS)ãããã« 8ããããåå²ããŠè§£èªãããŸããTable 1ã¯ããã2ã€ã® 4ãããã»ã°ã«ãŒãã®åæ°ãã€ã㪠(2 é² ) ã§ããããããã®ã瀺ããŠããŸããTable 1 ã®âVMSâãšâVLSâæ¬ããåŸãããé»å§ãå ããã°ãããžã¿ã«è¡šç€º (VREF/2ïŒ 2.560Vã®æ )ã®å ¬ç§°å€ã決å®ã§ããŸããäŸãã° LED衚瀺åºåã 1011 0110ãŸã㯠B6 (16é² )ã«ãšã£ãŠã¯ããã®ããŒãã«ããã®é»å§å€ã¯3.520ïŒ0.120ã€ãŸã3.640VDCã§ãããããã®é»å§å€ã¯å®å šãªA/Dã³ã³ããŒã¿ã®äžå¿å€ãè¡šãããŠããŸãããã®è©Šéšçµæã®å€æã§éåå誀差ã®åœ±é¿ãä¿èšŒããªããã°ãªããŸããã
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FIGURE 9. Basic A/D Tester
ããé«éã®ãã¹ãã·ã¹ãã ããŸãã¯ãããããããããŒã¿ãåŸãããã«ã¯ããã®ãã¹ãã®ã»ããã¢ããã®ããã« D/Aã³ã³ããŒã¿ãå¿ èŠãšããŸããA/Dã®ããã®ç²Ÿå¯é»å§æºãšããŠæ£ç¢ºãª 10ãããDACã圹ç«ã¡ãŸããè©Šéšäžã® A/Dã®èª€å·®ã¯ã¢ããã°é»å§ãŸã㯠2ã€ã®ããžã¿ã«ã¯ãŒãã«ãããå·®ã®ã©ã¡ãããšããŠè¡šãããŸãã
DACã䜿ããã¢ããã°åºåé»å§ãšããŠèª€å·®ãçºçããåºæ¬çãªA/Dãã¹ã¿ã Figure 10ã«ç€ºããŸããæ°åæžç®æ©èœä» DVM ããã®å·®é»å§âA-CâãçŽæ¥èªããå Žåã¯ããã® 2ã€ã®ãªãã¢ã³ããçç¥ã§ããŸããäœåšæ³¢ã©ã³ãçºçåšããã®ã¢ããã°å ¥åé»å§ãäŸçµŠã§ããã¢ããã°èª€å·® (Y軞 )察ã¢ããã°å ¥å (X軞 )ãäœæããã®ã« X-Yãããã¿ã䜿çšã§ããŸãã
ãã€ã¯ãããã»ããµãŸãã¯ã³ã³ãã¥ãŒã¿ã«ããšã¥ããã¹ãã·ã¹ãã ã®åäœã§ã¯ãããžã¿ã«çã«ãã®èª€å·®ãè¡šããç¹ã§ããã«äŸ¿å©ã§ãããã㯠Figure 11ã®åè·¯ã§å®è¡ã§ããŸããããã§ã¯ 10ãããDACããã®å ¥åå¢å ã«åŸãããã®åºåã³ãŒãã®å€åãæç¥ã§ããŸãããã¹ãããã 8ãããA/Dã«å¯ŸããŠã¯ 1/4 LSBã®ã¹ããããäœããŸãããã¹ãã®çµæãX軞äžã§ã¢ããã°å ¥åãY軞äžã§ãã®ãšã©ãŒ(LSB
ã«ãã㊠)ãšããŠèªåçã«ããããããããã°ããã¹ãçµæã®ããšã§A/Dã®æçšãªè»¢éé¢æ°ãšãªããŸããåå ¥ããã¹ãã§ã¯ããã®ããããã¯äžå¿ èŠã§ãåã³ãŒãã«å¯Ÿãã蚱容誀差ã®å éšãªããããèšããã°ããã®ãã¹ãé床ãäžããããšãã§ããŸãã
4.0 ãã€ã¯ãããã»ããµã»ã€ã³ã¿ãã§ãŒã¹
8080Aãš6800ãã€ã¯ãããã»ããµãšã®ã€ã³ã¿ãã§ãŒã¹ã«ã€ããŠèª¬æããã«ããããéåžžã®ãµã³ãã«ã»ãµãã«ãŒãã³ã䜿çšããŸãããã€ã¯ãããã»ããµã¯A/Då€æãéå§ããã16ã®é次å€æã®çµæãèªã¿ããããæ ŒçŽããŸãããããããŠãŒã¶ãŒã®ããã°ã©ã ã«åŸ©åž°ããŸãããã® 16ãã€ãããŒã¿ã¯ 16ã®é次ã¡ã¢ãªã¹ããŒã¹ã«æ ŒçŽãããŸãããã¹ãŠã®ããŒã¿ãšã¢ãã¬ã¹ã¯ 16é²æ³ã§äžããããŸãããœãããŠã§ã¢ãšããŒããŠã§ã¢ã®è©³çŽ°ã¯ãã€ã¯ãããã»ããµã®åã¿ã€ãã«ããå¥ ã«ã 説æããŠãããŸãã
4.1 8080 ãã€ã¯ãããã»ããµã»ãã¡ããªãšã®ã€ã³ã¿ãã§ãŒã¹(8084ã8085)
ãã®ã³ã³ããŒã¿ã«ã¯8080ç³»ãã€ã¯ãããã»ããµãšçŽæ¥ã€ã³ã¿ãã§ãŒã¹ã§ããããã«èšèšãããŠããŸãããã® A/D ãã¡ã¢ãªã»ã¹ããŒã¹ã«(CSãMEMRãMEMW ã¹ãããŒãã«å¯Ÿãæšæºã¡ã¢ãªã»ã¢ãã¬ã¹ã»ãã³ãŒãã£ã³ã°ã䜿çšã㊠)ãããã³ã°ã§ããŸããããã㯠I/O RãšI/O Wã¹ãããŒãã䜿çšã㊠CSå ¥åãåŸãããã«ãã¢ãã¬ã¹ãããA0â A7 (ãããã¯ããããåã 8ãããã»ã¢ãã¬ã¹æ å ±ãå«ãã§ããæã«ã¯ã¢ãã¬ã¹ã»ãããA8â A15)ããã³ãŒãã£ã³ã°ããã°ãI/Oããã€ã¹ãšããŠãã® A/Dãå¶åŸ¡ã§ããŸããI/Oã¹ããŒã¹ã®äœ¿çšã¯ 256ã®è¿œå ã¢ãã¬ã¹ãäœããç°¡å㪠8ãããã»ã¢ãã¬ã¹ã»ãã³ãŒããå¯èœã«ããŸãããããããã®ããŒã¿ã¯ãã®ã¢ãã¥ãã¥ã¬ãŒã¿ã«å¯Ÿãåã«å ¥åãããã ãã§ããããã«ã¡ã¢ãªåç §åœä»€ã䜿çšããã«ã¯ããã® A/Dã¯ã¡ã¢ãªã¹ããŒã¹å ã«ãããã³ã°ãããªããŠã¯ãªããŸãããI/Oã¹ããŒã¹ã§ã® A/Dã®äŸã¯ Figure 12ã«ç€ºãããŠããŸãã
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FIGURE 10. A/D Tester with Analog Error Output
FIGURE 11. Basic âDigitalâ A/D Tester
TABLE 1. DECODING THE DIGITAL OUTPUT LEDs
Note 15: åºåïŒVMSã°ã«ãŒãïŒVLSã°ã«ãŒãã衚瀺ããŸãã
OUTPUT VOLTAGEFRACTIONAL BINARY VALUE FOR CENTER VALUES
HEX BINARY WITHVREF/2ïŒ 2.560 VDC
MS GROUP LS GROUP VMS GROUP (Note 15)
VLS GROUP (Note 15)
F 1 1 1 1 15/16 15/256 4.800 0.300
E 1 1 1 0 7/8 7/128 4.480 0.280
D 1 1 0 1 13/16 13/256 4.160 0.260
C 1 1 0 0 3/4 3/64 3.840 0.240
B 1 0 1 1 11/16 11/256 3.520 0.220
A 1 0 1 0 5/8 5/128 3.200 0.200
9 1 0 0 1 9/16 9/256 2.880 0.180
8 1 0 0 0 1/2 1/32 2.560 0.160
7 0 1 1 1 7/16 7/256 2.240 0.140
6 0 1 1 0 3/8 3/128 1.920 0.120
5 0 1 0 1 5/16 2/256 1.600 0.100
4 0 1 0 0 1/4 1/64 1.280 0.080
3 0 0 1 1 3/16 3/256 0.960 0.060
2 0 0 1 0 1/8 1/128 0.640 0.040
1 0 0 0 1 1/16 1/256 0.320 0.020
0 0 0 0 0 0 0
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Note 16: *端åçªå·ã¯DP8228ã·ã¹ãã ã³ã³ãããŒã©ã®ç«¯åçªå·ã§ãããã®ä»ã®çªå·ã¯ INS8080Aã®ç«¯åçªå·ã§ãã
Note 17: ãµã³ãã«ã»ããã°ã©ã ã䌎ãå¿ èŠããããå²ã蟌ã¿ãèªç¥ãããæã«ã¯ RST 7åœä»€ãçºçãããããã«ã1kΩã®æµæã䜿ã£ãŠ INS8228ã®ãã³23ãïŒ 12V
ã«æ¥ç¶ããŠãã ããã
FIGURE 12. ADC0801_INS8080A CPU Interface
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SAMPLE PROGRAM FOR Figure 12 ADC0801âINS8080A CPU INTERFACE
Note 18: RST 7åœä»€ã¯ãã®ã¹ã¿ãã¯äžã« PCãããã·ã¥ããã®ã§ããã®ã¹ã¿ãã¯ã»ãã€ã³ã¿ãèšããŠãã ããã
Note 19: 䜿çšãããŠãããã¹ãŠã®ã¢ãã¬ã¹ã¯ä»»æã«éžæããããã®ã§ãã
8080 ã® CSãRDãWRã®æšæºå¶åŸ¡ãã¹ä¿¡å·ã A/Dã®ããžã¿ã«å¶åŸ¡å ¥åã«çŽæ¥çµç·ã§ããã³ã³ããŒã¿ã®å§åããã³ããŒã¿ã»ãã¹äžãžã®ããŒã¿åºåã®äž¡æ¹ãå¯èœã«ãããã¹ã»ã¿ã€ãã³ã°èŠæ±ã«åèŽããŠããŸãããã倧ããããªãã€ã¯ãããã»ããµã§ã¯ãã¹ã»ãã©ã€ãã䜿çšããªããŠã¯ãªããŸãããããã§ã¯ããŒã¿ã»ãã¹ã¯ PC åºæ¿ããåããããã㊠100pF以äžã®è² è·å®¹éãé§åã§ããªããŠã¯ãªããŸããã
4.1.1 8080A CPUãšã®ã€ã³ã¿ãã§ãŒã¹åè·¯ãšããã°ã©ã äŸ
Figure 12ã«ç€ºãããé¢é£ããŒããŠã§ã¢ãšãã®åŸã«ãããµã³ãã«ã»ããã°ã©ã ããã®ã³ã³ããŒã¿ãã INS8080A CPU ãããã»ãã(INS8080A ãã€ã¯ãããã»ããµãNS8228 ã·ã¹ãã ã³ã³ãããŒã©ãINS8224ã¯ããã¯ã»ãžã§ãã¬ãŒã¿ã§æ§æããã )ã«ããŒã¿ãå ¥åããã®ã«äœ¿çšã§ããŸããç°¡åã«ãA/D㯠I/Oããã€ã¹ãšããŠå¶åŸ¡ãããç¹ã«8ãããåæ¹åæ§ããŒãã¯ä»»æã«éžæããããŒãã¢ãã¬ã¹âE0âã«çœ®ãããŸããA/Dã®TRI-STATEåºåèœåã¯åšèŸºã®ã€ã³ã¿ãã§ãŒã¹ã»ããã€ã¹ã®å¿ èŠæ§ããªãããŸããããããã®ã³ã³ããŒã¿ã«å¯Ÿãé©åãªCSãçºçãããã®ã«ã¢ãã¬ã¹ã»ãã³ãŒãã£ã³ã°ãå¿ èŠãšããŸãã
A/Dã³ã³ããŒã¿ã 8ã€ã®å ã® 1ã€ãããã¯ããå°ãªã I/Oãããã³ã°ã»ããã€ã¹ã§ããå Žåã«ã¯ãã¢ãã¬ã¹ã»ãã³ãŒãã£ã³ã°åè·¯ãå¿ èŠãšããªãç¹ã«æ³šæããããšã倧åã§ãã8ã€ã®ã¢ãã¬ã¹ããã(A0
ïœA7)ã®å Iã /Oããã€ã¹çšã« 1ã€ãCSå ¥åãšããŠçŽæ¥å©çšã§ããŸãã
4.1.2 INS8048ãšã®ã€ã³ã¿ãã§ãŒã¹
ADC0801ã·ãªãŒãº (Figure 13 åç § )ãçšã㊠INS8048ãã€ã³ã¿ãã§ãŒã¹ããæè¡ã¯ã8080A CPU ã€ã³ã¿ãã§ãŒã¹ãã容æã§ãã8048ã«ã¯ 24ã® I/Oã©ã€ã³ãš3ã€ã®ãã¹ãå ¥åã©ã€ã³ããããŸãããããã®äœåã«ãã I/Oã©ã€ã³ã§ããã® I/Oã©ã€ã³ (ããŒã1ã®ããã0)ã® 1ã€ã¯ A/Dã«å¯Ÿãããããã»ã¬ã¯ãä¿¡å·ãšããŠäœ¿ãããäœåãªã¢ãã¬ã¹ãã³ãŒãã®äœ¿çšãé€ãããšãã§ããŸãã8048ã®ãã¹å¶åŸ¡ä¿¡å· RDãWRãINTã¯çŽæ¥ A/Dã«æ¥ç¶ãããŸãããã® 16ã®å€æãããããŒã¿ã¯ãŒã㯠20ïœ 2F (HEX)ãŸã§ã®ãªã³ããã RAM
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FIGURE 13. INS8048 Interface
SAMPLE PROGRAM FOR Figure 13 INS8048 INTERFACE
4.2 Z-80ãšã®ã€ã³ã¿ãã§ãŒã¹
Z-80å¶åŸ¡ãã¹ã¯ 8080ãšã¯å°ãç°ãªããŸããZ-80ã¯éåžžã® RDããã³WRã¹ãããŒãããã¡ãå¥ã®ã¡ã¢ãªèŠæ±âMREQâä¿¡å·ãšI/O èŠæ±âIORQâä¿¡å·ã䜿ããã8080 ä¿¡å·ãšåããã®ãäœãã®ã«ç·æ¬ããã¹ãããŒããšçµåãããªããŠã¯ãªããŸãããZ-80 ã䜿ã£ãŠ I/Oã¹ããŒã¹ã§A/Dãåäœãããå©ç¹ã¯ãCPUã 1ã€ã®åŸ ã¡ç¶æ (1ã€ã®ã¯ããã¯æéã ã RDãšWRã¹ãããŒããæ¡åŒµããŸã )ãèªåçã«æ¿å ¥ããŠãI/Oããã€ã¹ãå¿çããããã®æéãäžããããšã§ãã I/Oã¹ããŒã¹ã« A/Dããããã³ã°ããããã®ããžãã¯åè·¯ã Figure 14ã«ç€ºããŸãã
FIGURE 14. Mapping the A/D as an I/O Devicefor Use with the Z-80 CPU
ãœãããŠã§ã¢DMAã«ãŒãã³ãšããŠããã« I/Oã®åªäœæ§ãåŸãããI/Oå ¥ååœä»€ã®éäžäœ 8ã¢ãã¬ã¹ã©ã€ã³ (A8ïœA15)äžã«ååšããåºåããŒã¿ã®äŒéãããã®äœ¿çšã«ããè¡ããŸããäŸãã°ãA/D
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5.1 MC6800CPUã€ã³ã¿ãã§ãŒã¹ã«å¯Ÿããè€æ°ã® ADC0801ã·ãªãŒãº
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Note 20: ã«ãã³ã®æ°åã¯MC6800CPU端ååºåã«é¢ãããã®ã§ãã
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FIGURE 15. ADC0801-MC6800 CPU Interface
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Note 22: ãµãã«ãŒãã³ãšã€ã³ã¿ã©ãã (å²ã蟌㿠)ããµãŒãã¹ãããã€ã¯ãããã»ããµã®ããã«ãã¹ã¿ãã¯ã»ãã€ã³ã¿ã¯ãŠãŒã¶ãŒã®ããã°ã©ã ã«ãã£ãŠç¢ºä¿ãããªããŠã¯ãªããŸããã
FIGURE 16. ADC0801âMC6820 PIA Interface
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次ã®åè·¯ãšãµã³ãã«ã»ãµãã«ãŒãã³ (DATA IN)ã¯MC6800 CPU
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FIGURE 17. Interfacing Multiple A/Ds in an MC6800 System
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SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A/D's IN AN MC6800 SYSTEM
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1ã€ä»¥äžã®A/Dã³ã³ããŒã¿(ãŸãã¯ä»ã®åšèŸºããã€ã¹ )ããã€ã¯ãããã»ããµã®ããã°ã©ã ã«å²ã蟌ã¿ããããããŒã¿ã»ã¢ã¯ã€ãžã·ã§ã³ã»ã·ã¹ãã ã§ã¯ãæããã« CPUã¯ã©ã®A/Dã«ãµãŒãã¹ãããã決ããå¿ èŠããããŸããFigure 22ãšããã«ãšããªããœãããŠã§ã¢ã¯ã7åã® ADC0801ã³ã³ããŒã¿ãå€æãå®äºãã (INTRãã¢ãµãŒã )å²ã蟌ã¿ãèŠæ±ããã®ã決ããæ¹åŒã§ãããã®åè·¯ã¯ã©ã®ã·ãŒã±ã³ã¹ã§ã A/D ã³ã³ããŒã¿ã®å§åãå¯èœã«ããŸãããåªå ã·ãŒã±ã³ã¹ãæ〠A/D 1ãæåã«èªãŸãã2çªç®ã«A/D 2ã3çªç®ã« A/D 3
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FIGURE 20. Flow Chart for Auto-Zero Routine
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FIGURE 21. Software for Auto-Zeroed Differential A/D
5.3 Z-80Rå²ã蟌ã¿é§åã¢ãŒãã«ãããè€æ°ã® A/Dã³ã³ããŒã¿(ã€ã¥ã )
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ããããšãCPUã¯èªåçã« RST 7åœä»€ãå®è¡ãããã®ãšä»®å®ããŠããŸããã€ãŸããµãã«ãŒãã³ã¯X0038ã®ã¹ã¿ãŒãã»ã¢ãã¬ã¹ã«ãããŸãã
2) Z-80 ããã®ã¢ãã¬ã¹ã»ãã¹ãš Z-80 ã«å¯ŸããããŒã¿ã»ãã¹ã¯ãã¹ã»ãã©ã€ãã«ããå転ããããã®ãšããŸãã
3) A/DããŒã¿ãšèªèã¯ãŒãã¯ä»»æã«éžã°ããã¢ãã¬ã¹X3E00ã§ã¹ã¿ãŒãããã·ãŒã±ã³ã·ã£ã«ã»ã¡ã¢ãªã»ãã±ãŒã·ã§ã³ã§æ ŒçŽããããã®ãšããŸãã
4) RST 7åœä»€ã¯èªåçã«ã¹ã¿ãã¯äžã« PCãããã·ã¥ãããããŠãã®ãµãã«ãŒãã³ãè¿œå ã® 6ã¹ã¿ãã¯ã»ã¢ãã¬ã¹ã䜿çšããéã«ãã¡ã€ã³ããã°ã©ã§ãã®ã¹ã¿ãã¯ã»ãã€ã³ã¿ã確ä¿ããªããŠã¯ãªããŸããã
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FIGURE 22. Multiple A/Ds with Z-80 Type Microprocessor
16é²ããŒãã¢ãã¬ã¹ ããªãã§ã©ã«00 NM74 C374 8ãããã»ããªãããããã01 A/D 1
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16é²ããŒãã¢ãã¬ã¹ ããªãã§ã©ã«04 A/D 4
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06 A/D 6
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