IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 7, JULY 2003 1261

Brief Papers_______________________________________________________________________________

A 0.5-V 1-�W Successive Approximation ADCJens Sauerbrey, Doris Schmitt-Landsiedel, Member, IEEE, and Roland Thewes, Member, IEEE

Abstract—A successive approximation analog-to-digital con-verter (ADC) is presented operating at ultralow supply voltages.The circuit is realized in a 0.18- m standard CMOS technology.Neither low- devices nor voltage boosting techniques are used.All voltage levels are between supply voltage and ground

. A passive sample-and-hold stage and a capacitor-baseddigital-to-analog converter are used to avoid application ofoperational amplifiers, since opamp operation requires highervalues for the lowest possible supply voltage. The ADC hassignal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supplyvoltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s andpower consumptions of 30 and 0.85 W, respectively. Properoperation is achieved down to a supply voltage of 0.4 V.

Index Terms—Analog-to-digital converters (ADCs), CMOSanalog integrated circuits, low power, low supply voltage, succes-sive approximation, switched-capacitor circuits.

I. INTRODUCTION

I N MODERN CMOS processes, the maximally allowedsupply voltage is continuously decreasing, but the

threshold voltage of the devices is not scaled in proportionto due to off-state currents and the related static powerconsumption in logic circuits [1]. In the digital world, theincreasing ratio of is usually acceptable, however,for analog circuits, decreased signal swings and crucial designrestrictions result from that trend. In particular for valuesbelow the sum of the threshold voltages of n- and pMOSFETs( ), only a very limited number of circuit topologiesis still usable.

Specific process options as provision of low-devices helpthe analog circuit designer to overcome these constraints, butlead to increased process complexity and to increased costs.Adapted analog design approaches which avoid such optionsbut provide the same performance thus represent an attractivealternative.

Switched opamp circuits [2]–[5], reset-opamp circuits [6],and circuits using bootstrapping techniques [7], [8] have beenshown to be particularly suited under low conditionswithout specific process options. In the case of the latter designtechnique, however, gate voltages are applied to part of thedevices which exceed so that enhanced device stressoccurs.

Manuscript received November 25, 2002; revised February 21, 2003.J. Sauerbrey and R. Thewes are with Infineon Technologies AG, Corporate

Research, D-81730 Munich, Germany (e-mail: jens.sauerbrey@infineon.com).D. Schmitt-Landsiedel is with the Institute of Technical Electronics, Tech-

nical University of Munich, D-80333 Munich, Germany.Digital Object Identifier 10.1109/JSSC.2003.813217

Fig. 1. Successive approximation converter architecture.

In this paper, a successive approximation analog-to-digitalconverter (ADC) technique based on another approach is pre-sented which is suitable for medium-speed/medium-resolutionconverters. Similar to switched-opamp or reset-opamp circuits,this ADC is designed in a way that only reference voltages areswitched. Contrary to switched-opamp or reset-opamp circuits,which work well down to a minimum ratio of about1.5, the proposed circuit is able to be operated even at muchlower ratios. This is achieved using an opamp-free ar-chitecture, a capacitor-based digital-to-analog converter (DAC),and a passive sample-and-hold (S&H) stage.

The test circuit is realized to investigate the minimum supplyvoltage for ADCs using standard digital transistors. All voltagelevels are inside the supply voltage range, and bootstrappingtechniques are avoided. The circuit is based on existing low-voltage components from other work [5], [9]. The maximumclock frequency at a given supply voltage is determined by de-sign requirements of these components for their original pur-pose. Bandwidth optimization has not been performed in thiswork, i.e., the reported data do not necessarily represent themaximally achievable sampling rates.

II. CONVERTERPRINCIPLE

A. Basic Principle of Successive Approximation Converters

In Fig. 1, the basic architecture of a successive approxima-tion ADC is shown. The converter consists of a S&H stage, acomparator, a successive approximation register (SAR), and aDAC. Using a binary search algorithm, the DAC output voltage

successively approximates the sampled input voltage.In each clock cycle, one bit of the digital output signalis ob-tained.

B. Successive Approximation Converter Based on a ChargeRedistribution Principle

In Fig. 2, a converter based on a charge redistribution prin-ciple is depicted. Binary weighted capacitors are used for theDAC. The S&H function is realized by the DAC itself. Theswitching point of the comparator is independent of the value of

0018-9200/03$17.00 © 2003 IEEE

1262 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 7, JULY 2003

Fig. 2. Successive approximation architecture based on a charge redistributionprinciple.

Fig. 3. Modified architecture.

the input signal. During conversion, at the comparator input pos-itive and negative voltages referred to analog ground occur,whose magnitude is continuously decreasing with the number ofconversion steps performed within a complete conversion cycle.Consequently, at the end of the conversion cycle, i.e., whenhighest precision is demanded, both comparator inputs are op-erated near analog ground.

To avoid leakage currents at switch, analog ground shouldbe adjusted in the middle between and . On the otherhand, switch operation at ultralow supply voltages (e.g., under

conditions) is only possible if thedc level of the signal to be switched is close to or .Since theses requirements cannot be fulfilled simultaneously,the approach shown in Fig. 2 is not suitable for ultralow voltageapplications.

C. Modified Successive Approximation Converter

A modified architecture using a capacitor-based DAC isshown in Fig. 3. The DAC simply tracks the sampled ADCinput signal . and are used as reference levels.A shunt capacitor is operated as a capacitive divider toadjust the signals according to the low supply voltage oper-ating conditions of the circuit. Corresponding to 9- or 8-bitoperation, or is chosen as input voltage rangehere. Minimum input voltage equals in all cases. Thisadjustment guarantees proper comparator operation as well asproper S&H operation within the whole input voltage range.

In this architecture, the S&H function is no longer realizedby the capacitor array itself as in Fig. 2. A passive S&H stage isused here. This is sufficient as the load of the S&H stage onlyconsists of the MOSFET gate capacitance of the input transistorof the comparator. An advantage of this approach is that theinput capacitance of the whole converter is not determined bythe DAC capacitor array.

TABLE ICAPACITOR VALUES

Fig. 4. Comparator circuit.

III. CIRCUIT IMPLEMENTATION

A. Capacitor Array

The capacitors – in Fig. 3 are realized as multiples ofa unit capacitor of 20 fF. The chosen values result from thefact that approximately 10 pF are needed to guarantee the 9-bitlinearity requirement, further, 10 pF are required to realize theshunt capacitor . Since small differences of the value ofreferred to the value of capacitances provided by the capacitorarray only result in a small gain error but do not affect the lin-earity, is realized as a nonsubdivided large-area device for9-bit mode operation. In the 8-bit case, the shunt capacitor isobtained by connecting and from the 9-bit version inparallel (Table I).

The 9-bit mode is used when the supply voltage is largeenough for proper S&H and comparator function for a max-imum input voltage of . For smaller values of , the8-bit mode is used.

B. Comparator

The comparator is designed as a simple regenerative resetablecircuit (Fig. 4) [3] followed by inverters for signal level re-covery. The input common-mode voltage range is between 0 Vand or between 0 V and , respectively (cf. Sec-tion II-C). The bias current is provided by an external resistor.At V, a current of approximately 0.3A resultsin the comparator input stage. Depending on the comparatorinput signal, under this condition the pMOS input transistorsare operated at values between 46 and 113 mV.Although these transistors are not operated in strong inversionunder ultralow conditions, reasonable sampling rates areobtained (cf. Fig. 12) since only small capacitive loads have tobe driven by this subcircuit.

C. Successive Approximation Register

The SAR is realized in static CMOS logic. The related logiccircuit block also generates the clock signals for the comparator

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Fig. 5. Sample-and-hold circuit.

Fig. 6. Chip photograph.

and the S&H circuit. All clock signals are derived from an ex-ternally provided master clock.

D. S&H Circuit

The S&H circuit block diagram is given in Fig. 5. The sam-pling clock provided by the SAR is divided by two and anonoverlapping two-phase clock is generated. Both signals areprovided in complementary form to control the nMOS switchesand the related nMOS dummy switch devices. The sampling ca-pacitors and are alternately operated in sample and inhold operation.

The operating point of the switch transistors determines theminimum settling time. At low supply voltage these transistorsare no longer operated in strong inversion when switchedON.However, a relaxation of the impact of this operating conditionis obtained due to the fact that the sampling frequency is an orderof magnitude lower than the operating frequency of the com-parator. Moreover, the switching frequency is two times lowercompared to the sampling frequency since two time-interleavedsampling paths are used.

The sampling capacitors are not integrated on-chip here sincethe main goal of this work was to investigate the DAC corebehavior. We use relatively large values of 47 pF in our casein order to suppress packaging- and bondwire-related artifacts(i.e., crosstalk between the sampling paths which is caused bythe discrete assembly of the sampling capacitors, and the relatedcapacitive coupling between bondwires and between packagepins). Integration of these capacitors on-chip allows to signifi-cantly decrease their value, as will be discussed in more detailin Section IV-C.

IV. EXPERIMENTAL RESULTS

The ADC is fabricated in a standard 0.18-m n-well CMOSprocess with a single poly layer, four metal layers, and ametal–insulator–metal capacitor (MIMCAP) option. Thethreshold voltages are 0.43 V for the nMOS and0.38 V forthe pMOS device. A chip photograph is shown in Fig. 6. Chiparea is 0.11 mm.

Fig. 7. Measured INL and DNL in 9-bit mode atV = 1 V.

Fig. 8. Measured FFT spectrum atV = 0:5 V, 200 Hz input signalfrequency, 0.125 V input signal swing, and 4.1 kS/s sampling rate (8-bit mode,C = 47 pF).

Fig. 9. Measured FFT spectrum atV = 1 V, 6.4 kHz input signalfrequency, 0.5 V input signal swing, and 150 kS/s sampling rate (9-bit mode,C = 47 pF).

A. Static Measurements

Fig. 7 shows measured data of the integral nonlinearity (INL)and the differential nonlinearity (DNL) in the 9-bit mode at

V. To evaluate these parameters in the 8-bit mode,it is sufficient to consider only the codes from 1 to 256 in thesediagrams.

B. Dynamic Measurements

Fig. 8 shows a full-scale 200-Hz sine-wave spectrum mea-sured at V at a sampling rate of 4.1 kS/s in the

1264 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 7, JULY 2003

Fig. 10. SNDR versus input frequency atV = 0:5 V, sampling rate=4:1 kS=s,V = 0 dB (0.125 V),�3,�6,�10,�20,�30, and�40 dB (8-bitmode,C = 47 pF).

Fig. 11. SNDR versus input frequency atV = 1 V, sampling rate=150 kS=s,V = 0 dB (0.5 V),�3,�6,�10,�20,�30, and�40 dB (9-bitmode,C = 47 pF).

8-bit mode. In Fig. 9, a 6.4-kHz sine-wave spectrum measuredat V at a sampling rate of 150 kS/s in 9-bit mode isdepicted.

Signal-to-noise-plus-distortion ratio (SNDR) versus sinu-soidal input frequency at input levels between 0 and40 dBis shown in Figs. 10 and 11 at supply voltages of 0.5 and 1 V,respectively.

Fig. 12 shows the maximum sampling rate and the relatedpower dissipation as a function of supply voltage. The samplingrate decreases with a moderate slope from 150 to 34 kS/s forsupply voltages from 1 to 0.6 V. For smaller supply voltages, thedrop of the sampling rate is more pronounced. The maximumclock frequency is determined by malfunction of the digital cir-cuitry, proven by incorrect codes at higher clock rates.

Measured SNDR as a function of is shown in Fig. 13. Areasonable SNDR value under 9-bit mode operation is obtaineddown to a supply voltage of approximately 0.6 V. In 8-bit mode,the circuit shows proper operation down to a supply voltage of0.4 V. There, an SNDR of 38.9 dB at a sampling rate of 0.6 kS/sis achieved.

Characterization is performed at room temperature usingeight bonded samples from one wafer with typical processparameters. Measured results of all chips are very similar;differences in linearity are smaller than 0.2 LSB and deviationsof the maximum clock frequency are less than 2%. Measureddata are summarized in Table II.

Fig. 12. Maximum sampling rate and power dissipation versus supply voltage.

Fig. 13. SNDR versus supply voltage (C = 47 pF).

TABLE IIMEASUREDADC PERFORMANCE

C. Scaling of Sampling Capacitors

In this section, we estimate the impact of the value of thesampling capacitors when realized on-chip. The parasiticpackaging- and bondwire-related artifacts briefly discussed inSection III-D are most prominent at high frequencies within thespecified bandwidth, so that, in general, ADC characterization isperformed using large values of the externally realized samplingcapacitors ( pF) to suppress these effects.

These parasitic effects do not show under operation with low-frequency input signals. Fig. 14 shows SNDR versus sinusoidalinput frequency at input levels between 0 and40 dB at

V using a sampling capacitor of 5 pF. The degradation ofthe SNDR at high frequencies is obvious. At low frequencies,however, only minor deviations compared to the data obtainedwith pF (Fig. 10) are obtained.

Fig. 15 shows the low-frequency SNDR as a function of theused sampling capacitor value for supply voltages of 1 and 0.5 V,

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Fig. 14. SNDR versus input frequency atV = 0:5 V, sampling rate=4:1 kS=s,V = 0 dB (0.125 V),�3,�6,�10,�20,�30, and�40 dB (8-bitmode,C = 5 pF).

Fig. 15. Low-frequency SNDR versus sampling capacitor valueC .

respectively. Approximately 3-dB loss is measured for a sam-pling capacitor of 5 pF independent of the value.

This capacitance value corresponds well with simulated re-sults. There, a decrease of 3 dB in resolution is predicted fora sampling capacitor of 3.6 pF. Moreover, simulation revealsthat this loss in resolution is mainly determined by comparatorkickback noise. Note that distortion due to mismatch of the twosampling capacitors is irrelevant here, as the comparator inputcapacitance is much smaller compared to.

On the basis of these measurements and simulations, we iden-tify a reasonable value for on-chip sampling capacitors to be oforder 3–10 pF.

D. Figure of Merit

As a commonly used figure of merit (FOM) for ADCs con-sidering resolution, bandwidth, and power, we use

FOM

Sampling rate

Power dissipation(1)

FOM as a function of supply voltage is shown in Fig. 16 for8-bit and 9-bit operation. The resulting curves show a maximumin the range between 0.55–0.8 V, respectively. In this region, themost effective operation is obtained for the used devices withthreshold voltages of about 400 mV. These data translate into aratio of supply voltage and threshold voltage between 1.4 and 2.

E. Comparison With Other Approaches

Also in Fig. 13, published data about low-voltage succes-sive approximation converters from the literature are considered

Fig. 16. Figure of merit versus supply voltage (C = 47 pF).

[10]–[12]. As a consequence of the converter principle, the res-olution of all converters is of similar range. Concerning the min-imum supply voltage however, in this work the lowest value byfar is achieved.

V. CONCLUSION

A successive approximation converter suitable for operationat ultralow supply voltage is realized in a standard 0.18-mCMOS technology using transistors with threshold voltages ofapproximately 400 mV and avoiding bootstrapping techniques.Test results indicate that the circuit is well suited for opera-tion far below 1 V. Proper operation is shown down to a supplyvoltage of 0.4 V, which is approximately equal to the thresholdvoltages of the devices used.

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