ad9444 14-bit, 80 msps, a/d converter data sheet (rev. 0) · dcs mode dfs output mode t/h buffer 14...
TRANSCRIPT
14-Bit, 80 MSPS, A/D Converter
AD9444
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
80 MSPS guaranteed sampling rate 100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz 73.1 dB SNR with 70 MHz input 97 dBc SFDR with 70 MHz input Excellent linearity
DNL = ±0.4 LSB typical INL = ±0.6 LSB typical
1.2 W power dissipation 3.3 V and 5 V supply operation 2.0 V p-p differential full-scale input LVDS outputs (ANSI-644 compatible) Data format select Output clock available
APPLICATIONS
Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar, infared imaging Communications instrumentation
GENERAL DESCRIPTION
The AD9444 is a 14-bit monolithic, sampling analog-to-digital converter (ADC) with an on-chip, track-and-hold circuit and is optimized for power, small size, and ease of use. The product operates at up to an 80 MSPS conversion rate and is optimized for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment.
The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS-compatible (ANSI-644) or CMOS-compatible and include the means to reduce the overall current needed for short trace distances.
FUNCTIONAL BLOCK DIAGRAM
CMOSOR
LVDSOUTPUTSTAGING
CLOCKAND TIMING
MANAGEMENT
AGND DRGND DRVDD
VREF
CLK+
VIN+
AD9444
VIN–
CLK–DCO
0508
9-00
1
AVDD1 AVDD2
DCS MODE
DFS
OUTPUT MODE
T/H
BUFFER14
PIPELINEADC
2
28
2
OR
D13–D0
REF
REFBSENSE REFT
Figure 1.
Optional features allow users to implement various selectable operating conditions, including data format select and output data mode.
The AD9444 is available in a 100-lead surface-mount plastic package (100-lead TQFP/EP) specified over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High performance: Outstanding SFDR performance for mul-ticarrier, multimode 3G and 4G cellular base station receivers.
2. Ease of use: On-chip reference and track-and-hold. An output clock simplifies data capture.
3. Packaged in a Pb-free, 100-lead TQFP/EP.
4. Clock DCS maintains overall ADC performance over a wide range of clock pulse widths.
5. OR (out-of-range) outputs indicate when the signal is beyond the selected input range.
AD9444
Rev. 0 | Page 2 of 40
TABLE OF CONTENTS DC Specifications ............................................................................. 3
AC Specifications.............................................................................. 4
Digital Specifications........................................................................ 5
Switching Specifications .................................................................. 6
Explanation of Test Levels........................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Definitions of Specifications ........................................................... 9
Pin Configurations and Function Descriptions ......................... 10
Equivalent Circuits ......................................................................... 14
Typical Performance Characteristics ........................................... 15
Theory of Operation ...................................................................... 20
Analog Input and Reference Overview ................................... 20
Clock Input Considerations...................................................... 22
Power Considerations................................................................ 23
Digital Outputs ........................................................................... 23
Timing ......................................................................................... 23
Operational Mode Selection ..................................................... 23
Evaluation Board ........................................................................ 24
LVDS Evaluation Board Schematics ........................................ 25
LVDS Mode Evaluation Board Bill of Materials (BOM) ...... 30
CMOS Evaluation Board Schematics ...................................... 32
CMOS Mode Evaluation Board Bill of Materials (BOM)..... 37
Outline Dimensions ....................................................................... 39
Ordering Guide .......................................................................... 39
REVISION HISTORY
10/04—Revision 0: Initial Version
AD9444
Rev. 0 | Page 3 of 40
DC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 1. AD9444BSVZ-80
Parameter Temp Test Level Min Typ Max Unit
RESOLUTION Full VI 14 Bits ACCURACY
No Missing Codes Full VI Guaranteed Offset Error Full VI 6 ±0.3 6 mV Gain Error1 Full VI −3.0 ±0.4 +3.0 % FSR Differential Nonlinearity (DNL)2 Full VI −0.8 ±0.4 +0.8 LSB Integral Nonlinearity (INL)2 25°C I −1.3 ±0.6 +1.3 LSB
Full VI −1.7 +1.7 LSB TEMPERATURE DRIFT
Offset Error Full V 12 µV/°C Gain Error Full V 0.002 %FS/°C
VOLTAGE REFERENCE Output Voltage1 Full VI 0.87 1.0 1.13 V Load Regulation @ 1.0 mA Full V ±2 mV Reference Input Current (External 1.0 V Reference) Full VI 80 125 µA
INPUT REFERRED NOISE 25°C V 1.0 LSB rms ANALOG INPUT
Input Span Full V 2 V p-p Input Common-Mode Voltage Full V 3.5 V Input Resistance3 Full V 1 kΩ Input Capacitance3 Full V 2.5 pF
POWER SUPPLIES Supply Voltage
AVDD1 Full IV 3.14 3.3 3.46 V AVDD2 Full IV 4.75 5.0 5.25 V DRVDD—LVDS Outputs Full IV 3.0 3.6 V DRVDD—CMOS Outputs Full IV 3.0 3.3 3.6 V
Supply Current AVDD1 Full VI 217 240 mA AVDD22 Full VI 71 80 mA IDRVDD2—LVDS Outputs Full VI 55 62 mA IDRVDD2—CMOS Outputs Full V 12 mA
PSRR Offset Full V 1 mV/V Gain Full V 0.2 %/V
POWER CONSUMPTION DC Input—LVDS Outputs Full VI 1.21 1.4 W DC Input—CMOS Outputs Full V 1.07 W Sine Wave Input2—LVDS Outputs Full VI 1.25 W Sine Wave Input2—CMOS Outputs Full V 1.11 W
1 The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444. 2 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode. 3 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to for the equivalent analog input
structure. Figure 6
AD9444
Rev. 0 | Page 4 of 40
AC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 2. AD9444BSVZ-80
Parameter Temp Test Level Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR) fIN = 10 MHz 25°C IV 73.0 74.0 dB
Full IV 72.7 dB fIN = 35 MHz 25°C I 72.4 73.7 dB Full IV 72.3 dB fIN = 70 MHz 25°C IV 72.3 73.1 dB
Full IV 72.0 dB fIN = 100 MHz 25°C V 72.3 dB
SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 10 MHz 25°C IV 73.0 74.0 dB
Full IV 72.7 dB fIN = 35 MHz 25°C I 72.4 73.7 dB Full IV 72.2 dB fIN = 70 MHz 25°C IV 72.2 73.1 dB
Full IV 72.0 dB fIN = 100 MHz 25°C V 72.3 dB
EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C V 12.1 Bits fIN = 35 MHz 25°C V 12.0 Bits fIN = 70 MHz 25°C V 11.9 Bits fIN = 100 MHz 25°C V 11.8 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 10 MHz 25°C IV 91 97 dBc
Full IV 87 dBc fIN = 35 MHz 25°C I 91 97 dBc Full IV 87 dBc fIN = 70 MHz 25°C IV 90 97 dBc
Full IV 87 dBc fIN = 100 MHz 25°C V 96 dBc
WORST HARMONIC, SECOND OR THIRD fIN = 10 MHz 25°C IV −97 −91 dBc
Full IV −87 dBc fIN = 35 MHz 25°C I −97 −91 dBc Full IV −87 dBc fIN = 70 MHz 25°C IV −97 −90 dBc
Full IV −87 dBc fIN = 100 MHz 25°C V −96 dBc
WORST SPUR EXCLUDING SECOND OR HARMONICS fIN = 10 MHz 25°C IV −102 −93 dBc
Full IV −93 dBc fIN = 35 MHz 25°C I −103 −93 dBc Full IV −93 dBc fIN = 70 MHz 25°C IV −102 −93 dBc
Full IV −93 dBc fIN = 100 MHz 25°C V −99 dBc
TWO-TONE SFDR fIN = 10.8 MHz @ −7 dBFS, 9.8 MHz @ −7 dBFS 25°C V −102 dBFS fIN = 70.3 MHz @ −7 dBFS, 69.3 MHz @ −7 dBFS 25°C V −100 dBFS
ANALOG BANDWIDTH Full V 650 MHz
AD9444
Rev. 0 | Page 5 of 40
DIGITAL SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 kΩ, unless otherwise noted.
Table 3. AD9444BSVZ-80
Parameter Temp Test Level Min Typ Max Unit
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Full IV 2.0 V Low Level Input Voltage Full IV 0.8 V High Level Input Current Full VI +200 µA Low Level Input Current Full VI −10 +10 µA Input Capacitance Full V 2 pF
DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR)1 DRVDD = 3.3 V
High Level Output Voltage Full IV 3.25 V Low Level Output Voltage Full IV 0.2 V
DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR) VOD Differential Output Voltage2 Full VI 247 545 mV VOS Output Offset Voltage Full VI 1.125 1.375 V
CLOCK INPUTS (CLK+, CLK−) Differential Input Voltage Full IV 0.2 V Common-Mode Voltage Full VI 1.3 1.5 1.6 V Differential Input Resistance Full V 8 10 12 kΩ Differential Input Capacitance Full V 4 pF
1 Output voltage levels measured with 5 pF load on each output. 2 LVDS RTERM = 100 Ω.
AD9444
Rev. 0 | Page 6 of 40
SWITCHING SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4. AD9444BSVZ-80
Parameter Temp Test Level Min Typ Max Unit
CLOCK INPUT PARAMETERS Maximum Conversion Rate Full VI 80 MSPS Minimum Conversion Rate Full V 10 MSPS CLK Period Full V 12.5 ns CLK Pulse Width High1 (tCLKH) Full V 4 ns CLK Pulse Width Low1 (tCLKL) Full V 4 ns
DATA OUTPUT PARAMETERS Output Propagation Delay—CMOS (tPD)2 (DX, DCO+) Full IV 3 5.25 8 ns Output Propagation Delay—LVDS (tPD)3 (DX+, DCO+) Full VI 3 5 7.5 ns Pipeline Delay (Latency) Full V 12 Cycles Aperture Delay (tA) Full V ns Aperture Uncertainty (Jitter, tJ) Full V 0.2 ps rms
1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load. 3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
N–12 N–11 N N+1
AIN
CLK+
CLK–
DATA OUT
DCO+
DCO–
N
N+1
N–1
tCLKH
tCLKL
1/fS
tPD
12 CLOCK CYCLES
tCPD
0508
9-00
2
Figure 2. LVDS Mode Timing Diagram
AD9444
Rev. 0 | Page 7 of 40
N+1N+2
N–1
tCLKL
12 CYCLES
0508
9-00
3
N
tCLKH
tPD
VIN
CLK+
CLK–
DX
DCO+
DCO–
tDCOPD
N-12 N-11 N-1 N
Figure 3. CMOS Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level Definitions I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
AD9444
Rev. 0 | Page 8 of 40
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter With Respect to Min Max Unit
ELECTRICAL AVDD1 AGND −0.3 +4 V AVDD2 AGND −0.3 +6 V DRVDD DGND −0.3 +4 V AGND DGND −0.3 +0.3 V AVDD1 DRVDD −4 +4 V AVDD2 DRVDD −4 +6 V AVDD2 AVDD1 −4 +6 V D0 to D13 DGND –0.3 DRVDD + 0.3 V CLK, MODE AGND –0.3 AVDD1 + 0.3 V VIN+, VIN− AGND –0.3 AVDD2 + 0.3 V VREF AGND –0.3 AVDD1 + 0.3 V SENSE AGND –0.3 AVDD1 + 0.3 V REFT, REFB AGND –0.3 AVDD1 + 0.3 V
ENVIRONMENTAL Storage Temperature –65 +125 °C Operating Temperature Range –40 +85 °C Lead Temperature Range
(Soldering 10 sec) 300 °C
Junction Temperature 150 °C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Resistance
The heat sink of the AD9444 package must be soldered to ground.
Table 6. Package Type θJA θJB θJC Unit 100-Lead TQFP/EP 19.8 8.3 2 °C/W
Typical θJA = 19.8°C/W (heat-sink soldered) for multilayer board in still air.
Typical θJB = 8.3°C/W (heat-sink soldered) for multilayer board in still air.
Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal resistance through heat-sink path.
Airflow increases heat dissipation effectively reducing θJA. Also, more metal directly in contact with the package leads, from metal traces, through holes, ground, and power planes, reduces the θJA. It is required that the exposed heat sink be soldered to the ground plane.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprie-tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD9444
Rev. 0 | Page 9 of 40
DEFINITIONS OF SPECIFICATIONS Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter, tJ) The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes must be present over all operating ranges.
Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula
( )6.02
1.76−=
SINADENOB
Gain Error The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1 ½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1 ½ LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
Maximum Conversion Rate The clock rate at which parametric testing is performed.
Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Offset Error The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point.
Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
Output Propagation Delay (tPD) The delay between the clock rising edge and the time when all bits are within valid logic levels.
Power-Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.
Signal-to-Noise and Distortion (SINAD) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo-nent may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale).
Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX.
Total Harmonic Distortion (THD) The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components.
Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.
AD9444
Rev. 0 | Page 10 of 40
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
26 27 28 29 30
5554535251
TOP VIEW(Not to Scale)
AD9444
AVD
D1
AVD
D1
AVD
D2
AVD
D2
AVD
D2
5432
76
98
1
1110
16151413
1817
2019
2221
12
2423
25
32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 5031 37
AVD
D2
AG
ND C1
AVD
D1
AVD
D1
CLK
+C
LK–
AVD
D1
AVD
D2
AVD
D2
AVD
D1
AVD
D1
(LSB
) D0–
D0+ D1–
D1+
DR
VDD
DR
GN
DD
2–D
2+
80D
13–
79D
12+
78D
12–
77D
11+
76D
11–
75 DRVDD74 DRGND73 D10+72 D10–71 D9+70 D9–69 D8+68 D8–67 DRGND66 D7+65 D7–64 DCO+63 DCO–62 DRVDD61 DRGND60 D6+59 D6–58 D5+57 D5–56 D4+
D4–DRVDDDRGNDD3+D3–
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DC
S M
OD
EA
GN
DA
VDD
1A
GN
DA
GN
DA
VDD
1A
VDD
1A
VDD
1A
VDD
1A
VDD
1A
VDD
1A
VDD
1A
GN
DA
VDD
1A
GN
DO
R+
OR
–D
RVD
DD
RG
ND
D13
+ (M
SB)
AVDD1DNCDNCDNC
OUTPUT MODEDFS
LVDSBIASAVDD1AVDD1SENSE
VREFAGNDREFTREFBAGND
AVDD1AVDD1AVDD1AVDD2AGND
VIN+VIN–
AGNDAVDD1AVDD1
0508
9-00
4DNC = DO NOT CONNECT
Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode
AD9444
Rev. 0 | Page 11 of 40
Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode Pin No. Mnemonic Description 1, 8 to 9, 16 to 18, 24 to 27, 34 to 35, 38, 41 to 42, 87, 89 to 95, 98
AVDD1 3.3 V (±5%) Analog Supply.
2 to 4 DNC Do Not Connect. These pins should float.
5 OUTPUT MODE
CMOS Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode, and OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
6 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos comple-ment, DFS = low (ground) for offset binary format.
7 LVDSBIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
10 SENSE Reference Mode Selection. Connect to AGND for internal 1 V reference, and connect to AVDD2 for external reference.
11 VREF 1.0 V Reference I/O—Function Dependent on SENSE. Decouple to ground with 0.1 µF and 10 µF capacitors.
12, 15, 20, 23, 32, 86, 88, 96 to 97, 99, Exposed Heat Sink
AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND.
13 REFT Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB (Pin 14) with 0.1 µF and 10 µF capacitors.
14 REFB Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT (Pin 13) with 0.1 µF and 10 µF capacitors.
19, 28 to 31, 39 to 40
AVDD2 5.0 V Analog Supply (±5%).
21 VIN+ Analog Input—True. 22 VIN− Analog Input—Complement. 33 C1 Internal Bypass Node. Connect a
0.1 µF capacitor from this pin to AGND.
36 CLK+ Clock Input—True. 37 CLK− Clock Input—Complement. 43 D0− (LSB) D0 Complement Output Bit
(LVDS Levels).
Pin No. Mnemonic Description 44 D0+ D0 True Output Bit. 45 D1− D1 Complement Output Bit. 46 D1+ D1 True Output Bit. 47, 54, 62, 75, 83
DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
48, 53, 61, 67, 74, 82
DRGND Digital Ground.
49 D2− D2 Complement Output Bit. 50 D2+ D2 True Output Bit. 51 D3− D3 Complement Output Bit. 52 D3+ D3 True Output Bit. 55 D4− D4 Complement Output Bit. 56 D4+ D4 True Output Bit. 57 D5− D5 Complement Output Bit. 58 D5+ D5 True Output Bit. 59 D6− D6 Complement Output Bit. 60 D6+ D6 True Output Bit. 63 DCO− Data Clock Output—Complement. 64 DCO+ Data Clock Output—True. 65 D7− D7 Complement Output Bit. 66 D7+ D7 True Output Bit. 68 D8− D8 Complement Output Bit. 69 D8+ D8 True Output Bit. 70 D9− D9 Complement Output Bit. 71 D9+ D9 True Output Bit. 72 D10− D10 Complement Output Bit. 73 D10+ D10 True Output Bit. 76 D11− D11 Complement Output Bit. 77 D11+ D11 True Output Bit. 78 D12− D12 Complement Output Bit. 79 D12+ D12 True Output Bit. 80 D13− D13 Complement Output. 81 D13+ (MSB) D13 True Output Bit. 84 OR− Out-of-Range Complement
Output Bit. 85 OR+ Out-of-Range True Output Bit. 100 DCS MODE Clock Duty Cycle Stabilizer (DCS)
Control Pin, CMOS-Compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS.
AD9444
Rev. 0 | Page 12 of 40
26 27 28 29 30
5554535251
TOP VIEW(Not to Scale)
AD9444
AVD
D1
AVD
D1
AVD
D2
AVD
D2
AVD
D2
5432
76
98
1
1110
16151413
1817
2019
2221
12
2423
25
32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 5031 37
AVD
D2
AG
ND C1
AVD
D1
AVD
D1
CLK
+C
LK–
AVD
D1
AVD
D2
AVD
D2
AVD
D1
AVD
D1
DN
CD
NC
DN
CD
NC
DR
VDD
DR
GN
DD
NC
DN
C
80 79 78 77 76
75 DRVDD74 DRGND73 D672 D571 D470 D369 D268 D167 DRGND66 D0 (LSB)65 DNC64 DCO+63 DCO–62 DRVDD61 DRGND60 DNC59 DNC58 DNC57 DNC56 DNC
DNCDRVDDDRGNDDNCDNC
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AVDD1DNCDNCDNC
OUTPUT MODEDFSDNC
AVDD1AVDD1SENSE
VREFAGNDREFTREFBAGND
AVDD1AVDD1AVDD1AVDD2AGND
VIN+VIN–
AGNDAVDD1AVDD1
0508
9-00
5
DNC = DO NOT CONNECT
DC
S M
OD
EA
GN
DA
VDD
1
AG
ND
AG
ND
AVD
D1
AVD
D1
AVD
D1
AVD
D1
AVD
D1
AVD
D1
AVD
D1
AG
ND
AVD
D1
AG
ND
OR
D13
(MSB
)D
RVD
DD
RG
ND
D12
D11
D10
D9
D8
D7
Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode
AD9444
Rev. 0 | Page 13 of 40
Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode Pin No. Mnemonic Description 1, 8 to 9, 16 to 18, 24 to 27, 34 to 35, 38, 41 to 42, 87, 89 to 95, 98
AVDD1 3.3 V (±5%) Analog Supply.
2 to 4, 7, 43 to 46, 49 to 52, 55 to 60, 65
DNC Do Not Connect. These pins should float.
5 OUTPUT MODE
CMOS Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode, and OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
6 DFS Data Format Select Pin. CMOS control pin that de-termines the format of the output data. DFS = high (AVDD1) for twos comple-ment, DFS = low (ground) for offset binary format.
10 SENSE Reference Mode Selection. Connect to AGND for internal 1 V reference, and connect to AVDD2 for external reference.
11 VREF 1.0 V Reference I/O— Function Dependent on SENSE. Decouple to ground with 0.1 µF and 10 µF capacitors.
12, 15, 20, 23, 32, 86, 88, 96 to 97, 99, Exposed Heat Sink
AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND.
13 REFT Differential Reference Out-put. Decoupled to ground with 0.1 µF capacitor and to REFB (Pin 14) with 0.1 µF and 10 µF capacitors.
14 REFB Differential Reference Out-put. Decoupled to ground with a 0.1 µF capacitor and to REFT (Pin 13) with 0.1 µF and 10 µF capacitors.
19, 28 to 31, 39 to 40
AVDD2 5.0 V Analog Supply (±5%).
21 VIN+ Analog Input—True. 22 VIN− Analog Input—Complement.
Pin No. Mnemonic Description 33 C1 Internal Bypass Node.
Connect a 0.1 µF capacitor from this pin to AGND.
36 CLK+ Clock Input—True. 37 CLK− Clock Input—Complement. 47, 54, 62, 75, 83
DRVDD 3.3 V Digital Output Supply (2.5V to 3.6 V).
48, 53, 61, 67, 74, 82
DRGND Digital Ground.
63 DCO− Data Clock Output— Complement (CMOS Levels).
64 DCO+ Data Clock Output— True.
66 D0 (LSB) D0 Output Bit (LSB) (CMOS Levels).
68 D1 D1 Output Bit. 69 D2 D2 Output Bit. 70 D3 D3 Output Bit. 71 D4 D4 Output Bit. 72 D5 D5 Output Bit. 73 D6 D6 Output Bit. 76 D7 D7 Output Bit. 77 D8 D8 Output Bit. 78 D9 D9 Output Bit. 79 D10 D10 Output Bit. 80 D11 D11 Output Bit. 81 D12 D12 Output Bit. 84 D13 (MSB) D13 Output Bit. 85 OR Out-of-Range Output. 100 DCS MODE Clock Duty Cycle Stabilizer
(DCS) Control Pin, CMOS- Compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS.
AD9444
Rev. 0 | Page 14 of 40
EQUIVALENT CIRCUITS
X1
AVDD2
3.5V
1kΩ
1kΩ
AVDD2
VIN+
VIN–
SHA
AVDD2
0508
9-00
62.5pF
2.5pF
Figure 6. Equivalent Analog Input Circuit
0508
9-00
7
1.2V
DRVDD DRVDD
K
3.74kΩ ILVDSOUT
LVDSBIAS
Figure 7. Equivalent LVDS BIAS Circuit
DRVDD
DX– DX+
V
V
V
V
0508
9-00
8
Figure 8. Equivalent LVDS Digital Output Circuit
DX
DRVDD
0508
9-00
9
Figure 9. Equivalent CMOS Digital Output Circuit
DCS MODE,OUTPUT MODE,
DFS
VDD
30kΩ
0508
9-01
0
Figure 10. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE
CLK+
12kΩ
10kΩ
150Ω 150Ω
12kΩ
10kΩ
AVDD2
CLK–
0508
9-01
1
Figure 11. Equivalent Sample Clock Input Circuit
AD9444
Rev. 0 | Page 15 of 40
TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, sample rate = 80 MSPS, LVDS mode, DCS enabled, TA = 25°C, 2 V p-p differential input, AIN = −0.5 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted.
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30 35 40FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0508
9-01
2
80MSPS10.1MHz @ –0.5dBFSSNR: 73.9dBENOB: 12.0BITSSFDR: 97dBc
0
Figure 12. 64K Point Single-Tone FFT/80 MSPS/10.1 MHz
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30 35 40FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0508
9-01
3
80MSPS30.3MHz @ –0.5dBFSSNR: 74.0dBENOB: 12.1BITSSFDR: 95dBc
0
Figure 13. 64K Point Single-Tone FFT/80 MSPS/30.3 MHz
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30 35 40FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0508
9-01
4
80MSPS70.3MHz @ –0.5dBFSSNR: 73.3dBENOB: 11.9BITSSFDR: 100dBc
0
Figure 14. 64K Point Single-Tone FFT/80 MSPS/70 MHz
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30 35 40FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0508
9-01
5
80MSPS100.3MHz @ –0.5dBFSSNR: 72.3dBENOB: 11.8BITSSFDR: 96dBc
0
Figure 15. 64K Point Single-Tone FFT/80 MSPS/100 MHz
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30 35 40FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0508
9-01
6
080MSPS125MHz @ –0.5dBFSSNR: 71.2dBENOB: 11.6BITSSFDR: 91dBc
Figure 16. 64K Point Single-Tone FFT/80 MSPS/125 MHz
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30 35 40FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0508
9-01
780MSPS151MHz @ –0.5dBFSSNR: 71.1dBENOB: 11.5BITSSFDR: 87dBc
0
Figure 17. 64K Point Single-Tone FFT/80 MSPS/151 MHz
AD9444
Rev. 0 | Page 16 of 40
65
66
67
68
69
70
71
72
73
74
75
0 20 40 60 80 100 120 140 160 180 200ANALOG INPUT FREQUENCY (MHz)
(dB
)
0508
9-01
8
SNR dB @ +85°C
SNR dB @ –40°C
SNR dB @ +25°C
Figure 18. SNR vs. Analog Input Frequency, 80 MSPS/LVDS Mode 05
089-
01970
75
80
85
90
95
105
0 20 40 60 80 100 120 140 160 180 200ANALOG INPUT FREQUENCY (MHz)
(dB
)
SFDR dBc @ +85°CSFDR dBc @ +25°C
100
SFDR dBc @ –40°C
Figure 19. SFDR vs. Analog Input Frequency, 80 MSPS/LVDS Mode
10
20
30
40
50
60
70
80
90
100
110
120
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0ANALOG INPUT AMPLITUDE (dBc)
(dB
)
0508
9-02
0
THIRD –dBFS SECOND –dBFS
SFDR –dBFS
THIRD –dBc
SECOND –dBc
SFDR –dBFS
Figure 20. Single-Tone SFDR/Second/Third vs. Analog Input Level, 80 MSPS, AIN = 30.3 MHz
0508
9-02
165
66
67
68
69
70
71
72
73
74
75
0 20 40 60 80 100 120 140 160 180 200ANALOG INPUT FREQUENCY (MHz)
(dB
)
SNR dB @ +85°C
SNR dB @ –40°C
SNR dB @ +25°C
Figure 21. SNR vs. Analog Input Frequency, 80 MSPS/CMOS Mode
0508
9-02
2
0 20 40 60 80 100 120 140 160 180 200ANALOG INPUT FREQUENCY (MHz)
SFDR dBc @ +25°C
SFDR dBc @ –40°C
SFDR dBc @ +85°C
70
75
80
85
90
95
100
105
(dB
)
Figure 22. SFDR vs. Analog Input Frequency, 80 MSPS/CMOS Mode
0508
9-02
310
20
30
40
50
60
70
80
90
100
110
120
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
ANALOG INPUT AMPLITUDE (dBc)
(dB
)
THIRD –dBFSSECOND –dBFS
SFDR –dBFS
THIRD –dBc
SECOND –dBc
SFDR –dBFS
Figure 23. Single-Tone SFDR/Second/Third vs. Analog Input Level 80 MSPS, AIN = 70.30 MHz
AD9444
Rev. 0 | Page 17 of 40
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30 35 40FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0508
9-02
4
0SFDR: 102dBFS
Figure 24. 32K Point Two-Tone FFT 80 MSPS/9.8 MHz/10.8 MHz
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30 35 40FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0508
9-02
50
–110
–90
–70
–50
–30
–10SFDR: –100dBFS
Figure 25. 32K Point Two-Tone FFT 80 MSPS/69.3 MHz/70.3 MHz
70
75
80
85
90
95
100
20 30 40 50 60 70 80 90 100 110SAMPLE RATE (MSPS)
SFD
R (d
B)
0508
9-02
6
Figure 26. SFDR vs. Sample Rate, VIN = 10.3 MHz @ −0.5 dBFS
–120
–100
–80
–60
–40
–20
IMD
(dB
FS)
0508
9-02
7
0
–110
–90
–70
–50
–30
–10
–110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0ANALOG INPUT LEVEL (dBFS)
WORST THIRD-ORDER IMD (dBFS)
SFDR (dBFS)
WORST THIRD-ORDER IMD (dBc)
90dBFS REFERENCE LINE
SFDR (dBc)
Figure 27. Two-Tone SFDR vs. Analog Input Level, AIN = 9.8 MHz/10.8 MHz
–120
–100
–80
–60
–40
–20
SFD
R A
ND
IMD
3 (d
B)
0508
9-02
8
0
–110
–90
–70
–50
–30
–10
–110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0ANALOG INPUT LEVEL (dBFS)
WORST THIRD-ORDER IMD (dBFS)
SFDR (dBFS)
WORST THIRD-ORDER IMD (dBc)
90dBFS REFERENCE LINE
SFDR (dBc)
Figure 28. Two-Tone SFDR vs. Analog Input Level, AIN = 69.3 MHz/70.3 MHz
70
75
80
85
90
95
100
10 20 30 40 50 60 70 80 90 100 110SAMPLE RATE (MSPS)
SFD
R (d
B)
0508
9-02
9
Figure 29. SFDR vs. Sample Rate, VIN = 70.3 MHz @ −0.5 dBFS
AD9444
Rev. 0 | Page 18 of 40
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 7.68 15.36 23.04 30.72FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0508
9-03
0
61.44MSPSTOTAL INPUT SIGNALPOWER: –30dBFS
Figure 30. 64K FFT, 61.44 MSPS, 4 @ WCDMA, IF = 46.08 MHz
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 5 10 15 20 25 30 35 40FREQUENCY (MHz)
AM
PLIT
UD
E (d
BFS
)
0508
9–03
1
NPR: 63.1dB
Figure 31. NPR, 80 MSPS/18 MHz Notch
0508
9-03
270
75
80
85
90
95
100
105
20 30 40 50 60 70 80CLOCK DUTY CYCLE (%)
dB
SFDR - DCS OFF (dBFS)
SFDR - DCS ON (dBFS)
SNR - DCS OFF (dB)
SNR - DCS ON (dB)
Figure 32. Single-Tone SNR/SFDR vs. Clock Duty Cycle, FSAMPLE = 80 MSPS, 10.3 MHz @ −0.5 dBFS
0508
9-03
30
2000
4000
6000
8000
10000
12000
8179 8180 8181 8182 8183 8184 8185 8186 8187BIN
FREQ
UEN
CY
Figure 33. Ground Input Histogram 80 MSPS, VIN+ = VIN−, 32K Samples
0508
9-03
450
70
90
110
130
150
170
190
210
230
250
20 30 40 50 60 70 80 90 100 110 120 130SAMPLE RATE (MSPS)
CU
RR
ENT
(mA
) AVDD1 (3.3V)
AVDD2 (5.0V)DRVDD (3.3V)
Figure 34. ISUPPLY vs. Sample Rate, AIN = 10.3 MHz @ −0.5 dBFS
60
65
70
75
80
85
90
95
100
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9VIN COMMON-MODE (V)
(dB
)
0508
9-03
5
SFDR (dBc)
SNR (dB)
Figure 35. Single-Tone SNR/SFDR vs. VIN Common-Mode Voltage 80 MSPS/10.3 MHz
AD9444
Rev. 0 | Page 19 of 40
0508
9-03
60.951
0.952
0.953
0.954
0.955
0.956
0.957
0.958
0.959
0.960
0.961
–20 0 20 40 60 80TEMPERATURE (°C)
REF
EREN
CE
VOLT
AG
E (V
)
–40
Figure 36. VREF vs. Temperature
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
0 2048 4096 6144 8192 10240 12288 14336 16384OUTPUT CODE
DN
L ER
RO
R (L
SB)
0508
9-03
7
Figure 37. DNL Error vs. Output Code, 80 MSPS, AIN = 15 MHz
0508
9-03
8
–20 0 20 40 60 80TEMPERATURE (°C)
–40–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
GA
IN (%
FS)
Figure 38. Gain vs. Temperature
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
0 2048 4096 6144 8192 10240 12288 14336 16384OUTPUT CODE
INL
ERR
OR
(LSB
)
0508
9-03
9
Figure 39. INL Error vs. Output Code, 80 MSPS, AIN = 15 MHz
AD9444
Rev. 0 | Page 20 of 40
THEORY OF OPERATION The AD9444 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated, high bandwidth, track-and-hold circuit that samples the signal prior to quantiza-tion by the 14-bit pipeline ADC core. The device includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT MODE pin.
ANALOG INPUT AND REFERENCE OVERVIEW A stable and accurate 0.5 V voltage reference is built into the AD9444. The input range can be adjusted by varying the refer-ence voltage applied to the AD9444, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are described in the next few sections.
Internal Reference Connection
A comparator within the AD9444 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resis-tor divider (see Figure 40), setting VREF to ~1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a ~0.5 V reference output. If a resistor divider is connected, as shown in Figure 41, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as
⎟⎠⎞
⎜⎝⎛ +×=
R1R2
VREF 10.5
In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
Internal Reference Trim
The internal reference voltage is trimmed during the produc-tion test to adjust the gain (analog input voltage range) of the AD9444. Therefore, there is little advantage to the user supply-ing an external voltage reference to the AD9444. The gain trim is performed with the AD9444’s input range set to 2 V p-p nominal (SENSE connected to AGND). Because of this trim, and because the 2 V p-p analog input range provides maximum ac performance, there is little benefit to using analog input ranges < 2 V p-p. Users are cautioned that the differential nonlinearity of the ADC varies with the reference voltage. Configurations that use < 2 V p-p may exhibit missing codes and, therefore, degraded noise and distortion performance.
10µF+
0.1µF
VREF
SENSE
0.5V
AD9444
VIN–
VIN+
REFT
0.1µF0.1µF 10µF
0.1µF
REFB
SELECTLOGIC
ADCCORE
+
0508
9-04
3
Figure 40. Internal Reference Configuration
0508
9-04
2
10µF+
0.1µF
VREF
SENSE
R2
R1 0.5V
AD9444
VIN–
VIN+
REFT
0.1µF0.1µF 10µF
0.1µF
REFB
SELECTLOGIC
ADCCORE
+
Figure 41. Programmable Reference Configuration
AD9444
Rev. 0 | Page 21 of 40
Table 9. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A 2 × External Reference Internal Fixed Reference VREF 0.5 1.0 Programmable Reference 0.2 V to VREF
⎟⎠⎞
⎜⎝⎛ +×
R1R2
10.5 (See Figure 41) 2 × VREF
Internal Fixed Reference AGND to 0.2 V 1.0 2.0 External Reference Operation
The AD9444’s internal reference is trimmed to enhance the gain accuracy of the ADC. An external reference may be more stable over temperature, but the gain of the ADC is not likely to be improved. Figure 36 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes.
When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V.
Analog Inputs
As with most new high speed, high dynamic range ADCs, the analog input to the AD9444 is differential. Differential inputs improve on-chip performance as signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. Second, they provide good rejection of common-mode signals, such as local oscillator feedthrough. The specified noise and distortion of the AD9444 cannot be realized with a single-ended analog input, so such configurations are discouraged. Contact ADI for recommenda-tions of other 14-bit ADCs that support single-ended analog input configurations.
With the 1 V reference (nominal value, see the Internal Refer-ence Trim section), the differential input range of the AD9444’s analog input is nominally 2 V p-p or 1 V p-p on each input (VIN+ or VIN−).
3.5V
VIN+
VIN–
1Vp-p
DIGITAL OUT = ALL 1s DIGITAL OUT = ALL 0s
0508
9-04
5
Figure 42. Differential Analog Input Range for VREF = 1 V
The AD9444 analog input voltage range is offset from ground by 3.5 V. Each analog input connects through a 1 kΩ resistor to the 3.5 V bias voltage and to the input of a differential buffer. The internal bias network on the input properly biases the buffer for maximum linearity and range (see the Equivalent Circuits section). Therefore, the analog source driving the AD9444 should be ac-coupled to the input pins. The recom-mended method for driving the analog input of the AD9444 is to use an RF transformer to convert single-ended signals to differential (see Figure 44). Series resistors between the output of the transformer and the AD9444 analog inputs help isolate the analog input source from switching transients caused by the internal sample-and-hold circuit. The series resistors, along with the 1 kΩ resisters connected to the internal 3.5 V bias, must be considered in impedance matching the transformers input. For example, if RT were set to 51 Ω and RS were set to 33 Ω, along with a 1:1 impedance ratio transformer, the input would match a 50 Ω source with a full-scale drive of 10.0 dBm. The 50 Ω impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation board sche-matic (see Figure 47 and Figure 59).
0508
9-04
60.1µF
RT AD9444AIN
AINRS
RSADT1–1WTANALOGINPUT
SIGNAL
Figure 43. Transformer-Coupled Analog Input Circuit
AD9444
Rev. 0 | Page 22 of 40
CLOCK INPUT CONSIDERATIONS Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. For that reason, considerable care was taken in the design of the clock inputs of the AD9444, and the user is advised to give careful thought to the clock source.
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic perform-ance characteristics. The AD9444 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. As shown in Figure 32, noise and distortion performance are nearly flat for a 30% to 70% duty cycle with the DCS enabled. The DCS circuit locks to the rising edge of CLK+ and optimizes timing internally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not re-duced by the internal stabilization circuit. The duty cycle con-trol loop does not function for clock rates less than 30 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can change dynamically, which requires a wait time of 1.5 µs to 5 µs after a dynamic clock frequency increase (or decrease) before the DCS loop is relocked to the input signal. During the time period the loop is not locked, the DCS loop is bypassed, and the internal device timing is dependant on the duty cycle of the input clock signal. In such an application, it may appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance.
The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (AGND) on DCS MODE enables the duty cycle stabi-lizer, and logic high (AVDD1 = 3.3 V) disables the controller.
The AD9444 input sample clock signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on the encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz analog input signals when using a high jitter clock source. (See AN-501, Aperture Uncertainty and ADC System Performance, for complete details.) For optimum performance, the AD9444 must be clocked differentially. The sample clock inputs are internally biased to ~2.2 V, and the input signal is usually ac-coupled into
the CLK+ and CLK− pins via a transformer or capacitors. Figure 44 shows one preferred method for clocking the AD9444. The clock source (low jitter) is converted from single-ended-to-differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD9444 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9444 and limits the noise presented to the sample clock inputs.
If a low jitter clock is available, another option is to ac couple a differential ECL/PECL signal to the encode input pins, as shown in Figure 46.
0508
9-04
7
0.1µFAD9444
CLK+
CLK–HSMS2812
DIODES
CLOCKSOURCE
ADT1–1WT
Figure 44. Crystal Clock Oscillator, Differential Encode
0508
9-04
8
0.1µF
AD9444ENCODE
ENCODE
0.1µF
VT
VT
ECL/PECL
Figure 45. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fINPUT) and rms amplitude due only to aperture jitter (tJ) can be calculated using the following equation.
SNR = 20 log[2πfINPUT × tJ]
In the equation, the rms aperture jitter represents the root-mean square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, see Figure 46.
The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9444. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other meth-ods), it should be retimed by the original clock at the last step.
AD9444
Rev. 0 | Page 23 of 40
INPUT FREQUENCY (MHz)
SNR
(dB
c)
140
75
70
65
60
55
50
45
100010010
0508
9-04
9
0.2ps
0.5ps
1.0ps
1.5ps
2.0ps2.5ps3.0ps
Figure 46. SNR vs. Input Frequency and Jitter
POWER CONSIDERATIONS Care should be taken when selecting a power source. The use of linear dc supplies is highly recommended. Switching supplies tend to have radiated components that may be received by the AD9444. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 µF chip capacitors.
The AD9444 has separate digital and analog power supply pins. The analog supplies are denoted AVDD1 (3.3 V) and AVDD2 (5 V) and the digital supply pins are denoted DRVDD. Although the AVDD1 and DRVDD supplies may be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that both AVDD1 and AVDD2 must be held within 5% of the specified voltage.
The DRVDD supply of the AD9444 is a dedicated supply for the digital outputs, in either LVDS or CMOS output modes. When in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode, the DRVDD supply may be connected from 2.5 V to 3.6 V to be compatible with the receiving logic.
DIGITAL OUTPUTS LVDS Mode
The off-chip drivers on the chip can be configured to provide LVDS-compatible output levels via Pin 5 (OUTPUT MODE). LVDS outputs are available when OUTPUT MODE is CMOS logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET resistor is placed at Pin 7 (LVDSBIAS) to ground. Dynamic performance, including both SFDR and SNR, is maximized when the AD9444 is used in LVDS mode, and designers are encouraged to take advantage of this mode. The AD9444 out-puts include complimentary LVDS outputs for each data bit (DX+/DX−), the overrange output (OR+/OR−), and the output data clock output (DCO+/DCO−). The RSET resistor current is ratioed on-chip, setting the output current at each output equal to a nominal 3.5 mA (11 × ). A 100 Ω differential termina-
tion resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor as close to the receiver as possible. It is recommended to keep the trace length less than 1 inch to 2 inches and to keep differential output trace lengths as equal as possible.
SETRI
CMOS Mode
In applications that can tolerate a slight degradation in dynamic performance, the AD9444 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. CMOS outputs are available when OUTPUT MODE is CMOS logic low (or AGND for convenience). In this mode, the output data bits are single-ended CMOS, DX, as is the overrange output, OR. The output clock is provided as a differential CMOS signal, DCO+/DCO−. Lower supply voltages are recommended to avoid coupling switching transients back to the sensitive analog sections of the ADC. The capacitive load to the CMOS outputs should be minimized, and each output should be connected to a single gate through a series resistor (220 Ω) to minimize switching transients caused by the capacitive loading.
TIMING The AD9444 provides latched data outputs with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and Figure 3 for detailed timing diagrams.
OPERATIONAL MODE SELECTION Data Format Select
The data format select (DFS) pin of the AD9444 determines the coding format of the output data. This pin is 3.3 V CMOS compatible, with logic high (or AVDD1, 3.3 V) selecting twos complement, and DFS logic low (AGND) selecting offset binary format. Table 10 summarizes the output coding.
Output Mode Select
The OUPUT MODE pin controls the logic compatibility, as well as the pinout of the digital outputs. This pin is a CMOS compatible input. With OUTPUT MODE = 0 (AGND), the AD9444 outputs are CMOS-compatible and the pin assignment for the device is defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3 V), the AD9444 outputs are LVDS-compatible and the pin assignment for the device is defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (AGND) on DCS MODE enables the DCS, and logic high (AVDD1, 3.3 V) disables the controller.
AD9444
Rev. 0 | Page 24 of 40
Table 10. Digital Output Coding
Code VIN+ − VIN− Input Span = 2 V p-p (V)
VIN+ − VIN− Input Span = 1 V p-p (V)
Digital Output Offset Binary (D9••••••D0)
Digital Output Twos Complement (D9••••••D0)
16383 1.000 0.500 11 1111 1111 1111 01 1111 1111 1111 8192 0 0 10 0000 0000 0000 00 0000 0000 0000 8191 −0.000122 −0.000061 01 1111 1111 1111 11 1111 1111 1111 0 −1.00 −0.5000 00 0000 0000 0000 10 0000 0000 0000
EVALUATION BOARD Evaluation boards are offered to configure the AD9444 in either CMOS or LVDS mode. Each represents a recommended configuration for using the device over a wide range of sample rates and analog input frequencies. These evaluation boards provide all the support circuitry required to operate the ADC in its various modes and configurations. Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level.
It is critical that signal sources with very low phase noise (< 1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance.
The evaluation boards are shipped with an ac to 6 V dc power supply. The evaluation boards include low dropout regulators to generate the various dc supplies required by the AD9444 and its support circuitry. Separate power supplies are provided to iso-late the DUT from the support circuitry. Each input configura-tion can be selected by proper connection of various jumpers (see Figure 47 to Figure 50 and Figure 59 to Figure 61).
Both the LVDS and CMOS versions of the evaluation board are compatible with the high speed ADC FIFO evaluation kit (part number HSC-ADC-EVALA-SC). The kit includes a high speed data capture board that provides a hardware solution for captur-ing up to 32Ksamples of high speed ADC output data in a FIFO memory chip (user upgradeable to 256K samples). Software is provided to enable the user to download the captured data to a PC via the USB port. This software also includes a behavioral model of the AD9444 and many other high speed ADCs.
Behavioral modeling of the AD9444 is also available at www.analog.com/ADIsimADC. The ADIsimADC™ software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between the AD9444 and other high speed ADCs, with or without hardware evaluation boards.
The AD9444 LVDS evaluation board includes an on-board, LVDS-to-CMOS translator, but the user may choose to remove the translator and terminations to access the LVDS outputs directly.
The CMOS evaluation board includes a buffer for the output data and the DCO output clock of the AD9444.
AD9444
Rev. 0 | Page 25 of 40
LVDS EVALUATION BOARD SCHEMATICS
C400.1µF
100Ω
OPTIONAL
15 20 23
9796
86
12 21 2216
95
24 25
2627
34929394
28293031
4039
19
4142
35
38
9091
87
189
64 63
4344
7273
767778798081 45
46
4950
51525556575859606566686970716
88
8485
48
53616774
82
47
546275
83
3233
100
893637
101
987 141310
99
11 172 3 4 5 81
VCC
GN
DR
91k
Ω
R12
R15
VCC
GN
DR3
3.8kΩ
5432
678
P5
DR
BN
DR
NE2
4EX
TREF
D2_CND2_TN
D3_
CN
D3_
TN
D4_
CN
D4_
TND
5_C
ND
5_TN
D6_
CN
D6_
TN
D7_
CN
D7_
T/D
0_YN
D8_
C/D
1_YN
D8_
T/D
2_YN
D9_
C/D
3_YN
D9_
T/D
4_YN
D10
_C/D
5_YN
D10
_T/D
6_YN
GN
DC
39
10µF
GN
D
DOR_T/DOR_YN
E41
E25
E27
E26
VCC
GN
D
E38
E40
H4MTHOLE6
E39
GND
GN
D
C30.1µF
C90.1µF
C86
0.1µ
F
R1
3.8kΩ
GN
D
ENCBENC
DRVDD
DR
VDD
DR
VDD
DR
VDD
DRVDD
GND
GN
D
GN
D
GN
D
GN
D
GND
DOR_C/D13_YN
D1_TND1_CND13_T/D12_YN
D13_C/D11_YND12_T/D10_YND12_C/D9_YND11_T/D8_YND11_C/D7_YN
D0_TND0_CN
VCC
VCC
VCC
VCC
VCC
VCCVCC
5V
5V
5V
VCC
VCCVCC
VCC
VCC
VCC
VCC
VCC
GN
D
GNDGND
GN
D
GN
D
GN
D
C13
20pF
33ΩR35
R2833Ω
R13
xxC910.1µF
GN
D
E20
EXTR
EF
GND
VDLGND
DRVDDGND
VCC
5V
GND
GN
D
VCC
GN
D
GNDGND
EPADA
D94
44U
1PI
N D
EFIN
ITIO
NS
LVD
S/C
MO
S
R4
36Ω
1
H3MTHOLE6
H1MTHOLE6
H2MTHOLE6
AVD
D1
DN
CD
NC
DN
CO
UTP
UT
MO
DE
DFS
LVD
SBIA
S/D
NC
AVD
D1
AVD
D1
SEN
SEVR
EFA
GN
DR
EFT
REF
BA
GN
DA
VDD
1A
VDD
1A
VDD
1A
VDD
2A
GN
DVI
N+
VIN
–A
GN
DA
VDD
1A
VDD
1
VCC
VCC
VCCVCCVCCVCCVCC
GND
GND
1kΩ
1kΩ
GN
DR
14
1kΩ
E1E2E3
GN
D
VCC
C12
0.1µ
F
C5
0.1µ
F
J4 GN
D
R5
xx
GN
D
T5A
DT1
-1W
T1 5 3
6 2 4N
C TIN
B
GN
D
AN
ALO
G
L1E1
5R
636
Ω
R2
3.8kΩ
C5110µF
C20.1µF
C240.1µF
GN
DGND
0508
9-05
0
AD
T1-1
WT
PRI
SEC
NC
ENC
ENC
B
R39XX
GN
D
GN
DJ5
50ΩR7
C260.1µF
C360.1µF
XTA
LIN
PUT
12
356
T3
13
2
CR2
C42
0.1µ
F
GN
D
50ΩR8
XTALINPUTB
GN
D
4
GN
DJ1
DR
VDD
DR
GN
DD
10+
D10
–D
9+D
9–D
8+D
8–D
RG
ND
D7+
D7–
DC
O+
DC
O–
DR
VDD
DR
GN
DD
6+D
6–D
5+D
5–D
4+D
4–D
RVD
DD
RG
ND
D3+
D3–
D13–D12+D12–D11+D11–
DCS MODAGNDAVDD1AGNDAGNDAVDD1AVDD1
AVDD1AVDD1AVDD1AVDD1AVDD1
AGNDAVDD1AGNDOR+OR–DRVDDDRGNDD13+ (MSB)
AVDD1AVDD1
AVDD2AVDD2AVDD2AVDD2
AGNDC1
AVDD1AVDD1
CLK+CLK–
AVDD1
AVDD2AVDD2
AVDD1AVDD1
(LSB) D0–D0+D1–D1+
DRVDDDRGND
D2–D2+
OU
TVC
C
VEE
~OU
T
OU
TPU
TO
UTP
UTB
VCC
GN
DN
CE/
D
JN00
158
+
FOR
VEC
TRO
N X
TAL
FOR
VF
XTA
L
GN
D
XTA
LIN
PUTB
XTA
LIN
PUT
E52
C92
0.1µ
FC
4410
µFE4
7
R38
XX
R27XX
R37XX
R20XX
R17 XX
R19
XX
R18 XX
456
321
U2
814 7
U6
ECLO
SC
R36XX
R40
XX
C93
0.1µ
F
E46
VXTA
L
GN
D
GN
D
GN
D
XTA
LOU
TB
XTA
LOU
T
XTA
LOU
TXT
ALO
UTB
5V VCC
GN
D
GN
D
GN
DVX
TAL
VXTA
L
VXTA
L
VXTA
L
VXTA
L
1
ENC
OD
E
GN
D
+
GN
DTO
UT
TOU
TB
OPT
ION
AL
ENC
OD
E C
IRC
UIT
SEN
CO
DE
Figure 47. LVDS Mode Evaluation Board Schematic
AD9444
Rev. 0 | Page 26 of 40
IN
OUT OUT1
3.3V
C110µF
C5710µF
3
4 2
1
ADP3338U4
GN
D
GN
D
VDL
VDL
GN
D
VIN
GND
+
+
IN
OUT OUT1
3.3V
C3410µF
C8810µF
3
4 2
1
ADP3338U3
GN
D
GN
D
DR
VDD
DR
VDD
GN
D
VIN
GND
+
+
IN
OUT OUT1
3.3V
C610µF
C8710µF
3
4 2
1
ADP3338U15
GN
D
GN
D
VCC
VCC
GN
D
VIN
GND
+
+
IN
OUT OUT1
5V
C410µF
C8910µF
3
4 2
1
ADP3338U14
GN
D
GN
D
5V5V
GN
D
VIN
GND
+
+
PJ-102A
C3310µF
1
3
2
P4
GN
DG
ND
VIN
+
1
3
2
0508
9-05
1
POWER OPTIONS
Figure 48. LVDS Mode Evaluation Board Schematic (Continued)
0508
9-05
2
+ C6410µF
C750.1µF
VCC
GND
+ C6510µF
C470.1µF
C230.1µF
C220.1µF
C210.1µF
C200.1µF
DRVDD
GND
EXTREF
GND
+
C460.1µF
C610.1µF
C600.1µF
C500.1µF
C480.1µF
C270.1µF
C280.1µF
C300.1µF
C320.1µF
C350.1µF
C430.1µF
C90XX
VCC
GND
C18XX
C19XX
C29XX
C38XX
C37XX
C31XX
C15XX
C16XX
C17XX
C14XX
C11XX
C10XX
C69XX
C70XX
C45XX
C49XX
C59XX
DRVDD
GND
+ C5610µF
C850.1µF
C530.1µF
C520.1µF
C580.1µF
5V
GND
C71XX
C72XX
C73XX
C62XX
5V
GND
C5510µF
P19GND
Figure 49. LVDS Mode Evaluation Board Schematic (Continued)
AD9444
Rev. 0 | Page 27 of 40
P1
P3
P5
P7
P9
P11
P13
P15
P17
P19
P21
P23
P25
P27
P29
P31
P33
P35
P37
P39
P2
P4
P6
P8P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30
P32
P34
P36
P38
P40
P1
P3
P5
P7
P9
P11
P13
P15
P17
P19
P21
P23
P25
P27
P29
P31
P33
P35
P37
P39
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30
P32
P34
P36
P38
P40
P3C40MS
GND
PWR
74VCX86
+
RSO16ISO220
R8
R7
R6
R5
R4
R3
R1
R2
RSO16ISO220
8
7
6
5
4
3
1
2
16
15
14
13
12
11
10
9
RZ4
8
7
6
5
4
3
1
2
16
15
14
13
12
11
10
9
RZ5
7
14
11
8
6
3
U10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P6C40MS
D13O
D11O
D9O
D7O
D6O
D5O
D2O
D1O
D0O
D3O
D4O
D8O
D10O
D12O
ORO
D11_C/D7_YN
D10_C/D5_YN
D9_C/D3_YN
D8_C/D1_YN
D7_CN
DRBN
D6_CN
D5_CN
D0_CN D0_TN
D1_TN
D2_TN
D3_TN
D4_TN
D5_TN
D6_TN
DRN
D7_T/D0_YND8_T/D2_YN
D9_T/D4_YN
D10_T/D6_YND11_T/D8_YN
D12_T/D10_YND13_T/D12_YN
DRO
D0O
D1O
D3O
D4O
D5O
D6O
D2O
DOR_C/D13_YN DOR_T/DOR_YN
D13_C/D11_YND12_C/D9_YN
D1_CN
D2_CN
D3_CN
D4_CN
GND
GND
GND GND
GND
GND
GND GND
GND
GND
D7O
D8O
D9O
D10O
D11O
D12O
D13O
ORO
E34
E43E32
VDL
GND
GND5VCC6VCC5GND4
ENDD4YD3YD2YD1YENCC4YC3YC2YC1Y
GND3VCC4VCC3GND2
B4YB3YB2YB1YENBA4YA3YA2YA1YENA
GND1VCC2VCC1GND
D4BD4AD3BD3AD2BD2AD1BD1AC4BC4AC3BC3AC2BC2AC1BC1AB4BB4AB3BB3AB2BB2AB1BB1AA4BA4AA3BA3AA2BA2AA1BA1A
3334353637383940414243444546474849505152535455565758596061626364
3231302928272625242322212019181716151413121110987654321
U7SN75LVDS386
DOR_C/D13_YN
D13_C/D11_YN
D12_C/D9_YN
D11_C/D7_YN
D10_C/D5_YN
D9_C/D3_YN
D8_C/D1_YN
D3_CN
DOR_T/DOR_YN
D13_T/D12_YN
D12_T/D10_YN
D11_T/D8_YN
D10_T/D6_YN
D9_T/D4_YN
D8_T/D2_YN
D7_T/D0_YND7_CN
DRNDRBN
D6_TND6_CN
D5_CND5_TN
D4_TND4_CND3_TN
D2_TND2_CND1_TND1_CND0_TND0_CN
DRP
VDLVDL
GND
GND
GND
VDL
VDL
GNDVDLVDLGND
VDL
VDL
VDLVDLGND
R8
R7
R6
R5
R4
R3
R1
R2
4Y
3Y
2Y
1Y12459
101213
1A1B2A2B3A3B4A4B
C7610µF
C970.1µF
C820.1µF
C800.1µF
810.1µF
VDL
GND
GND
00
R53XORN
GND
00
R52
GND
VDL
DRO
0508
9-05
3
Figure 50. LVDS Mode Evaluation Board Schematic (Continued)
AD9444
Rev. 0 | Page 28 of 40
0508
9-05
7
Figure 51. LVDS Mode Evaluation Board Layout, Primary Side
0508
9-05
8
Figure 52. LVDS Mode Evaluation Board Layout, Secondary Side
0508
9-05
9
Figure 53. LVDS Mode Evaluation Board Layout, Ground Plane 1
0508
9-06
0
Figure 54. LVDS Mode Evaluation Board Layout, Ground Plane 2
0508
9-06
1
Figure 55. LVDS Mode Evaluation Board Layout, Power Plane 1
0508
9-06
2
Figure 56. LVDS Mode Evaluation Board Layout, Power Plane 2
AD9444
Rev. 0 | Page 29 of 40
0508
9-06
3
Figure 57. LVDS Mode Evaluation Board Layout, Primary Silkscreen
0508
9-06
4
Figure 58. LVDS Mode Evaluation Board Layout, Secondary Silkscreen
AD9444
Rev. 0 | Page 30 of 40
LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) Table 11. Item Qty. REFDES Description Manufacturer MFG_PART_NO
1 1 AD9444PCB PCB, AD9444 LVDS Engineering Evaluation Board PCSM AD9444LVDSCUSTREVC
2 16 C1, C4, C6, C33, C34, C39, C44, C55 to C57, C64, C65, C76, C87 to C89
Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10% KEMET T491C106K016AS
3 38 C2, C3, C5, C9, C12, C20 to C24, C26 to C28, C30, C32, C35, C40, C42, C43, C46 to C48, C50, C52, C53, C58, C60, C61, C75, C80 to C82, C85, C86, C91 to C93, C97
Capacitors, 0.1 µF 10 V Ceramic X5R 0402 Panasonic ECJ-0EB1A104K
4 1 C51 Capacitor, Ceramic 10 µF 6.3 V X5R 0805 KEMET C0805C106K9PACTU
5 1 CR2 Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA Panasonic MA716-(TX) 6 17 E1 to E3, E24,
to E27, E32, E34, E38, E39, E40, E41, E43, E46, E47, E52
40-Pin Breakable Header 3M 2340-611TN
7 2 J1, J4 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201
8 1 L1 10 nH Inductor Coilcraft 0603CJ-10NXGBU 9 1 P3 Header, 40-Pin, Male, 40-Pin Right Angle Samtec TSW-120-08-T-D-RA
10 1 P4 Power Jack Swithcraft RAPC722 11 1 R3 Resistor, 3.6 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2GEJ362X
12 2 R4, R6 Resistor, 36 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ360X 13 1 R8 Resistor, 49.9 Ω 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF49R9X
14 4 R9, R12, R14, R15
Resistor, 1.00 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF1001X
15 2 R28, R35 Resistor, 33 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ330X
16 3 R39, R52, R53
Resistor, 0 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GE0R00X
17 2 RZ4, RZ5 22 Ω Resistor Array, 16 Term CTS Corp. 742163220JTR 18 2 T3, T5 Transformer, ADT1-1WT, CD542, ADT1-1WT Mini-Circuits ADT1-1WT
19 1 U1 14-Bit, 80 MSPS ADC ADI AD9444BSVZ-80 20 3 U3, U4, U15 3.3 V Voltage Regulator ADI ADP3338-3.3 V
21 1 U14 5 V Voltage Regulator ADI ADP3338-5.0 V 22 1 U6 Clock Oscillator, 80 MHz CTS Reeves MX045-80
23 1 U7 LVDS-to-CMOS Translator with 100 Term Texas Instruments SN75LVDT386DGG 24 1 U10 2 Input XOR Gate Fairchild 74VCX86M
25 4 U6 Pin Sockets, Closed End AMP 5-330808-3
AD9444
Rev. 0 | Page 31 of 40
Item Qty. REFDES Description Manufacturer MFG_PART_NO
26 24 C10, C11, C13, to C19, C29, C31, C36 to C38, C45, C49, C59, C62, C69, C70 to C73, C901
Capacitors, Select 10 V Ceramic X5R 0402 Panasonic
27 1 J51 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201
28 2 P5, P61 Power Connectors Weiland 29 1 R1, R2, R5,
R7, R131 Resistors, Select 1/16 W 1% 0402 SMD Panasonic
30 1 R17 to R20, R27, R36 to R38, R401
Resistors, Select 1/16 W 1% 0402 SMD Panasonic
31 5 U21 XO Select Vectron
1 Parts not placed.
AD9444
Rev. 0 | Page 32 of 40
CMOS EVALUATION BOARD SCHEMATICS
C400.1µF
100Ω
OPTIONAL
15 20 23
9796
86
12 21 2216
95
24 25
2627
34929394
28293031
4039
19
4142
35
38
9091
87
189
64 63
4344
7273
767778798081 45
46
4950
51525556575859606566686970716
88
8485
48
53616774
82
47
546275
83
3233
100
893637
101
98
7 141310
9911 172 3 4 5 81
VCC
GN
DR
12
1kΩ
R9
1kΩ
R21
VCC
GN
DR3
3.8kΩ
CO
UTB
CO
UT
E24
EXTR
EF
D7T
/D0Y
D8C
/D1Y
D8T
/D2Y
D9C
/D3Y
D9T
/D4Y
D10
C/D
5YN
D10
T/D
6YN
GN
DC
39
10µF
GN
D
DORT/DORY
E41
E25
E27
E26
VCC
E38
E40
H4MTHOLE6
E39
GND
GN
D
C30.1µF
C90.1µF
R1
3.8kΩ
GN
D
ENCBENC
DRVDD
DR
VDD
DR
VDD
DRVDD
GND
GN
D
GN
D
GN
D
GN
D
GND
DORC/D13Y
D13T/D12YND13C/D11YND12T/D10YND12C/D9YND11T/D8YND11C/D7YN
VCC
VCC
VCC
VCC
VCC
VCCVCC
5V
5V
5V
VCC
VCCVCC
VCC
VCC
VCC
VCC
VCC
GN
D
GNDGND
GN
D
GN
D
GN
D
C13
20pF
33ΩR35
R2833Ω
R13
xx
C910.1µF
GN
D
E20
EXTR
EF
GN
D
VCC
GN
D
GNDGND
EPAD
AD
9444
U1
PIN
DEF
INIT
ION
SLV
DS/
CM
OS
R4
36Ω
H3MTHOLE6
H1MTHOLE6
H2MTHOLE6
VCC
VCC
VCCVCCVCCVCCVCC
GND
GND
1kΩ
GN
DR
15
1kΩ
E1E2E3
GN
D
VCC
C12
0.1µ
F
C5
0.1µ
F
J4 GN
D
R5 xx
GN
D
T5A
DT1
-1W
T1 5 3
6 2 4N
C TIN
B
GN
D
AN
ALO
G
L110
NH
E15
R6
36Ω
R2
3.8kΩ
C5110µF
C780.1µF
C20.1µF
GN
DGND
0508
9-05
4
DR
VDD
CT
EXTE
RN
AL
REF
EREN
CE
INPU
T
AD
T1-1
WT
PRI
SEC
NC
ENC
ENC
B
R39XX
GN
D
GN
DJ5
50ΩR7
C260.1µF
C360.1µF
XTA
LIN
PUT
12
356
T3
13
2
CR2
C42
0.1µ
F
GN
D
50ΩR8
XTA
LIN
PUTB
GN
D
4
GN
DJ1
OU
TVC
C
VEE
~OU
T
OU
TPU
TO
UTP
UTB
VCC
GN
DN
CE/
D
JN00
158
+
FOR
VEC
TRO
N X
TAL
FOR
VF
XTA
L
GN
D
XTA
LIN
PUTB
XTA
LIN
PUT
E52
C92
0.1µ
FC
4410
µFE4
7
R38
XX
R27XX
R37XX
R20XX
R17 XX
R19
XX
R18 XX
456
321
U2
814 7
U6
ECLO
SC
R36XX
R40
XX
C93
0.1µ
F
E46
VXTA
L
GN
D
GN
D
GN
D
XTA
LOU
TB
XTA
LOU
T
XTA
LOU
TXT
ALO
UTB
5V VCC
GN
D
GN
D
GN
DVX
TAL
VXTA
L
VXTA
L
VXTA
L
VXTA
L
1
DR
VDD
DR
GN
D D6
D5
D4
D3
D2
D1
DR
GN
DD
0 (L
SB)
DN
CD
CO
+D
CO
–D
RVD
DD
RG
ND
DN
CD
NC
DN
CD
NC
DN
CD
NC
DR
VDD
DR
GN
DD
NC
DN
C
AVDD1AVDD1
AVDD2AVDD2AVDD2AVDD2
AGNDC1
AVDD1AVDD1
CLK+CLK–
AVDD1
AVDD2AVDD2
AVDD1AVDD1
DNCDNCDNCDNC
DRVDDDRGND
DNCDNC
AVD
D1
DN
CD
NC
DN
CO
UTP
UT
MO
DE
DFS
LVD
SBIA
SA
VDD
1A
VDD
1SE
NSE
VREF
AG
ND
REF
TR
EFB
AG
ND
AVD
D1
AVD
D1
AVD
D1
AVD
D2
AG
ND
VIN
+VI
N–
AG
ND
AVD
D1
AVD
D1
C96
0.1µ
F
5432
678
P5
GND
VDLGND
DRVDDGND
VCC
5V
GND
1
+
GN
DTO
UT
TOU
TB
PRI
SEC
OPT
ION
AL
ENC
OD
E C
IRC
UIT
SEN
CO
DE
GN
D
DCS MODEAGNDAVDD1AGNDAGNDAVDD1AVDD1AVDD1AVDD1AVDD1AVDD1AVDD1AGNDDRVDDAGNDOR(MSB) D13DRVDDDRGNDD12D11D10D9D8D7
Figure 59. CMOS Mode Evaluation Board Schematic
AD9444
Rev. 0 | Page 33 of 40
IN
OUT OUT1
3.3V
C110µF
C5710µF
3
4 2
1
ADP3338U8
GN
D
GN
D
VDL
VDL
GN
D
VIN
GND
+
+
IN
OUT OUT1
3.3V
C3410µF
C8810µF
3
4 2
1
ADP3338U3
GN
D
GN
D
DR
VDD
DR
VDD
GN
D
VIN
GND
+
+
IN
OUT OUT1
3.3V
C610µF
C8710µF
3
4 2
1
ADP3338U15
GN
D
GN
D
VCC
VCC
GN
D
VIN
GND
+
+
IN
OUT OUT1
5V
C410µF
C8910µF
3
4 2
1
ADP3338U14
GN
D
GN
D
5V5V
GN
D
VIN
GND
+
+
PJ-102A
C3310µF
1
3
2
P4
GN
DG
ND
VIN
+
1
3
2
0508
9-05
5
Figure 60. CMOS Mode Evaluation Board Schematic (Continued)
AD9444
Rev. 0 | Page 34 of 40
P1
P3
P5
P7
P9
P11
P13
P15
P17
P19
P21
P23
P25
P27
P29
P31
P33
P35
P37
P39
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30
P32
P34
P36
P38
P40
P3C40MS
GND
PWR
U474VCX86
+
RSO16ISO220
R8
R7
R6
R5
R4
R3
R1
R2
8
7
6
5
4
3
1
2
16
15
14
13
12
11
10
9
RZ4
8
7
6
5
4
3
1
2
16
15
14
13
12
11
10
9
RZ5
7
14
11
8
6
3
U10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
D13M
D11M
D9M
D7M
D6M
D5M
D2M
D1M
D0M
D3M
D4M
D8M
D10M
D12M
ORM
DRM
D0M
D1M
D3M
D4M
D5M
D6M
D2M
GND GND
GND
GND
D7M
D8M
D9M
D10M
D11M
D12M
D13M
ORM
E30
E32E31
VDL
GND
U5SN74LVCH16373A
R8
R7
R6
R5
R4
R3
R1
R2
4Y
3Y
2Y
1Y12459
101213
1A1B2A2B3A3B4A4B
C6610µF
C250.1µF
C410.1µF
C240.1µF
VDL
GND
GND
00
R16XORZIN
GATE2
00
R42
GND
VDL
DRM
0508
9-05
6
RSO16ISO220
R8
R7
R6
R5
R4
R3
R1
R2
RSO16ISO
8
7
6
5
4
3
1
2
16
15
14
13
12
11
10
9
RZ4
8
7
6
5
4
3
1
2
16
15
14
13
12
11
10
9
RZ1
R8
R7
R6
R5
R4
R3
R1
R2
220RZ2
D7T/D0Y
D8C/D1Y
D8T/D2Y
D9C/D3Y
D9T/D4Y
D10C/D5Y
D10T/D6Y
D11C/D7Y
D11T/D8Y
D12C/D9Y
D12T/D10Y
D13C/D11Y
D13T/D12Y
DORC/D13Y
DORT/DORY
XOR2IN
4746
4443
4140
38373635
3332
3029
2726
45
39
34
28
48
25
42
31
23
56
89
11121314
1617
1920
2223
4
10
15
21
7
18
1
24
1D11D2
1D31D4
1D51D6
1D71D8
1Q11Q2
1Q31Q4
1Q51Q6
1Q71Q8
2D12D2
2D32D4
2D52D6
2D72D8
2Q12Q2
2Q32Q4
2Q52Q6
2Q72Q8
GND
LE1
LE2
VCC
OE1
OE2
VCC
VCC
VCC
GND
GND
GND GND
GND
GNDGND
Q = OUTPUTD = INPUT
GND
VDL
GND
GND
GND
XOR2IN
VDL
GND
GND
VDL
GND
GND
VDL
GND
GND
RSO16ISO220RZ5
00
R14DRM
00R41
GATE
C680.1µF
C670.1µF
630.01µF
E45
E49E42
VDL
GND
00
R50
NOT PLACED
COUTB
COUT
Figure 61. CMOS Mode Evaluation Board Schematic (Continued)
AD9444
Rev. 0 | Page 35 of 40
0508
9-06
5
Figure 62. CMOS Mode Evaluation Board Layout, Primary Side 05
089-
066
Figure 63. CMOS Mode Evaluation Board Layout, Secondary Side
0508
9-06
7
Figure 64. CMOS Mode Evaluation Board Layout, Ground Plane 1
0508
9-06
8
Figure 65. CMOS Mode Evaluation Board Layout, Ground Plane 2
0508
9-06
9
Figure 66. CMOS Mode Evaluation Board Layout, Power Plane 1
0508
9-07
0
Figure 67. CMOS Mode Evaluation Board Layout, Power Plane 2
AD9444
Rev. 0 | Page 36 of 40
0508
9-07
1
Figure 68. CMOS Mode Evaluation Board Layout, Primary Silkscreen
0508
9-07
2
Figure 69. CMOS Mode Evaluation Board Layout, Secondary Silkscreen
AD9444
Rev. 0 | Page 37 of 40
CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. Item Qty. REFDES Description Manufacturer MFG_PART_NO
1 1 AD9444PCB PCB, AD9444 LVDS Evaluation Board PCSM AD9444LVDSCUSTREVC
2 16 C1, C4, C6, C33, C34, C39, C44, C55 to C57, C64 to C66, C87 to C89
Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10% KEMET T491C106K016AS
3 32 C2, C3, C5, C9, C12, C20 to C23, C26 to C28, C30, C32, C35, C40, C42, C43, C46 to C48, C50, C52, C53, C58, C60, C61, C75, C78, C85, C91, C92
Capacitors, 0.1 µF 10 V Ceramic X5R 0402 Panasonic ECJ-0EB1A104K
4 5 C24, C25, C41, C67, C68
Capacitors, 0.1 µF 16 V Ceramic X7R 0603 Panasonic ECJ-1VB1C104K
5 1 C51 Capacitor, Ceramic 10 µF 6.3 V X5R 0805 KEMET C0805C106K9PACTU 6 1 CR2 Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA Panasonic MA716-(TX)
7 20 E1 to E3, E24 to E27, E30 to E32, E38 to E42, E45 to E47, E49, E52
40-Pin Breakable Header 3M 2340-611TN
8 2 J1, J4 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201 9 1 L1 10 nH O402 Inductor Coilcraft 0402CS-10NX_B_
10 1 P3 Header, 40-Pin, Male, 40-Pin Right Angle Samtec TSW-120-08-T-D-RA 11 1 P4 Power Jack Swithcraft RAPC722
12 1 R3 Resistor, 3.6 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2GEJ362X 13 2 R4, R6 Resistors, 36 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ360X
14 1 R8 Resistor, 49.9 Ω 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF49R9X 15 4 R9, R12, R15, R21 Resistors, 1.00 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF1001X
16 2 R14, R50 Resistors, 0 Ω 1/10 W 5% 0603 SMD Panasonic ERJ-3GEY0R00V 17 2 R28, R35 Resistors, 33 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ330X
18 1 R39 Resistor, 0 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GE0R00X 19 4 RZ1 to RZ3, RZ6 220 Ω Resistor Array, 16 Term CTS Corp. 742163221JTR
20 2 T3, T5 Transformer, ADT1-1WT, CD542, ADT1-1WT Mini-Circuits ADT1-1WT 21 1 U1 14-Bit, 80 MSPS ADC ADI AD9444BSVZ-80
22 4 U3, U8, U15 3.3 V Voltage Regulator ADI ADP3338-3.3 V 23 1 U14 5 V Voltage Regulator ADI ADP3338-5.0 V
24 1 U5 16-Bit Flip Flop Fairchild 74LVTH162374 25 4 U6 Pin Sockets, Closed End AMP 5-330808-3
AD9444
Rev. 0 | Page 38 of 40
Item Qty. REFDES Description Manufacturer MFG_PART_NO
26 26 C10, C11, C13, C14 to C19, C29, C31, C36 to C37, C38, C45, C49, C59, C62,C69, C70 to C73, C90, C93, C961
Capacitors, Select 10 V Ceramic X5R 0402 Panasonic
27 1 J51 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201 28 15 R1,R2,R5,R7, R13,
R17 to R20, R27, R36 to R401
Resistors, Select 1/16 W 1% 0402 SMD Panasonic
29 3 R16, R41, R421 Resistors, Select 1/16 W 5% 0603 SMD Panasonic
30 1 C631 Capacitor, Select 10 V Ceramic X5R 0603 Panasonic 31 1 U41 XOR 74VCX86D Fairchild 74VCX86D
32 2 P5, P61 Power Connectors Weiland
1 Parts not placed.
AD9444
Rev. 0 | Page 39 of 40
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026AED-HDNOTES1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.3. THE EXPOSED HEAT SINK SOLDERED TO THE GROUND PLANE IS REQUIRED FOR THE 100-LEAD TQFP/EP.
1
2526 50
7610075
51
14.00 SQ16.00 SQ
0.270.220.17
0.50 BSC
1.051.000.95
0.150.05
0.750.600.45
SEATINGPLANE
1.20MAX
1
252650
76 10075
51
6.50NOM7°
3.5°0°
COPLANARITY0.08
0.200.09
TOP VIEW(PINS DOWN)
BOTTOM VIEW(PINS UP)
CONDUCTIVEHEAT SINK
Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-1)
Dimensions shown in millimeters
ORDERING GUIDE Model Temperature Range Package Description Package Outline AD9444BSVZ-801 –40°C to +85°C 100-Lead TQFP_EP SV-100-1 AD9444-CMOS/PCB CMOS Mode Evaluation Board AD9444-LVDS/PCB LVDS Mode Evaluation Board
1 Z = Pb-free part.
AD9444
Rev. 0 | Page 40 of 40
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05089–0–10/04(0)