ad8099
TRANSCRIPT
Ultralow Distortion, High Speed 0.95 nV/Hz Voltage Noise Op Amp
Data Sheet AD8099
Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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FEATURES Ultralow noise: 0.95 nV/√Hz, 2.6 pA/√Hz
Ultralow distortion 2nd harmonic RL = 1 kΩ , G = +2
−92 dB @ 10 MHz 3rd harmonic RL = 1 kΩ , G = +2
−105 dB @ 10 MHz High speed GBWP: 3.8 GHz
–3 dB bandwidth: 700 MHz (G = +2) 550 MHz (G = +10)
Slew rate: 475 V/μs (G = +2) 1350 V/μs (G = +10)
New pinout Custom external compensation, gain range –1, +2 to +10 Supply current: 15 mA Offset voltage: 0.5 mV max Wide supply voltage range: 5 V to 12 V
APPLICATIONS Pre-amplifiers Receivers Instrumentation Filters IF and baseband amplifiers A-to-D drivers DAC buffers Optical electronics
CONNECTION DIAGRAMS
0451
1-0-
001
DISABLE 1
FEEDBACK 2
–IN 3
+IN 4
+VS8
VOUT7
CC6
–VS5
NOTES1. SOLDER THE EXPOSED PADDLE TO
THE GROUND PLANE. 0451
1-0-
002
1FEEDBACK
2–IN
3+IN
–VS 4
DISABLE8
+VS7
VOUT6
CC5
NOTES1. SOLDER THE EXPOSED PADDLE TO
THE GROUND PLANE.
Figure 1. 8-Lead LFCSP (CP-8-2) Figure 2. 8-Lead SOIC-EP (RD-8-1)
GENERAL DESCRIPTION The AD8099 is an ultralow noise (0.95 nV/√Hz) and distortion (–92 dBc @10 MHz) voltage feedback op amp, the combination of which make it ideal for 16- and 18-bit systems. The AD8099 features a new, highly linear, low noise input stage that increases the full power bandwidth (FPBW) at low gains with high slew rates. ADI’s proprietary next generation XFCB process enables such high performance amplifiers with relatively low power.
The AD8099 features external compensation, which lets the user set the gain bandwidth product. External compensation allows gains from +2 to +10 with minimal trade-off in band-width. The AD8099 also features an extremely high slew rate of 1350 V/μs, giving the designer flexibility to use the entire dynamic range without trading off bandwidth or distortion. The AD8099 settles to 0.1% in 18 ns and recovers from overdrive in 50 ns.
The AD8099 drives 100 Ω loads at breakthrough performance levels with only 15 mA of supply current. With the wide supply voltage range (5 V to 12 V), low offset voltage (0.1 mV typ), wide bandwidth (700 MHz for G = +2), and a GBWP up to 3.8 GHz, the AD8099 is designed to work in a wide variety of applications.
The AD8099 is available in a 3 mm × 3 mm lead frame chip scale package (LFCSP) with a new pinout that is specifically optimized for high performance, high speed amplifiers. The new LFCSP package and pinout enable the breakthrough performance that previously was not achievable with amplifiers. The AD8099 is rated to work over the extended industrial temperature range, −40°C to +125°C.
0451
1-A-
013
FREQUENCY (MHz)0.1 1.0 10.0
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–130
–40
–110
–100
–90
–80
–70
–60
–50
–120SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = +2VOUT = 2V p-pVS = ±5VRL = 1k
Figure 3. Harmonic Distortion vs. Frequency and Gain (SOIC)
IMPORTANT LINKS for the AD8099*Last content update 08/25/2013 09:10 pm
PARAMETRIC SELECTION TABLESFind Similar Products By Operating Parameters
High Speed Amplifiers Selection Table
DOCUMENTATIONAN-0993: Active Filter Evaluation Board for Analog Devices, Inc., - LowDistortion Pinout Op Amps
AN-649: Using the Analog Devices Active Filter Design Tool
AN-581: Biasing and Decoupling Op Amps in Single SupplyApplications
AN-402: Replacing Output Clamping Op Amps with Input ClampingAmps
AN-417: Fast Rail-to-Rail Operational Amplifiers Ease DesignConstraints in Low Voltage High Speed Systems
MT-101: Decoupling Techniques
MT-059: Compensating for the Effects of Input Capacitance on VFBand CFB Op Amps Used in Current-to-Voltage Converters
MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps
MT-056: High Speed Voltage Feedback Op Amps
MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR
MT-052: Op Amp Noise Figure: Don’t Be Mislead
MT-050: Op Amp Total Output Noise Calculations for Second-OrderSystem
MT-049: Op Amp Total Output Noise Calculations for Single-PoleSystem
MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, andEquivalent Noise Bandwidth
MT-047: Op Amp Noise
MT-033: Voltage Feedback Op Amp Gain and Bandwidth
MT-032: Ideal Voltage Feedback (VFB) Op Amp
A Stress-Free Method for Choosing High-Speed Op Amps
UG-064: AD8099 Evaluation Board User Guide
Low-Cost Video Multiplexing Using High-Speed Amplifiers
A Practical Guide to High-Speed Printed-Circuit-Board Layout
Op-amp Architecture Claims Better Balance of Trade-offs
EVALUATION KITS & SYMBOLS & FOOTPRINTSView the Evaluation Boards and Kits page for documentation andpurchasing
Symbols and Footprints
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
dBm/dBu/dBv Calculator
Analog Filter Wizard 2.0
Power Dissipation vs Die Temp
ADIsimOpAmp™
OpAmp Stability
AD8099 SPICE Macro-Model
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Quality and ReliabilityLead(Pb)-Free Data
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AD8099
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AD8099 Data Sheet
Rev. D | Page 2 of 28
TABLE OF CONTENTS Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
General Description ......................................................................... 1
Specifications ..................................................................................... 3
Specifications with ±5 V Supply ................................................. 3
Specifications with +5 V Supply ................................................. 4
Absolute Maximum Ratings ............................................................ 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 15
Applications ..................................................................................... 16
Using the AD8099 ...................................................................... 16
Circuit Components .................................................................. 16
Recommended Values ............................................................... 17
Circuit Configurations .............................................................. 17
Performance vs. Component values ........................................ 19
Total Output Noise Calculations and Design ......................... 20
Input Bias Current and DC Offset ........................................... 21
DISABLE Pin and Input Bias Cancellation ............................. 21
16-Bit ADC Driver ..................................................................... 22
Circuit Considerations .............................................................. 23
Design Tools and Technical Support ....................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide ............................................................................... 25
REVISION HISTORY
8/13—Rev. C to Rev. D
Changes to Figure 42 Caption ....................................................... 12 Changes to Figure 49 ...................................................................... 13 Changes to Ordering Guide .......................................................... 25
1/13—Rev. B to Rev. C
Added EPAD Note to Figure 1 and Figure 2 ................................. 1 Changes to PCB Layout Section and Design Tools and Technical Support Section ............................................................. 23 Deleted Figure 72, Figure 73, Evaluation Boards Section, and Table 7 .............................................................................................. 24 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26
6/04—Data Sheet changed from Rev. A to Rev. B
Change to General Description ...................................................... 1 Changes to Maximum Power Dissipation section ....................... 5 Changes to Applications section .................................................. 16 Changes to Table 7 .......................................................................... 24 Changes to Ordering Guide .......................................................... 26
1/04—Data Sheet changed from Rev. 0 to Rev. A
Inserted new Figure 3 ................................................................... 1 Changes to Specifications ............................................................. 3 Inserted new Figures 22 to 34 ...................................................... 8 Inserted new Figures 51 to 55 ................................................... 14 Changes to Theory of Operation section ................................ 16 Changes to Circuit Components section ................................ 17 Changes to Table 4 ...................................................................... 18 Changes to Figure 60 .................................................................. 18 Changes to Total Output Noise Calculations and Design section ........................................................................ 21 Changes to Figure 60 .................................................................. 22 Changes to Figure 62 .................................................................. 23 Changes to 16-Bit ADC Driver section ................................... 23 Changes to Table 6 ...................................................................... 23 Additions to PCB Layout section ............................................. 23
11/03—Revision 0: Initial Version
Data Sheet AD8099
Rev. D | Page 3 of 28
SPECIFICATIONS SPECIFICATIONS WITH ±5 V SUPPLY TA = 25°C, G = +2, RL = 1 kΩ to ground, unless otherwise noted. Refer to Figure 60 through Figure 66 for component values and gain configurations. Table 1. Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE –3 dB Bandwidth G = +5, VOUT = 0.2 V p-p 450 510 MHz
G = +5, VOUT = 2 V p-p 205 235 MHz Bandwidth for 0.1 dB Flatness (SOIC/LFCSP) G = +2, VOUT = 0.2 V p-p 34/25 MHz Slew Rate G = +10, VOUT = 6 V Step 1120 1350 V/µs G = +2, VOUT = 2 V Step 435 470 V/µs Settling Time to 0.1% G = +2, VOUT = 2 V Step 18 ns
NOISE/DISTORTION PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 fC = 500 kHz, VOUT = 2 V p-p, G = +10 –102/–111 dBc
fC = 10 MHz, VOUT = 2 V p-p, G = +10 –84/–92 dBc Input Voltage Noise f = 100 kHz 0.95 nV/√Hz
Input Current Noise f = 100 kHz, DISABLE pin floating 2.6 pA/√Hz
f = 100 kHz, DISABLE pin = +VS 5.2 pA/√Hz
DC PERFORMANCE Input Offset Voltage 0.1 0.5 mV Input Offset Voltage Drift 2.3 µV/°C Input Bias Current DISABLE pin floating –6 –13 µA
DISABLE pin = +VS –0.1 –2 µA
Input Bias Current Drift 3 nA/°C Input Bias Offset Current 0.06 1 µA Open-Loop Gain 82 85 dB
INPUT CHARACTERISTICS Input Resistance Differential mode 4 kΩ Common mode 10 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range –3.7 to +3.7 V Common-Mode Rejection Ratio VCM = ±2.5 V 98 105 dB
DISABLE PIN
DISABLE Input Voltage Output disabled <2.4 V
Turn-Off Time 50% of DISABLE to < 10% of final VOUT, VIN = 0.5 V, G = +2
105 ns
Turn-On Time 50% of DISABLE to < 10% of final VOUT, VIN = 0.5 V, G = +2
39 ns
Enable Pin Leakage Current DISABLE =+5 V 17 21 µA
DISABLE Pin Leakage Current DISABLE = –5 V 35 44 µA
OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rise/Fall) VIN = -2.5 V to 2.5 V, G =+2 30/50 ns Output Voltage Swing RL = 100 Ω –3.4 to +3.5 –3.6 to +3.7 V RL = 1 kΩ –3.7 to +3.7 –3.8 to +3.8 V Short-Circuit Current Sinking and sourcing 131/178 mA Off Isolation f = 1 MHz, DISABLE = low –61 dB
POWER SUPPLY Operating Range ±5 ±6 V Quiescent Current 15 16 mA Quiescent Current (Disabled) DISABLE = Low 1.7 2 mA
Positive Power Supply Rejection Ratio +VS = 4 V to 6 V, –VS = –5 V (input referred) 85 91 dB Negative Power Supply Rejection Ratio +VS = 5 V, –VS = –6 V to –4 V (input referred) 86 94 dB
AD8099 Data Sheet
Rev. D | Page 4 of 28
SPECIFICATIONS WITH +5 V SUPPLY VS = 5 V @ TA = 25°C, G = +2, RL = 1 kΩ to midsupply, unless otherwise noted. Refer to Figure 60 through Figure 66 for component values and gain configurations . Table 2. Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE –3 dB Bandwidth G = +5, VOUT = 0.2 V p-p 415 440 MHz
G = +5, VOUT = 2 V p-p 165 210 MHz Bandwidth for 0.1 dB Flatness (SOIC/LFCSP) G = +2, VOUT = 0.2 V p-p 33/23 MHz Slew Rate G = +10, VOUT = 2 V Step 630 715 V/µs G = +2, VOUT = 2 V Step 340 365 V/µs Settling Time to 0.1% G = +2, VOUT = 2 V Step 18 ns
NOISE/DISTORTION PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 fC = 500 kHz, VOUT = 1 V p-p, G = +10 –82/–94 dBc
fC = 10 MHz, VOUT = 1 V p-p, G = +10 –80/–75 dBc Input Voltage Noise f = 100 kHz 0.95 nV/√Hz
Input Current Noise f = 100 kHz, DISABLE pin floating 2.6 pA/√Hz
f = 100 kHz, DISABLE pin = +VS 5.2 pA/√Hz
DC PERFORMANCE Input Offset Voltage 0.1 0.5 mV Input Offset Voltage Drift 2.5 µV/°C Input Bias Current DISABLE pin floating –6.2 –13 µA
DISABLE pin = +VS –0.2 –2 µA
Input Bias Offset Current 0.05 1 µA Input Bias Offset Current Drift 2.4 nA/°C Open-Loop Gain VOUT = 1 V to 4 V 76 81 dB
INPUT CHARACTERISTICS Input Resistance Differential mode 4 kΩ Common mode 10 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range 1.3 to 3.7 V Common-Mode Rejection Ratio VCM = 2 V to 3 V 88 105 dB
DISABLE PIN
DISABLE Input Voltage Output disabled <2.4 V
Turn-Off Time 50% of DISABLE to <10% of Final VOUT, VIN = 0.5 V, G = +2
105 ns
Turn-On Time 50% of DISABLE to <10% of Final VOUT, VIN = 0.5 V, G = +2
61 ns
Enable Pin Leakage Current DISABLE = 5 V 16 21 µA
DISABLE Pin Leakage Current DISABLE = 0 V 33 44 µA
OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rise/Fall) VIN = 0 to 2.5 V, G = +2 50/70 ns Output Voltage Swing RL = 100 Ω 1.5 to 3.5 1.2 to 3.8 V RL = 1 kΩ 1.2 to 3.8 1.2 to 3.8 V Short-Circuit Current Sinking and Sourcing 60/80 mA Off Isolation f = 1 MHz, DISABLE = Low –61 dB
POWER SUPPLY Operating Range ±5 ±6 V Quiescent Current 14.5 15.4 mA Quiescent Current (Disabled) DISABLE = Low 1.4 1.7 mA
Positive Power Supply Rejection Ratio +VS = 4.5 V to 5.5 V, –VS = 0 V (input referred) 84 89 dB Negative Power Supply Rejection Ratio +VS =5 V, -VS= –0.5 V to +0.5 V (input referred) 84 90 dB
Data Sheet AD8099
Rev. D | Page 5 of 28
ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage 12.6 V Power Dissipation See Figure 4 Differential Input Voltage ±1.8 V Differential Input Current ±10mA Storage Temperature –65°C to +125°C Operating Temperature Range –40°C to +125°C Lead Temperature Range (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8099 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die will locally reach the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8099. Exceeding a junction temperature of 150°C for an extended period can result in changes in silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (θJA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as
( )JADAJ θPTT ×+=
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power – Load Power)
( )L
2OUT
L
OUTSSSD R
V–
RV
2V
IVP
×+×=
RMS output voltages should be considered. If RL is referenced to VS–, as in single-supply operation, then the total drive power is VS × IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply:
( ) ( )L
SSSD R
/VIVP
24+×=
In single-supply operation with RL referenced to VS–, worst case is VOUT = VS/2.
Airflow will increase heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the θJA. Soldering the exposed paddle to the ground plane significantly reduces the overall thermal resistance of the package. Care must be taken to minimize parasitic capaci-tances at the input leads of high speed op amps, as discussed in the PCB Layout section.
Figure 4 shows the maximum safe power dissipation in the package versus the ambient temperature for the exposed paddle (e-pad) SOIC-8 (70°C/W), and LFCSP (70°C/W), packages on a JEDEC standard 4-layer board. θJA values are approximations.
0451
1-0-
115
AMBIENT TEMPERATURE (°C)120–40 –20 0 20 40 60 80 100
MA
XIM
UM
PO
WER
DIS
SIPA
TIO
N (W
atts
)
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
LFCSP AND SOIC
Figure 4. Maximum Power Dissipation
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD8099 Data Sheet
Rev. D | Page 6 of 28
TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: VS = ±5 V, TA = 25°C, RL = 1 kΩ tied to ground unless otherwise noted. Refer to Figure 63 through Figure 66 for component values and gain configurations.
FREQUENCY (MHz)
NO
RM
ALI
ZED
CLO
SED
-LO
OP
GA
IN (d
B)
1–10–9–8–7–6–5–4–3–2–1
01234
10 100 1000
0451
1-0-
074
G = +20
G = +5
G = +2
G = +10
G = –1
VOUT = 0.2V p-pVS = ±5VRLOAD = 1k
Figure 5. Small Signal Frequency Response for Various Gains (SOIC)
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
17
10
9
8
14
13
12
11
16
15
17
10 100 1000
0451
1-0-
076
G = +5VS = ±5VVOUT = 0.2V p-p
RL = 100, SOIC
RL = 1k, SOIC
RL = 100, CSPRL = 1k, CSP
Figure 6. Small Signal Frequency Response for Various Load Resistors
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
6
5
4
3
2
1
10
9
8
7
11
10001 10 100
G = +2VS = ±5VRL = 1k
+125°C
+85°C
–40°C
+25°C
0451
1-0-
098
VOUT = 0.2V p-p
Figure 7. Small Signal Frequency Response for Various Temperatures (SOIC)
FREQUENCY (MHz)
NO
RM
ALI
ZED
CLO
SED
-LO
OP
GA
IN (d
B)
1–10–9–8–7–6–5–4–3–2–1
01234
10 100 1000
0451
1-0-
073
G = +20
G = –1
G = +2
G = +5
G = +10
VOUT = 0.2V p-pVS = ±5VRLOAD = 1k
Figure 8. Small Signal Frequency Response for Various Gains (LFCSP)
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
17
10
9
8
14
13
12
11
16
15
17
10 100 1000
0451
1-0-
077
G = +5RL = 1kVOUT = 0.2V p-p
VS = ±2.5V, CSP
VS = ±2.5V, SOIC
VS = ±5V, SOIC
VS = ±5V, CSP
Figure 9. Small Signal Frequency Response for Various Supply Voltages
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
6
5
4
3
2
1
10
9
8
7
11
10001 10 100
G = +2VS = ±5VRL = 1k
+125°C
+25°C
–40°C
+85°C
0451
1-0-
097
VOUT = 0.2V p-p
Figure 10. Small Signal Frequency Response for Various Temperatures (LFCSP)
Data Sheet AD8099
Rev. D | Page 7 of 28
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
19
10
18
19
16
14
12
17
15
13
11
20
10 100 1000
5pF, CSP
5pF, SOIC
1pF, CSP
1pF, SOIC
0451
1-0-
104
G = +5VS = ±5V
Figure 11. Small Signal Frequency Response for Various Capacitive Loads
FREQUENCY (MHz)
NO
RM
ALI
ZED
CLO
SED
-LO
OP
GA
IN (d
B)
1 10 100 1000
0451
1-0-
011
1
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0G = +2
G = +5
G = +10
G = +20
VS = ±5VVOUT = 2V p-pRLOAD = 1k
Figure 12. Large Signal Frequency Response for Various Gains (SOIC)
0451
1-0-
009
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
15.5
10 100
6.5
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
VOUT = 200mV p-p
VOUT = 1.4V p-pVS = ±5VG = +2RL = 150
Figure 13. 0.1 dB Flatness (SOIC)
0451
1-0-
080
FREQUENCY (MHz)
OPE
N-L
OO
P G
AIN
(dB
)
OPE
N-L
OO
P PH
ASE
(Deg
rees
)
0.001 0.01 0.1 1.0 10 100 1000–10
40
0
10
50
60
20
30
70
80
90
–180
–105
–165
–150
–90
–75
–135
–120
–60
–45
–30
VS = ±5VRL = 1kUNCOMPENSATED
PHASE
MAGNITUDE
Figure 14. Open Loop Frequency Response
FREQUENCY (MHz)
NO
RM
ALI
ZED
CLO
SED
-LO
OP
GA
IN (d
B)
1 10 100 1000
0451
1-0-
012
2
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
VS = ±5VVOUT = 2V p-pRLOAD = 1k
G = +5
G = +10
G = +20
G = +2
Figure 15. Large Signal Frequency Response for Various Gains (LFCSP)
0451
1-0-
008
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
15.5
10 100
6.5
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
VOUT = 200mV p-p
VOUT = 1.4V p-pVS = ±5VG = +2RL = 150
Figure 16. 0.1 dB Flatness (LFCSP)
AD8099 Data Sheet
Rev. D | Page 8 of 28
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
15
8
7
6
12
11
10
9
14
13
15
10 100 1000
0451
1-0-
078
G = +5VS = ±5VVOUT = 2V p-p
RL = 100, SOIC
RL = 1k, SOIC
RL = 100, CSP
RL = 1k, CSP
Figure 17. Large Signal Frequency Response for Various Load Resistances
FREQUENCY (MHz)
INPU
T IM
PED
AN
CE
(k
)
10.001
0.1
1.0
10.0
0.01
100.0
10 100 1000
0451
1-0-
105
VS = ±5VG = +2
Figure 18. Input Impedance vs. Frequency
FREQUENCY (MHz)
OU
TPU
T IM
PED
AN
CE
()
0.1
0.01
1
10
100
1000.1 1 10 1000
G = +2
G = +5
G = +10
VS = ±5V
0451
1-0-
100
Figure 19. Output Impedance vs. Frequency for Various Gains
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
15
8
7
6
12
11
10
9
14
13
15
10 100 1000
0451
1-0-
079
G = +5RL = 1kVOUT = 2V p-p
VS = ±2.5V, CSP
VS = ±2.5V, SOIC
VS = ±5V, CSP
VS = ±5V, SOIC
Figure 20. Large Signal Frequency Response for Various Supply Voltages
FREQUENCY (MHz)
OFF
ISO
LATI
ON
(dB
)
0.1–90
–80
–40
–60
–20
–50
–70
–30
–10
1 10 100 1000
0451
1-0-
094
SOICCSP
G = +2RL = 1kVS = ±5VVDIS = 0V
Figure 21. Off Isolation vs. Frequency
0451
1-A-
008
FREQUENCY (MHz)0.1 1.0 10.0
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–120
–50
–100
–90
–80
–70
–60
–110SOLID LINES – SECOND HARMONICSDOTTED LINE – THIRD HARMONICSSOLID LINES – SECOND HARMONICSDOTTED LINES – THIRD HARMONICS
G = +5VOUT = 2V p-pVS = ±5VRL = 100
SOIC
CSP
Figure 22. Harmonic Distortion vs. Frequency
Data Sheet AD8099
Rev. D | Page 9 of 28
0451
1-A-
009
FREQUENCY (MHz)0.1 1.0 10.0
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–130
–50
–110
–100
–90
–80
–70
–60
–120SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = +5VOUT = 2V p-pVS = ±5VRL = 1k
Figure 23. Harmonic Distortion vs. Frequency (SOIC)
04
511-
A-01
0
FREQUENCY (MHz)0.1 1.0 10.0
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–130
–40
–110
–100
–90
–80
–70
–60
–50
–120SOLID LINES – SECOND HARMONICSDOTTED LINE – THIRD HARMONICS
SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = +2VOUT = 2V p-pVS = ±5VRL = 1k
Figure 24. Harmonic Distortion vs. Frequency (SOIC)
0451
1-A-
011
FREQUENCY (MHz)0.1 1.0 10.0
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–130
–40
–110
–100
–90
–80
–70
–60
–50
–120SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = –1VOUT = 2V p-pVS = ±5VRL = 1k
Figure 25. Harmonic Distortion vs. Frequency (SOIC)
0451
1-A-
012
FREQUENCY (MHz)0.1 1.0 10.0
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–130
–50
–110
–100
–90
–80
–70
–60
–120SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = +5VOUT = 2V p-pVS = ±5VRL = 1k
Figure 26. Harmonic Distortion vs. Frequency (LFCSP)
0451
1-A-
013
FREQUENCY (MHz)0.1 1.0 10.0
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–130
–40
–110
–100
–90
–80
–70
–60
–50
–120SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = +2VOUT = 2V p-pVS = ±5VRL = 1k
Figure 27. Harmonic Distortion vs. Frequency (LFCSP)
0451
1-A-
014
FREQUENCY (MHz)0.1 1.0 10.0
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–130
–40
–110
–100
–90
–80
–70
–60
–50
–120SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = –1VOUT = 2V p-pVS = ±5VRL = 1k
Figure 28. Harmonic Distortion vs. Frequency (LFCSP)
AD8099 Data Sheet
Rev. D | Page 10 of 28
0451
1-A-
015
FREQUENCY (MHz)0.1 1.0 10.0
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–120
–50
–100
–90
–80
–70
–60
–110SOLID LINES – SECOND HARMONICSDOTTED LINES – THIRD HARMONICS
G = +10RL = 1k
VS = ±2.5VVOUT = 1V p-p
VS = ±5VVOUT = 2V p-p
Figure 29. Harmonic Distortion vs. Frequency and Supply Voltage (SOIC)
04
511-
A-01
6
OUTPUT AMPLITUDE (V p-p)71 2 3 4 5 6
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–110
–40
–90
–80
–70
–60
–50
–100SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = +5VS = ±5Vf = 10MHzRL = 100
Figure 30. Harmonic Distortion vs. Output Amplitude (SOIC)
0451
1-A-
017
OUTPUT AMPLITUDE (V p-p)71 2 3 4 5 6
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–120
–110
–40
–90
–80
–70
–60
–50
–100
SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = +5VS = ±5Vf = 10MHzRL = 1k
Figure 31. Harmonic Distortion vs. Output Amplitude (SOIC)
0451
1-A-
018
FREQUENCY (MHz)0.1 1.0 10.0
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–120
–110
–50
–90
–80
–70
–60
–100
SOLID LINES – SECOND HARMONICSDOTTED LINE – THIRD HARMONICSSOLID LINES – SECOND HARMONICSDOTTED LINES – THIRD HARMONICS
G = +10RL = 1k
VS = ±2.5VVOUT = 1V p-p
VS = ±5VVOUT = 2V p-p
Figure 32. Harmonic Distortion vs. Frequency for Various Supplies (LFCSP)
0451
1-A-
019
OUTPUT AMPLITUDE (V p-p)71 2 3 4 5 6
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–110
–40
–90
–80
–70
–60
–50
–100SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = +5VS = ±5Vf = 10MHzRL = 100
Figure 33. Harmonic Distortion vs. Output Amplitude (LFCSP)
0451
1-A-
021
OUTPUT AMPLITUDE (V p-p)71 2 3 4 5 6
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
–120
–110
–40
–90
–80
–70
–60
–50
–100
SOLID LINE – SECOND HARMONICDOTTED LINE – THIRD HARMONIC
G = +5VS = ±5Vf = 10MHzRL = 1k
Figure 34. Harmonic Distortion vs. Output Amplitude (LFCSP)
Data Sheet AD8099
Rev. D | Page 11 of 28
TIME (ns)
OU
TPU
T VO
LTA
GE
(V)
0 5 10–0.20
–0.05
–0.10
–0.15
0.15
0.10
0.05
0
0.20
15 20 25 30 35 40 45 50
1pF
10pF, 20 RSNUB
0451
1-0-
095
RSNUB
CL RLG = +5VS = ±5VRL = 1k
Figure 35. Small Signal Transient Response for Various Capacitive Loads (SOIC)
TIME (ns)
OU
TPU
T VO
LTA
GE
(V)
0 10–0.15
–0.05
–0.10
0.10
0.05
0
0.15
20 30 40 50
G = +10RL = 1k
VS = ±5.0VAND ±2.5V, SOIC
VS = ±5.0VAND ±2.5V, CSP
0451
1-0-
107
Figure 36. Small Signal Transient Response for Various Supply Voltages
0451
1-A-
017
TIME (ns)10000 100 200 300 400 500 600 700 800 900
OU
TPU
T VO
LTA
GE
(V)
–5
5
4
3
2
1
0
–1
–2
–3
–4
RL = 1k
RL = 100
INPUT × 2
Figure 37. Output Overdrive Recovery for Various Resistive Loads
0451
1-0-
096
TIME (ns)
OU
TPU
T VO
LTA
GE
(V)
0 5 10–0.20
–0.05
–0.10
–0.15
0.15
0.10
0.05
0
0.20
15 20 25 30 35 40 45 50
10pF, 20 RSNUB
1pF
RSNUB
CL RLG = +5VS = ±5VRL = 1k
Figure 38. Small Signal Transient Response for Various Capacitive Loads (LFCSP)
TIME (ns)
OU
TPU
T VO
LTA
GE
(V)
0 10–0.20
–0.05
–0.10
–0.15
0.15
0.10
0.05
0
0.20
20 30 40 50
RL = 1k, 100VOUT = 200mV p-pG = +5
VS = ±2.5VCSP VS = ±5.0V
CSP
VS = ±5.0VSOIC
VS = ±2.5VSOIC
0451
1-0-
102
Figure 39. Small Signal Transient Response for Various Supply Voltages
0451
1-0-
010
TIME (ns)
OU
TPU
T VO
LTA
GE
(V)
–0.52000 50 100 150
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0TURN ON
TURN ONINPUT
TURN OFF
TURN OFFINPUT
VS = ±5VG = 2
Figure 40. Disable/Enable Switching Speed
AD8099 Data Sheet
Rev. D | Page 12 of 28
TIME (ns)
OU
TPU
T VO
LTA
GE
(V)
0 10–1.5
–0.5
–1.0
1.0
0.5
0
1.5
20 30 40 50
G = +10RL = 1k
VS = ±2.5V
VS = ±5.0V
0451
1-0-
106
Figure 41. Large Signal Transient Response vs. Supply Voltage (LFCSP)
TIME (ns)
OU
TPU
T VO
LTA
GE
(V)
0 10–1.5
–0.5
–1.0
1.0
0.5
0
1.5
20 30 40 50
VS = ±5.0V
G = +10RL = 1k
VS = ±2.5V
0451
1-0-
118
Figure 42. Large Signal Transient Response vs. Supply Voltage (SOIC)
TIME (ns)
OU
TPU
T VO
LTA
GE
(V)
0 10–1.5
–0.5
–1.0
1.0
0.5
0
1.5
20 30 40 50
RL = 1k, 100G = +5
VS = ±5V
VS = ±2.5V
0451
1-0-
101
Figure 43. Large Signal Transient Response for Various Supply Voltages and Load Resistances (SOIC and LFCSP)
0451
1-0-
052
TIME (ns)
OU
TPU
T/IN
PUT
VOLT
AG
E (V
)
0 5 10 15 20 25 30 35 40–1.5
–0.5
–1.0
0
0.5
1.0
1.5
–0.3%
–0.1%
–0.2%
0%
0.1%
0.2%
0.3%
45
INPUT
ERROR
OUTPUT
G = +2RLOAD = 1kVs = ±5V
Figure 44. Short Term Settling Time (LFCSP)
0451
1-0-
051
TIME (ns)
OU
TPU
T/IN
PUT
VOLT
AG
E (V
)
0 5 10 15 20 25 30 35 40–1.5
–0.5
–1.0
0
0.5
1.0
1.5
–0.3%
–0.1%
–0.2%
0%
0.1%
0.2%
0.3%
45
G = +2RLOAD = 1kVs = ±5V
INPUT
ERROR
OUTPUT
Figure 45. Short Term Settling Time (SOIC)
0451
1-0-
050
TIME (s)
OU
TPU
T/IN
PUT
VOLT
AG
E (V
)
0 50 100 150 200 250 300 350 400 450–1.5
–0.5
–1.0
0
0.5
1.0
1.5
–0.30%
–0.10%
–0.20%
0%
0.10%
0.20%
0.30%
500
INPUT
ERROR
OUTPUTG = +2VS = ±5V
Figure 46. Long Term Settling Time
Data Sheet AD8099
Rev. D | Page 13 of 28
0451
1-0-
113
FREQUENCY (MHz)10000.1 1.0 10 100
CO
MM
ON
-MO
DE
REJ
ECTI
ON
(dB
)
–110
–20
–30
–50
–70
–40
–60
–80
–90
–100
G = +2RL = 1k
Figure 47. Common-Mode Rejection vs. Frequency
04
511-
0-00
4
1 10 100 1k 10k 100k 1M 10M 100M 1G1
10
100
1000
FREQUENCY (Hz)
INPU
T C
UR
REN
T N
OIS
E (p
A H
z)
Figure 48. Input Current Noise vs. Frequency (DISABLE = Open)
0451
1-0-
005
1 10 100 1k 10k 100k 1M 10M 100M 1G0.1
1
10
100
FREQUENCY (Hz)
INPU
T VO
LTA
GE
NO
ISE
(nV
Hz)
Figure 49. Input Voltage Noise vs. Frequency
0451
1-0-
114
FREQUENCY (MHz)10000.01 0.10 1.0 10 100
POW
ER S
UPP
LY R
EJEC
TIO
N (d
B)
–100
0
–20
–10
–40
–60
–30
–50
–70
–80
–90
G = +5RL = 1k
POSITIVE
NEGATIVE
Figure 50. Power Supply Rejection vs. Frequency
0451
1-0-
003
FREQUENCY (Hz)
INPU
T C
UR
REN
T N
OIS
E (p
A H
z)
1 10 100 1k 10k 100k 1M 10M 100M 1G1
10
100
1000
Figure 51. Input Current Noise vs. Frequency (DISABLE = +VS)
VOFFSET (V)
CO
UN
T
–3000
60
40
20
100
80
120
–200 0–100 100 200
0451
1-0-
075
VS = ±5VN = 1,200X = –70V = 80VX
Figure 52. Input Offset Voltage Distribution
AD8099 Data Sheet
Rev. D | Page 14 of 28
0451
1-A-
003
TEMPERATURE (C)125–40 –25 –10 5 20 35 50 65 80 95 110
OFF
SET
VOLT
AG
E (
V)
–200
400
200
100
300
0
–100
VS = 5V
VS = ±5V
Figure 53. Input Offset Voltage vs. Temperature
04
511-
A-00
4
TEMPERATURE (C)125–40 –25 –10 5 20 35 50 65 80 95 110
BIA
S C
UR
REN
T (
A)
–6.6
–5.4
–5.8
–6.0
–5.6
–6.2
–6.4
IB+, VS = ±5V
IB+, VS = 5V
IB–, VS = ±5V
IB–, VS = 5V
Figure 54. Input Bias Current vs. Temperature (DISABLE Pin Floating)
0451
1-A-
005
TEMPERATURE (C)125–40 –25 –10 –5 20 35 50 65 80 95 110
OU
TPU
T SA
TUR
ATI
ON
VO
LTA
GE
(V)
1.12
1.24
1.20
1.18
1.22
1.16
1.14+VS – VOUT
VS = 5V
VS = ±5V
+VS – VOUT
–VS + VOUT
–VS + VOUT
Figure 55. Output Saturation Voltage vs. Temperature
0451
1-A-
006
TEMPERATURE (C)125–40 –25 –10 5 20 35 50 65 80 95 110
SUPP
LY C
UR
REN
T (m
A)
8
20
16
14
18
12
10
VS = 5V
VS = ±5V
Figure 56. Supply Current vs. Temperature
0451
1-A-
007
TEMPERATURE (C)125–40 –25 –10 5 20 35 50 65 80 95 110
BIA
S C
UR
REN
T (
A)
–1.0
1.0
–0.2
–0.4
0
0.2
0.4
0.6
0.8
–0.6
–0.8
IB+, VS = 5V
IB+, VS = ±5V
IB–, VS = 5V
IB–, VS = ±5V
Figure 57. Input Bias Current vs. Temperature (DISABLE Pin = +VS)
Data Sheet AD8099
Rev. D | Page 15 of 28
THEORY OF OPERATION The AD8099 is a voltage feedback op amp that employs a new highly linear low noise input stage. With this input stage, the AD8099 can achieve better than 90 dB distortion for a 2 V p-p, 10 MHz output signal with an input referred voltage noise of less than 1 nV/√Hz. This noise level and distortion performance has been previously achievable only with fully uncompensated amplifiers. The AD8099 achieves this level of performance for gains as low as +2. This new input stage also triples the achievable slew rate for comparably compensated 1 nV/√Hz amplifiers.
The simplified AD8099 topology is shown in Figure 58. The amplifier is a single gain stage with a unity gain output buffer fabricated in Analog Devices’ extra fast complimentary bipolar process (XFCB). The AD8099 has 85 dB of open-loop gain and maintains precision specifications such as CMRR, PSRR, VOS, and VOS/T to levels that are normally associated with topologies having two or more gain stages.
BUFFERgmCCR1 RL
VOUT
0451
1-0-
060
Figure 58. AD8099 Topology
The AD8099 can be externally compensated down to a gain of 2 through the use of an RC network. Above gains of 15, no exter-nal compensation network is required. To realize the full gain bandwidth product of the AD8099, no PCB trace should be connected to or within close proximity of the external compen-sation pin for the lowest possible capacitance.
External compensation allows the user to optimize the closed-loop response for minimal peaking while increasing the gain bandwidth product in higher gains, lowering distortion errors that are normally more prominent with internally compensated parts in higher gains. For a fixed gain bandwidth, wideband distortion products would normally increase by 6 dB going from a closed-loop gain of 2 to 4. Increasing the gain bandwidth product of the AD8099 eliminates this effect with increasing closed-loop gain.
The AD8099 is available in both a SOIC and an LFCSP, each of which has a thermal pad for lower operating temperature. To help avoid this pad in board layout, both packages have an extra output pin on the opposite side of the package for ease in con-necting a feedback network to the inputs. The secondary output pin also isolates the interaction of any capacitive load on the
output and self-inductance of the package and bond wire from the feedback loop. While using the secondary output for feed-back, inductance in the primary output will now help to isolate capacitive loads from the output impedance of the amplifier. Since the SOIC has greater inductance in its output, the SOIC will drive capacitive loads better than the LFCSP. Using the primary output for feedback with both packages will result in the LFCSP driving capacitive load better than the SOIC.
The LFCSP and SOIC pinouts are identical, except for the rotation of all pins counterclockwise by one pin on the LFCSP. This isolates the inputs from the negative power supply pin, removing a mutually inductive coupling that is most prominent while driving heavy loads. For this reason, the LFCSP second harmonic, while driving a heavy load, is significantly better than that of the SOIC.
A three-state input pin is provided on the AD8099 for a high impedance power-down and an optional input bias current cancellation circuit. The high impedance output allows several AD8099s to drive the same ADC or output line time inter-leaved. Pulling the DISABLE pin low activates the high impedance state. See Table 5 for threshold levels. When the DISABLE pin is left floating, the AD8099 operates normally. With the DISABLE pin pulled within 0.7 V of the positive supply, an optional input bias current cancellation circuit is turned on, which lowers the input bias current to less than 200 nA. In this mode, the user can drive the AD8099 with a high dc source impedance and still maintain minimal output referred offset without having to use impedance matching techniques. In addition, the AD8099 can be ac-coupled while setting the bias point on the input with a high dc impedance network. The input bias current cancellation circuit will double the input referred current noise, but this effect is minimal as long as wideband impedance is kept low (see Figure 48 and Figure 51).
A pair of internally connected diodes limits the differential voltage between the noninverting input and the inverting input of the AD8099. Each set of diodes has two series diodes, which are connected in anti-parallel. This limits the differential voltage between the inputs to approximately 1.8 V. All of the AD8099 pins are ESD protected with voltage limiting diodes connected between both rails. The protection diodes can handle 5 mA of steady state current. Currents should be limited to 5 mA or less through the use of a series limiting resistor.
AD8099 Data Sheet
Rev. D | Page 16 of 28
APPLICATIONS USING THE AD8099 The AD8099 offers unrivaled noise and distortion performance in low signal gain configurations. In low gain configurations (less than15), the AD8099 requires external compensation. The amount of gain and performance needed will determine the compensation network.
Understanding the subtleties of the AD8099 gives the user insight on how to exact its peak performance. Use the component values and circuit configurations shown in the Applications section as starting points for designs. Specific circuit applications will dictate the final configuration and value of your components.
CIRCUIT COMPONENTS The circuit components are referenced in Figure 59, the recommended noninverting circuit schematic for the AD8099. See Table 4 for typical component values and performance data.
1
84
7
53
6
2
AD8099
C50.1µF
CC
CF
C1
C410µF
C210µF
C30.1µF
RC
RF
RG
RS
R1
+VS
–VS
VOUT
DISABLE
0451
1-0-
061
VIN
Figure 59. Wideband Noninverting Gain Configuration (SOIC)
RF and RG—The feedback resistor and the gain set resistor determine the noise gain of the amplifier; typical RF values range from 250 Ω to 499 Ω.
CF—Creates a zero in the loop response to compensate the pole created by the input capacitance (including stray capacitance) and the feedback resistor RF. CF helps reduce high frequency peaking and ringing in the closed-loop response. Typical range is 0.5 pF to 1.5 pF for evaluation circuits used here.
R1—This resistor terminates the input of the amplifier to the source resistance of the signal source, typically 50 Ω. (This is application specific and not always required.)
RS—Many high speed amplifiers in low gain configurations require that the input stage be terminated into a nominal impedance to maintain stability. The value of RS should be kept to 50 Ω or lower to maintain low noise performance. At higher gains, RS may be reduced or even eliminated. Typical range is 0 Ω to 50 Ω.
CC—The compensation capacitor decreases the open-loop gain at higher frequencies where the phase is degrading. By decreas-ing the open-loop gain here, the phase margin is increased and the amplifier is stabilized. Typical range is 0 pF to 5 pF. The value of CC is gain dependent.
RC—The series lead inductance of the package and the com-pensation capacitance (CC) forms a series resonant circuit. RC dampens this resonance and prevents oscillations. The recommended value of RC is 50 Ω for a closed-loop gain of 2. This resistor introduces a zero in the open-loop response and must be kept low so that this zero occurs at a higher frequency. The purpose of the compensation network is to decrease the open-loop gain. If the resistance becomes too large, the gain will be reduced to the resistor value, and not necessarily to 0 Ω, which is what a single capacitor would do over frequency. Typical value range is 0 Ω to 50 Ω.
C1—To lower the impedance of RC , C1 is placed in parallel with RC. C1 is not required, but greatly reduces peaking at low closed-loop gains. The typical value range is 0 pF to 2 pF.
C2 and C3—Bypass capacitors are connected between both supplies for optimum distortion and PSRR performance. These capacitors should be placed as close as possible to the supply pins of the amplifier. For C3, C5, a 0508 case size should be used. The 0508 case size offers reduced inductance and better frequency response.
C4 and C2—Electrolytic bypass capacitors.
Data Sheet AD8099
Rev. D | Page 17 of 28
RECOMMENDED VALUES Table 4. Recommended Values and AD8099 Performance
Gain Package
Feedback Network Values
Compensation Network Values
−3 dB SS Bandwidth
(MHz) Slew Rate
(V/s) Peaking
(dB)
Output Noise (AD8099 Only)
(nV/√Hz)
Total Output NoiseIncluding Resistors
(nV/√Hz) RF RG RS CF RC CC C1
−1, 2 SOIC 250 250 50 1.5 50 4 1.5 440/700 515 0.3/3.1 2.1 4
2 LFCSP 250 250 50 0.5 50 5 2 700 475 3.2 2.1 4
−1 LFCSP 250 250 50 1.0 50 5 2 420 475 0.8 2.1 4
5 LFCSP/SOIC 499 124 20 0.5 50 1 0 510 735 1.4 4.9 8.6
10 LFCSP/SOIC 499 54 0 0 0 0.5 0 550 1350 0.8 9.6 13.3
20 LFCSP/SOIC 499 26 0 0 0 0 0 160 1450 0 19 23.3
CIRCUIT CONFIGURATIONS Figure 60 through Figure 66 show typical schematics for the AD8099 in various gain configurations. Table 4 data was collected using the schematics shown in Figure 60 through Figure 66. Resistor R1, as shown in Figure 60 through Figure 66,
is the test equipment termination resistor. R1 is not required for normal operation, but is shown in the schematics for completeness.
1
84
7
53
6
2
AD8099
C50.1F
CC4pF
CF1.5pF
C11.5pF
C410F
C210F
C30.1F
RC50
RF250
RG250
RS50
R150
+VS
–VS
VOUT
0451
1-0-
116
VIN
RL1k
DISABLE
Figure 60. Amplifier Configuration for SOIC Package, Gain = –1
1
84
7
53
6
2
AD8099
C50.1F
CC4pF
CF1.5pF
C11.5pF
C410F
C210F
C30.1F
RC50
RF250
RG250
RS50
R150
+VS
–VS
VOUT
0451
1-0-
054
VINRL1k
DISABLE
Figure 61. Amplifier Configuration for SOIC Package, Gain = +2
2
15
8
64
7
3
AD8099
C50.1F
CC5pF
CF1pF
C12pF
C410F
C210F
C30.1F
RC50
RF250
RS50
+VS
–VS
VOUT
0451
1-0-
108
RG250
R150
VIN
RL1k
DISABLE
Figure 62. Amplifier Configuration for LFCSP Package, Gain =–1
2
15
8
64
7
3
AD8099
C50.1F
CC5pF
CF0.5pF
C12pF
C410F
C210F
C30.1F
RC50
RF250
RG250
RS50
R150
+VS
–VS
VOUT
0451
1-0-
053
VINRL1k
DISABLE
Figure 63. Amplifier Configuration for LFCSP Package, Gain = +2
AD8099 Data Sheet
Rev. D | Page 18 of 28
FB
AD8099
C50.1µF
CC1pF
CF0.5pF
C410µF
C210µF
C30.1µF
RC50Ω
RF499Ω
RG124Ω
RS20Ω
R150Ω
+VS
–VS
VOUT
0451
1-0-
055
VINRL1kΩ
–
+
D–V
CC
VO
+V
DISABLE
Figure 64. Amplifier Configuration for LCSP and SOIC Package, Gain = +5
AD8099
C50.1µF
CC0.5pFC4
10µF
C210µF
C30.1µF
RF499Ω
RG54Ω
R150Ω
+VS
–VS
VOUT
0451
1-0-
056
VINRL1kΩ
FB–
+
D–V
CC
VO
+V
DISABLE
Figure 65. Amplifier Configuration for LFCSP and SOIC Packages, Gain = +10
AD8099
C50.1µF
C410µF
C210µF
C30.1µF
RF499Ω
RG26Ω
R150Ω
+VS
–VS
VOUT
0451
1-0-
057
VINRL1kΩ
FB–
+
D–V
CC
VO
+V
DISABLE
Figure 66. Amplifier Configuration for LFCSP and SOIC Packages, Gain = +20
Data Sheet AD8099
Rev. D | Page 19 of 28
PERFORMANCE VS. COMPONENT VALUES The influence that each component has on the AD8099 frequency response can be seen in Figure 67 and Figure 68. In Figure 67 and Figure 68, all component values are held constant, except for the individual component shown, which is varied. For example, in the RS performance plot of Figure 68, all components are held constant except RS, which is varied from 0 Ω to 50 Ω.; and clearly indicates that RS has a major influence on peaking and bandwidth of the AD8099.
1
84
7
53
6
2
AD8099
C50.1F
CC
CF
C1
C410F
C210F
C30.1F
RC
RF
RG
RS
R1
+VS
–VS
VOUT
SOIC PINOUT SHOWN
VIN
DISABLE
0451
1-0-
117
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
–23000
0451
1-0-
020
1 10 100 1000
9
8
7
6
5
4
3
2
1
0
–1
VS = ±5VG = +2RLOAD = 1kSOIC PACKAGE
C1 = 0pF
C1 = 2pF
C1 = 1.5pF
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
–13000
0451
1-0-
024
1 10 100 1000
10
9
8
7
6
5
4
3
2
1
0
CC = 3pF
CC = 4pF
CC = 5pF
VS = ±5VG = +2RLOAD = 1kSOIC PACKAGE
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
–13000
0451
1-0-
030
1
10
8
9
7
6
5
4
3
2
1
0
VS = ±5VG = +2RLOAD = 1kSOIC PACKAGE
10 100 1000
RC = 50
RC = 35
RC = 20
Figure 67. Frequency Response for Various Values of C1, CC, RC
AD8099 Data Sheet
Rev. D | Page 20 of 28
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
–13000
0451
1-0-
032
1
10
8
9
7
6
5
4
3
2
1
0
VS = ±5VG = +2RLOAD = 1kSOIC PACKAGE
10 100 1000
RF = RG = 200
RF = RG = 250
RF = RG = 300
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
1–1
10
9
8
7
6
5
4
3
2
1
0
10 100 1000 3000
0451
1-0-
058
CF = 1pF
CF = 0.5pF
CF = 1.5pF
VS = ±5VG = +2RLOAD = 1kSOIC PACKAGE
FREQUENCY (MHz)
CLO
SED
-LO
OP
GA
IN (d
B)
010000
0451
1-0-
034
1
12
10
11
9
8
7
6
5
4
3
2
1
VS = ±5VG = +2RLOAD = 1kSOIC PACKAGE
10 100 1000
RS = 0
RS = 50
RS = 20
1
84
7
53
6
2
AD8099
C50.1F
CC
CF
C1
C410F
C210F
C30.1F
RC
RF
RG
RS
R1
+VS
–VS
VOUT
SOIC PINOUT SHOWN
VIN
DISABLE
0451
1-0-
117
Figure 68. Frequency Response for Various Values of RF, CF, RS
TOTAL OUTPUT NOISE CALCULATIONS AND DESIGN To analyze the noise performance of an amplifier circuit, the individual noise sources must be identified. Then determine if the source has a significant contribution to overall noise perfor-mance of the amplifier. To simplify the noise calculations, we will work with noise spectral densities, rather than actual voltages to leave bandwidth out of the expressions (noise spectral density, which is generally expressed in nV/Hz, is equivalent to the noise in a 1 Hz bandwidth).
The noise model shown in Figure 69 has six individual noise sources: the Johnson noise of the three resistors, the op amp voltage noise, and the current noise in each input of the amplifier. Each noise source has its own contribution to the
noise at the output. Noise is generally specified RTI (referred to input), but it is often simpler to calculate the noise referred to the output (RTO) and then divide by the noise gain to obtain the RTI noise.
All resistors have a Johnson noise of (4kBTR), where k is Boltzmann’s Constant (1.38 × 10–23 J/K), T is the absolute temperature in Kelvin, B is the bandwidth in Hz, and R is the resistance in ohms. A simple relationship, which is easy to remember, is that a 50 Ω resistor generates a Johnson noise of 1 nVHz at 25C. The AD8099 amplifier has roughly the same equivalent noise as a 50 Ω resistor.
Data Sheet AD8099
Rev. D | Page 21 of 28
0451
1-0-
070
GAIN FROM"B" TO OUTPUT = – R2
R1
GAIN FROM"A" TO OUTPUT =
NOISE GAIN =
NG = 1 + R2R1
IN–
VN
VN, R1
VN, R3
R1
R2
IN+R3
4kTR2
4kTR1
4kTR3
VN, R2
B
A
VN2 + 4kTR3 + 4kTR1 R2 2
R1 + R2
IN+2R32 + IN–2 R1 × R2 2 + 4kTR2 R1 2
R1 + R2 R1 + R2RTI NOISE =
RTO NOISE = NG × RTI NOISE
VOUT
+
Figure 69. Op Amp Noise Analysis Model
In applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. Each resistor is a noise source. Attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. A summary of noise performance for the amplifier and associated resistors can be seen in Table 4.
INPUT BIAS CURRENT AND DC OFFSET In high noise gain configurations, the effects of output offset voltage can be significant, even with low input bias currents and input offset voltages. Figure 70 shows a comprehensive offset voltage model, which can be used to determine the referred to output (RTO) offset voltage of the amplifier or referred to input (RTI) offset voltage.
0451
1-0-
071
GAIN FROM"B" TO OUTPUT = – R2
R1
GAIN FROM"A" TO OUTPUT =
NOISE GAIN =
NG = 1 + R2R1
IB–
VOS
R1
R2
IB+R3
B
A
OFFSET (RTO) = VOS 1 + R2 + IB+ × R3 1 + R2 – IB– × R2R1 R1
OFFSET (RTI) = VOS + IB+ × R3 – IB–R1 × R2R1 + R2
OFFSET (RTI) = VOS IF IB+ = IB– AND R3 = R1 × R2 R1 + R2
VOUT
FOR BIAS CURRENT CANCELLATION:
Figure 70. Op Amp Total Offset Voltage Model
For RTO calculations, the input offset voltage and the voltage generated by the bias current flowing through R3 are multiplied by the noise gain of the amplifier. The voltage generated by IB– through R2 is summed together with the previous offset voltages to arrive at a final output offset voltage. The offset voltage can also be referred to the input (RTI) by dividing the calculated output offset voltage by the noise gain.
As seen in Figure 70 if IB+ and IB– are the same and R3 equals the parallel combination of R1 and R2, then the RTI offset voltage can be reduced to only VOS. This is a common method used to reduce output offset voltage. Keeping resistances low helps to minimize offset error voltage and keeps the voltage noise low.
DISABLE PIN AND INPUT BIAS CANCELLATION
The AD8099 DISABLE pin performs three functions; enable, disable, and reduction of the input bias current. When the DISABLE pin is brought to within 0.7 V of the positive supply, the input bias current is reduced by an approximate factor of 60. However, the input current noise doubles to 5.2 pA/Hz. Table 5 outlines the DISABLE pin functionality.
Table 5. DISABLE Pin Truth Table Supply Voltage ±5 V +5 V
Disable –5 to +2.4 0 to 2.4 Enable Open Open Low Input Bias Current 4.3 to 5 4.3 to 5
AD8099 Data Sheet
Rev. D | Page 22 of 28
8
1
4
7
53
6
2
AD8099
AD7667
C410µF
CC9pF
C12pF
C50.1µF
C110µF
C20.1µF
RC50Ω
RF150Ω
RG150Ω
RS50Ω
R1590Ω
R2590Ω
+VS
–VS
DISABLE
VIN
0451
1-0-
072
IN
REFGND
REF
INGND
AGND AVDD DGND DVDD
DVDD
C62.7nF
R715Ω
AVDD
1µF 47µF
REF
0.1µF 0.1µF
+2.5V
Figure 71. ADC Driver
16-BIT ADC DRIVER Ultralow noise and distortion performance make the AD8099 an ideal ADC driver. Even though the AD8099 is not unity gain stable, it can be configured to produce a net gain of +1 amplifier, as shown in Figure 71. This is achieved by combining a gain of +2 and a gain of –1 for a net gain of +1. The input range of the ADC is 0 V to 2.5 V.
Table 6 shows the performance data of the AD8099 and the Analog Devices AD7667 a 1 MSPS 16-bit ADC.
Table 6. ADC Driver Performance, fC = 20 kHz, VOUT = 2.24 V p-p Parameter Measurement (dB) Second Harmonic Distortion –111.4 Third Harmonic Distortion –103.2 THD –101.4 SFDR 102.2 SNR 88.1
Data Sheet AD8099
Rev. D | Page 23 of 28
CIRCUIT CONSIDERATIONS Optimizing the performance of the AD8099 requires attention to detail in layout and signal routing of the board. Power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier. The AD8099 features an exposed paddle on the backs of both the LFCSP and SOIC packages. The exposed paddle provides a low thermal resistive path to the ground plane. For best performance, solder the exposed paddle to the ground plane.
PCB Layout
The compensation network is determined by the amplifier gain requirements. For lower gains, the layout and component placement are more critical. For higher gains, there are fewer compensation components, which results in a less complex layout. With diligent consideration to layout, grounding, and component placement, the AD8099 evaluation boards have been optimized for peak performance. These are the same evaluation boards that are available to customers; see the Ordering Guide for ordering information.
Parasitics
The area surrounding the compensation pin is very sensitive to parasitic capacitance. To realize the full gain bandwidth product of the AD8099, there should be no trace connected to or within close proximity of the external compensation pin for the lowest possible capacitance. When compensation is required, the traces to the compensation pin, the negative supply, and the interconnect between components (i.e. CC, C1, and RC in Figure 59) should be made as wide as possible to minimize inductance.
All ground and power planes under the pins of the AD8099 should be cleared of copper to prevent parasitic capacitance between the input and output pins to ground. A single mount-ing pad on a SOIC footprint can add as much as 0.2 pF of capacitance to ground as a result of not clearing the ground or power plane under the AD8099 pins. Parasitic capacitance can cause peaking and instability, and should be minimized to ensure proper operation.
The new pinout of the AD8099 reduces the distance between the output and the inverting input of the amplifier. This helps to minimize the parasitic inductance and capacitance of the feedback path, which, in turn, reduces ringing and second harmonic distortion.
Grounding
When possible, ground and power planes should be used. Ground and power planes reduce the resistance and inductance of the power supply feeds and ground returns. If multiple planes are used, they should be “stitched” together with multiple vias. The returns for the input, output terminations, bypass capacitors, and RG should all be kept as close to the AD8099 as possible. Ground vias should be placed at the very end of the component mounting pad to provide a solid ground return. The output load ground and the bypass capacitor grounds should be returned to a common point on the ground plane to minimize parasitic inductance and improve distortion performance. The AD8099 packages feature an exposed paddle. For optimum performance, solder this paddle to ground. For more infor-mation on PCB layout and design considerations, refer to section 7-2 of the 2002 Analog Devices Op Amp Applications book.
Power Supply Bypassing
The AD8099 power supply bypassing has been optimized for each gain configuration as shown in Figure 60 through Figure 66 in the Circuit Configurations section. The values shown should be used when possible. Bypassing is critical for stability, frequency response, distortion, and PSRR performance. The 0.1 µF capacitors shown in Figure 60 through Figure 66 should be as close to the supply pins of the AD8099 as possible and the electrolytic capacitors beside them.
Component Selection
Smaller components less than 1206 SMT case size, offer smaller mounting pads, which have less parasitics and allow for a more compact layout. It is critical for optimum performance that high quality, tight tolerance (where critical), and low drift compo-nents be used. For example, tight tolerance and low drift is critical in the selection of the feedback capacitor used in Figure 60. The feedback compensation capacitor in Figure 60 is 1.5pF. This capacitor should be specified with NPO material. NPO material typically has a ±30 ppm/°C change over –55°C to +125°C temperature range. For a 100°C change, this would result in a 4.5 fF change in capacitance, compared to an X7R material, which would result in a 0.23 pF change, a 15% change from the nominal value. This could introduce excessive peaking, as shown in Figure 68, CF vs. Frequency Response.
DESIGN TOOLS AND TECHNICAL SUPPORT Analog Devices is committed to the design process by providing technical support and online design tools. ADI offers technical support via evaluation boards, sample ICs, SPICE models, interactive evaluation tools, application notes, phone and email support—all available at www.analog.com.
AD8099 Data Sheet
Rev. D | Page 24 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-012-AA 06-0
2-20
11-B
1.270.40
1.751.35
2.29
2.29
0.356
0.457
4.003.903.80
6.206.005.80
5.004.904.80
0.10 MAX0.05 NOM
3.81 REF
0.250.17
8°0°
0.500.25
45°
COPLANARITY0.10
1.04 REF
8
1 4
5
1.27 BSC
SEATINGPLANE
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE CONNECTION DIAGRAMSSECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VIEW
0.510.31
1.651.25
Figure 72. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body
(RD-8-1) Dimensions shown in millimeters
1
EXPOSEDPAD
(BOTTOM VIEW)
0.50BSC
PIN 1INDICATOR0.50
0.400.30
TOPVIEW
12° MAX 0.70 MAX0.65 TYP0.90 MAX
0.85 NOM 0.05 MAX0.01 NOM
0.20 REF
1.891.741.59
4
1.601.451.30
3.253.00 SQ2.75
2.952.75 SQ2.55
5 8
PIN 1INDICATOR
SEATINGPLANE
0.300.230.18
0.60 MAX
0.60 MAX
04-0
4-20
12-A
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE CONNECTION DIAGRAMSSECTION OF THIS DATA SHEET.
Figure 73. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2) Dimensions shown in millimeters
Data Sheet AD8099
Rev. D | Page 25 of 28
ORDERING GUIDE
Model1 Ordering Quantity Temperature Range Package Description Branding
Package Option
AD8099ARD 98 –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1
AD8099ARD-REEL 2,500 –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1
AD8099ARD-REEL7 1,000 –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1
AD8099ARDZ 98 –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1
AD8099ARDZ-REEL 2,500 –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1
AD8099ARDZ-REEL7 1,000 –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1
AD8099ACPZ-R2 250 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] HDB CP-8-2
AD8099ACPZ-REEL 5,000 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] HDB CP-8-2
AD8099ACPZ-REEL7 1,500 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] HDB CP-8-2
AD8099ACPI-EBZ Evaluation Board for Inverting 8-Lead LFCSP_VD
AD8099ACPN-EBZ Evaluation Board for Noninverting 8-Lead LFCSP_VD
AD8099ARDI-EBZ Evaluation Board for Inverting 8-Lead SOIC_N_EP
AD8099ARDN-EBZ Evaluation Board for Noninverting 8-Lead SOIC_N_EP
1 Z = RoHS Compliant Part.
AD8099 Data Sheet
Rev. D | Page 26 of 28
NOTES
Data Sheet AD8099
Rev. D | Page 27 of 28
NOTES
AD8099 Data Sheet
Rev. D | Page 28 of 28
NOTES
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