a&d electronics assignment

Colchester InstituteCentre for EngineeringCertificate in Engineering (2800)Level 3

Practical Assignment

Analogue and Digital Electronics

Unit 57 – Assignment Guide

2800-057

C&G2800 RcMUnit 57 A&D Electronics Oct 08 of 21

Colchester InstituteC&G2800 Engineering Certificate Level 3Unit 57: Analogue & Digital Electronics

Assignment Guide 2C Issue Date: Oct 2008

Recommended time allocation – 10 hours

General Guidance

The Assignment should take place in a workshop/laboratory with appropriate machines, testing equipment and relevant tools. Adequate supervision needs to be provided in accordance with HASWA regulations.

Safety equipment and codes of practice associated with the machinery and practices MUST be understood and implemented by the candidate. Failure to work safely will result in the failure of the assignment.

It is the responsibility of the assessor to monitor candidates attitude and practice of safety at ALL times and to ensure that ALL PPE is appropriately used and that all safety codes of practice associated with the assignment are obeyed.

The candidate will be issued with the assessment guide and any additional information referred to in the instructions. The response-sheets for the candidate are included in this Assignment Guide. Candidates may use additional sheets should they require more space for detail.

Candidates may seek guidance from their assessor in the interpretation of working drawings and symbols/standards.

NOTE: In order to pass this assignment ALL aspects of safety MUST be demonstrated to the assessor at ALL times. Failure to so will result in the assignment being halted.


System Explanation:

This assignment is based around the Multisim circuit provided (Fig:#1). The diagram represents a prototype design for a system that combines both digital and analogue elements. However, the initial design uses “virtual” components throughout. A working design using specified, practical components is required.

The Multisim circuit is a working simulation of the majority of the required functions:-

With the Count / Reset switch closed (key = T) the 555 Clock Generator is permanently reset, both counters in the Time Count section are “zeroed” via the Reset Logic and the counter CLR functions (the counter display shows 00). The dc Regulator output is held at zero via the transistor Q2. The “dc Output” l.e.d. (LED2) is off and the “Time Expired” l.e.d. (LED1) is also off.

When the Count / Reset switch is opened the 555 clock generator is enabled and the output pulses (1Hz nom.) are fed to the counter circuits which are now also enabled. The display will start to increment. At the same time the voltage regulator is activated and a stabilised dc voltage is available across Rload. LED2 will illuminate to indicate that the dc output is on.

As presently designed, the counter will count to 99 and reset to 00 on the next pulse. The dc output will be inhibited and LED2 will go off. LED1 will come on to indicate that the time has period expired. The counter will continue to cycle (there is no indication of the number cycles completed).

Closing the Count / Reset switch, at any time, will immediately reset the displays to 00, disable the clock generator and, if required, extinguish LED1. The stabilised dc output will be inhibited and the system will be fully reset in preparation for the next count cycle.


U1

1

DIS7

OUT3

RST4

8

THR6

CON5

TRI2

GND

VCC

555_VIRTUAL*

R168kohm

C1

100nFC210nF

U2

DCD_HEX

4 3 2 1U3

GEN_CNTR_4ABIN*

QAQBQCQDIN

CLR

U4

AND3*

U5

DCD_HEX

4 3 2 1U6

GEN_CNTR_4ABIN*

QAQBQCQDIN

CLR

U7

AND3*U12

OR2*

U13

OR2*

Count_ResetKey = T

R21kOhm

U14

OR2*

U15

NOT*

R3

Key = A 10kOhm

50%V112 V

D1

5 V

R4

1kOhm

U16

SR_FF*

SQ

~Q R

LED1

R5100 Ohm

R71kOhm dc_Regulator

BJT_NPN_VIRTUAL

R810 Ohm

R91kOhm

D26.2 V

C31uF

Q2BJT_NPN_VIRTUAL

R6

1kOhm

U8

OR2*

U9

NOT*

LED2 Rload10 Ohm

Time Expired

Clock Generator

Time Count

Reset Logic

FreqAdjust

DC_Output

Fig #1 Test Circuit(shown cycling after expiry of the initial count)

Assignment content and candidates’ instructions

This assignment is intended to assess the practical activities and underpinning knowledge for Unit 57 – Analogue and Digital Electronics. It is intended to test the ability and skill level of the candidates over an agreed period of time.

Candidates are advised to read the entire document and study the outline of the assignment before starting work. They should check with their assessor that the materials equipment and information/data sources are available.

This assignment consists of FOUR tasks

1) Develop a section of an electronic circuit from a basic design

and produce a circuit diagram suitable for purpose

2) Construct an electronic circuit module that forms part of

the overall system

3) Test the operation of a circuit module

4) Fault-find to component level


The candidate must achieve a pass mark for all tasks in order to be awarded a pass, credit or distinction for the unit. A failure in one particular task will result in the failure of the whole unit.

Tasks: It is required that this preliminary design is carried forward to a working circuit. The circuit can be divided in to FOUR sub-sections:-

(A) The Clock Generator

(B) The Counter Logic & Display

(C) The Switchable Stabilised dc Supply

(D) The Control & Reset Logic

These sub-sections need to be developed such that they can be modelled and constructed using actual devices. There are some design guidelines that will need to be applied to each of these elements. A 12V dc supply voltage is assumed throughout.

General PASS Grading

Planning, preparation and recording

Pass: A pass candidate may have

sought advice prior to carrying out tasks required assistance in planning and setting up required assistance in selecting equipment and consumables needed help in preparing materials before commencing tasks produced report forms that show only a minimum of required detail

Practical activities

Pass: A pass candidate must have

attempted all the basic tasks specified (individually or as part of a team), with a good degree of success, providing all evidence required in the form of products and data


(A) CLOCK GENERATOR

This could use a practical 555 device. The output frequency should be adjustable to be nominally 1Hz + 5%(min). All components must be standard preferred values. All appropriate calculations should be provided to justify the component value selection. A working Multisim simulation of this circuit element should be provided.

NOTE: it will not be necessary to limit the output voltage using a resistor and 5V zener diode when this circuit is combined with the CMOS logic devices required which operate from a 12V supply

Possible extension tasks

(i) the consideration and design of appropriate circuitry to provide an alternative source of clock pulses (e.g 4060) and the provision of a working Multisim simulation of this circuit element.

(ii) the building and testing of the improved circuit design

SEE CREDIT & DISTINCTION GRADING CRITERIA BELOW

CREDIT Grading


Credit: A credit candidate will complete the tasks in an efficient manner ensure that all procedures, specifications and documentation are available including a working

Multisim simulation of the circuit ensure that all consumables, equipment, prepared materials are available report forms that show most of the required detail


Credit: A credit candidate will have successfully completed the basic tasks specified (individually or as part of a team) in an

efficient manner providing all evidence required in the form of products and data have, individually, attempted the technical extension tasks suggested, with a good degree of

success providing all evidence required in the form of products and data

DISTINCTION Grading


Distinction: In addition to the above a Distinction candidate will have Worked independently Made efficient use of consumables, equipment and prepared materials Considered/designed appropriate circuitry to implement other elements of the system report forms that show all of the required detail


Distinction: In addition to the above a Distinction candidate will have


successfully implemented the technical extension tasks suggested (or an agreed equivalent extension of the work), providing all evidence required in the form of products and data

(B) COUNTER LOGIC & DISPLAYS

This element should be designed using the following CMOS logic devices: 4081, 4511 and 4516. Suitable l.e.d. Common-Cathode seven-segment displays will be supplied and appropriate E12 series resistors should be used to limit the current in each segment. All appropriate calculations should be provided to justify the component value selection. Appropriate elements may be added to the Multisim circuit to simulate any inputs required.


(i) the consideration and design of circuitry to allow the maximum count to be adjustable and pre-set prior to the count cycle being initiated and the provision of a working Multisim simulation of this circuit element.



CREDIT Grading








DISTINCTION Grading




Distinction: In addition to the above a Distinction candidate will have successfully implemented the technical extension tasks suggested (or an agreed equivalent

extension of the work), providing all evidence required in the form of products and data


(C) SWITCHABLE STABILISED dc SUPPLY

Practical devices must be specified. Suitable resistor values must be calculated and used to ensure that the power dissipation in D2 and LED2 is acceptable. A BC547 may be used for Q2. Q1 must be specified such that the power dissipation when it is supplying a 10 ohm load is less than 50% of the maximum rating. All appropriate calculations should be provided to justify the component value selection. A simple switch circuit may be added to simulate the signal from the reset logic within the Multisim circuit.


(i) the consideration and design of circuitry to allow closed-loop control of a variable dc voltage to be available and the provision of a working Multisim simulation of this circuit element.



CREDIT Grading








DISTINCTION Grading




Distinction: In addition to the above a Distinction candidate will have successfully implemented the technical extension tasks suggested (or an agreed equivalent

extension of the work), providing all evidence required in the form of products and data


(D) CONTROL & RESET LOGIC

CMOS logic elements are to be used. The INVERTER elements are available within the 4069. The 4002 may be used, with slight adjustment, to provide the other combinational logic functions as well as the SR Bi-stable. However, any devices giving equivalent logical functionality may be used. A suitable resistor value must be calculated and used to ensure that the power dissipation in LED1 is acceptable. All appropriate calculations should be provided to justify the component value selection. A simple switch circuit may be added to simulate the SET signal and indicators to show the status of the output signals required within the Multisim circuit.


(i) the consideration and design of appropriate circuitry to indicate the number of count cycles completed and the provision of a working Multisim simulation of this circuit element.



CREDIT Grading








DISTINCTION Grading




Distinction: In addition to the above a Distinction candidate will have


successfully implemented the technical extension tasks suggested(or an agreed equivalent extension of the work), providing all evidence required in the form of products and data

TASKS

TASK1(PRODUCING THE CIRCUIT DIAGRAM ):

The chosen section of the overall system will need a working Multisim circuit diagram, suitable for purpose.

Candidates should identify and agree with the assessor the module to be worked on. Any working and records of the process and the degree of success should be kept for assessment.

The circuit diagram of the module to be constructed must be available as hardcopy as well as being demonstrated to your tutor. Any comments, describing the activity and any changes or modifications made during the development process, should be entered onto sheet 57.1a.

TASK 2 (CONSTRUCTING THE CIRCUIT):

Each candidate will produce a complete “Parts List” (incl. circuit references, values, details etc.) for the module to be constructed using sheet 57.2a and obtain all the necessary components.

Candidates should identify and agree with the assessor the method of construction to be used (e.g. veroboard, pcb etc.). Protobloc may be used for testing the functionality of designed circuits.

A component layout diagram should be produced for approval prior to construction and any alterations and / or improvements are to be recorded on sheet 57.2b.

The circuit should be constructed in accordance with the layout produced. A visual inspection should be carried out and any necessary corrections made. Sheet 57.2c should be used to record any evidence of inspection and rework.


TASK 3 (TESTING THE CIRCUIT):

Candidates must perform any necessary static checks on the circuit using appropriate test equipment and record the tests, the test results and the equipment used on sheet 57.3a.

Candidates will carry out any dynamic testing required on the circuit using appropriate test equipment. The tests, test results and equipment used should be recorded on sheet 57.3a. These tests should be observed by the tutor.

Only after the successful completion of the dynamic tests should the candidate’s electronic module be incorporated into a complete working system. Your tutor must confirm the correct operation of the circuit within the overall system. Record the results on sheet 57.3b. If the inserted module does not function correctly, take appropriate remedial action recording all re-work undertaken on sheet 57.3b (see Fault-Finding below).

Draw up a test specification for the overall system. This should include checks on all functionality as well as the electrical input and output requirements for the circuit.

TASK 4 (FAULT-FINDING):

Each candidate will be expected to perform dynamic and static tests to locate faults, to component level on power-up of their module. Sheet 57.4a should be completed identifying the tests performed and the results obtained. Sheet 57.4b should be used to record the symptoms observed and the most probable cause of the fault (one component). Where possible this should be supported by the findings of a Multisim simulation of the faulted circuit / circuit element.

ALTERNATIVELY

Candidates should carry out a comprehensive fault-finding procedure on a representative faulted circuit (one single fault) and to produce a failure analysis report (sheets 57.4a and 57.4b) that describes the symptoms observed, the tests performed, the results obtained and the probable cause of the fault. Where possible this should be supported by the


findings of a Multisim simulation of the faulted circuit / circuit element.

RECORD SHEET 57.1a- Circuit Design Candidate Name:

Module: Date:


RECORD SHEET 57.2a- Parts List Candidate Name:

Module: Date:


RECORD SHEET 57.2b- Component layout and circuit construction Candidate Name:

Module: Date:


RECORD SHEET 57.2c- Visual inspection and rework Candidate Name:

Module: Date:


RECORD SHEET 57.3a- Testing the operation of the circuit module Candidate Name:

Module: Date:


RECORD SHEET 57.3b- Testing the operation of the system Candidate Name:

Module: Date:


RECORD SHEET 57.3c- Test specification Candidate Name:

Module: Date:


RECORD SHEET 57.4a- Fault-finding tests performed and results obtained Candidate Name:

Module: Date:


RECORD SHEET 57.4b- Symptoms and most probable cause of fault Candidate Name:

Module: Date:


Analogue and Digital Electronics - Unit 057C&G2800 Certificate in Engineering Level 3

Candidate Name: ……………………….....

Mark distribution


Pass 1

Credit 2

Distinction 3


Pass 2

Credit 4

Distinction 6

Underpinning knowledge questions

50 – 64% Pass 1

65 – 79% Credit 2

80 – 100% Distinction 3

Overall grade

4 – 6 Marks Pass

7 – 9 Marks Credit

10 – 12 Marks Distinction


a&d electronics assignment

Documents

practical assignment

count reset switch

dc output

time count section

time expired

reset logic

dc regulator output

digital electronics