ad 624
TRANSCRIPT
REV. C
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aAD624
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 Ā© Analog Devices, Inc., 1999
PrecisionInstrumentation Amplifier
PRODUCT DESCRIPTIONThe AD624 is a high precision, low noise, instrumentationamplifier designed primarily for use with low level transducers,including load cells, strain gauges and pressure transducers. Anoutstanding combination of low noise, high gain accuracy, lowgain temperature coefficient and high linearity make the AD624ideal for use in high resolution data acquisition systems.
The AD624C has an input offset voltage drift of less than0.25 ĀµV/Ā°C, output offset voltage drift of less than 10 ĀµV/Ā°C,CMRR above 80 dB at unity gain (130 dB at G = 500) and amaximum nonlinearity of 0.001% at G = 1. In addition to theseoutstanding dc specifications, the AD624 exhibits superior acperformance as well. A 25 MHz gain bandwidth product, 5 V/Āµsslew rate and 15 Āµs settling time permit the use of the AD624 inhigh speed data acquisition applications.
The AD624 does not need any external components for pre-trimmed gains of 1, 100, 200, 500 and 1000. Additional gainssuch as 250 and 333 can be programmed within one percentaccuracy with external jumpers. A single external resistor canalso be used to set the 624ās gain to any value in the range of 1to 10,000.
PRODUCT HIGHLIGHTS1. The AD624 offers outstanding noise performance. Input
noise is typically less than 4 nV/āHz at 1 kHz.
2. The AD624 is a functionally complete instrumentation am-plifier. Pin programmable gains of 1, 100, 200, 500 and 1000are provided on the chip. Other gains are achieved throughthe use of a single external resistor.
3. The offset voltage, offset voltage drift, gain accuracy and gaintemperature coefficients are guaranteed for all pretrimmedgains.
4. The AD624 provides totally independent input and outputoffset nulling terminals for high precision applications.This minimizes the effect of offset voltage in gain rangingapplications.
5. A sense terminal is provided to enable the user to minimizethe errors induced through long leads. A reference terminal isalso provided to permit level shifting at the output.
FEATURES
Low Noise: 0.2 V p-p 0.1 Hz to 10 Hz
Low Gain TC: 5 ppm max (G = 1)
Low Nonlinearity: 0.001% max (G = 1 to 200)
High CMRR: 130 dB min (G = 500 to 1000)
Low Input Offset Voltage: 25 V, max
Low Input Offset Voltage Drift: 0.25 V/C max
Gain Bandwidth Product: 25 MHz
Pin Programmable Gains of 1, 100, 200, 500, 1000
No External Components Required
Internally Compensated
FUNCTIONAL BLOCK DIAGRAM
225.3
124
4445.7
80.2
50
VB
50
20k 10k
10k
10k
AD624
āINPUT
G = 100
G = 200
G = 500
RG1
RG2
+INPUT
SENSE
OUTPUT
REF
20k 10k
REV. Cā2ā
AD624āSPECIFICATIONSModel AD624A AD624B AD624C AD624S
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
GAINGain Equation
(External Resistor GainProgramming)
40,000
RG
+ 1
Ā± 20%
40,000
RG
+ 1
Ā± 20%
40,000
RG
+ 1
Ā± 20%
40,000
RG
+ 1
Ā± 20%
Gain Range (Pin Programmable) 1 to 1000 1 to 1000 1 to 1000 1 to 1000Gain Error
G = 1 Ā±0.05 Ā±0.03 Ā±0.02 Ā±0.05 %G = 100 Ā±0.25 Ā±0.15 Ā±0.1 Ā±0.25 %G = 200, 500 Ā±0.5 Ā±0.35 Ā±0.25 Ā±0.5 %
NonlinearityG = 1 Ā± 0.005 Ā± 0.003 Ā± 0.001 Ā± 0.005 %G = 100, 200 Ā± 0.005 Ā± 0.003 Ā± 0.001 Ā± 0.005 %G = 500 Ā± 0.005 Ā± 0.005 Ā± 0.005 Ā± 0.005 %
Gain vs. TemperatureG = 1 5 5 5 5 ppm/Ā°CG = 100, 200 10 10 10 10 ppm/Ā°CG = 500 25 15 15 15 ppm/Ā°C
VOLTAGE OFFSET (May be Nulled)Input Offset Voltage 200 75 25 75 ĀµV
vs. Temperature 2 0.5 0.25 2.0 ĀµV/Ā°COutput Offset Voltage 5 3 2 3 mV
vs. Temperature 50 25 10 50 ĀµV/Ā°COffset Referred to the Input vs. Supply
G = 1 70 75 80 75 dBG = 100, 200 95 105 110 105 dBG = 500 100 110 115 110 dB
INPUT CURRENTInput Bias Current Ā±50 Ā±25 Ā±15 Ā±50 nA
vs. Temperature Ā± 50 Ā± 50 Ā± 50 Ā± 50 pA/Ā°CInput Offset Current Ā±35 Ā±15 Ā±10 Ā±35 nA
vs. Temperature Ā± 20 Ā± 20 Ā± 20 Ā± 20 pA/Ā°C
INPUTInput Impedance
Differential Resistance 109 109 109 109 Ī©Differential Capacitance 10 10 10 10 pFCommon-Mode Resistance 109 109 109 109 Ī©Common-Mode Capacitance 10 10 10 10 pF
Input Voltage Range1
Max Differ. Input Linear (VDL) Ā± 10 Ā± 10 Ā± 10 Ā± 10 V
Max Common-Mode Linear (VCM) 12 V ā
G
2Ć VD
12 V āG
2Ć VD
12 V ā
G
2Ć VD
12 V ā
G
2Ć VD
V
Common-Mode Rejection dcto 60 Hz with 1 kĪ© Source Imbalance
G = 1 70 75 80 70 dBG = 100, 200 100 105 110 100 dBG = 500 110 120 130 110 dB
OUTPUT RATINGV
OUT
, RL = 2 kĪ© Ā± 10 Ā± 10 Ā± 10 Ā± 10 V
DYNAMIC RESPONSESmall Signal ā3 dB
G = 1 1 1 1 1 MHzG = 100 150 150 150 150 kHzG = 200 100 100 100 100 kHzG = 500 50 50 50 50 kHzG = 1000 25 25 25 25 kHz
Slew Rate 5.0 5.0 5.0 5.0 V/ĀµsSettling Time to 0.01%, 20 V Step
G = 1 to 200 15 15 15 15 ĀµsG = 500 35 35 35 35 ĀµsG = 1000 75 75 75 75 Āµs
NOISEVoltage Noise, 1 kHz
R.T.I. 4 4 4 4 nV/āHzR.T.O. 75 75 75 75 nV/āHz
R.T.I., 0.1 Hz to 10 HzG = 1 10 10 10 10 ĀµV p-pG = 100 0.3 0.3 0.3 0.3 ĀµV p-pG = 200, 500, 1000 0.2 0.2 0.2 0.2 ĀµV p-p
Current Noise0.1 Hz to 10 Hz 60 60 60 60 pA p-p
SENSE INPUTRIN 8 10 12 8 10 12 8 10 12 8 10 12 kĪ©IIN 30 30 30 30 ĀµAVoltage Range Ā± 10 Ā± 10 Ā± 10 Ā± 10 VGain to Output 1 1 1 1 %
(@ VS = 15 V, RL = 2 k and TA = +25C, unless otherwise noted)
REV. C ā3ā
AD624Model AD624A AD624B AD624C AD624S
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
REFERENCE INPUTRIN 16 20 24 16 20 24 16 20 24 16 20 24 kĪ©IIN 30 30 30 30 ĀµAVoltage Range Ā± 10 Ā± 10 Ā± 10 Ā± 10 VGain to Output 1 1 1 1 %
TEMPERATURE RANGESpecified Performance ā25 +85 ā25 +85 ā25 +85 ā55 +125 Ā°CStorage ā65 +150 ā65 +150 ā65 +150 ā65 +150 Ā°C
POWER SUPPLYPower Supply Range 6 15 18 6 15 18 6 15 18 6 15 18 VQuiescent Current 3.5 5 3.5 5 3.5 5 3.5 5 mA
NOTES1VDL is the maximum differential input voltage at G = 1 for specified nonlinearity, V DL at other gains = 10 V/G. VD = actual differential input voltage.
1Example: G = 10, VD = 0.50. VCM = 12 V ā (10/2 Ć 0.50 V) = 9.5 V.Specifications subject to change without notice.Specifications shown in boldface are tested on all production unit at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minand max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ā±18 VInternal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 420 mWInput Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ā±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Ā±VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . IndefiniteStorage Temperature Range . . . . . . . . . . . . . ā65Ā°C to +150Ā°COperating Temperature Range
AD624A/B/C . . . . . . . . . . . . . . . . . . . . . . . ā25Ā°C to +85Ā°CAD624S . . . . . . . . . . . . . . . . . . . . . . . . . . . ā55Ā°C to +125Ā°C
Lead Temperature (Soldering, 60 secs) . . . . . . . . . . . . +300Ā°C*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.
CONNECTION DIAGRAM
āINPUT
+INPUT
RG1
OUTPUT NULL
INPUT NULL
REF
āVS
G = 200
G = 500
SENSE
RG2
INPUT NULL
OUTPUT NULL
G = 100
+VS OUTPUT
1
2
5
6
7
3
4
8
16
15
12
11
10
14
13
9
TOP VIEW(Not to Scale)
AD624 SHORT TORG2 FORDESIREDGAIN
FOR GAINS OF 1000 SHORT RG1 TO PIN 12AND PINS 11 AND 13 TO RG2
METALIZATION PHOTOGRAPHContact factory for latest dimensions
Dimensions shown in inches and (mm).ORDERING GUIDE
Temperature Package PackageModel Range Description Option
AD624AD ā25Ā°C to +85Ā°C 16-Lead Ceramic DIP D-16AD624BD ā25Ā°C to +85Ā°C 16-Lead Ceramic DIP D-16AD624CD ā25Ā°C to +85Ā°C 16-Lead Ceramic DIP D-16AD624SD ā55Ā°C to +125Ā°C 16-Lead Ceramic DIP D-16AD624SD/883B* ā55Ā°C to +125Ā°C 16-Lead Ceramic DIP D-16AD624AChips ā25Ā°C to +85Ā°C DieAD624SChips ā25Ā°C to +85Ā°C Die
*See Analog Devicesā military data sheet for 883B specifications.
REV. C
AD624āTypical Characteristics20
00 20
15
5
5
10
1510SUPPLY VOLTAGE ā V
INP
UT
VO
LT
AG
E R
AN
GE
ā
V
+25C
Figure 1. Input Voltage Range vs.Supply Voltage, G = 1
8.0
00 20
6.0
2.0
5
4.0
1510SUPPLY VOLTAGE ā V
AM
PL
IFIE
R Q
UIE
SC
EN
T C
UR
RE
NT
ā m
A
Figure 4. Quiescent Current vs.Supply Voltage
16
020
4
2
50
8
6
10
12
14
1510INPUT VOLTAGE ā V
INP
UT
BIA
S C
UR
RE
NT
ā
nA
Figure 7. Input Bias Current vs. CMV
20
00 20
15
5
5
10
1510SUPPLY VOLTAGE ā V
OU
TP
UT
VO
LT
AG
E S
WIN
G ā
V
Figure 2. Output Voltage Swing vs.Supply Voltage
16
020
4
2
50
8
6
10
12
14
1510
SUPPLY VOLTAGE ā V
INP
UT
BIA
S C
UR
RE
NT
ā
nA
Figure 5. Input Bias Current vs.Supply Voltage
ā1
78.0
5
6
1.00
3
4
2
1
0
7.06.05.04.03.02.0WARM-UP TIME ā Minutes
V
OS
FR
OM
FIN
AL
VA
LU
E ā
V
Figure 8. Offset Voltage, RTI, TurnOn Drift
10 100 10k1k
30
20
0
10
LOAD RESISTANCE ā
OU
TP
UT
VO
LT
AG
E S
WIN
G ā
V p
-p
Figure 3. Output Voltage Swing vs.Load Resistance
40
ā40125
ā20
ā30
ā75
0
ā10
10
20
30
7525ā25TEMPERATURE ā C
INP
UT
BIA
S C
UR
RE
NT
ā n
A
ā125
Figure 6. Input Bias Current vs.Temperature
0
500
100
10
1
1 10 10M1M100k10k1k100FREQUENCY ā Hz
GA
IN ā
V/V
Figure 9. Gain vs. Frequency
ā4ā
REV. C
AD624
ā5ā
01 10 10M1M100k10k1k100
FREQUENCY ā Hz
ā100
ā80
ā60
ā40
CM
RR
ā d
B
ā120
ā140
ā20
G = 500
G = 1
G = 100
Figure 10. CMRR vs. Frequency RTI,Zero to 1k Source Imbalance
160
0100k
40
20
10
80
60
100
120
140
10k1k100FREQUENCY ā Hz
PO
WE
R S
UP
PL
Y R
EJE
CT
ION
ā d
B
G = 500
G = 100
G = 1
āVS = ā15V dc+ 1V p-p SINEWAVE
Figure 13. Negative PSRR vs.Frequency
Figure 16. Low Frequency VoltageNoise, G = 1 (System Gain = 1000)
30
20
0
10
FU
LL
-PO
WE
R R
ES
PO
NS
E ā
V p
-p
FREQUENCY ā Hz10k1k 100k 1M
G = 1, 100G = 500
G = 100G = 1000
BANDWIDTH LIMITED
-
Figure 11. Large Signal FrequencyResponse
VO
LT
NS
D ā
nV
/ H
z
0.1
100
1
10
1000
100k101 10k1k100FREQUENCY ā Hz
G = 1
G = 10
G = 100, 1000G = 1000
Figure 14. RTI Noise SpectralDensity vs. Gain
Figure 17. Low Frequency VoltageNoise, G = 1000 (System Gain =100,000)
160
0100k
40
20
10
80
60
100
120
140
10k1k100FREQUENCY ā Hz
PO
WE
R S
UP
PL
Y R
EJE
CT
ION
ā d
B
G = 500
G = 100
G = 1
āVS = ā15V dc+1V p-p SINEWAVE
Figure 12. Positive PSRR vs.Frequency
10
10k
100
1000
100k
100k10.1 10k10010FREQUENCY ā Hz
CU
RR
EN
T N
OIS
E S
PE
CT
RA
L D
EN
SIT
Y ā
fA
/ H
z
Figure 15. Input Current Noise
20
8 TO ā8
12 TO ā12
0
OUTPUTSTEP āV
4 TO ā4
ā4 TO 4
ā8 TO 8
ā12 TO 12
15105SETTLING TIME ā s
1%
1% 0.1% 0.01%
0.1% 0.01%
Figure 18. Settling Time, Gain = 1
REV. C
AD624
ā6ā
Figure 19. Large Signal PulseResponse and Settling Time, G = 1
Figure 22. Range Signal PulseResponse and Settling Time,G = 500
20
8 TO ā8
12 TO ā12
0
OUTPUTSTEP āV
4 TO ā4
ā4 TO 4
ā8 TO 8
ā12 TO 12
15105SETTLING TIME ā s
1%
1% 0.1%
0.01%0.1%
0.01%
Figure 20. Settling Time Gain = 100
20
8 TO ā8
12 TO ā12
0
OUTPUTSTEP āV
4 TO ā4
ā4 TO 4
ā8 TO 8
ā12 TO 12
15105SETTLING TIME ā s
0.1%
0.1%1%
1%
0.01%
0.01%
Figure 23. Settling Time Gain = 1000
Figure 21. Large Signal PulseResponse and Settling Time,G = 100
Figure 24. Large Signal PulseResponse and Settling Time,G = 1000
REV. C
AD624
ā7ā
AD624
+VS VOUT
10k1%
1k10T
10k1%
RG1
G = 100
G = 200
G = 500
RG2
āVS
2000.1%
100k1%
5000.1%
1k0.1%
INPUT20V p-p
Figure 25. Settling Time Test Circuit
THEORY OF OPERATIONThe AD624 is a monolithic instrumentation amplifier based ona modification of the classic three-op-amp instrumentationamplifier. Monolithic construction and laser-wafer-trimmingallow the tight matching and tracking of circuit components andthe high level of performance that this circuit architecture is ca-pable of.
A preamp section (Q1āQ4) develops the programmed gain bythe use of feedback concepts. Feedback from the outputs of A1and A2 forces the collector currents of Q1āQ4 to be constantthereby impressing the input voltage across RG.
The gain is set by choosing the value of RG from the equation,
Gain =
40 kRG
+ 1. The value of RG also sets the transconduct-
ance of the input preamp stage increasing it asymptotically tothe transconductance of the input transistors as RG is reducedfor larger gains. This has three important advantages. First, thisapproach allows the circuit to achieve a very high open loop gainof 3 Ć 108 at a programmed gain of 1000 thus reducing gainrelated errors to a negligible 3 ppm. Second, the gain bandwidthproduct which is determined by C3 or C4 and the input trans-conductance, reaches 25 MHz. Third, the input voltage noisereduces to a value determined by the collector current of theinput transistors for an RTI noise of 4 nV/āHz at G ā„ 500.
AD624
+VS
100
200
RG2
āVS
16.2k
+VS
1/2AD712
9.09k
G1, 100, 200
1k
1F
G500
100
1F
1.62M
āVS1F
16.2k
1.82k
5001/2
AD712
Figure 26. Noise Test Circuit
INPUT CONSIDERATIONSUnder input overload conditions the user will see RG + 100 Ī©and two diode drops (~1.2 V) between the plus and minusinputs, in either direction. If safe overload current under allconditions is assumed to be 10 mA, the maximum overloadvoltage is ~ Ā±2.5 V. While the AD624 can withstand this con-tinuously, momentary overloads of Ā±10 V will not harm thedevice. On the other hand the inputs should never exceed thesupply voltage.
The AD524 should be considered in applications that requireprotection from severe input overload. If this is not possible,external protection resistors can be put in series with the inputsof the AD624 to augment the internal (50 Ī©) protection resis-tors. This will most seriously degrade the noise performance.For this reason the value of these resistors should be chosen tobe as low as possible and still provide 10 mA of current limitingunder maximum continuous overload conditions. In selectingthe value of these resistors, the internal gain setting resistor andthe 1.2 volt drop need to be considered. For example, to pro-tect the device from a continuous differential overload of 20 Vat a gain of 100, 1.9 kĪ© of resistance is required. The internalgain resistor is 404 Ī©; the internal protect resistor is 100 Ī©.There is a 1.2 V drop across D1 or D2 and the base-emitterjunction of either Q1 and Q3 or Q2 and Q4 as shown in Figure27, 1400 Ī© of external resistance would be required (700 Ī© inseries with each input). The RTI noise in this case would be
4 KTRext +(4 nV / Hz)2 = 6.2 nV / Hz
50
1350A
I150A
C3
I250A
R5720k
R5620k
500
SENSE
+IN
VO
REFI4
50A200
100
4445
80.2
124
225.3
āIN
āVS
RG1 RG2
C4
VB
A2
R5210k
R5510k
A3
R5310k
R5410k
+VS
50
Q1, Q3 Q2,Q4
A1
Figure 27. Simplified Circuit of Amplifier; Gain Is Definedas (R56 + R57)/(RG) + 1. For a Gain of 1, RG Is an OpenCircuit.
INPUT OFFSET AND OUTPUT OFFSETVoltage offset specifications are often considered a figure ofmerit for instrumentation amplifiers. While initial offset maybe adjusted to zero, shifts in offset voltage due to temperaturevariations will cause errors. Intelligent systems can often correctfor this factor with an autozero cycle, but there are many small-signal high-gain applications that donāt have this capability.
Voltage offset and offset drift each have two components; inputand output. Input offset is that component of offset that is
REV. C
AD624
ā8ā
directly proportional to gain i.e., input offset as measured atthe output at G = 100 is 100 times greater than at G = 1.Output offset is independent of gain. At low gains, output offsetdrift is dominant, while at high gains input offset drift domi-nates. Therefore, the output offset voltage drift is normallyspecified as drift at G = 1 (where input effects are insignificant),while input offset voltage drift is given by drift specification at ahigh gain (where output offset effects are negligible). All input-related numbers are referred to the input (RTI) which is to saythat the effect on the output is āGā times larger. Voltage offsetvs. power supply is also specified at one or more gain settingsand is also RTI.
By separating these errors, one can evaluate the total error inde-pendent of the gain setting used. In a given gain configura-tion both errors can be combined to give a total error referred tothe input (R.T.I.) or output (R.T.O.) by the following formula:
Total Error R.T.I. = input error + (output error/gain)
Total Error R.T.O. = (Gain Ć input error) + output error
As an illustration, a typical AD624 might have a +250 ĀµV out-put offset and a ā50 ĀµV input offset. In a unity gain configura-tion, the total output offset would be 200 ĀµV or the sum of thetwo. At a gain of 100, the output offset would be ā4.75 mVor: +250 ĀµV + 100 (ā50 ĀµV) = ā4.75 mV.
The AD624 provides for both input and output offset adjust-ment. This optimizes nulling in very high precision applicationsand minimizes offset voltage effects in switched gain applica-tions. In such applications the input offset is adjusted first at thehighest programmed gain, then the output offset is adjusted atG = 1.
GAINThe AD624 includes high accuracy pretrimmed internalgain resistors. These allow for single connection program-ming of gains of 1, 100, 200 and 500. Additionally, a varietyof gains including a pretrimmed gain of 1000 can be achievedthrough series and parallel combinations of the internal resis-tors. Table I shows the available gains and the appropriatepin connections and gain temperature coefficients.
The gain values achieved via the combination of internalresistors are extremely useful. The temperature coefficient of thegain is dependent primarily on the mismatch of the temperaturecoefficients of the various internal resistors. Tracking of theseresistors is extremely tight resulting in the low gain TCs shownin Table I.
If the desired value of gain is not attainable using the inter-nal resistors, a single external resistor can be used to achieveany gain between 1 and 10,000. This resistor connected between
AD624G = 100
RG2
āVS
OUTPUTSIGNALCOMMON
VOUT
10kāINPUT
RG1
G = 200
G = 500
+INPUT
INPUTOFFSETNULL
+VS
Figure 28. Operating Connections for G = 200
Table I.
TemperatureGain Coefficient Pin 3(Nominal) (Nominal) to Pin Connect Pins
1 ā0 ppm/Ā°C ā ā100 ā1.5 ppm/Ā°C 13 ā125 ā5 ppm/Ā°C 13 11 to 16137 ā5.5 ppm/Ā°C 13 11 to 12186.5 ā6.5 ppm/Ā°C 13 11 to 12 to 16200 ā3.5 ppm/Ā°C 12 ā250 ā5.5 ppm/Ā°C 12 11 to 13333 ā15 ppm/Ā°C 12 11 to 16375 ā0.5 ppm/Ā°C 12 13 to 16500 ā10 ppm/Ā°C 11 ā624 ā5 ppm/Ā°C 11 13 to 16688 ā1.5 ppm/Ā°C 11 11 to 12; 13 to 16831 +4 ppm/Ā°C 11 16 to 121000 0 ppm/Ā°C 11 16 to 12; 13 to 11
Pins 3 and 16 programs the gain according to the formula
RG = 40k
G ā1(see Figure 29). For best results RG should be a precision resis-tor with a low temperature coefficient. An external RG affects bothgain accuracy and gain drift due to the mismatch between it andthe internal thin-film resistors R56 and R57. Gain accuracy isdetermined by the tolerance of the external RG and the absoluteaccuracy of the internal resistors (Ā±20%). Gain drift is determinedby the mismatch of the temperature coefficient of RG and the tem-perature coefficient of the internal resistors (ā15 ppm/Ā°C typ),and the temperature coefficient of the internal interconnections.
AD624
RG2
āVS
REFERENCE
VOUT
āINPUT
RG1
2.105k
+INPUT
+VS
OR
1.5k
1k
G = + 1 = 20 20%40.0002.105
Figure 29. Operating Connections for G = 20
The AD624 may also be configured to provide gain in the out-put stage. Figure 30 shows an H pad attenuator connected tothe reference and sense lines of the AD624. The values of R1,R2 and R3 should be selected to be as low as possible to mini-mize the gain variation and reduction of CMRR. Varying R2will precisely set the gain without affecting CMRR. CMRR isdetermined by the match of R1 and R3.
AD624G = 100
RG2
āVS
VOUT
āINPUT
RG1
G = 200
G = 500
+INPUT
+VS
RL
R36k
R25k
R16k
(R2||20k) + R1 + R3)
(R2||20k)G =
(R1 + R2 + R3) || RL 2k
Figure 30. Gain of 2500
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AD624
ā9ā
NOISEThe AD624 is designed to provide noise performance near thetheoretical noise floor. This is an extremely important designcriteria as the front end noise of an instrumentation amplifier isthe ultimate limitation on the resolution of the data acquisitionsystem it is being used in. There are two sources of noise in aninstrument amplifier, the input noise, predominantly generatedby the differential input stage, and the output noise, generatedby the output amplifier. Both of these components are presentat the input (and output) of the instrumentation amplifier. Atthe input, the input noise will appear unaltered; the outputnoise will be attenuated by the closed loop gain (at the output,the output noise will be unaltered; the input noise will be ampli-fied by the closed loop gain). Those two noise sources must beroot sum squared to determine the total noise level expected atthe input (or output).
The low frequency (0.1 Hz to 10 Hz) voltage noise due to theoutput stage is 10 ĀµV p-p, the contribution of the input stage is0.2 ĀµV p-p. At a gain of 10, the RTI voltage noise would be
1 ĀµV p-p,
10G
2
+ 0.2( )2. The RTO voltage noise would be
10.2 ĀµV p-p,
102 + 0.2 G( )( )2. These calculations hold for
applications using either internal or external gain resistors.
INPUT BIAS CURRENTSInput bias currents are those currents necessary to bias the inputtransistors of a dc amplifier. Bias currents are an additionalsource of input error and must be considered in a total errorbudget. The bias currents when multiplied by the source resis-tance imbalance appear as an additional offset voltage. (What isof concern in calculating bias current errors is the change in biascurrent with respect to signal voltage and temperature.) Inputoffset current is the difference between the two input bias cur-rents. The effect of offset current is an input offset voltage whosemagnitude is the offset current times the source resistance.
AD624
āVS
+VS
LOAD
TOPOWERSUPPLYGROUND
a. Transformer Coupled
AD624
āVS
+VS
LOAD
TOPOWERSUPPLYGROUND
b. Thermocouple
AD624
āVS
+VS
LOAD
TOPOWERSUPPLYGROUND
c. AC-Coupled
Figure 31. Indirect Ground Returns for Bias Currents
Although instrumentation amplifiers have differential inputs,there must be a return path for the bias currents. If this is notprovided, those currents will charge stray capacitances, causingthe output to drift uncontrollably or to saturate. Therefore,when amplifying āfloatingā input sources such as transformersand thermocouples, as well as ac-coupled sources, there muststill be a dc path from each input to ground, (see Figure 31).
COMMON-MODE REJECTIONCommon-mode rejection is a measure of the change in outputvoltage when both inputs are changed by equal amounts. Thesespecifications are usually given for a full-range input voltagechange and a specified source imbalance. āCommon-ModeRejection Ratioā (CMRR) is a ratio expression while āCommon-Mode Rejectionā (CMR) is the logarithm of that ratio. Forexample, a CMRR of 10,000 corresponds to a CMR of 80 dB.
In an instrumentation amplifier, ac common-mode rejection isonly as good as the differential phase shift. Degradation of accommon-mode rejection is caused by unequal drops acrossdiffering track resistances and a differential phase shift due tovaried stray capacitances or cable capacitances. In many appli-cations shielded cables are used to minimize noise. This tech-nique can create common-mode rejection errors unless theshield is properly driven. Figures 32 and 33 shows active dataguards which are configured to improve ac common-moderejection by ābootstrappingā the capacitances of the inputcabling, thus minimizing differential phase shift.
AD624RG2
āVS
REFERENCE
VOUT
āINPUT
+INPUT
+VS
G = 200
AD711
100
Figure 32. Shield Driver, G ā„ 100
AD624
RG1
āVS
REFERENCE
VOUT
āINPUT
+INPUT
+VS
āVS
AD712
100
100
RG2
Figure 33. Differential Shield Driver
REV. C
AD624
ā10ā
GROUNDINGMany data-acquisition components have two or more groundpins which are not connected together within the device. Thesegrounds must be tied together at one point, usually at the sys-tem power supply ground. Ideally, a single solid ground wouldbe desirable. However, since current flows through the groundwires and etch stripes of the circuit cards, and since these pathshave resistance and inductance, hundreds of millivolts can begenerated between the system ground point and the data acqui-sition components. Separate ground returns should be providedto minimize the current flow in the path from the most sensitivepoints to the system ground point. In this way supply currentsand logic-gate return currents are not summed into the samereturn path as analog signals where they would cause measure-ment errors (see Figure 34).
OUTPUTREFERENCE
ANALOGGROUND*
*IF INDEPENDENT, OTHERWISE RETURN AMPLIFIER REFERENCE TO MECCA AT ANALOG P.S. COMMON
SIGNALGROUND
AD574ADIGITALDATAOUTPUT
+
1F
0.1F 1F1F
DIGCOM
0.1F
0.1F
0.1F
AD624SAMPLE
AND HOLD
AD583
ANALOG P.S.+15V C ā15V +5V
DIGITAL P.S.C
Figure 34. Basic Grounding Practice
Since the output voltage is developed with respect to the poten-tial on the reference terminal an instrumentation amplifier cansolve many grounding problems.
SENSE TERMINALThe sense terminal is the feedback point for the instrumentamplifierās output amplifier. Normally it is connected to theinstrument amplifier output. If heavy load currents are to bedrawn through long leads, voltage drops due to current flowingthrough lead resistance can cause errors. The sense terminal canbe wired to the instrument amplifier at the load thus putting theIxR drops āinside the loopā and virtually eliminating this errorsource.
AD624
V+
OUTPUTCURRENTBOOSTER
Vā
VIN+
VINā
X1
RL
(REF)
(SENSE)
Figure 35. AD624 Instrumentation Amplifier with OutputCurrent Booster
Typically, IC instrumentation amplifiers are rated for a fullĀ±10 volt output swing into 2 kĪ©. In some applications, how-ever, the need exists to drive more current into heavier loads.Figure 35 shows how a current booster may be connected
āinside the loopā of an instrumentation amplifier to provide therequired current without significantly degrading overall perfor-mance. The effects of nonlinearities, offset and gain inaccuraciesof the buffer are reduced by the loop gain of the IA outputamplifier. Offset drift of the buffer is similarly reduced.
REFERENCE TERMINALThe reference terminal may be used to offset the output by upto Ā±10 V. This is useful when the load is āfloatingā or does notshare a ground with the rest of the system. It also provides adirect means of injecting a precise offset. It must be remem-bered that the total output swing is Ā±10 volts, from ground, tobe shared between signal and reference offset.
AD624
VIN+
VINā
REF
SENSE
LOAD
AD711
āVS
+VS
VOFFSET
Figure 36. Use of Reference Terminal to Provide OutputOffset
When the IA is of the three-amplifier configuration it is neces-sary that nearly zero impedance be presented to the referenceterminal. Any significant resistance, including those caused byPC layouts or other connection techniques, which appearsbetween the reference pin and ground will increase the gain ofthe noninverting signal path, thereby upsetting the common-mode rejection of the IA. Inadvertent thermocouple connectionscreated in the sense and reference lines should also be avoidedas they will directly affect the output offset voltage and outputoffset voltage drift.
In the AD624 a reference source resistance will unbalance theCMR trim by the ratio of 10 kĪ©/RREF. For example, if the refer-ence source impedance is 1 Ī©, CMR will be reduced to 80 dB(10 kĪ©/1 Ī© = 80 dB). An operational amplifier may be used toprovide that low impedance reference point as shown in Figure36. The input offset voltage characteristics of that amplifier willadd directly to the output offset voltage performance of theinstrumentation amplifier.
An instrumentation amplifier can be turned into a voltage-to-current converter by taking advantage of the sense and referenceterminals as shown in Figure 37.
AD624
+INPUT
REF
R1+VXā
SENSE
LOAD
AD711
A2
IL
āINPUT
40.000RG
1 +IL = =VXR1
VINR1
Figure 37. Voltage-to-Current Converter
REV. C
AD624
ā11ā
By establishing a reference at the ālowā side of a current settingresistor, an output current may be defined as a function of inputvoltage, gain and the value of that resistor. Since only a smallcurrent is demanded at the input of the buffer amplifier A2, theforced current IL will largely flow through the load. Offset anddrift specifications of A2 must be added to the output offset anddrift specifications of the IA.
PROGRAMMABLE GAINFigure 38 shows the AD624 being used as a software program-mable gain amplifier. Gain switching can be accomplished withmechanical switches such as DIP switches or reed relays. Itshould be noted that the āonā resistance of the switch in serieswith the internal gain resistor becomes part of the gain equationand will have an effect on gain accuracy.
A significant advantage in using the internal gain resistors in aprogrammable gain configuration is the minimization of thermo-couple signals which are often present in multiplexed dataacquisition systems.
If the full performance of the AD624 is to be achieved, the usermust be extremely careful in designing and laying out his circuitto minimize the remaining thermocouple signals.
The AD624 can also be connected for gain in the output stage.Figure 39 shows an AD547 used as an active attenuator in theoutput amplifierās feedback loop. The active attenuation pre-sents a very low impedance to the feedback resistors thereforeminimizing the common-mode rejection ratio degradation.
Another method for developing the switching scheme is to use aDAC. The AD7528 dual DAC which acts essentially as a pair ofswitched resistive attenuators having high analog linearity and
symmetrical bipolar transmission is ideal in this application. Themultiplying DACās advantage is that it can handle inputs ofeither polarity or zero without affecting the programmed gain.The circuit shown uses an AD7528 to set the gain (DAC A) andto perform a fine adjustment (DAC B).
VDD GND
225.3
124
4445.7
80.2
5016
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
10k
20k VB 20k
10k
10k
50
āVS
+VS
1F35V
āIN
+IN
10k
10k
INPUTOFFSET
NULL
OUTPUTOFFSETNULL
10k
TO āV
(+INPUT)
(āINPUT)
VOUT
39.2k
WRA4A3A2A1
VSS
1k
10pF
+VS
28.7k
316k
1k
1kāVS
AD624
AD7590
AD711
Figure 39. Programmable Output Gain
225.3
124
4445.7
80.2
50
G = 100K1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
10k
20k VB 20k
10k
10k
50
āVS
+VS
1F35V
āIN
+IN
R210k
R110k
INPUTOFFSET
TRIM
OUTPUTOFFSETTRIM
RELAYSHIELDS
G = 200K2
G = 500K3
D1 D2 D3
Y0
K2 K3
74LS138DECODER
7407NBUFFERDRIVER
A
BY1
Y2
INPUTSGAIN
RANGE
+5V
10F
C1 C2
K1 ā K3 =THERMOSEN DM2C4.5V COILD1 ā D3 = IN4148
ANALOGCOMMON
GAIN TABLEA B GAIN0 0 1000 1 5001 0 2001 1 1
LOGICCOMMON
K1
OUT
10k
+5V
AD624
NC
Figure 38. Gain Programmable Amplifier
REV. C
AD624
ā12ā
225.3
124
4445.7
80.2
50
VB
50
20k 10k
10k
10k
AD624G = 100
G = 200
G = 500
RG1RG2
āINPUT(+INPUT)
VOUT
20k 10k
+INPUT(āINPUT)
AD7528
1/2AD712
256:1DATA
INPUTS
CS
WR
DAC A/DAC B
DB0
DB7
+VS
DAC A
DAC B
1/2AD712
Figure 40. Programmable Output Gain Using a DAC
AUTOZERO CIRCUITSIn many applications it is necessary to provide very accuratedata in high gain configurations. At room temperature the offseteffects can be nulled by the use of offset trimpots. Over theoperating temperature range, however, offset nulling becomes aproblem. The circuit of Figure 41 shows a CMOS DAC operat-ing in the bipolar mode and connected to the reference terminalto provide software controllable offset adjustments.
AD624
āVS
+VS
VOUT
G = 100
G = 200
G = 500
RG1
RG2
+INPUT
āINPUT
DATAINPUTS
CS
WR
MSB
LSB
+VS
AD7524
C1OUT1
OUT2 1/2AD712
RFB
+VS
R320k
R410k
R520k
āVS
R65k āVS
GND
AD589
39k VREF
1/2AD712
Figure 41. Software Controllable Offset
In many applications complex software algorithms for autozeroapplications are not available. For these applications Figure 42provides a hardware solution.
AD624
āVS
+VS
VOUT
RG1
RG2 1k
12 11
9 100.1F LOWLEAKAGE
CH
15 16
14
13
VSS
VDD
GND
A1 A2 A3 A4
AD7510DIKD
200s
ZERO PULSE
AD542
Figure 42. Autozero Circuit
The microprocessor controlled data acquisition system shown inFigure 43 includes includes both autozero and autogain capabil-ity. By dedicating two of the differential inputs, one to groundand one to the A/D reference, the proper program calibrationcycles can eliminate both initial accuracy errors and accuracyerrors over temperature. The autozero cycle, in this application,converts a number that appears to be ground and then writesthat same number (8 bit) to the AD624 which eliminates thezero error since its output has an inverted scale. The autogaincycle converts the A/D reference and compares it with full scale.A multiplicative correction factor is then computed and appliedto subsequent readings.
RG1
RG2
AD624
1/2AD712
AD583
AGND
VIN
VREF
AD574AAD7507
EN A1A2A0
ADDRESS BUS
āVREF
5k
10k
20k
LATCH
20k
1/2AD712
CONTROL
DECODE
AD7524
MICRO-PROCESSOR
Figure 43. Microprocessor Controlled Data AcquisitionSystem
REV. C
AD624
ā13ā
WEIGH SCALEFigure 44 shows an example of how an AD624 can be used tocondition the differential output voltage from a load cell. The10% reference voltage adjustment range is required to accom-modate the 10% transducer sensitivity tolerance. The highlinearity and low noise of the AD624 make it ideal for use inapplications of this type particularly where it is desirable tomeasure small changes in weight as opposed to the absolutevalue. The addition of an autogain/autotare cycle will enable thesystem to remove offsets, gain errors, and drifts making possibletrue 14-bit performance.
G100
G200
G500
RG2
AD624
+INPUT
āINPUT
R53M
R6100kZERO ADJUST(COARSE)
A/DCONVERTER
+10V FULLSCALE
OUTPUT
REFERENCE
SENSE
GAIN = 500R410kZEROADJUST(FINE)
100
R310
+15V
R130k
NOTE 210V 10%
R220k
R310k
SCALEERRORADJUST
AD584
+10V
+5V
+2.5V
VBG
TRANSDUCERSEE NOTE 1
NOTES1. LOAD CELL TEDEA MODEL 1010 10kG. OUTPUT 2mV/V10%.2. R1, R2 AND R3 SELECTED FOR AD584. OUTPUT 10V 10%.
+15V
AD707 2N2219
R7100k
OUT
Figure 44. AD624 Weigh Scale Application
AC BRIDGEBridge circuits which use dc excitation are often plagued byerrors caused by thermocouple effects, l/f noise, dc drifts in theelectronics, and line noise pickup. One way to get around theseproblems is to excite the bridge with an ac waveform, amplifythe bridge output with an ac amplifier, and synchronouslydemodulate the resulting signal. The ac phase and amplitudeinformation from the bridge is recovered as a dc signal at theoutput of the synchronous demodulator. The low frequencysystem noise, dc drifts, and demodulator noise all get mixed tothe carrier frequency and can be removed by means of a low-pass filter. Dynamic response of the bridge must be traded offagainst the amount of attenuation required to adequately sup-press these residual carrier components in the selection of thefilter.
Figure 45 is an example of an ac bridge system with the AD630used as a synchronous demodulator. The oscilloscope photo-graph shows the results of a 0.05% bridge imbalance caused bythe 1 Meg resistor in parallel with one leg of the bridge. The toptrace represents the bridge excitation, the upper middle trace isthe amplified bridge output, the lower-middle trace is the out-put of the synchronous demodulator and the bottom trace is thefiltered dc system output.
This system can easily resolve a 0.5 ppm change in bridgeimpedance. Such a change will produce a 6.3 mV change in thelow-pass filtered dc output, well above the RTO drifts and noise.
The AC-CMRR of the AD624 decreases with the frequency ofthe input signal. This is due mainly to the package-pin capaci-tance associated with the AD624ās internal gain resistors. IfAC-CMRR is not sufficient for a given application, it can betrimmed by using a variable capacitor connected to the amplifierāsRG2 pin as shown in Figure 45.
AD624C
āVS
+VS
VOUT
G = 1000
RG1
RG2
10k
1kHzBRIDGE
EXCITATION
1M
1k
1k1k
1k
4ā49pFCERAMIC ac
BALANCECAPACITOR
āV
10k
B
10k
5k
2.5k
āVS
PHASESHIFTER
AD630
MODULATEDOUTPUTSIGNAL
+VS
MODULATIONINPUT
CARRIERINPUT
2.5k
B
A
COMP
Figure 45. AC Bridge
0V
0V
0V
0V
BRIDGE EXCITATION(20V/div) (A)
AMPLIFIED BRIDGEOUTPUT (5V/div) (B)
DEMODULATED BRIDGEOUTPUT (5V/div) (C)
FILTER OUTPUT2V/div) (D)2V
Figure 46. AC Bridge Waveforms
REV. C
AD624
ā14ā
AD624C
āVS
+VS
G = 100
RG1
RG2
10k
350
+10V
14-BITADC
0 TO 2VF.S.350
350
350
Figure 47. Typical Bridge Application
Table II. Error Budget Analysis of AD624CD in Bridge Application
Effect on Effect onAbsolute Absolute Effect
AD624C Accuracy Accuracy onError Source Specifications Calculation at TA = +25C at TA = +85C Resolution
Gain Error Ā±0.1% Ā±0.1% = 1000 ppm 1000 ppm 1000 ppm āGain Instability 10 ppm (10 ppm/Ā°C) (60Ā°C) = 600 ppm _ 600 ppm āGain Nonlinearity Ā±0.001% Ā±0.001% = 10 ppm ā ā 10 ppmInput Offset Voltage Ā±25 ĀµV, RTI Ā±25 ĀµV/20 mV = Ā±1250 ppm 1250 ppm 1250 ppm āInput Offset Voltage Drift Ā±0.25 ĀµV/Ā°C (Ā±0.25 ĀµV/Ā°C) (60Ā°C)= 15 ĀµV
15 ĀµV/20 mV = 750 ppm ā 750 ppm āOutput Offset Voltage1 Ā±2.0 mV Ā±2.0 mV/20 mV = 1000 ppm 1000 ppm 1000 ppm āOutput Offset Voltage Drift1 Ā±10 ĀµV/Ā°C (Ā±10 ĀµV/Ā°C) (60Ā°C) = 600 ĀµV
600 ĀµV/20 mV = 300 ppm ā 300 ppm āBias CurrentāSource Ā±15 nA (Ā±15 nA)(5 Ī© ) = 0.075 ĀµV
Imbalance Error 0.075 ĀµV/20mV = 3.75 ppm 3.75 ppm 3.75 ppm āOffset CurrentāSource Ā±10 nA (Ā±10 nA)(5 Ī©) = 0.050 ĀµV
Imbalance Error 0.050 ĀµV/20 mV = 2.5 ppm 2.5 ppm 2.5 ppm āOffset CurrentāSource Ā±10 nA (10 nA) (175 Ī©) = 1.75 ĀµV
Resistance Error 1.75 ĀµV/20 mV = 87.5 ppm 87.5 ppm 87.5 ppm āOffset CurrentāSource Ā±100 pA/Ā°C (100 pA/Ā°C) (175 Ī©) (60Ā°C) = 1 ĀµV
ResistanceāDrift 1 ĀµV/20 mV = 50 ppm ā 50 ppm āCommon-Mode Rejection 115 dB 115 dB = 1.8 ppm Ć 5 V = 9 ĀµV
5 V dc 9 ĀµV/20 mV = 444 ppm 450 ppm 450 ppm āNoise, RTI
(0.1 Hzā10 Hz) 0.22 ĀµV p-p 0.22 ĀµV p-p/20 mV = 10 ppm _ ā 10 ppm
Total Error 3793.75 ppm 5493.75 ppm 20 ppm
NOTE1Output offset voltage and output offset voltage drift are given as RTI figures.
For a comprehensive study of instrumentation amplifier designand applications, refer to the Instrumentation Amplifier ApplicationGuide, available free from Analog Devices.
ERROR BUDGET ANALYSISTo illustrate how instrumentation amplifier specifications areapplied, we will now examine a typical case where an AD624 isrequired to amplify the output of an unbalanced transducer.Figure 47 shows a differential transducer, unbalanced by ā5 Ī©,supplying a 0 to 20 mV signal to an AD624C. The output of theIA feeds a 14-bit A to D converter with a 0 to 2 volt input volt-age range. The operating temperature range is ā25Ā°C to +85Ā°C.Therefore, the largest change in temperature āT within theoperating range is from ambient to +85Ā°C (85Ā°C ā 25Ā°C =60Ā°C.)
In many applications, differential linearity and resolution are ofprime importance. This would be so in cases where the absolutevalue of a variable is less important than changes in value. Inthese applications, only the irreducible errors (20 ppm =0.002%) are significant. Furthermore, if a system has an intelli-gent processor monitoring the A to D output, the addition of anautogain/autozero cycle will remove all reducible errors and mayeliminate the requirement for initial calibration. This will alsoreduce errors to 0.002%.
REV. C
AD624
ā15ā
OUTLINE DIMENSIONSDimensions shown in inches and (mm).
Side-Brazed Solder Lid Ceramic DIP(D-16)
16
1 8
9
0.080 (2.03) MAX
0.310 (7.87)0.220 (5.59)
PIN 1
0.005 (0.13) MIN
0.100(2.54)BSC
SEATINGPLANE
0.023 (0.58)0.014 (0.36)
0.060 (1.52)0.015 (0.38)
0.200 (5.08)MAX
0.200 (5.08)0.125 (3.18)
0.070 (1.78)0.030 (0.76)
0.150(3.81)MAX
0.840 (21.34) MAX
0.320 (8.13)0.290 (7.37)
0.015 (0.38)0.008 (0.20)
ā16ā
C80
5dā0
ā7/9
9P
RIN
TE
D IN
U.S
.A.