The Only ASIC Design Flow FPGA

A c t e l ’ s P r o A S I C F a m i l y

• ASIC-like Design Flow-Easy Timing Closure-Familiar Design Tools

• Nonvolatile and Reprogrammable

• Low Power Consumption

• Flexible Embedded User Memory-Built in FIFO control logic

• JTAG/IEEE 1149.1 Compliant

• High Performance Routing-100% Automatic Place and Route

at 100% utilization-Fix Pins at >90% utilization

H i g h D e n s i t yWith densities ranging from 98,000to 473,000 gates, 200MHz system performance, and up to 65kbits of embedded SRAM memory,Actel’s ProASIC™ 500K family ofprogrammable logic delivers highdensity programmable logic solu-tions. Using a .25µ standardCMOS/Flash process, ProASIC500K devices combine high performance and low power with nonvolatility and reprogrammability.Combining industry standard ASICor FPGA design methodologies andtools with easy IP re-use ProASIC500K devices offer true reprogram-mable system integration solutions.

H i g h P e r f o r m a n c eA r c h i t e c t u r eBased on .25µ Flash technology thatallows for performance enhancingarchitectural innovations, the smallsize of the Flash cell allows more programmable elements to be addedinto the routing, resulting in lowresistance and low capacitance rout-ing segments. These segments offer

predictable performance, improvedutilization, and greater routing effi-ciency. The very fine-grained logicdrastically improves logic utilizationand predictability. The ProASIC500K devices also offer the abilityto fix pins at greater than 90% logicutilization, resulting in easier systemdesign and faster design iteration.ProASIC 500K devices are the optimal programmable solution to allow designers to easily meet performance goals.

L o w P o w e rAlong with the high performancecomes low power consumption. Withthe inherent efficiency of the routingstructure and the architecture of thelogic cell, ProASIC 500K devicesconsume 1/2 the power compared to SRAM based FPGAs. This lowerpower consumption results in asignificant reduction in overall

system cost.

T h e F l a s h A d v a n t a g e

0

100

200

300

400

500

600

700

800

900

1000

Frequency (MHz)

Pow

er C

onsu

mpt

ion

(mW

)

20 30 40 50 60 70 80 90 100 120

SRAM FPGAProASIC

110 instances of 16-bit binary counters

SEL 1 SEL 2

SWITCHFLASH

WORD LINE

ProASIC Flash Switch

ProASIC Power Consumption

N o n v o l a t i l e a n d R e p r o g r a m m a b l eBecause the ProASIC 500K devicesare nonvolatile, they retain theirconfiguration for a period exceedingthe requirements of most sysyemlifetimes. This eliminates the cost ofa boot PROM and the associatedboard space. Nonvolatile also meanslive on power up, so there is noperiod of nonfunctionality whileconfiguration data is being down-loaded from an external device.Additionally, ProASIC devices allowdesigners the flexibility to repro-gram their devices if design changesare necessary. As they are live atpower-up, ProASIC devices mayimplement the logic to control thepower-up sequencing of other partson the board.

D e s i g n S e c u r i t yWith the increasing complexity anddensity of devices, design security is a growing concern. ProASIC 500Kdevices offer an unprecedented levelof design security. Without a startupbitstream, there is no possibility ofthe device’s configuration data beingintercepted. The devices also contain aread-protect security mechanism thatprevents the programming contentfrom being read out of the device.This read-protect mechanism can-not be cleared unless the entiredevice is erased.

I P R e - U s e With increasing time-to-marketpressures, designers do not have the luxury of developing every function from scratch. Design re-use is an important factor inmeeting productivity goals. Due

to the ProASIC 500K family’s ASIC methodology and gate array-like architecture, bi-directional portability of functional blocks and commercially available IP betweenASICs and ProASIC is easily achieved.

A S I C a n d F P G A D e s i g n F l o w s ProASIC devices work equally well with ASIC and FPGA methodologies. Designers whowork in an FPGA design flow cantake advantage of the ease of useand fast run times they have cometo expect. ASIC designers willappreciate the high degree of control and easy integration intotheir existing design environment.

Because of the architecture, ProASIC500K devices can use the sameVHDL and Verilog HDL descriptionsthat are targeted for gate arrays andstandard cells, freeing the designerfrom the limitations imposed uponHDL by some FPGA architectures.Additionally, standard ASIC toolsare supported, protecting the design-ers’ investment in tools and trainingwhile streamlining the design environment. As a result, the designteam can focus on getting the designto market faster.

Compact Flash switches configurethe chip functionality, the associatedrouting and clocking, and theunderlying logic cell that providesthe programmable gates. Each switch consists of an NMOS transistor combined with a Flashmemory cell and is controlled by acommon floating gate, resulting in higher performance with lower power consumption.

ProASIC A500K130 Die

Actual Size

L o g i c T i l e sThe small Flash switches makes itpossible to utilize a fine-grained logiccell, resulting in better logic utiliza-tion. The basic logic tile consists of aprogrammable 3-input, 1-outputcell. With the ability to programeach input for signal inversion, thewasteful usage of cells as inverters iseliminated. Virtually any 3 inputcombinational logic function can beprogrammed, including flip-flops.This provides a great deal of flexibili-ty, allowing a programming rangefrom 100% combinatorial to 100%sequential. Through the program-ming of the local switch matrix, thecell is configured and combinedwith adjacent cells to form largerlogic functions. Similar to a sea-of-gates gate array architecture, thebasic logic tiles are stepped andrepeated in the horizontal and vertical directions to create a programmable Sea-of-Tiles™.

R o u t i n g R e s o u r c e sThe interconnect routing resourcesare organized in four hierarchicallevels, providing high performancewith routing flexibility. This hierar-chical routing structure providesoptimal place and route solutionsfor varying design styles and application types. The four levels of routing networks are as follows:

• Ultra Fast Local resources are high speed dedicated lines thatallow a direct connection from theoutput of every tile to I/O buffers,memory blocks, or the eight surrounding tiles.

• Efficient Long Line resources varyin length from 1, 2, or 4 tiles andprovide routing for greater distanceand higher fanout connections.

• High Speed Bus resources run vertically and horizontally across achip. They are able to travel acrossthe chip with minimal delay andcan be used for busses, datapathfunctions, or very high fanout nets.

• High Performance Global networks are used to distributeclocks, resets, and other netsrequiring high fanout with minimal delay and skew.

P r o A S I C A r c h i t e c t u r e

A Te c h n o l o g y o f I n n o v a t i o n

PAD RING

PAD RING

PAD

RING

I/O R

ING

I/O RING0

1 0

1(long)

(local)

Data

CLK

Set/Reset

ProASIC Logic Tile

High Speed Bus Resource

E m b e d d e d Tw o - P o r t S R A MAs chip densities increase, embeddedand dedicated memories becomeessential. The ProASIC 500Kdevices provide up to 65k bits ofembedded two-port SRAMs.Depending on the device, availablememory ranges from 6 to 28 blocksthat can support a variety of possiblememory configurations. Each blockcontains a 256-word deep by 9-bitwide memory. With every block,there is the option to program it asan independent memory, or com-bine it with other blocks to formlarger, more complex memories. Eachmemory block can be configured as synchronous or asynchronous, FIFO or SRAM. In addition, the memory blocks include hardwireddecoder logic, I/O circuits, parity generation or detection circuits,FIFO flags generation logic, andtiming and control circuits to minimize external logic gate countand complexity.

P r o g r a m m a b l e I / O sThe ProASIC 500K devices providefully configurable I/Os for greaterflexibility and performance. Eachpad can be programmed as aninput, an output, a three-state driver, or a bi-directional buffer.

Additional programming optionsinclude pull-up resistors and selectable drive and slew rates thatenable close matching to a widerange of bus interface conditions.The cells are programmed for LVCMOS or 3.3V PCI interfacespecifications. ProASIC 500Kdevices provide the capability toindividually select each input/outputdevice to interface with either 2.5Vor 3.3V components.

Logic Cell

1 Tile Long2 Tiles Long4 Tiles Long

1 Tile Long2 Tiles Long4 Tiles Long

Logic Tile

LL L L L L

LL L L L L

LL L L L L

LL L L L L

LL L L L L

PAD RING

PAD

RING

GlobalPads

GlobalPads

High Performace

PAD RING

I/O R

ING

I/O RING

Global Network

Ultra Fast Local andEfficient Long Line Resources

High Performance Global Networks

Actel’s ProASIC 500K devices aresupported by ASICmaster™ andMEMORYmaster™ software, as wellas third party CAE tools, offeringdesigners an open design environ-ment. ProASIC devices work equallywell in ASIC and FPGA designenvironments, allowing designers toleverage their existing design tools.

A S I C m a s t e rASICmaster is an automatic place and route tool that runs on SunOS®, Solaris®, and HP-UX®, as well as on Windows® NT™.ASICmaster accepts standard ASICformatted netlists and performstiming-driven place and route.Incremental place and route is supported for ASIC-like ECO(Engineering Change Orders) capability. ASICmaster can be used as a push button tool, or as afully user controlled process.ASICmaster also includes a powerestimator and provides back annotat-ed delay information for simulation or static timing analysis.

M E M O R Y m a s t e rMEMORYmaster is a tool that automatically generates RAMS andFIFOs according to configurationoptions set by the designer. Thedesigner has the ability to select thedepth and width, synchronous orasynchronous functionality of theports, and usage of parity generationor check. If it is a synchronous readport, the designer can choose whetherthe output is pipelined or transparent.MEMORYmaster also generates a constraints file that contains placement information for created memory. Simulation models for allthe configurations are provided in the design kit delivered on theASICmaster CD.

D e s i g n To o l s

Design Creation/Verification

Design Implementation

Synthesis Tool

High-LevelDescription

(Verilog or VHDL)

ASICmaster(P&R Tool)

P&R UserConstraints

Simulation(mixed-level,

structural)

SynthesisLibrary

Programming

SiliconSculptor

Silicon Explorer II

TimingLibraries

SimulationLibrary

SDFTiming

File

ForwardConstraints

ProgrammingData

TimingAnalyzer

Timing and Simulation

Backannotation

SimulationLibrarySimulation

StructuralNetlist

PlacementConstraints MEMORYmaster

Behavioral

S i l i c o n S c u l p t o rProASIC 500K devices have in-system programming capabilitiesusing Actel’s Silicon Sculptor. Toprogram a device, the configurationdata is supplied through a standardJTAG interface. Silicon Sculptor is aconcurrent programmer that allowsmultiple sites to operate indepen-dently and enables the concurrentprogramming of multiple devices,speeding high volume productionprogramming. The upcomingSilicon Explorer II will also provideconfiguration support.

P r o t o c o l D e s i g n S e r v i c e sThe One Stop Design SolutionWith a ten-year history of providinghardware and software services,Actel’s Protocol Design Servicesteam offers its customers designsupport at all stages of project development. With extensiveknowledge of FPGA design andprototyping, services are deliveredon time, within budget, and to the customers’ specifications.

T h i r d P a r t y S u p p o r t

Syn thes is S imula t ion S ta t ic T iming

Design Compiler VSS Prime TimeFPGA Compiler II

FPGA Express

BuildGates Verilog-XL

Leonardo Spectrum

ModelSim

Synplify

VB VHDLVB Verilog

Synopsys

Cadence

Exempla r

Mode l Techo logy

Synp l ic i t y

Ver iBes t

Actel Corporation • 955 East Arques Avenue • Sunnyvale, California USA 94086Tel: (408) 739-1010 • Fax: (408) 739-1540 Actel Europe, Ltd. • Daneshill House, Lutyens Close • Basingstoke, Hampshire RG24 8AG • United KingdomTel: +44 (0) 125-630-5600 • Fax: +44 (0) 125-635-5420Actel Japan • EXOS Ebisu Building 4F • 1-24-14 Ebisu Shibuya-ku • Tokyo 150 • JapanTel: +81 (0) 3-3445-7671 • Fax: +81 (0) 3-3445-7668

©2001 Actel Corporation. All rights reserved. Actel and the Actel logo are trademarks of Actel Corporation. ASICmaster, MEMORYmaster, and ProASIC are trademarks of Gatefield Corporation. All other brand or product names are the property of their owners.

5 1 9 2 2 6 7 - 3 / 2 . 0 1

For more information about Actel’s products, call 1.888.99.ACTEL orvisit our Web site at http://www.actel.com

A500K050 A500K130 A500K180 A500K270

Maximum Gates 98,000 287,000 369,000 473,000

Typical Gates 43,000 105,000 150,000 215,000

Maximum Flip-Flops 5,376 12,800 18,432 26,880

Embedded RAM Bits 14k 46k 55k 65k

Embedded RAM Blocks (256x9) 6 20 24 28

Logic Tiles 5,376 12,800 18,432 26,880

User I/O 210 312 368 446

JTAG Yes Yes Yes Yes

PCI Yes Yes Yes Yes

P r o A S I C 5 0 0 K F a m i l y S e l e c t o r G u i d e