acquisition crate design
DESCRIPTION
Acquisition Crate Design. BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’. Acquisition Crate Design Philosophy. The design philosophy is the following: Performance Improving System Reliability Protection and Current Limiting - PowerPoint PPT PresentationTRANSCRIPT
Acquisition Crate Design
BI Technical Board
26 August 2011
Beam Loss Monitoring Section
William Vigano’
26 August 2011
Acquisition Crate Design Philosophy
The design philosophy is the following:
• Performance Improving• System Reliability• Protection and Current Limiting• Total separation between System Functionality and System
Safety Functions• Remote Diagnosis• Remote control and calibration
26 August 2011
Acquisition Crate
Extract by the 3D model of the Acquisition Crate26 August 2011
BLEDP – Block Diagram
FRONT ENDCH 1
Calibration Interface
Reset Interface
Data Out
FRONT ENDCH 8
Calibration Interface
Reset Interface
Data Out
SFPTransceiver
Main FPGA
Data In / Out
Ext. PowerPOWER SUPPLY SECTION
PSU
Link
Fully Protected Power Channelswith Diagnosis
FILTERS & PROTECTIONS
OPTICAL LINK
JTAGProg. Interface
PROMProg. Interface
Temperature &Humidity Sensor
SFPTransceiverData In / Out Ethernet LINK
ID Chip
Auxiliary ADCfor HK MonitorData Out HV Feedback
Available Resources: 8 Input Analog Interfaces; FPGA local or remote programming; bidirectional optical link; power supplies with protection and diagnosis; temperature and humidity measurement; ID Chip; auxiliary Ethernet link for diagnosis; Auxiliary ADC for Housekeeping Monitor.
26 August 2011
BLEDP
High Reliability Dc/Dc Converters
Mixed Connector -> 24 pin + 8 Coaxial inserts
Shielded BoxSFP - Transceiver
26 August 2011
BLEDP - Analog Front End principle
The new analog Front End input channel is based on matching two principles:• Advanced Current to Frequency converter (it is a fully
differential Front End based on Giuseppe Venturini’s proposal for the CERN ASIC)
• Direct Acquisition (using the fast ADC capability for the current measurement on the input shunt)
ACFC DADC
Data Output
Reset Interface
Calibration Interface
Input from theMonitor
26 August 2011
ACFC PrincipleFully differential IntegratorInput switch
A status signal selects in which branch of a fully deferential stage the input current is integrated.
Two comparators check the deferential output voltage against a threshold, whenever is exceeded, the status signal changes to the complementary value (0 ! 1 or 1 ! 0) and the input current is integrated in the other branch.
26 August 2011
DADC Principle
R 8 9
10 0
R 9 8
10 0
R 99
1 0 0
R 90
1 0 0
R 84 1 0 0
R 1 0 1 1 0 0
R 9 6
1 0 0
R 9 1
1 0 0
C 21 54 7 p F
C 2 1 24 7 pF
C 2 1 84 7 pF
C 2 1 647 p F
+5 V D C _ 1
-5V D C _ 1
+5 V D C _ 1
-5 V D C _ 1
+5 V D C _ 1
-5 V D C _ 1
+5 V D C _ 1
U 5 5 A
7 4 A B T7 4
C L K3
CLR
1
D2
PR
E4
Q5
VC
C14
GN
D7
Q6
-5 V D C _ 1+5 V D C _ 1
-5 V D C _1
+5 V D C _ 1
-5 V D C _1
+5 V D C _ 1
-2 . 5 V D C _ 1
+5 V D C _ 1
-5V D C _ 1
+2 .5 V D C _ 1
-5 V D C _ 1
+5 V D C _ 1
+5 V D C _ 1
-2 . 5 V D C _ 1
+2 . 5 V D C _ 1
-5 V D C _ 1
+5 V D C _ 1S h u n t _ 1
S h un t _ 1
+5 V D C _ 1 -5 V D C _ 1
-5 V D C _ 1
+5 V D C _ 1
+5 V D C _ 1
S h un t _R e f _1
S TO P _ 1
S TO P _ 1
+5 V D C _ 1
S TO P _ 1
W 1 _ 1A1 _ 1
B1 _ 1
S TO P _ 1
+2 . 5 V D C _ 1
W 1 _ 1
-2 . 5 V D C _ 1
+2 .5 V D C _ 1
B 1 _ 1
A 1 _ 1
A 2 _ 1S hu n t _ R e f _1
A2 _ 1W 2 _ 1
+5 V D C _ 1
+5 V D C _ 1 -5 V D C _ 1
-5V D C _ 1
W 2 _ 1
+5 V D C _ 1
-5 V D C _ 1
R 1 201 0 0
R 10 51 0 0
R 9 51 0 0
C 2 5 46 8 u F
R 1 28
1 K
U5 1 A
M A X9 1 2 C S E
+8
-7
L E4
GN
D1
14
Q1
Q2
V+
11G
ND
03
V-
6
C 2 2 510 0 n F
R 1 1 9
4 7 0K
C 2 3 06 8 u F
L 2 9
2 2 0u
U 5 3 A
74 A B T0 0
1
23
714
C 2 4 51 0µ
C 2 3 51 0 µ
R 1 0 6
4 7 0K
R 1 2 7
1 K
C 2 2 11 0n F
R 9 3
1 K
U 4 7
A D G 8 4 9I N
1
S 14D
5 S 26V D D
2
G N D3
C 2 141 0n F
R 1 3 0 1 0 0
R 1 1 61 K
U 5 0
A D G 71 1
I N 11
I N 21 6
I N 39
I N 48
S 13
D 12
S 21 4
D 21 5
S 31 1
D 31 0
S 46
D 47
VDD
13G
ND
5
C 2 3 61 u F
C 2 4 11 nF
R 8 7
3
U4 3 -2
O P A 2 6 9 0
+5
-6
V+
8V
-4
O U T7
R 8 5
5 M e g
C 2 2 81 0 0n F
C 2 2 61 0µ
C 2 0 71 0 n F
C 2 2 01 0 0 n F
R 9 71 0 0
Q 2 1B S S 1 3 8
C 2 471 0 µ
C 2 5 11 0µ
C 2 0 31 0 0n F
C 2 2 4
1 0 0 p F
R 10 21 0 0
C 2 1 91 0 µ
C 2 3 9
1 0 0 p F
R 8 2
10 0
U 4 4 B
M A X9 1 2 C S E
+9
-1 0
LE1 3
GN
D1
14
Q1 6
Q1 5
V+
11
GN
D0
3V
-6
C 2 1 11 0µ
R 1 0 0
5 1 0
U4 4 A
MA X9 1 2 C S E
+8
-7
L E4
GN
D1
14
Q1
Q2
V+
11G
ND
03
V-
6
R 8 8
1K
C 2 5 01 0 0 nF
R 1 2 9 1 0 0
U 4 6
A D G 1 2 1 9
IN8
S A7 D
6S B5 V D D
2
G N D3
V S S4
E N1
C 2 0 41 0 nF
D 2
B A V 7 4
12
3
C 2 4 81 0 n F
R 9 4 1 K
C 2 3 71 0 0 nF
R 8 32 5 0 K
1 Kohm
256 Step
1 Kohm
256 Step
U 5 7
A D 5 2 5 2
W P3
W 14
V D D1
A D 02 B 1
5A 1
6S D A7
V S S8
S C L9
D G N D1 0
A D 11 1
A 31 2
B 31 3W 31 4
R 11 4
1 K
U 4 8 A
7 4 A B T3 2
1
23
147
C 2 5 51 0 n F
R 1 1 7
1 0 0
U 5 6
TP S 73 0 2 5
IN2
O U T5
GN
D1
E N3
N R4
R 1 2 4 1 0 0
R 1 2 3
1 K
C 2 5 210 0 n F
U 5 8
TP S 73 0 2 5
IN2
O U T5
GN
D1
E N3
N R4
C 2 1 01 0 0 n F
R 1 2 6
1 K
C 2 4 31 0 µ
R 8 12 5 0 K
R 1 2 5 1 0 0
U4 9
O P A 6 5 9
+3
-4
V+
5V
-2
O U T1
+
-
U 4 5
T H S 4 5 0 2
O U T+4
+8
-1
V+
3V
-6
O U T-5
V O C M2
R 1 1 2
1 0 0
C 2 1 71 u F
R 12 11 0 0
C 2 3 11 0 0n F
Q 2 0B S S 1 3 8
C 2 4 21 00 n F
C 2 4 01 0 0 p F
R 1 081 0 0
C 2 4 41 0 0 nF L 2 8
2 2 0u
U 4 2
A D G 1 2 1 9
IN8
S A7 D
6S B5 V D D
2
G N D3
V S S4
E N1
R 8 6
4 7
C 2 0 91 0 µ
C 2 2 71 0 0 p F
C 2 0 61 0 0 nF
R 1 0 7
1 0 0
U4 3 -1
O P A 2 6 9 0
+3
-2
V+
8V
-4
O U T1
C 2 3 41 00 n F
C 2 2 31 u F
C 2 3 24 7 0p F
U5 4
O P A 6 5 9
+3
-4
V+
5V
-2
O U T1
U 4 1
TP S 7 2 3 0 1
I N2
O U T5
GN
D1
E N3
F B4
C 2 4 96 8 u F
F T92 2 n F
13
2
R 1 2 2
1 K
F T1 02 2 n F
13
2
R 11 51 0 0
C 2 2 96 8 u F
C 2 2 21 nF
+
-
U 5 2
T H S 4 5 0 2
O U T+4
+8
-1
V+
3V
-6
O U T-5
V O C M2
R 1 0 4 1 00
C 2 3 31 0 0p F
C 2 1 31 0 nF
C 2 4 610 0 n F
C 2 0 51 0 µ
D 1B A V 1 9 9
21
3
C 2 531 0 µ
R 9 23 K 3
C 2 3 81 0 µ
U5 1 B
M A X9 1 2 C S E
+9
-10
L E13
GN
D1
14
Q1 6
Q1 5
V+
11G
ND
03
V-
6
R 1 0 31 K
R 1 1 8 1 00
C 2 0 81 00 n F
C 2 0 21 0µ
+5 V d c _ C B 1
C L R _1
-5 V d c _ C B 1
S TO P L _ 1
P R E _1
C O U N T+_ 1
C O U N T-_ 1
S D L _ 1S D A _ 1
I N _ 1
W P _1
V in + _ 1
V in -_ 1
V o c m _1
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N DA G N D
A G N D
A G N D
A G N D
A G N D
A G N DA G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N DA G N D A G N DA G N D
A G N D
A G N D
NOTMOUNTED
A G N D
NOTMOUNTED
NOTMOUNTED
S t op O ut _ 1S TO P _ 1 R 1 3 1 1 0 0
+2 . 5 V D C _ 1
R 1 1 010 0
R 1 1 310 0
R 1 0 9
4 7 0K
R 1 1 1
4 7 0K
A G N D
+5V D C _ 1
+5V D C _ 1
+5V D C _ 1
-5V D C _ 1
-5V D C _ 1
-5 V D C _ 1
+5V D C _ 1
+5 V D C _ 1
+5 V d c _ C B 1
+5 V d c _ C B 1
+5 V d c _ C B 1
Input 50 ohm resistor split in two: 47 + 3 ohm Re-routing on the ADC buffer amplifier
26 August 2011
Analog Front End Block Diagram
Comparator+Double Integrator
FRONT END
In. Filter &Protection
Comparator-
Input_Switchfor ADC acquisition
Input Switchfor Integrator
Filp Flop D Type
G=0.5 ADC 16 Bit10 Msps
CK
LOGIC
Reset
DQNQ
CNT-
CNT+
Enable
BUS
Saturationmonitor
Filter
Input
Recovery
Recovery
Current TestGenerator
The two different measurement principles are implemented in a machine able to use the same components but connected in a different way. Some switches in the circuit allow commutation from ACFC to DADC and the opposite.
26 August 2011
ACFC & DADCThe input channel circuit is able to measure current input from 10pA to 200mA.
The measurement of the current input is performed by two different techniques: 1) Advanced Current to Frequency Converter (ACFC) used in the range 10pA to 30mA2) Direct ADC acquisition (DADC) used in the range 20.3µA to 200mA
The passage between the 2 ranges is managed by the FPGA.When the FPGA measures the maximum ACFC counts, it switches the circuit to the modality DADC. When the value of the DADC returns below a threshold, the FPGA switches the circuit to the ACFC modality.
26 August 2011
Analog Crate Calibration
BLEDP Input Channel
Input Selector
Monitor Input
Current Source
Optical Transceiver
Analog Comparator Threshold
Offset Current
Internal Flash Memory
48Vdc
Backplane Mezzanine
Parameters settable remotely: Analog Comparator Threshold (Digital potentiometer value – channel A) Offset Current (Digital potentiometer value – channel B) Measurement Period Current Source available on the Backplane with precision 2% Current Source available external with precision 0.1%
26 August 2011
All the Channels of all the Cards in the CRATE can be calibrated from remote with the same current reference (Internal or External)
Main Panel
Power Supply Presence LEDs
Status of Calibration Relays
Main Switch
Input connector for external Current Source
26 August 2011
CRATE Power Supply
The Main Power Supply will be integrated in the CRATE, maintaining the possibility to be replaced in 1 working hour.
It generates a common voltage bus of 48 Volts for all the cards in order to limit the current flowing on the backplane, optimizing in the meantime the ripple noise.
26 August 2011
FILTER±5Vdc @ 20Watt
Dc/Dc Converter FILTER
Circuit BreakerWith full Diagnosis
Analog Front EndChannels 1,2,3,4
Circuit BreakerWith full Diagnosis
Analog Front EndChannels 5,6,7,8
PROM + FPGA VCCIO
SFP - Transceiver
Dc/Dc Converter 1.2V @ 3A
Linear Voltage Regulator2.5V @ 200mA
Front End Card n.N
Front End Card n.1
External Link
Acquisition Crate
FPGA VCCA_GXBFPGA VCCH_GXBFPGA VCCAFPGA VCC_CLKIN
FPGA VCCINTFPGA VCCD_PLLFPGA VCCL_GXB
Optical Link
48V @ 300Watt
Ac/Dc ConverterPower Input EMI FILTER
EMI FILTERInternal CoolingSystem FILTER
3.3Vdc @ 10Watt
Dc/Dc Converter FILTER
Optical Link
Power Supply Structure Block Diagram
Main Power Supply
Local creation of all required voltages in the BLEDP Cards26 August 2011
Circuit Breakers
Backplane
The Backplane will manage the following functions:
• Monitor input wiring• 48Vdc Power Distribution and protection by Resettable Fuses• Internal Current Source• Relays Multiplexer for Calibration of all the channels with the same current
26 August 2011
BLECU
The BLECU is a Controller Card. It will be implemented in a second stage of the project to improve the functionalities of the Backplane.
It will manage the following functions:• Detection of the current break for the 48V lines• Global CRATE current consumption measurement• Remote On/Off of the BLEDP Cards• Current Source selection (Internal/External)• Current Value selection for the Internal Current Source• CRATE Temperature and Humidity measurement
(Sensor mounted on the Backplane)• CRATE Identifier chip readout (Chip mounted on the
Backplane)
26 August 2011
Simulation Models
BLEDP Analog Input Interface PSPICE ModelCurrent Source PSPICE Model
PSPICE Models were create to simulate several working conditions like worst case, Monte Carlo analysis, extreme performance.
Dc/Dc Converter – TI SwitcherPro Model
26 August 2011
The BLEDP Analog Input Interface PSPICE model allows to verify and evaluate all the circuit delay errors, input leakage current and signal distortion.
Prototype Verification
Current SourceBLEDP
Analog Input Interface
Prototypes have been created to verify the BLEDP Analog Input Interface and the Current Source
26 August 2011
Prototype ResultsThe BLEDP Analog Input Interface Prototype allow to measure the current in the range:
3 pA ÷ 200mA
26 August 2011
Better evaluation of performances will be done with the BLEDP PCB (currently in the design and manufacturing phase)
