acer extensa 5620z - wistron columbia_tangiz

A

B

C

D

Columbia/Tangiz Block DiagramMobile CPU4

SYSTEM DC/DCMAX8744INPUTS 38 OUTPUTS5V_S5(6A) DCBATOUT 3D3V_S5(7A)

E

Project code: 91.4T301.001 PCB P/N : 48.4T301.0SA REVISION : 06236-SAPCB STACKUP

CLK GEN.ICS 9LPRS502 (RTM875T-605) 371.09502.00W

Merom 479 2G/2.33G2.0G : 71.MEROM.A0U 2.33G : 71.MEROM.B0U

G79220 4, 5

4

SYSTEM DC/DCMax8717INPUTSDCBATOUT 1D8V_S3(8.5A)

TV Out CRT LCD15

39 OUTPUTS

14

TOP

HOST BUS

667/[email protected]

DVI

VCC

1D05V_S0(9.5A)

DDR2533/667 MHz12,13

44

S S GND BOTTOM

533/667MHz

Crestline AGTL+ CPU I/FDDR Memory I/F INTEGRATED GRAHPICS LVDS, CRT I/F 71.CREST.00U

TPS511001D8V_S3

41DDR_VREF_S0 (1.5A) DDR_VREF_S3

14

DDR2533/667 MHz312,13

533/667MHz

6,7,8,9,10,11

VGA Borad28PCMCIA I/F

APL59151D8V_S3 1D25V_S0 (2A)

41

X4 DMI 400MHz AZALIA

C-Link0 PWR SWCP2211F

3

Line In

CodecALC26830

PCMCIA SLOT26 Support TypeII 27

APL5312303D3V_S0 2D5V_S0 (300mA)

ICH8M6 PCIe ports PCI/PCI BRIDGE ACPI 1.1 3 SATA 1 PATA 66/100

TI PCI7412PCI BUS

APW59123D3V_S5 1D5V_S3 (7.5A)

40

MIC In14

Cardbus Cardreader25/26

1394 CONN

27

MS/MS Pro/xD/ MMC/SD5 in 1

ISL CHARGERISL6255 INPUTS 41 OUTPUTS CHG_PWR18V 5V 4.0A 100mA

27

31

OP AMPG1431Q 31

10 USB 2.0/1.1 ports ETHERNET (10/100/1000MbE) High Definition Audio LPC I/F Serial Peripheral I/F Matrix Storage Technology(DO) Active Managemnet Technology(DO)

2

INT.SPKR

LAN GIGABCM5787M 23 PCIex1

TXFM24

RJ4524

DCBATOUT

UP+5V

2

OP AMP G1412Line Out (No-SPDIF)31

CPU DC/DC Mini CardKedron a/b/g/n

MAX8770 29 INPUTS

35,36

OUTPUTS VCC_CORE_S00~1.3V 47A

RJ11

MODEM MDC Card22

71.0ICH8.A0U

DCBATOUT

16,17,18,19

LPC BUS

SATA

PATA

USB

New card 291

PCI Express

MINI USB BlueToothFinger print

Winbond22

KBC

SPI I/F 32

BIOSW25X80-VSS

WPC8768L

34

DEBUG CONN. 35

LPC

P2231NFC129

HDD 21

CDROM21

34

Touch Pad 33

INT. KB 33

1

FIR 32Title Size A3 Document Number

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

USB 4 Port22

CAMERA

BLOCK DIAGRAMRev

13

Columbia/TangizSheet 1 of 45

-1

Date: Monday, February 26, 2007

A

B2.0V1page 16

C

D

E1.0

ICH8M Functional Strap Definitions ICH8-M EDS 21762Signal HDA_SDOUT Usage/When Sampled XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK Comment

ICH8M Integrated Pull-up and Pull-down ResistorsICH8-M EDS 21762 2.0V1

Crestline Strapping Signals and Crestline EDS 20954 Configuration page 7Pin Name CFG[2:0] Strap Description FSB Frequency Select Configuration 001 = FSB533 011 = FSB667 010 = FSB800 others = Reserved

Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h) This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h) This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high. ESI compatible mode is for server platforms only. This signal should not be pulled low for desttop and mobile. Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. Enables integrated VccSus1_05, VccSus1_5 and VccCL1_5 VRM's when sampled high

SIGNALHDA_BIT_CLK HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GNT[3:0] GPIO[20] LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED# SPI_CS1# SPI_CLK SPI_MOSI SPI_MISO TACH_[3:0] SPKR TP[3] USB[9:0][P,N] CL_RST#

Resistor Type/ValuePULL-DOWN 20K NONE PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 10K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 15K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 15K PULL-UP 13K

4

HDA_SYNC GNT2# GPIO20 GNT1#/ GPIO51

PCIE config1 bit0, Rising Edge of PWROK. PCIE config2 bit0, Rising Edge of PWROK. Reserved ESI Strap (Server Only) Rising Edge of PWROK

CFG[4:3] CFG5 CFG[8:6]

Reserved DMI x2 Select Reserved Low Power PCI Express 0 = Normal mode 1 = Low Power mode (Default) 0 = DMI x2 1 = DMI x4 (Default)

4

CFG9

GNT3#

Top-Block Swap Override. Rising Edge of PWROK.

PCI Express Graphics Lane Reversal Reserved XOR/ALL Z test straps

0 = Reverse Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane Numbered in order

CFG[11:10] CFG[13:12]

GNT0#/ SPI_CS1#

INTVRMEN

Boot BIOS Destination Selection. Rising Edge of PWROK. Integrated VccSus1_05, VccSus1_5 and VccCL1_5 VRM Enable/Disable. Always sampled. Integrated VccLAN1_05 and VccCL1_05 VRM Enable/Disable. Always sampled. PCI Express Lane Reversal. Rising Edge of PWROK. No Reboot. Rising Edge of PWROK.

00 01 10 11

= = = =

Reserved XOR mode enabled All Z mode enabled Normal Operation (Default)

CFG[15:14] CFG16

Reserved FSB Dynamic ODT

Reserved 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default)

CFG[18:17] CFG19

Reserved DMI Lane Reversal 0 = Normal operation (Default):lane Numbered in order 1 =Reverse Lane,4->0,3->1 ect...

3LAN100_SLP

Enables integrated VccLAN1_05 and VccCL1_05 VRM's when sampled high

3

SATALED# SPKR

Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8) If sampled high, the system is strapped to the "No Reboot" mode(ICH8 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit. This signal should not be pull low unless using XOR Chain testing. This signal has a weak internal pull-up. Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be in effect.This should only be used in manufacturing environments.

CFG20

SDVO/PCIE Concurrent SDVO Present

0 = Only SDVO or PCIE x1 is operational (Default) 1 =SDVO and PCIE x1 are operating simultaneously via the PEG port 0 = No SDVO Card present (Default) 1= SDVO Card present

SDVOCRTL _DATA

TP3

XOR Chain Entrance. Rising Edge of PWROK. Flash Descriptor Security Override Strap Rising Edge of PWROK

NOTE: All strap signals are sampled with respect to the leading edge of the Crestline GMCH PWORK in signal.

GPIO33/ HDA_DOCK _EN#

History

2

2

ICH8M IDE Integrated Series Termination ResistorsDD[15:0], DIOW#, DIOR#, DREQ, approximately 33 ohm DDACK#, IORDY, DA[2:0], DCS1#, DCS3#, IDEIRQ

PCI RoutingIDSEL TI7412 INT

page 17

USB TableUSB Pair 0 1 2 3 4 Device USB1 NC USB2 USB4 USB3 BLUETOOTH WEBCAM FT MINICARD NEW1Title UMA

REQ

GNT 0

G:CARDBUS 0 AD22 B:1394 F:Flash Media G:SD Host

1

1

PCIE RoutingLANE1 LANE2 LANE3 LAN BCM5787M MiniCard WLAN NewCard WLAN

5 6 7 8 9


ReferenceSize A3 Document Number Rev

Columbia/TangizSheet 2 of 45

-1


A

B

C

D

E

3D3V_S0 3D3V_S0 R211 1 2 0R3-0-U-GP 3D3V_48MPWR_S0 SC4D7U6D3V3KX-GP 2 1 SB 3D3V_CLKPLL_S0 -1 3D3V_CLKGEN_S0

-11 R170 2 0R0603-PAD

3D3V_S0

1

1

1

1

1

1

1

1

C265

C266 SC1U16V3ZY-GP

EC119

C257 SCD1U16V2ZY-2GP

C255 SC4D7U10V5ZY-3GP




1

2 R189 1 0R0603-PADC242 SCD1U16V2ZY-2GP

1

1

1

1

1




C238

C239

1 2


SCD1U16V2ZY-2GP

C272

DY2

DY2 2

2

2

2

2

2

2

2

2

2

4

2

SCD1U16V2ZY-2GP

2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3D3V_S0

4

U14 3D3V_CLKGEN_S0 3D3V_48MPWR_S0

DYR207 10KR2J-3-GP R208 10KR2J-3-GP

DYR209 10KR2J-3-GP

DYR210 10KR2J-3-GP

2 9 16 61 39 55

VDDPCI VDD48 VDDPLL3 VDDREF VDDSRC VDDCPU VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN X2 X1 USB_48MHZ/FSLA FSLB/TEST_MODE REF0/FSLC/TEST_SEL GNDPCI GND48 GND GND GNDSRC GNDSRC GNDCPU GNDREF GNDSRC

SDATA SCLK SRCT0/DOTT_96 SRCC0/DOTC_96 27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2 SRCT2/SATAT SRCC2/SATAC SRCT3/CR#_C SRCC3/CR#_D SRCT4 SRCC4 PCI_STOP# CPU_STOP# SRCT6 SRCC6 SRCT7/CR#_F SRCC7/CR#_E CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 CPUT1_F CPUC1_F CPUT0 CPUC0 CK_PWRGD/PD# NC#48 SRCT9 SRCC9 SRCC11/CR#_G SRCT11/CR#_H SRCT10 SRCC10

63 64 13 14 17 18 21 22 24 25 27 28 38 37 41 40 44 43 47 46 51 50 54 53 56 48 30 31 32 33 34 35

SMBD_ICH 12,19 SMBC_ICH 12,19 DREFCLK_1 DREFCLK#_1 CLK_PCIE_NEW_R CLK_PCIE_NEW#_R CLK_PCIE_SATA_1# CLK_PCIE_SATA_1 CLK_MCH_3GPLL_1 CLK_MCH_3GPLL_1# CLK_PCIE_MINI_12 CLK_PCIE_MINI_12#

2

2

2

2

1

1

1

PCLKCLK2 PCLKCLK3 PCLKCLK4 PCLKCLK5

1

4 3 2 1 2 1 2 1 2 1

UMA

1 RN30 2 SRN33J-5-GP-U 3 4 SRN0J-6-GP RN31 3 SRN0J-6-GP 4 RN32 3 4 3 4SRN0J-6-GP RN33 SRN0J-6-GP RN34

DREFCLK 7 DREFCLK# 7 CLK_PCIE_NEW 29 CLK_PCIE_NEW# 29 CLK_PCIE_SATA 16 CLK_PCIE_SATA# 16 CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7 CLK_PCIE_MINI1 29 CLK_PCIE_MINI1# 29

3D3V_CLKPLL_S0

DYR192 10KR2J-3-GP R193 10KR2J-3-GP R194 10KR2J-3-GP R195 10KR2J-3-GP

32 PCLK_SIO

R604 2

1 22R2J-2-GPTPAD30 TP66

PCLKCLK0 PCLKCLK1 PCLKCLK2 PCLKCLK3 PCLKCLK4 PCLKCLK5

12 20 26 36 45 49 1 3 4 5 6 7 59 60

2

2

2

1

1

1

1

2

26 34 323

PCLK_PCM PCLK_FWH PCLK_KBC PCLK_ICH

R182 2 R183 2 R184 2 R185 2

1 22R2J-2-GP 1 22R2J-2-GP 1 22R2J-2-GP 1 22R2J-2-GP

PM_STPPCI# 17 PM_STPCPU# 17 CLK_PCIE_ICH_1 CLK_PCIE_ICH_1# DREFSSCLK_1 DREFSSCLK#_1 CLK_PCIE_LAN_R CLK_PCIE_LAN#_R CLK_MCH_BCLK_1 CLK_MCH_BCLK_1# CLK_CPU_BCLK_1 CLK_CPU_BCLK_1#

C253 SC27P50V2JN-2-GP 1 2

1 2 3 4 1 2 1 2 1 2

4 3

RN26 SRN0J-6-GP

CLK_PCIE_ICH 17 CLK_PCIE_ICH# 17 DREFSSCLK 7 DREFSSCLK# 7 CLK_PCIE_LAN 23 CLK_PCIE_LAN# 23 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 CLK_CPU_BCLK 4 CLK_CPU_BCLK# 43

17 GEN_XTAL_IN

C244 1 2

R180 2 1 10MR2J-L-GP R176 1 GEN_XTAL_OUT 2 -1 X2 0R0402-PAD R188 2 1 22R2J-2-GP 17 CLK48_ICH X-14D31818M-44GP 4,7 R186 2 1 2K2R2J-2-GP CPU_SEL0

1

DY

UMA

CLK48

10 57 62 8 11 15 19 23 42 52 58 29

2 1 SRN33J-5-GP-U RN25 RN24 4 SRN0J-6-GP 3 4 3 4 3RN23 SRN0J-6-GP RN22 SRN0J-6-GP 3D3V_S0

GEN_XTAL_OUT_R

4,7 4,7 17 32

CPU_SEL1 CPU_SEL2 CLK_ICH14 CLK14_SIO R172 2 R171 2 R605 2 R187 2 1 22R2J-2-GP

2

SC27P50V2JN-2-GP

1 2K2R2J-2-GP CPU_SEL2_R 1 22R2J-2-GP 1 22R2J-2-GPCLK48

CLK_PWRGD 17 10KR2J-3-GP 1 DY 2 R173 -1

26 CLK48_CARDBUS

CLK_PCIE_PEG 28 SRN0J-6-GP CLK_PCIE_PEG_1 2 G72 CLK_PCIE_PEG_1# 1 RN21

1 3 4

DY2

ER19 330R2J-3-GP

2

ICS9LPRS365YGLFT-GP 71.09365.00W

CLK_PCIE_PEG# 28

2

UMA:71.09502.A0W=>56pin G72:71.09365.00W=>64pin

U1456pin RN22,23,24,26,31,32,33,3466.33036.04L

ICS9LPR502HGLFT-GP setting table PIN NAME DESCRIPTION PCI0/CR#_AByte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed

RTM875T-605 setting table PIN NAME DESCRIPTION PCI0/CR#_AByte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed 0 = Pin29 as CPU_STOP# , pin 30 as PCI_STOP#. 1 = Pins29,30 as SRC-5 differential pair. 0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# 1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0# 0 =SRC8/SRC8# 1 = ITP/ITP# Title UMA

SEL2 SEL1 SEL0 FSC FSB FSA 1 0 0 0 0 0 1 1 1 1 1 0

CPU100M 133M 166M 200M

FSBX X 667M 800M1

PCI1/CR#_B1

PCI1/CR#_B PCI2/TME PCI3/SRC-5_EN PCI4/27M_SEL PCI_F5/ITP_EN

PCI2/TME PCI4/SRC5_EN PCI_F5/ITP_ENA


0 = Pin29 as CPU_STOP# , pin 30 as PCI_STOP#. 1 = Pins29,30 as SRC-5 differential pair. 0 =SRC8/SRC8# 1 = ITP/ITP#

Clock GeneratorSize Document Number Rev

Columbia/TangizDate: Monday, February 26, 2007B C D

SA45

SheetE

3

of

A

B

C

D

E

6

H_A#[35..3]

H_A#[35..3] H_DINV#[3..0] U43A 1 OF 4 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 TP20 TPAD30 H_DSTBN#[3..0] 6 6 6 1D05V_S0 H_DSTBP#[3..0] H_D#[63..0] H_DINV#[3..0] H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0] 6 6 6 64

4

6 6

H_ADSTB#0 H_REQ#[4..0]

J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1

A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6 KEY_NC

ADS# BNR# BPRI#

H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# H_RS#0 H_RS#1 H_RS#2

H_ADS# H_BNR# H_BPRI#

ADDR GROUP 0

CONTROL

DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM#

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 H_BREQ#0 6 H_IERR# H_INIT# 16

1R81 56R2J-4-GP

2

Place testpoint on H_IERR# with a GND 0.1" away

3

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 6 16 16 16 16 16 16 16 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TP19 TP18 TP17 TP16 TP24 TP30 TP22 TP26 TP25 TP21 TP27 RSVD_CPU_1 RSVD_CPU_2 RSVD_CPU_3 RSVD_CPU_4 RSVD_CPU_5 RSVD_CPU_6 RSVD_CPU_7 RSVD_CPU_8 RSVD_CPU_9 RSVD_CPU_10 RSVD_CPU_11

Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 B1

H_HIT# H_HITM# TP6 TP5 TP7 TP9 TP8 TP12 TP13 TP15 TP10 TP14 TP11 TP23

6 6 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30

H_THERMDA

XDP/ITP SIGNALS

BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#

H_THERMDC

1D05V_S0 6 H_DSTBN#0 6 H_DSTBP#0 6 H_DINV#0 56R2J-4-GP

2

C88 SC2200P50V2KX-2GP

DATA GRP2

H_REQ#0 K3 H_REQ#1 H2 H_REQ#2 K2 H_REQ#3 J3 H_REQ#4 L1

H_LOCK# 6 H_CPURST# 6,33 H_RS#[2..0]

U43B 2 OF 4 6 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_TRDY# 6

R85

1

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25

D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL0 BSEL1 BSEL2

D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3 R71 1 R70 1 R62 1 R67 1

DATA GRP0

1

THERMTRIP#

C7

2 R86 1 0R0402-PAD

-1

PM_THRMTRIP-A# 7,16,35

HCLK

BCLK0 BCLK1

A22 A21

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 PM_THRMTRIP# should connect to ICH8 and MCH without T-ing ( No stub) 1D05V_S0

2

RESERVED

1 1

Layout Note: "CPU_GTLREF0" 0.5" max length.

1KR2F-3-GP R57 SC1KP50V2KX-1GP 2 1

6 6 6

H_DSTBN#1 H_DSTBP#1 H_DINV#1

CPU_GTLREF0

DATA GRP3

PROCHOT# THRMDA THRMDC

D21 A24 B25

CPU_PROCHOT#_R H_THERMDA 20 H_THERMDC 20

2

ADDR GROUP 1

3

THERMAL

H_D#16 N22 H_D#17 K25 H_D#18 P26 H_D#19 R23 H_D#20 L23 H_D#21 M24 H_D#22 L22 H_D#23 M23 H_D#24 P25 H_D#25 P23 H_D#26 P22 H_D#27 T24 H_D#28 R24 H_D#29 L25 H_D#30 T25 H_D#31 N25 L26 M26 N24

DATA GRP1

ICH ICH

2

R56 2KR2F-3-GP

DY C32

TPAD30 TP28 TPAD30 TPAD30 3,7 3,7 3,7 TP4 TP31

BGA479-SKT6-GPU3

2

AD26 TEST1 C23 TEST2 D25 RSVD_CPU_12 C24 TEST4 AF26 RSVD_CPU_13 AF1 RSVD_CPU_14 A26 B22 B23 C21

MISC

2 2 2 2

27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP

2

62.10079.001

CPU_SEL0 CPU_SEL1 CPU_SEL2

H_DPRSTP# 7,16,37 H_DPSLP# 16 H_DPWR# 6 H_PWRGD 16,33,35 H_CPUSLP# 6 PSI# 37

1D05V_S0

BGA479-SKT6-GPU3 TEST1 1KR2J-1-GP TEST2 1KR2J-1-GP Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .

XDP_TMS XDP_TDI XDP_BPM#5 XDP_TDO H_CPURST#

R65 R66 R63 R64 R89

1 1 1 1 1

2 39R2F-GP 2 150R2F-1-GP

1 R83 1 R84C30

DY DY

2 2

DY DY DY

2 54D9R2F-L1-GP 2 54D9R2F-L1-GP 2 54D9R2F-L1-GP3D3V_S0

TEST4 2 1 DY SCD1U10V2KX-4GP

Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals

1

XDP_DBRESET# R82

1

DY

2 150R2F-1-GP

UMA

1

XDP_TCK XDP_TRST#

R58 R59

1 1

2 27D4R2F-L1-GP 2 649R2F-GPTitle


All place within 2" to CPU

CPU (1 of 2)Size Document Number Rev

Columbia/TangizDate: Monday, February 26, 2007A B C D

-145

SheetE

4

of

A

B

C

D

E

VCC_CORE_S0 VCC_CORE_S04

U43D VCC_CORE_S0

4 OF 4

U43C 3 OF 4

3

2

A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCA VCCA VID0 VID1 VID2 VID3 VID4 VID5 VID6 VCCSENSE VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 CPU_G21 CPU_V6 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26 AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7 1H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

C60 SCD1U10V2KX-4GP

C61 SCD1U10V2KX-4GP

C84 SCD1U10V2KX-4GP

C81 SCD1U10V2KX-4GP

2

2

2

2

DY

-1VCC_CORE_S0

DY1 1 1C44 SC10U6D3V5MX-3GP C50 SC10U6D3V5MX-3GP C87 SC10U6D3V5MX-3GP

DY1 1C91 SC10U6D3V5MX-3GP C43 SC10U6D3V5MX-3GP

-11C69 SC10U6D3V5MX-3GP

SC1 1C34 SC10U6D3V5MX-3GP C55 SC10U6D3V5MX-3GP

-11 1 1 1 1C82 SC10U6D3V5MX-3GP C37 SC10U6D3V5MX-3GP C54 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP C78 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP C68 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP

C40 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP

DY

DY

1D05V_S0

1 R77

2 0R0402-PAD 1 R69 2 0R0402-PAD

C47 SCD1U10V2KX-4GP

2

2

C79

1D05V_S0

layout note: "1D5V_VCCA_S0" as short as possible1 1 1 1 1 1 11D5V_VCCA_S0 L1 1D5V_S0 C57 SCD1U10V2KX-4GP SCD1U10V2KX-4GP C77 SCD1U10V2KX-4GP SCD1U10V2KX-4GP C64 SCD1U10V2KX-4GP SCD1U10V2KX-4GP C56 SCD1U10V2KX-4GP SCD1U10V2KX-4GP C67 SCD1U10V2KX-4GP C38 SCD1U10V2KX-4GP C83 SC4D7U6D3V3KX-GP

C51 SC4D7U6D3V3KX-GP

2

2

2

2

2

2

2

SCD01U16V2KX-3GP 2 1

C86

37 VCC_CORE_S0 37 37 37 37 R54 37 100R2F-L1-GP-U 37

2

1

VCC_SENSE 37 VSS_SENSE 37 Layout Note: R53 100R2F-L1-GP-U VCCSENSE and VSSSENSE lines should be of equal length.

BGA479-SKT6-GPU3

2

Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.1

2

1 2 HCB1608KF121T30-GP 68.00230.041 C85 SC4D7U6D3V3KX-GP

1

2

DY

DY

A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

4

1

1

1

1

2

2

2

2

2

2

2

2

2

2

2

2

2

2

1

3

1SCD1U10V2KX-4GP

1

1

2

BGA479-SKT6-GPU3

1

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

CPU (2 of 2)Size Document Number Rev


-145

SheetE

5

of

A

B

C

D

E

U48A 1 OF 10 44

H_D#[63..0]

H_D#[63..0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SWING H_RCOMP

H_A#[35..3]

H_SWING routing Trace width and Spacing use 10 / 20 mil H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )1

1D05V_S0

R331 221R2F-2-GP

H_SWING C444 SCD1U10V2KX-4GP

R334 100R2F-L1-GP-U

H_SCOMP and H_SCOMP# Resistors and Capacitors close MCH 500 mil ( MAX )3

1D05V_S0

1 R333 1D05V_S0 1 R332

2 H_SCOMP 54D9R2F-L1-GP

2 H_SCOMP# 54D9R2F-L1-GP

H_RCOMP routing Trace width and Spacing use 10 / 20 mil1 R335 2 H_RCOMP 24D9R2F-L-GP

Place them near to the chip ( < 0.5")2

H_REF Decoupling Crestline close Crestline 100 mil

E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 B3 C2 W1 W2 B6 E5 B9 A9

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SWING H_RCOMP

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3 H_DPWR# 4 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4

H_A#[35..3]

44

2

2

1

2

1

3

HOST

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#[3..0]

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2

K5 L2 AD13 AE13 M7 K3 AD2 AH11 L7 K2 AC2 AJ10 M14 E13 A11 H13 B12 E12 D7 D8

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#[3..0] H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#[3..0] H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2

H_DINV#[3..0]

4

H_DSTBN#[3..0]

42

H_DSTBP#[3..0]

4

1D05V_S0

2

H_SCOMP H_SCOMP# R340 1KR2F-3-GP 4,33 H_CPURST# 4 H_CPUSLP# H_AVREF

H_REQ#[4..0]

4

H_SCOMP H_SCOMP# H_CPURST# H_CPUSLP# H_AVREF H_DVREF

H_RS#[2..0]

4

1

1

2

1

CRB v0.9 REQUEST

1

R339 2KR2F-3-GP


2

CRESTLINE-GP-U

UMA

1

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number

GMCH (1 of 6) Columbia/TangizSheetE

Rev

-145

Date: Monday, February 26, 2007A B C D

6

of

A

B

C

D

E

U48B 2 OF 10 P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20 RSVD#P36 RSVD#P37 RSVD#R35 RSVD#N35 RSVD#AR12 RSVD#AR13 RSVD#AM12 RSVD#AN13 RSVD#J12 RSVD#AR37 RSVD#AM36 RSVD#AL36 RSVD#AM37 RSVD#D20 SM_CK0 SM_CK1 SM_CK3 SM_CK4 SM_CK#0 SM_CK#1 SM_CK#3 SM_CK#4 AV29 BB23 BA25 AV23 AW30 BA23 AW25 AW23 BE29 AY32 BD39 BG37 BG20 BK16 BG16 BE13 BH18 BJ15 BJ14 BE16 BK31 BL31 BL15 BK14 AR49 AW4 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS0# M_CS1# M_CS2# M_CS3# M_ODT0 M_ODT1 M_ODT2 M_ODT3 SM_RCOMP_VOH SM_RCOMP_VOL TPAD30 TP54 M_RCOMPP M_RCOMPN DDR_VREF_S3 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12,13 12 12 12 12 12 12 12 12

UMA14 32 L_BKLTCTL GMCH_BL_ON LCTLA_CLK LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID GMCH_LCDVDD_ON LIBG L_LVBG J40 H39 E39 E40 C37 D35 K40 L41 L43 N41 N40 D46 C45 D44 E42

1D05V_S0 U48C 3 OF 10 R155 L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 PEG_COMPI PEG_COMPO PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 N43 M43 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 PEG_CMP 2 1 24D9R2F-L-GP PEG_RXN[15..0] 28

14 CLK_DDC_EDID 14 DAT_DDC_EDID 14 GMCH_LCDVDD_ON TPAD30 TP52

4

1D8V_S3 R350 20R2F-GP 1 2 M_RCOMPP R348 20R2F-GP M_RCOMPN 1 2

SM_CKE0 SM_CKE1 SM_CKE3 SM_CKE4 SM_CS#0 SM_CS#1 SM_CS#2 SM_CS#3 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3

H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BH39 AW20 BK20

14 14 14 14

GMCH_TXACLKGMCH_TXACLK+ GMCH_TXBCLKGMCH_TXBCLK+

RSVD#H10 RSVD#B51 RSVD#BJ20 RSVD#BK22 RSVD#BF19 RSVD#BH20 RSVD#BK18 RSVD#BJ18 RSVD#BF23 RSVD#BG23 RSVD#BC23 RSVD#BD24 RSVD#BH39 RSVD#AW20 RSVD#BK20 RSVD#B44 RSVD#C44 RSVD#A35 RSVD#B37 RSVD#B36 RSVD#B34 RSVD#C34

TPAD30 TP53

G51 14 GMCH_TXAOUT0E51 14 GMCH_TXAOUT1F49 14 GMCH_TXAOUT2GMCH_TXAOUT3- C48 14 GMCH_TXAOUT0+ 14 GMCH_TXAOUT1+ 14 GMCH_TXAOUT2+ GMCH_TXAOUT3+ 14 GMCH_TXBOUT014 GMCH_TXBOUT114 GMCH_TXBOUT214 GMCH_TXBOUT0+ 14 GMCH_TXBOUT1+ 14 GMCH_TXBOUT2+ G50 E50 F48 D47 G44 B47 B45 E44 A47 A45

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 1 G72 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C203 C189 C205 C211 C213 C200 C192 C207 C229 C221 C217 C517 C228 C226 C514 C219 C201 C187 C204 C208 C215 C193 C190 C206 C224 C220 C216 C518 C227 C225 C515 C218

DDR MUXING

4

LVDS

SM_VREF#AR49 SM_VREF#AW4

3D3V_S0 R110 1 R104 1 R133 1 R106 13

2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2

CFG18 CFG19 CFG20 CFG3 CFG4 CFG5 CFG6 3,4 CFG7 3,4 3,4 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CPU_SEL0 CPU_SEL1 CPU_SEL2 P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 B44 C44 A35 B37 B36 B34 C34

DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#

B42 C42 H48 H47 K44 K45

DREFCLK DREFCLK# DREFSSCLK DREFSSCLK#

DREFCLK 3 DREFCLK# 3 DREFSSCLK 3 DREFSSCLK# 3 CLK_MCH_3GPLL 3 CLK_MCH_3GPLL# 3 15 15 15 3D3V_S0

PCI_EXPRESS GRAPHICS

R126 1 R117 1 R101 1 R121 1 R108 1 R107 1 R125 1 R122 1 R131 1 R124 1 R102 1 R120 1 R109 1 R127 1

CLK

RSVD RSVD

PEG_RXP[15..0] 28

SM_RCOMP_VOH SM_RCOMP_VOL SM_RCOMP SM_RCOMP#

PEG_TXN[15..0] 28 SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 PEG_TXP[15..0] 28

PEG_CLK PEG_CLK#

TV_DACA TV_DACB TV_DACC

E27 G27 K27 F27 J27 L27

TVA_DAC TVB_DAC TVC_DAC

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

AN47 AJ38 AN42 AN46 AM47 AJ39 AN41 AN45 AJ46 AJ41 AM40 AM44 AJ47 AJ42 AM39 AM43

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17

RN15 1 2 3 4 8 7 6 5 SRN2K2J-2-GP TV_DCONSEL0 TV_DCONSEL1

TVA_RTN TVB_RTN TVC_RTN TV_DCONSEL0 TV_DCONSEL1

M35 P33

GRAPHICS VID

CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

UMA15 GMCH_BLUE GMCH_BLUE GMCH_GREEN GMCH_RED 15 GMCH_GREEN 15 GMCH_RED H32 G32 K29 J29 F29 E29 CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

N45 GTXN0 U39 GTXN1 U47 GTXN2 N51 GTXN3 R50 GTXN4 T42 GTXN5 Y43 GTXN6 W46 GTXN7 W38 GTXN8 AD39 GTXN9 AC46 GTXN10 AC49 GTXN11 AC42 GTXN12 AH39 GTXN13 AE49 GTXN14 AH44 GTXN15 M45 GTXP0 T38 GTXP1 T46 GTXP2 N50 GTXP3 R51 GTXP4 U43 GTXP5 W42 GTXP6 Y47 GTXP7 Y39 GTXP8 AC38 GTXP9 AD47 GTXP10 AC50 GTXP11 AD43 GTXP12 AG39 GTXP13 AE50 GTXP14 AH43 GTXP15

3

TV

DMI CFG CFG

VGA

15 GMCH_DDCCLK 15 GMCH_DDCDATA 15 GMCH_VSYNC 15 GMCH_HSYNC

4,16,37 H_DPRSTP#2

17,37 VGATE_PWRGD 17,20 7,21,23,28,29,32,34 PWROK PLT_RST1#

G41 17 PM_BMBUSY# H_DPRSTP#_MCH L39 R152 1 2 0R0402-PAD PM_EXTTS#0 L36 0R2J-2-GP R159 PM_EXTTS#1 J36 PWROK_GD AW49 2 1 RSTIN# AV20 NB_THERMTRIP# N20 R158 1 0R0402-PAD 2 R105 PM_DPRSLPVR_MCH G36 2 1 100R2J-2-GP

DY

PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#0 PM_EXT_TS#1 PWROK RSTIN# THERMTRIP# DPRSLPVR

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VR_EN

E35 A39 C38 B39 E36

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VR_EN

TP48 TP51 TP116 TP49 TP50

TPAD28 TPAD28 TPAD28 TPAD28 TPAD28

GMCH_DDCCLK K33 GMCH_DDCDATAG35 GMCH_VS E33 1 UMA 2 R369 33R2F-3-GP C32 GMCH_HS F33 1 UMA 2 R368 33R2F-3-GP 1 R360 CRT_IREF 2 1K3R2F-1-GP

CRT_DDC_CLK CRT_DDC_DATA CRT_VSYNC CRT_TVO_IREF CRT_HSYNC

CRESTLINE-GP-U 1D25V_S0 2 R161 1KR2F-3-GP 1

UMA UMAGMCH_BLUE R142 UMA 150R2F-1-GP 1 2 R139 UMA 150R2F-1-GP 1 2 R137 UMA 150R2F-1-GP 1 2 GMCH_BL_ON R149 1 2 100KR2J-1-GP 100KR2J-1-GP GMCH_LCDVDD_ON 1 2 R138

2

PM PM

FOR Calero: 255 ohm Crestline: 1.3k ohm

UMA

C153 SC100P50V2JN-3GP

ME

2

DY

4,16,35 PM_THRMTRIP-A# 17,37 PM_DPRSLPVR

R103 1 0R0402-PAD 2 R134 1 0R0402-PAD 2

2

MCH_ICH_SYNC#

17 2 SM_RCOMP_VOL 1 C473 1 C474 SC2D2U6D3V3MX-1-GP R358 1KR2F-3-GP 1

MISC

2

-13D3V_S0 1

BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2

NC#BJ51 NC#BK51 NC#BK50 NC#BL50 NC#BL49 NC#BL3 NC#BL2 NC#BK1 NC#BJ1 NC#E1 NC#A5 NC#C51 NC#B50 NC#A50 NC#A49 NC#BK2

CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF

AM49 AK50 AT43 CLPWROK_MCH R156 1 2 0R0402-PAD AN49 AM50 MCH_CLVREF -1

CL_CLK0 17 CL_DATA0 17 PWROK 17,20 CL_RST#0 17 C209 SCD1U10V2KX-4GP

CRT_IREF routing Trace width use 20 mil1D8V_S3 R353 1KR2F-3-GP 2 1

1

UMALIBG 2K4R2F-GP R154 1 2

GMCH_GREEN

UMAGMCH_VS R153G72 1 2 0R2J-2-GP R148 1 2 0R2J-2-GP

1

1

GMCH_RED SM_RCOMP_VOH 1 C465 SC2D2U6D3V3MX-1-GP

1

SDVO_CTRL_CLK SDVO_CTRL_DATA CLKREQ# ICH_SYNC# TEST1 TEST2

H35 K36 G39 G40

CLK_3GPLLREQ#

C468 R356 3K01R2F-3-GP SCD01U16V2KX-3GP

1

R157 392R2F-GP 2

2

2

1

2

R141 10KR2J-3-GP 2

2

NC NC

G72FOR Discrete change R137, R139 & R142 to 0 ohm

GMCH_HS

G723D3V_S0

SBR128 2 150R2F-1-GP 1 R129 2 150R2F-1-GP 1 R130 2 150R2F-1-GP 1 TV_DACA TV_DACB TV_DACC LCTLB_DATA LCTLA_CLK PM_EXTTS#0 PM_EXTTS#1 1 2 3 4 RN20

A37 R32 TEST2_GMCH R135 20KR2J-L2-GP

SCD01U16V2KX-3GP

UMA UMA UMA

CRESTLINE-GP-U 2

8 7 6 51

SRN10KJ-6-GP

1

CLK_3GPLLREQ#


GMCH (2 of 6)Size Document Number Rev

Columbia/TangizDate: Monday, February 26, 2007A B C D E

-145

Sheet

7

of

A

B

C

D

E

4

4

U48D 4 OF 10 12 M_A_DQ[63..0] M_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 U48E 5 OF 10

M_A_A[14..0] M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 SA_RCVEN# TP42 TPAD30

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_RAS# SA_RCVEN# SA_WE#

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BJ29 BE18 AY20 BA19

M_A_A[14..0] 12,13

DDR SYSTEM MEMORY B

3

2

AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2 SA_CAS# SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

BB19 BK19 BF29 BL17 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS[7..0] M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DM[7..0]

M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS#

12,13 12,13 12,13 12,13

12 M_B_DQ[63..0]

M_B_DQ[63..0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_A_DM[7..0] 12

M_A_DQS[7..0] 12

M_A_DQS#[7..0]

M_A_DQS#[7..0] 12

M_A_RAS# 12,13 M_A_WE# 12,13

Place Test PAD Near to Chip as could as possible

AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2 SB_CAS# SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_RAS# SB_RCVEN# SB_WE#

AY17 BG18 BG36 BE17 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 BE24 AV16 AY18 BC17M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS[7..0] M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 SB_RCVEN# M_B_DM[7..0]

M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS#

12,13 12,13 12,13 12,13

M_B_DM[7..0] 12

M_B_DQS[7..0] 12

DDR SYSTEM MEMORRY A

M_B_DQS#[7..0]

M_B_DQS#[7..0] 123

M_B_A[14..0]

M_B_A[14..0] 12,13

M_B_RAS# 12,13 TP41 TPAD30 M_B_WE# 12,132

Place Test PAD Near to Chip ascould as possible

CRESTLINE-GP-U CRESTLINE-GP-U

1

1




-145

SheetE

8

of

A

B

C

D

E

VCC_NCTF + VCC=1573mA1D05V_S0 U48F 6 OF 10

FOR VCC CORE AND VCC NCTFT17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y311D05V_S0 SB 1D05V_S0 U48G 7 OF 10

1573mA

C62 SCD1U10V2KX-4GP 2 1


VCC CORE

SB:Remove R123,R132,R136,R144

DYST220U2D5VBM-2GP

TC8

C116 SC10U6D3V5MX-3GP


C155 SCD1U10V2KX-4GP

4

AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

-1 R143 2VCC_GMCH1R30 1 0R0402-PAD

VCC

1D8V_S3

POWERAU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM

3138mA

3

2

1D05V_S0

SC1U10V3KX-3GP 2 1 C212

C150 SCD22U10V2KX-1GP 2 1 C191




SC1U10V3KX-3GP

1

SCD1U10V2KX-4GP 2 1

SCD1U10V2KX-4GP 2 1

1


1

1

1

1


1

C129

C210

SCD1U10V2KX-4GP

UMA

UMA




R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14

VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

Coupling CAP

1D05V_S0

FOR VCC CORE






VCC_AXG_NCTF + VCC_AXG=7700mA



2

2

VCC NCTF

1

1

VSS NCTF

308 mils from the Edge

UMAC161 SCD1U10V2KX-4GP

Coupling CAP 370 mils from the Edge

VCC GFX NCTF

2

UMA

2



UMA

1

VSS AXM


1


AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37

-1

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

1

1

1

1

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28

2

2

2

2

4

POWERVSS SCBVSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB A3 B2 C1 BL1 BL51 A51

3

VCC SM

1

1

VCC_AXM_S3

UMA2

UMA2

FOR VCC AXM NCTF AND VCC AXM1D05V_S0 VCC_AXM_S3







1

1

1

1 R147 2 0R1206-PAD

Coupling CAP

SB:DIS remove 0 ohm on C129,C210,C158,C161

Place on the Edge

VCC_AXM_NCTF + VCC_AXM=540mA

VCC GFX

AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33

VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF

VSS AXM NCTF

2

2

2

2

CRESTLINE-GP-U

VCC SM LF

1 C202

VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF

AW45SM_LF1_GMCH BC39 SM_LF2_GMCH BE39 SM_LF3_GMCH BD17 SM_LF4_GMCH BD4 SM_LF5_GMCH AW8 SM_LF6_GMCH AT6 SM_LF7_GMCH 1

Place CAP where LVDS and DDR2 taps

FOR VCC SM1D8V_S3

SCD47U16V3ZY-3GP

Place on the Edge

1

2

2

DY


C184

ST220U4VDM-23GP ST220U4VDM-23GP TC11

2

2

2

2

2

CRESTLINE-GP-U

2


Columbia/TangizDate: Monday, February 26, 2007 SheetE

-145

9

of

A

B

C

D

A

B

C

D

E

1D05V_S0

Place on the edgeC119 SC4D7U6D3V3KX-GP 2 1 C121 SC4D7U6D3V3KX-GP 2 1 C120 SC4D7U6D3V3KX-GP 2 1

1

1

3D3V_S0

1D25V_S0

-11 1 2 R162 1 0R0603-PADSC10U6D3V5MX-3GP4

2

2

2

M_VCCA_DPLLA C223 C222 SCD1U10V2KX-4GP

1

10mAR119 G72 0R2J-2-GP 1 2

R118 UMA 0R2J-2-GP

U48H 8 OF 10

UMA23D3V_SYNC_S0 C159 UMA 3D3V_CRTDAC_S0 SCD1U10V2KX-4GP

J32 A33 B33

VCC_SYNC VCCA_CRT_DAC VCCA_CRT_DAC VCCA_DAC_BG

1

1

2 R398 1 0R0603-PADSC10U6D3V5MX-3GP

M_VCCA_DPLLB C513 C527 SCD1U10V2KX-4GP 3D3V_S0

2

2

2 R362 1 0R2J-2-GP

M_VCCA_DAC_BG A30

1D25V_S0

1D25V_SUS_MCH_PLL2

1

2 R359 1M_VCCA_DAC_BG 0R3-0-U-GP

5mA 80mA M_VCCA_DPLLA 80mA M_VCCA_DPLLB 50mA M_VCCA_HPLL 150mA M_VCCA_MPLL0R2J-2-GP 1 21D8V_TXLVDS R393 UMA 0R2J-2-GP 2 1 R383

VTT

180ohm 100MHzUMAC472

G72

B32

VSSA_DAC_BG

UMAR100 0R0603-PAD

1

1

2

SCD1U10V2KX-4GP

2

2

1

AL2 AM2 A41 B41 K50 K49

VCCA_HPLL VCCA_MPLL VCCA_LVDS VSSA_LVDS VCCA_PEG_BG VSSA_PEG_BG

SC1U10V3KX-3GP

1 C173

G721D8V_TXLVDS_S3

PLL

R357 0R2J-2-GP

B49 H49

VCCA_DPLLA VCCA_DPLLB

1

1

C428

C429

1

C509 C437 SCD1U10V2KX-4GP 3D3V_S0 SC1KP50V2KX-1GP -1 2 R395 1 0R0402-PAD

UMA2

A LVDS

FCM1608KF-1-GP 1 2 L10 SC10U6D3V5MX-3GP

120ohm 100MHzM_VCCA_HPLL SC10U6D3V5MX-3GP

10mA

POWERAXD

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

1

U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 AT23 AU28 AU24 AT29 AT25 AT30 AR29 B23 B21 A21 AJ50

2

2

1D25V_SUS_AXD

2

UMA C475 SCD1U10V2KX-4GP

1

180ohm 100MHz2 R361 1 0R3-0-U-GP


1

3D3V_CRTDAC_S0


C66 SCD1U10V2KX-4GP

80mA

C123 SC2D2U6D3V3MX-1-GP 2 1

850mA

1D25V_S0

4

200mASC1U10V3KX-3GP

1

2 R145 1 0R0603-PAD 1 C174 1-1 C177 SC10U6D3V5MX-3GP

CRT

2

2

1D25V_S0

350mA

2

2


A PEG

1

120ohm 100MHz


2

1D25V_S0

VCC_AXD_NCTF VCC_AXF VCC_AXF VCC_AXF VCC_DMI VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK

1D8V_SUS_SM_CK

2

3

FCM1608KF-1-GP 1 2 L9

M_VCCA_MPLL

1

400uA

C516 SCD1U10V2KX-4GP 1D25V_RUN_PEGPLL SC1U10V3KX-3GP

1

3D3V_RUN_PEG_BG

100mA


G72

VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD

1D25V_S0

2

2

2

2

-1 1D8V_S3

3

2

U51 AW18 AV19 AU19 AU18 AU17 AT22 AT21 AT19 AT18 AT17 AR17 AR16 BC29 BB29

VCCA_PEG_PLL VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM

200mA

1

1

1

1


1

1D25V_S0




SC1U10V3KX-3GP

1 C154

1 C148

AXF

2 R140 1 0R0603-PAD

220ohm 100MHz1L13 BLM18BB221SN1D-GP 1D25V_RUN_PEGPLL 2


DY2

2

2

2

2

2

A SM

SCD1U10V2KX-4GP C508

1D25V_S0

SC1U10V3KX-3GP



VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM_NCTF VCCA_SM_NCTF VCCA_SM_CK VCCA_SM_CK VCCA_TVA_DAC VCCA_TVA_DAC VCCA_TVB_DAC VCCA_TVB_DAC VCCA_TVC_DAC VCCA_TVC_DAC VCCD_CRT VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS VCCD_LVDS

SM CK

BK24 BK23 BJ24 BJ23

1

1D8V_TXLVDS_S3

2

100mA

1 C164

2

1D8V_S3 R394 0R3-0-U-GP UMA 1 0R2J-2-GP 2 1

2

1

1

VCC_TX_LVDS

A43 C40 B40 AD51 W50 W51 V49 V50 AH50 AH51 A7 F2 AH1VTTLF1 VTTLF2 VTTLF3

3D3V_HV_S0

2

2

2

2

3D3VTVDAC

3D3V_S0

A CK

L11 UMA 1 2 HCB1608K-181T20GP

HV

180ohm 100MHz -112

VCC_HV VCC_HV VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG

100mA

C199 SC1KP50V2KX-1GP

1

G721D05V_S0

R392

M_VCCA_TVDACA

1

2 R349 1 0R0402-PAD

1

C439

1

M_VCCA_TVDACA C461 C460

2

2

SCD1U10V2KX-4GP

UMA

UMA

SC2D2U6D3V3MX-1-GP

TV/CRT

VTTLF

1

2

2

2

1


SCD1U10V2KX-4GP

UMA

UMA

SC2D2U6D3V3MX-1-GP


R160

0R0402-PAD

U48 J41 H42

LVDS

1

1



2

2

1

C466

1

C467

2

2 R351 1 0R0402-PAD

M_VCCA_TVDACC

150mA


2

1

-1

2

2

SCD1U10V2KX-4GP

UMA

UMA

1D05V_S0 D31

SC2D2U6D3V3MX-1-GP

CRESTLINE-GP-U

200608091D5V_S0 -1 1D5VRUN_TVDAC

2

1

1



2

1

2

2

R151 0R2J-2-GP

G72

SCD1U10V2KX-4GP

R377

2

2 R150 1 0R0603-PAD

2 R146 1 0R3-0-U-GP

UMA

2 R376 11D8V_SUS_DLVDS 0R3-0-U-GP C198 1VCCD_CRT 0R2J-2-GP 2 1

UMA

2 3


UMA

UMA

2

BAT54-7-F-GP


1D8V_S3

1

1

1

3D3V_S0 -1 10R2J-2-GP 1D05V_HV_S0 2 1 2 R372 1 R399 0R0402-PAD

2

C464

1

2 R352 1 0R0402-PAD

M_VCCA_TVDACB

FOR Discrete change C461, C464, C466 to 0 ohmC463

1D5VRUN_TVDAC 1D5VRUN_QDAC

1D25V_SUS_MCH_PLL2

5mA 1D25V_SUS_MCH_PLL2 250mA 100mA2PEGPLL_R 1D25V_RUN_PEGPLL 1

DMI

60mA

40mA M_VCCA_TVDACB 40mA M_VCCA_TVDACC 40mA 60mA VCCD_CRT

C25 B25 C27 B27 B28 A28 M32 L29 N28 AN2

TV

1200mASC10U6D3V5MX-3GP C146 SC10U6D3V5MX-3GP 1D05V_S02

PEG

2

VCC_RXR_DMI VCC_RXR_DMI VTTLF VTTLF VTTLF

250mA

1

2


1


3D3V_HV_S0

1

G721L2 UMA 1 2 HCB1608K-181T20GP 180ohm 100MHzC172


1D5VRUN_QDAC C166

2

2

SC10U6D3V5MX-3GP

UMA

UMA

FOR Discrete change C166 to 0 ohm

1

1

Title


SCD1U10V2KX-4GP


-145

SheetE

10

of

5

4

3

2

1

U48I

9 OF 10

D

C

B

A

A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

U48J10 OF 10

C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

D

VSS VSS VSS VSS VSS VSS VSS VSS

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

C

VSS

B

CRESTLINE-GP-UA


CRESTLINE-GP-U


Columbia/TangizDate: Monday, February 26, 20075 4 3 2

-145

Sheet1

11

of

A

B

C

D

E

DM1 DM2 8,13 M_B_A[14..0] M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_ODT2 M_ODT3 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 11 29 49 68 129 146 167 186 13 31 51 70 131 148 169 188 114 119 1 2 202 MH1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 OTD0 OTD1 VREF VSS GND MH1 DDR2-200P-22-GP-U1 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL VDDSPD SA0 SA1 NC#50 NC#69 NC#83 NC#120 NC#163/TEST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GND MH2 108 109 113 110 115 79 80 30 32 164 166 10 26 52 67 130 147 170 185 195 197 199 198 200 50 69 83 120 163 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 201 MH2 DDRB_SA02 R68 10KR2J-3-GP 1 1 2 SCD1U16V2ZY-2GP C48 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 8,13 M_A_A[14..0] M_B_RAS# 8,13 M_B_WE# 8,13 M_B_CAS# 8,13 M_CS2# 7,13 M_CS3# 7,13 1 M_CKE2 7,13 M_CKE3 7,13 M_CLK_DDR2 7 M_CLK_DDR#2 7 M_CLK_DDR3 7 M_CLK_DDR#3 7 M_B_DM[7..0] 8 1 2 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 MH1 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 50 69 83 120 163 7,13 7,13 7,13 7,13 8,13 8,13 8,13 M_CS0# M_CS1# M_CKE0 M_CKE1 M_A_RAS# M_A_CAS# M_A_WE# SMBC_ICH SMBD_ICH M_ODT0 M_ODT1 110 115 79 80 108 113 109 197 195 114 119 1 1 1 C195 MH1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 MH2 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 CK0 CK0# CK1 CK1# SA0 SA1 VDD_SPD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GND MH2 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 10 26 52 67 130 147 170 185 30 32 164 166 198 200 199 81 82 87 88 95 96 103 104 111 112 117 118 2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 202 1 C49 SCD1U16V2ZY-2GP M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS[7..0]

8

Place near DM1M_CLK_DDR0 1

Place near DM2M_CLK_DDR3

4

SC10P50V2JN-4GP M_CLK_DDR#3 M_CLK_DDR2

M_A_DQS#[7..0]

8

2

DY EC5

DY EC72SC10P50V2JN-4GP M_CLK_DDR#0 M_CLK_DDR14

1 M_A_DM[7..0] 8 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1 7 7 7 7 3D3V_S0 2

8,13 8,13 8,13

TPAD30 TP32 M_B_BS#2 M_B_BS#0 M_B_BS#1

DY EC73SC10P50V2JN-4GP M_CLK_DDR#2 8,13 8,13 8,13 M_A_BS#2 M_A_BS#0 M_A_BS#1

DY EC6SC10P50V2JN-4GP M_CLK_DDR#1

TPAD30 TP33

8 M_B_DQ[63..0]

2

8 M_A_DQ[63..0] SMBD_ICH 3,19 SMBC_ICH 3,19

3D3V_S0

3

NORMAL TYPE

2

3

NORMAL TYPE

1D8V_S3

1D8V_S3

2

2

8 M_B_DQS#[7..0]

NC#50 NC#69 NC#83 NC#120 NC#163/TEST CS0# CS1# CKE0 CKE1 RAS# CAS# WE# SCL SDA ODT0 ODT1 VREF GND

8 M_B_DQS[7..0]

DDR_VREF_S3 7,13 7,13

DDR_VREF_S31

7,13 7,13

1

C197 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

C196

DY

1

1

C194

201

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number

2

2

SKT-SODIMM20020U3GP

2

2

62.10017.661

62.10017.A61

High 5.2mmD

DDR2 Socket Columbia/TangizSheet 12 ofE

Rev

High 9.2mmB C

-145


A

A

B

C

D

E

DDR_VREF_S0

PARALLEL TERMINATIONRN13

8 7 6 5

1 2 3 4

M_A_A12 M_A_A8

Put decap near power(0.9V) and pull-up resistorM_CKE0 7,12 M_A_BS#2 8,12

Decoupling CapacitorDDR_VREF_S0

4

1

1

1

1

1

1

1

1

1

1





C103 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP




C97 SCD1U16V2ZY-2GP


1

8 7 6 5

SRN56J-5-GP RN12 M_B_A8 1 2 M_B_A9 3 M_B_A5 4 SRN56J-5-GP RN14 1 2 M_B_A12 3 4 SRN56J-5-GP RN7 1 2 3 4

Put decap near power(0.9V) and pull-up resistor4


2

2

2

2

2

2

2

2

2

2

8 7 6 5

M_CKE3 7,12 M_B_BS#2 8,12 M_CKE2 7,12

DY

DY

DY

1

1

1

1

1

1

1

1

1

1



C98 SCD1U16V2ZY-2GP






C99 SCD1U16V2ZY-2GP


1 2

8 7 6 5

M_B_A3 M_B_A1 M_B_A10 M_B_WE# 8,12

M_A_A[14..0] M_B_A[14..0]

M_A_A[14..0] 8,12 M_B_A[14..0] 8,12 C102 SCD1U16V2ZY-2GP

8 7 6 5

SRN56J-5-GP RN1 1 M_B_A13 2 3 4 SRN56J-5-GP RN5

2

2

2

2

2

2

2

2

2

DY

DY

DY

M_ODT2 7,12 M_ODT3 7,12 M_B_RAS# 8,12

3

8 7 6 5

1 2 3 4SRN56J-5-GP RN9

M_B_A2 M_B_A0 M_B_A4

M_B_BS#1 8,12 1D8V_S3

2

2

Place these Caps near DM11 1 1C446 SC2D2U6D3V3MX-1-GP C436 SC2D2U6D3V3MX-1-GP C432 SC2D2U6D3V3MX-1-GP C424 SC2D2U6D3V3MX-1-GP

3

1

1 2SCD1U16V2ZY-2GP

C417 SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP

8 7 6 5

1 2 3 4SRN56J-5-GP RN4

M_B_A14 M_B_A11 M_B_A7 M_B_A6

2

2

2

1

1

1




SRN56J-5-GP

2

2

2

RN3

8 7 6 52

1 2 3 4SRN56J-5-GP RN8

M_A_A13 M_ODT0 7,12 M_CS0# 7,12 M_A_RAS# 8,12

DY

DY

DY

DY

2

1

8 7 6 5

1 2 3 4

M_B_BS#0 8,12 M_B_CAS# 8,12 M_CS3# 7,12 M_CS2# 7,12

2C442

2

8 7 6 5

1 2 3 4SRN56J-5-GP

M_A_A0 M_A_A2 M_A_A4

M_A_BS#1 8,12 1D8V_S3

Place these Caps near DM21 1 1 1C447 SC2D2U6D3V3MX-1-GP C440 SC2D2U6D3V3MX-1-GP C433 SC2D2U6D3V3MX-1-GP C426 SC2D2U6D3V3MX-1-GP

RN2

1 2

C418 SC2D2U6D3V3MX-1-GP

8 7 6 5

1 2 3 4SRN56J-5-GP RN10 M_A_A9 M_A_A14 M_A_A5 M_A_A3

M_A_CAS# 8,12

2

2

2

M_ODT1 7,12 M_CS1# 7,12

1

1

1




1DY

8 7 6 5

1 2 3 4SRN56J-5-GP

2 2


2

2

RN11

1

8 7 6 5

1 2 3 4SRN56J-5-GP RN6

M_A_A6 M_A_A7 M_A_A11 M_CKE1 7,12

DY

DY

DY

2

1


8 7 6 5

1 2 3 4SRN56J-5-GP

M_A_A1 M_A_A10

M_A_BS#0 8,12 M_A_WE# 8,12 Size

DDR2 Termination ResistorDocument Number Rev


-145

SheetE

13

of

LCDVDD U38 R297 7 GMCH_LCDVDD_ON UMA 1 0R2J-2-GP

3D3V_S0

1

2

LCDVDD_ON_1 SCD1U16V2ZY-2GP 2 1 SC1U16V3ZY-GP SC1U16V3ZY-GP

1

1 2 3 4C354

IN#1 OUT EN GND

2

C353

GND IN#8 IN#7 IN#6 IN#5

9 8 7 6 5

Q29 GND 2 C359 32 FRONT_PWRLED IN R2 SC1U16V3ZY-GP

SB3 OUTR1

1

3D3V_S0

G5281RC1U-GP

84.00143.B1K CHDTC143ZUPT-GP

2

3D3V_S0

SBR524 LED-GY-14-GP 1 2FRONT_PWRLED#_R 3 100R2J-2-GP R523 STDBY_LED#_R 1 2 4 100R2J-2-GP LED2 3D3V_S5

1R336 DY 10KR2J-3-GP

33 FRONT_PWRLED#_Q D39 5V_S0 3D3V_S0 U37 LCDVDD LCDVDD_ON_1 33 STDBY_LED#_Q

1 2

2

DY2

D

WLAN_LED# 3 Q19 2N7002-11-GP

1 2 3

1 1R344 1KR2J-1-GP BAV99-5-GP D13

DY IN OUT GND GND ON/OFF# INAAT4280IGU-3-T1GP

6 5 4

SB

Q30 GND 2 R2

28 NV_LCDVDD_ON

G

DY

3 OUTR1

G722

S

DY2

32

STDBY_LED

IN

1

84.00143.B1K CHDTC143ZUPT-GP Q14

BT_LED

3 1BAV99-5-GP GND 2

5V_S0

LCD/INVERTER CONNLCDVDD LCD1

32

BT_LED

IN

1

R2 R1 84.00143.B1K CHDTC143ZUPT-GP

3 OUT

R295 1 2 BLT_LED#_1_R 100R2J-2-GP

LED6 2

LED-B-27-U-GP 1

3D3V_S5 Q13 GND 2 C357 C356 SCD1U25V3ZY-1GP C355

SBR2

LED4

USB_6USB_6+

41 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

DY

DY32 CHARGE_LED IN

3 OUTR1

1 2 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2

2

SC10U10V5ZY-1GP

SCD1U25V3ZY-1GP

1

84.00143.B1K CHDTC143ZUPT-GP

R527 CHARGE_LED#_R 1 2 100R2J-2-GP R526 1 2 DC_BATFULL#_R 100R2J-2-GP

1

1

1

4 3LED-GY-14-GP

2 1

3D3V_S0 NV_EDID_CLK NV_EDID_DAT CCD_PWR BRIGHTNESS_CN BLON_OUT DCBATOUT

SB

EC61 SCD1U50V3ZY-GP SCD1U50V3ZY-GP

F2 1 2 FUSE-3A32V-8-GP 69.43001.111

LCD_TXBCLK+ LCD_TXBCLKLCD_TXBOUT2+ LCD_TXBOUT2LCD_TXBOUT1+ LCD_TXBOUT1LCD_TXBOUT0+ LCD_TXBOUT0LCD_TXACLK+ LCD_TXACLKLCD_TXAOUT2+ LCD_TXAOUT2LCD_TXAOUT1+ LCD_TXAOUT1LCD_TXAOUT0+ LCD_TXAOUT0-

ER1 2 ER2 2 ER3 2 ER4 2

DY DY DY DY

0R2J-2-GP 1 0R2J-2-GP 1 0R2J-2-GP 1 0R2J-2-GP 1 0R2J-2-GP 1 0R2J-2-GP 1 0R2J-2-GP 1 0R2J-2-GP 1 29 WLAN_LED# 32 DC_BATFULL Q28 GND 2 R2 IN

3 OUTR1

ER5 DY 2 ER6 2 ER7 2 ER8 2

1

DY DY DY

84.00143.B1K CHDTC143ZUPT-GP 3D3V_S0

-1R589 1 2 33R2J-2-GP 2N7002-11-GP R294

C372

1

2

WLAN_LED#_R

LED1 2

LED-Y-29-GP 1

1 1

2 2

SB

75R2J-1-GP Q32

83.00190.S70

S

3D3V_S0

4 3 2 1RN46 SRN2K2J-2-GP R343 1

1

0R0402-PAD

UMA2 0R2J-2-GP

2

5 6 7 8

CCD_PWR

SC10U35V0ZY-GP

DY

20.F0993.04032 WLAN_TEST_LED

D

ACES-CONN40A-2GP

3D3V_S0

G

-1

R299

F1

FUSE-1A6V-2-GP 3D3V_CCD 1 2 U39 C362 SC4D7U10V5ZY-3GP 1 DY 2 CCD_ON 32 28 28 28 28 LCD_TXBOUT1LCD_TXBOUT1+ LCD_TXBOUT0LCD_TXBOUT0+ RN18 LCD_TXBOUT1LCD_TXBOUT1+ LCD_TXBOUT0LCD_TXBOUT0+

7 CLK_DDC_EDID 28 NV_EDID_CLK

NV_EDID_CLK



1

2

1

DY2


SRN0J-7-GP RN19 28 LCD_TXBCLK28 LCD_TXBCLK+ 28 LCD_TXBOUT228 LCD_TXBOUT2+ LCD_TXBCLKLCD_TXBCLK+ LCD_TXBOUT2LCD_TXBOUT2+

UMA8 7 6 5GMCH_TXBCLK- 7 GMCH_TXBCLK+ 7 GMCH_TXBOUT2- 7 GMCH_TXBOUT2+ 7

-1USB_6USB_6+ 0R0402-PAD 1 R306 0R0402-PAD 1 R307

1 2 3 4

2 2

USBPN6 USBPP6

17 17 28 LCD_TXACLK28 LCD_TXACLK+ 28 LCD_TXAOUT228 LCD_TXAOUT2+ L_BKLTCTL 7 BRIGHTNESS 32 BLON_OUT 32 28 28 28 28 LCD_TXAOUT1LCD_TXAOUT1+ LCD_TXAOUT0LCD_TXAOUT0+ LCD_TXACLKLCD_TXACLK+ LCD_TXAOUT2LCD_TXAOUT2+

SRN0J-7-GP RN17

UMA8 7 6 5GMCH_TXACLKGMCH_TXACLK+ GMCH_TXAOUT2GMCH_TXAOUT2+ 7 7 7 7

-1R302 2 BRIGHTNESS_CN BLON_OUT SC100P50V2JN-3GP 2 1 SC100P50V2JN-3GP 2 1 C369 C368 R300 2 10KR2J-3-GP

DY

1 2 3 4

1 0R2J-2-GP 1 0R2J-2-GP 1R301

SRN0J-7-GP RN16 LCD_TXAOUT1LCD_TXAOUT1+ LCD_TXAOUT0LCD_TXAOUT0+

2

G5240B1T1U-GP

1 2 3 4

8 7 6 5

GMCH_TXBOUT1GMCH_TXBOUT1+ GMCH_TXBOUT0GMCH_TXBOUT0+

7 7 7 7

28 NV_EDID_DAT

2

2

EC69 DY SCD1U16V2ZY-2GP

1

1 2 3

OUT DY IN GND NC#3 EN

5 4

7 DAT_DDC_EDID

R342 1

UMA2 0R2J-2-GP

NV_EDID_DAT EC70 DY SCD1U16V2ZY-2GP

1

1

UMA

UMA8 7 6 5GMCH_TXAOUT1GMCH_TXAOUT1+ GMCH_TXAOUT0GMCH_TXAOUT0+ 7 7 7 7 Title


1 2 3 4

2

SRN0J-7-GP

LCD CONN & LEDSize Date: Document Number Rev

Columbia/TangizMonday, February 26, 2007 Sheet 14 of 45

-1

A

B

C

D

E

Layout Note: Place these resistors close to the CRT-out connector 28 7 284

CRT I/F & CONNECTORFerrite bead impedance: 10 ohm@100MHzL8 CRT1 CRT_R CRT_R CRT_G DAT_DDC1_5

17 MH1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 MH2 16VIDEO-15-21-U4-GP CLK_DDC1_54

NV_RED GMCH_RED NV_GREEN

1 1 R113

2 FCB1608CF-GPL7

UMA

2

0R2J-2-GP

1 1 R112

2 FCB1608CF-GPL6

7 GMCH_GREEN 28 7 NV_BLUE

0R2J-2-GP

1

UMA

2

CRT_G CRT_HSYNC1 5V_CRT_S0 C419 SCD01U16V2KX-3GP C414 SC100P50V2JN-3GP

C415 SC100P50V2JN-3GP CRT_B CRT_VSYNC1

2

1 2 15V_S0

1 1 1 1 1 1 1SC22P50V2JN-4GP SC22P50V2JN-4GP SC22P50V2JN-4GP SC22P50V2JN-4GP

1

1

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

GMCH_BLUE

1

2

2

2

2

2

DY

DY

DY

SC

UMA

UMA

UMA

2

C405 SC18P50V2JN-1-GP

2

2

2

Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

For DIS C420--->78.15034.1FL C413,C409--->78.18034.1FL

2

20.20334.015

D1 R321 32 CRT_DEC#

5V_S0

2 1CRT_DEC_R 1C404 SC100P50V2JN-3GP

2

3

DY1BAV99-5-GP3

470R2J-2-GP3

Hsync & Vsync level shift5V_S0

2

2

1

2

4 3 2 1

3D3V_S0 RN44 SRN2K2J-2-GP

7 GMCH_HSYNC 28 NV_HSYNC

R363 1 2 0R2J-2-GP

UMA

14

5 6 7 8

7 GMCH_VSYNC 28 NV_VSYNC

R364 1 2 0R2J-2-GP

UMA

Q16 R366 1

1 2 3 4

2 14

1

-1

8 7 6 5


1

3D3V_S0

5V_CRT_S0

CH751H-40PT D23 3D3V_S0

SRN10KJ-6-GP RN43

4

7

CRT_HSYNC1_R 1 R324 2CRT_HSYNC1 0R0402-PAD U44A 28 NV_DDCDAT TSAHCT125PW-GP

3

CRT_DEC#

7 GMCH_DDCDATA

2 0R2J-2-GP

UMA

NV_DDCDAT

4 5 6

3 2 12N7002DW-1-GP

DAT_DDC1_5

5 1 1SC18P50V2JN-1-GP SC18P50V2JN-1-GP 7

6

CRT_VSYNC1_R

R322 2CRT_VSYNC1 1 0R0402-PAD 28 NV_DDCCLK 7 GMCH_DDCCLK R365 1

U44B TSAHCT125PW-GP

2

C412DY

2

C408

DY

2 0R2J-2-GP

UMA

NV_DDCCLK CLK_DDC1_52

2

DDC_CLK & DATA level shiftC565

TV CONN28 NV_TV_LUMA

1

2 SC33P50V2JN-3GP 1LUMA_1

8

1

1

2

7

TV_DACB

SC150P50V2JN-3GP C545

2

R115 UMA 0R2J-2-GP 1 2

1

L17 1 2 IND-1D2UH-5-GP C570


R430 150R2F-1-GP

4 2 5 7 6 3 9

5V_S0 D11 D5

5V_S0

2LUMA_1

2CRT_R 3

3

DY1BAV99-5-GP D8

DY1BAV99-5-GP D3

2

1

2 SC33P50V2JN-3GPCRMA_1

MINDIN7-22-GP TVOUT1

28 NV_TV_CRMA

1

1

2

71

TV_DACC

SC150P50V2JN-3GP C554

2

2

R116 UMA 0R2J-2-GP 1 2

1

L15 1 2 IND-1D2UH-5-GP C544

22.10021.I81CRMA_1

2 3

2CRT_G 3


R413 150R2F-1-GP

DY1BAV99-5-GP D9

DY1BAV99-5-GP D2

2

1 R111

UMA

2

R328 150R2F-1-GP

R325 150R2F-1-GP

R323

C416

C411

C407

C420

C413

1

2 FCB1608CF-GP

CRT_B C409

C406 SC18P50V2JN-1-GP

150R2F-1-GP

0R2J-2-GP

-1

1

1

2 SC33P50V2JN-3GPCOMP_1 COMP_1

2 3

2CRT_B 3

28 NV_TV_COMP

1

1

2

7

TV_DACA

SC150P50V2JN-3GP

2

R114 UMA 0R2J-2-GP 1 2

1

L16 1 2 IND-1D2UH-5-GP C558

DY1BAV99-5-GP

DY1BAV99-5-GP Title Size Document Number



R423 150R2F-1-GP

CRT/TV Connector Columbia/TangizSheetE

2

Rev

-1of 45


15

A

B

C

D

E

C503 SC12P50V2JN-3GP 1 2

RCT_X1

SB33D3V_AUX_S5 D30 X-32D768KHZ-38GPU RTC_AUX_S5 SC1U16V3ZY-GP

1R391 10MR2J-L-GP

X1

2 34

2

1

4 2

1

4

1RTC_BAT_R

C495

2

1D05V_S0

RTC circuitryRTC1

RCT_X2

AG25 AF24 AF23

SBPWR GND NP1 NP2

RTCX1 RTCX2

RTC

2

1

R408

C528 20 INTRUDER#

1

2

BAT-CON2-1-GP

DY C511 SCD1U16V2ZY-2GP

INTVRMEN LAN100_SLP

AF25 AD21 B24

LPC

RTC_BAT 1 2 NP1 NP2

1R384

1

2 1MR2J-1-GP

INTRUDER# AD22

INTRUDER# INTVRMEN LAN100_SLP GLAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GLAN_DOCK#/GPIO13 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#

FWH4/LFRAME# LDRQ0# LDRQ1#/GPIO23 A20GATE A20M#

C4 G9 E6 AF13 AG26 AF26 AE26 AD24 AG29 AF27 AE24 AC20 AH14 AD23 AG28 AA24 AE27 AA23 V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6 AA4 AA1 AB3 Y6 Y5 W4 W3 Y2 Y3 Y1 W5H_DPRSTP# 3D3V_LDRQ1_S0

LPC_LFRAME# 32,34 LDRQ0# 32 TP138 TPAD30 KA20GATE 32 H_A20M# 4 H_DPRSTP# 4,7,37 H_DPSLP# 4

H_DPSLP#

1D05V_S0

TPAD30

TP120

LAN_RSTYNC

1

D22 C21 B21 C22

LAN/GLAN

62.70001.011

DPRSTP# DPSLP# FERR# CPUPWRGD/GPIO49 IGNNE# INIT# INTR RCIN# NMI SMI# STPCLK# THRMTRIP#

R397 56R2J-4-GP

2

2

2 1KR2J-1-GP

R406 1

2 20KR2J-L2-GPSC1U16V3ZY-GP

RTC_RST#

RTCRST#

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

E5 F5 G8 F6

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

1

BAS40CW-GP

C525 SC12P50V2JN-3GP 1 2

U12A 1 OF 6

LPC_LAD[0..3]

LPC_LAD[0..3]

32,34 R385 56R2J-4-GP

DY

H_FERR# 4 H_PWRGD 4,33,35 H_IGNNE# 4 H_INIT# 4 H_INTR 4 KBRCIN# 32 R373 H_NMI 4 H_SMI# 4 H_STPCLK# 4 H_THERMTRIP_R ICH_TP8 TP117 TPAD30 IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 H_PWRGD R370 200R2F-L-GP 1 2 1D05V_S0

GLAN_COMP place within 500 mil of ICH8MEC101 SB 1 2 SC12P50V2JN-3GP3

1D5V_S0 GLAN_DOCK# 33R2J-2-GP R166 1

D21 E20 C20 AH21 D25 C25 AJ16 AJ15 AE14 AJ17 AH17 AH15 AD13

DY

22 ACZ_BTCLK_MDC 30 ACZ_BITCLK 22,30 ACZ_SYNC 22,30 ACZ_RST# 30 ACZ_SDATAIN0 22 ACZ_SDATAIN1 3D3V_S0 TPAD30 TP129 TPAD30 TP130

ACZ_BIT_CLK 1 2 R167 33R2J-2-GP ACZ_SYNC_R 1 R168 2 -1 0R0402-PAD SB ACZ_RST#_R 1 2 R420 39R2J-L-GP ACZ_SDIN2 ACZ_SDIN3 R419 1

CPU

2

SB

1 R390

2 GLAN_COMP 24D9R2F-L-GP

3

1 2 24D9R2F-L-GP

DY

PM_THRMTRIP-A# 4,7,35 1D05V_S0

R379 1

2

IHDA

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT

TP8 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DA0 DA1 DA2 DCS1# DCS3# DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ

56R2J-4-GP

22,30 ACZ_SDATAOUT TPAD30 33 21 21 21 21 21 21 21 21 TP132 SATA_LED# SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1 C595 C596 C594 C593 C603 C602 C591 C592 HDA_DOCK_RST#

1 R425

DY

ACZ_SDATAOUT_R AE13 2 39R2J-L-GP HDA_DOCK_EN# 2 AE10 8K2R2J-3-GP AG14

HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED# SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS

Layout Note: R133 needs to placed within 2" of ICH7, R334 must be placed within 2" of R169 w/o stub.

AF10 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2SC3900P50V3KX-GP SC3900P50V3KX-GP SC3900P50V3KX-GP SC3900P50V3KX-GP SC3900P50V3KX-GP SC3900P50V3KX-GP SC3900P50V3KX-GP SC3900P50V3KX-GP SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C SATA_RXN1_C SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C

AF6 AF5 AH5 AH6 AG3 AG4 AJ4 AJ3 AF2 AF1 AE4 AE3

3D3V_S02

SATA

IDE

1D05V_S0

3D3V_S5

IDE_PDA0 21 IDE_PDA1 21 IDE_PDA2 21 IDE_PDCS1# 21 IDE_PDCS3# 21 IDE_PDIOR# 21 IDE_PDIOW# 21 IDE_PDDACK# 21 INT_IRQ14 21 IDE_PDIORDY 21 IDE_PDDREQ 21

2

RN49 SRN10KJ-6-GP

3 CLK_PCIE_SATA# 3 CLK_PCIE_SATA SATARBIAS

AB7 AC6 AG1 AG2

8 7 6 5

1 R445 1 2 3 4GLAN_DOCK# SATA_LED#

2 24D9R2F-L-GP

H_INIT#_G

Place within 500 mils of ICH8 ballChange to 24.9 1% ohm when use SATA HD

ICH8-M-1-GP-U

H_INIT#

E

BQ21

SB

CMMBT3904-3-GP

FWH_INIT#

34 RTC_AUX_S5 RTC_AUX_S5

1

1

1

R388 330KR2F-L-GP

R409 330KR2F-L-GP

UMA

1

integrated VccSus1_05,VccSus1_5,VccCL1_52 2INTVRMEN R381 0R2J-2-GP LAN100_SLP R403 0R2J-2-GP


INTVRMEN LAN100_SLP

High=Enable High=Enable

Low=Disable Low=DisableSize Document Number

1

1

integrated VccLan1_05VccCL1_05

DY2

DY2

ICH8-M (1 of 4) Columbia/TangizSheetE

Rev

-145


16

of

A

B

C

D

E

U12D 4 OF 6 RN27 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

4

GPIO

D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3 F9 B5 C5 A10

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PIRQA# PIRQB# PIRQC# PIRQD#

PCI

REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 GNT3#/GPIO55 REQ3#/GPIO54 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# FRAME# PLOCK# SERR# STOP# TRDY# PLTRST# PCICLK PME#

A4 D7 E18 C18 B19 F18 C10 A11 C17 E15 F16 E17

TP123 TP134 TP131 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3

TPAD30 TPAD30 TPAD30 25 25 25 25

RI# SUS_STAT#/LPCPD# SYS_RESET# BMBUSY#/GPIO0 SMBALERT#/GPIO11

32 7

PM_SUS_STAT# PM_BMBUSY#

PM_SUS_STAT# F4 DBRESET# AD15

CLOCKS

PCI_REQ#1 PCI_GNT#1 PCI_REQ#2 PCI_GNT#2 PCI_GNT#3 PCI_REQ#3

PCI_REQ#0 26 PCI_GNT#0 26 TP126 TPAD30

-1

SMB

SATA

GPIO

25,26 PCI_AD[31..0]

3 U12C OF 6

19,23,29 SMB_CLK 19,23,29 SMB_DATA

AJ26 AD19 SMB_LINK_ALERT# AG21 0R0402-PAD SMLINK0 1 2 AC17 R598 0R0402-PAD SMLINK1 1 2 AE19 R599 PM_RI# AF17

SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 GPIO37 CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5#

AJ12 AJ10 AF11 AG11 AG9 G5 D3 AG23 AF21 AD18 AH27 AE23 AJ14 AE21 C2 AH20 AG27 E1 E3

SATA0GP SATA1GP SATA2GP ICH_GPIO37

1 2 3 4 SRN8K2J-1-GPCLK_ICH14 3 CLK48_ICH 3 PM_SUS_CLK 20

8 7 6 5

3D3V_S0

AG12SMB_ALERT#

SLPS5# S4_STATE#

PM_SLP_S3# 20,28,29,32,35,38,39,40,41 PM_SLP_S4# 29,32,39,41 TP125 TPAD30 TP55 TPAD30 PWROK R417 7,20 100R2J-2-GP 2 1 R418 1 2 DY 100KR2J-1-GP D35 BAS16-1-GP 1

4

AG22 AE20 AG18 AH11 AE17 AF12 AC13 AJ20 AJ22

3 PM_STPPCI# C8 PCI_IRDY# 26 3 PM_STPCPU# D9 PCI_PAR 25 1 2 G6 PCIRST# R439 PCIRST1# 26 26,32 PM_CLKRUN# 56R2J-4-GP PCI_DEVSEL# 26 D16 A7 PCI_PERR# 26 23,29

acer extensa 5620z - wistron columbia_tangiz

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