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TUNING HIGH FREQUENCY G,-C FILTERS
BASED ON SHORT CHANNEL MOSFETS
by
Geoffrey Julian Alibutt
A thesis submitted to the Department of Electncal and Cornputer
Engineering in confomiity with the requirements for
the degree of Master of Science (Engineering)
Queen's University at Kingston
Kingston, Ontario, Canada
September, 1997
copyright 8 Geoffrey Allbutt, 1997
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Abstract
At high frequencies, the tunable range of traditional g,-C filters is severely reduced due to
shoa channel effects. This thesis describes two techniques to allow tuning at high frequencies.
The first, a tunable capacitor, is based on the intrinsic capacitances of a MOSFET transistor, while
the second, a trioded transconductor, is based on intrinsic transconductances of a MOSFET
transistor. Both techniques use the regulated cascode circuit structure to control bias voltages of a
trioded transistor. Prototype filters for each technique were designed and fabricated. A filter
based on the tunable capacitor concept was tunable from 29-36 MHz with a dynamic range of 23
dB and a maiimum power dissipation of 30 mW. A filter based on the trioded transconductor
concept was tunable from 3-8.5 MHz with a dynamic range of 22 dB and a maximum power
dissipation less than I mW. The results from this work can be applied to creaiing high-
performance tunable analog filters.
Acknowledgrnents
The author would like to express his sincere appreciation to Professor D. Naim for his
invaluable advice, guidance and encouragement during the course of this work.
The contributions of the other members of the Faculty and of fellow graduate students are
aiso thankfully recognized.
The financial support of Micronet and the Natural Sciences and Engineering Research
Council gants held by Professor D. Naim is deeply appreciated.
The generous technicd assistance of the Canadian Mircoelectronics Corporation, in
conjunction with Nortel, is gratefully acknowledged.
Table of Contents
............................................................... Abstract i
.............................................*........ * Acknowledgments 11
ListofFigures ........................................................ vi
......................................................... ListofTables ix
ListofSyrnbols ........................................................ x
1.0 Introduction
1.1 Analog Filters in a Digital World ........................................ 1
1.2 High Speed Anaiog Filtering Techniques ................................. - 2
1.3 Trade-offs: Speed versus Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 The Future of High Speed Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 Purpose: To Explore Alternative Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.0 The Tunabie Capacitor
2.1 Why do we Need Tunable Capacitors? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 The Structure of a MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Parasitic Capacitances of the MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Using the Gate-to-Drain Capacitance ................................... - 2 0
2.3 A Tunable Capacitor Ce11 ............................................. 21
2.6 Design of a TunabIe Capacitor Filter ................................... -22
2.7 A First-Order Test Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -27
2.8 Results frorn the First-Order Test Filter ................................. - 3 3
2.9 Tunable Biquad Design ............................................... 37
2.10 Summary on Tunable Capacitor Based Filter Structures . . . . . . . . . . . . . . . . . . . - 4 2
3.0 The Trioded Transconductor
3.1 Why do we Need Tnoded Transconductors? ............................. -46
...................................... 3.2 Transconductances in MOSFETs -47
3.3 Using the Gate Transconductance ..................................... -50
3.4 A Trioded Transconductor Ce11 ........................................ 51
................................. 3.5 Design of a Trioded Transconductor Fiter 53
................................. 3.6 Simulations of the Fit-Order Test Filter 55
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Results from the First-Order Filter - 5 5
3.8 A Tunable Biquad Filter ............................................. - 6 3
3.9 Design of a Biquad Trioded Transconductor Ce11 .......................... -64
. . . . . . . . . . . . 3.10 Simulations and Results for the Tnoded Transconductor Biquad - 6 6
. . . . . . . . . . . . . . . . 3.1 1 S u m a r y on Trioded Transconductor Based Filter Structures 72
4.0 Comparison and Discussion
4.1 Lntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Architecture and Layout 75
.................................. 4.3 Cornparison and Discussion of Results - 7 8
. . . . . . . . . ..................................... 4.4 Relative Filter Merits -79
4.5 DesignSteps ....................................................... 83
4.5.1 The Tunable Capacitor ........................................ 83
.................................... 4.5.2 The Trioded Transconductor 85
4.6 S u m m q .......................................................... 86
5.0 Conclusion
5.2 Original Work and Results ............................................ 88
5.3 Suggestions for Future Work .......................................... 88
&ferences ............................................................. 90
Appendixes ............................................................... 93
Appendix A: Output Buffer Design ........................................ 93
................................................. AppexdixB: TestSetup 95
vita ..................................................................... -96
Figure 1 .
Figure 2 .
Figure 3 .
Figure 4 .
Figure 5 .
Figure 6 .
Figure 7 .
Figure 8 .
List of Figures Five Types of Filter Intepitors ......................................... 6
A Switched Tunable Capacitor ......................................... 13
The MOSFET Transistor ............................................. 14
Smaii Signal Capacitances of a MOSFET ................................ 18
A Tunable Capacitor Ce11 ............................................ - 2 3
A First Order Tunable Capacitor Filter ................................. - 2 5
Layout of a Unit Tunable Capacitor Cell ................................. 28
Layout of the First Order Tunable Capacitor Filter ......................... 29
Figure 9 . Simulated Capacitance Range vs . Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . . - 3 1
. Figure 10 Six Element Lumped Model of the MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
. . . . . . . . . . . . . . . . . . . . . . . . Figure 1 1 Distx-ibuted vs Non-Distributed Transistor Modelling 34
Figure 12 . Photornicrograph of the First Order Tunable Capacitor Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (1 -2 prn process) 35
Figure 13 . Measured and Simulated Results of the First Order Tunable
Capacitor Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
. Figure 14 The Tunable Capacitor Biquad Filter Design ............................. - 3 8
. Figure 15 Layout of the Biquad Tunable Capacitor Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
. ............................ Figure 16 Sirnulated Tuning Range for the Biquad Filter 43
Figure 17 . Photomicrograph of the Biquad Tunable Capacitor Circuit
.................................................. (0.8 pm process) -44
. . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 17 Simple Transconductance Mode1 of a Transistor 47
. Figure 18 MOSFET Transconductances ......................................... -49
. Figure 19 Relative Cornparison of Transconductances ............................. - 5 1
. Figure 20 Inverting Trioded Transconductor ..................................... - 5 2
. ............................................ Figure 2 1 A First Order g,. C Filter -54
. ..................* Figure 22 Layout of the First Order Trioded Transconductor Fiter - 56
Figure 23 . Simulated Transconductance Range of the First Order Trioded
.............................................. Transconductor Filter - 57
Figure 24 . Photomicrograph of the First Order Trioded Transconductor Filter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (0.8 pn process) -58
. - . . . . . . . . . . . Figure 25 Transfer Function of the First Order Trioded Transconductor Filter 60
Figure 26 . Transfer Function of the First Order Trioded Transconductor Filter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (Chip#5) 61
. ............ Figure 27 Output Spectrum of the First Order Trioded Transconductor Filter 62
. . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28 The Trioded Transconductor Biquad Elter Design 63
. Figure 29 Non-Inverting Trioded Transconductor Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 6 5
. ..................... Figure 30 Dummy Transconductor Cell with Feedback Amplifier 67
. ..... Figure 3 1 Simulated Transfer Functions of the Biquad Trioded Transconductor Filter 68
Figure 32 . Sirnulated Transconductance Range of the Biquad Tnoded
............................................... Transconductor Filter -69
. . . . . . . . . . . . . . . . . . . . . . . . . Figure 33 Layout of the Trioded Transconductor Biquad Filter 70
Figure 34 . Photomicrograph of the Trioded Transconductor Biquad Filter
(1.5 pm process) .................................................. - 7 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 35 . Transfer Function of the Buffer 73
. Figure 36 Tunable Filter Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 7 6
vii
. Figure 37 Unity Gain High Frequency Buffer .................................... - 9 3
. Figure 38 Simulated Transfer Functions of High Speed Buffers ...................... - 9 4
. Figure 39 Schematic Diagram of Test Setup ..................................... - 9 5
List of Tables ............................................ Table 1 : Survey of Recent Filter Papers 3
. . . . . . . . . . Table 2: Cument-Voltage Relationships for Short- and Long-Channel MOSFETs 16
........................ Table 3: Approximate Expressions for MOS Gate Capacitances 17
...................... Table 4: Simulation and Test Results for First Order Tunable Filter 37
............................ Table 5: Simulation Results for Second Order Biquad Filter - 4 2
. . . . . . . . . Table 6: Simulation & Test Results for Fit Order Tnoded Transconductor Filter - 5 9
. . . . . . . . . . . . . . . . Table 7: Simulation Results for the Biquad Trioded Transconductor Filter 72
. . . . . . . . . . . . . . . Table 8: Simulation & Test ResuIts for First Order Tunable Capacitor Filter 78
. . . . . . . . Table 9: Simulation & Test Results for First Order Trioded Transconductor Filter -79
. . . . . . . . . Table 10: The Relative Merits of the Tunable Capacitor and the Trioded Transistor 80
Table 1 1: Simulations of High Speed Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
List of Symbois Udess oiherwise stated, the foilowing symbol convention will be used. DC quantities are
represented by uppercase symbols with uppercase subscnpts. Small-signal quantities are
represented by lowercase symbols with lowercase subscripts. Combined quantities are
represented by uppercase symbols with lowercase subscripts.
Name of the Function
Degree of triode operation
S hoa channel effect parameters
Permittivity of free space
Relative permittivity
' s ~ o , Relative perrnittivity of SiOz
$1, 6 2 Discrete time clocking signais
OB Surface potential parameter
Y Body effect coefficient
P Carrier mobility
Pefi Effective carrier mobiiity
Vsat Saturation carrier drift current
Gate area
Capaci tance
Gate-to-buk capacitance
Gate-to-drain capacitance
Gate-to-source capacitance
Overlap capacitance per unit widih
Oxide capacitance per unit area
Critical longitqlinal channel field strength
Gate transconductance
MOSFET drain c m n t
Device parameter
Boltzmann's constant
Channel length
Effective channel-length
Drain-to-source resistance
Room temperature [Kelvin]
Gate oxide thickness
Drain-to-source voltage
Saturation drain voltage
Source-to-buk voltage
Threshold voltage
Channel width
hpedance
1.0 Introduction 1.1 Analog Filters in a Digital World
The desire for fully integrated high-frequency analog filters has increased with the growth
in digital signal processing @SP) based communication systems. Personai communication
devices require both bigh-speed and low power operation. These confiicting requirements lead to
the use of mixed signal (i.e., analogldigital) integrated circuits (ICs), which exploit the best circuit
techniques, be they anaiog or digitai. Digitai filtes, while capable of linear high order filtering,
are not capable of the high-speeds possible with analog filtering. Digital filters also require more
power than analog filters. By combining higher speed analog filtes with lower speed DSP
circuits, higher performance designs are possible. Thus the development of fast, efficient analog
filters is of great interest to the electronics community.
Most 'high-frequency communication signals are analog. Hence, analog-to-digital
converters (ADCs) and digital-to-analog converters (DACs) are needed to convert these signals to
a form suitable for digital signal processors. For ADCs, pre-filtenng of the input analog signal is
required to avoid aliasing of the incoming signai. Without pre-filtering, signals at frequencies
greater than half the sarnpiing frequency will be aliased into the baseband resulting in poor signal
versus noise performance. For DACs, the nonnai output resembles a series of offset square
waves. Here analog filters are used to smwth the steps by eliminating the high-frequency
components. As the frequencies of digital communication systems increases, the use of analog
filters for pre- and post-filtering continues to grow.
Tunable analog filters are even more valuable than their non-tunable counterparts. The
ability to alter the characteristics of filters after fabrication greatly increases their flexibility. In
addition to Uowing the fabrication of extremely high accuracy filters, tunable analog filters allow
the creation of multipurpose genenc circuits. One example of this is a phase lock loop (PLL).
PPLs have both narrowband and wideband applications. This bandwidth is normally set via an
analog filter in front of the voltage controiied oscillator- If a tunable filter were substituted for the
fixed filter, a single PLL chip design could now serve in place of the multiple designs needed to
provide both narrowband and wideband circuits. Other applications include the use of tunable
filters as part of a continuous automatic tuning circuit to adjust for poor temperature stable time
constants [l].
Since the analog filters are to be used with digital systems, it is preferable that the analog
circuits be fabricated onchip with the digital circuits. As digital fabrication processes are
optimized solely for digital circuits. analog circuits included on the same chip are at a
disadvantage compared to anaiog circuits fabricated from discrete components. Therefcre
common discrete filter designs based on active RC techniques cannot be used.
1.2 High-Speed Analog Filtering Techniques Most discrete analog filter designs are based on active-RC techniques. While active-RC
techniques perform well when created out of discrete components, problems occur when
integrated versions are fabricated. It is difficult to manufacture a high quality resistor in a CMOS
process, and those built suffer from low accuracy [2]. This makes them undesirable for high-
precision analog filters. Most high-speed filtering techniques revolve about finding replacements
for the resistor in active-RC designs.
A review of over 100 recently published filter papers was conducted by the author. This
review provided insight into the current state of technology in filter design. Of those filten
reviewed, 15 possessed notable results summarized in Table 1.
Table I : Survey af Recent Filter Papers
Reference / 1 Auihor 1 Type Number
S tzfanelIi Elliptic
30
7 Snelgrove BP
35 Kwan notch, BP, LP
-3dB/ Powcr Ares Powedpole Dynamic Type 1 Centre B q 1 1 (mW) / 1 (mW) / Tech 1 Range /
3 1 Hughes LP, FIR
Lee CT,CM1 42MHz 1 5 1 2 5 . 5 1 -28 1 5.1 1 Zpm I 6 9 d B 1 CMOS
Lp, Ladder
SI, CM 13.3 MHz 0.08 1 Pm CMOS
\
CT, 1 7 M H z 1 5 3 0 1 6 1 6 gm-C
CT, 1 98 MHz 1 3 1 670 1 1 225 1 3pm 1 72dB ( gm-C CMOS .
I
CT, 1 0.132 MHz 6.84 1.76 analog, CMOS
CT,NIC 1 100 MHz 1 3 1 40 1 1 13.3 1 Bipolar 1 30 dB 1 '
A widely used filtering technique today is the switched capacitor (SC) filter. This is a
discrete-time technique in which the resistor fiom an active-RC Nter is replaced with a switched
capacitor (see Fig. la & tb for active-RC & switched-C integrator). When the capacitor is
switched it hnctions as a resistor which is dependent on both the size of the capacitor, and on the
speed with which the capacitor is clocked. Switched capacitor filters are tunable by aitering the
switching speed. The accuracy of SC filters depends on the capacitance matching accuracy.
Matchjng of integrated capacitors cm be made to a high degree of accuracy, giving this filtering
technique a high resolution. This resolution cornes at a cost in speed, when compared to other
filtering techniques, as the maximum frequency the filter can operate at is generaily one tenth of
the capacitor clocking speed. In addition to lirniting the maximum speed, the need for clocking
introduces two other problems. Charge injection aises when the clock signal is coupled into the
signal path, thereby reducing the circuit's accuracy. Being a discrete-time system, SC filters are
vulnerable to aliasing noise, and hence require anti-aliasing filten of their own to function
properly. The fastest of recently reported SC filters has a -3 dB frequency of 10.7 MHz with a
dynamic range of 34 dB [3].
When the limitations of the switched capacitor design becarne clear, alternative solutions
were sought. By replacing the resistor with a MOSFET transistor operating in triode mode the
problem of poor quality resistors could be avoided [4]. The MOSFET-C integrator is shown in
Fig. lc. While the current to voltage relationship of a triode mode transistor is not linear, it c m be
approximately linear for small signals, and its resistance can be controlied by aitering the gate
bias voltage. The triode mode MOSFET can then be used as a tuning element in a filter. The
MOSFET-C technique, as this approach is known, is a continuous-time circuit. Hence, it avoids
discrete-time problems such as high-frequency aliasing, clock feedthrough, and charge injection.
Figure 1. Five Types of Filter integrators (a) the Miller Resistor-Capacitor integrator; (b) the Switched-Capacitor integrator; (c) the MOSFET-Capacitor integrator; (d) the Switched-Current integrator; (e) the Transconductance-Capacitor integrator.
However, the linearity restriction of the triode mode MOSFET resistor reduces the maximum
achievable resolution. The operating frequencies of MOSFET-C filten are not as fast as those of
SC filten. As both circuits make use of operational amplifiers, they are limited to the frequency
at which the op-arnp can function. The fastest of the recent MOSFET-C nIters had a -3 dB
frequency of 500 kHz with a dynamic range of 40 dB [5].
Current-mode devices were under development simultaneously with MOSFEFC filters.
If a current could be sampled, stored, and then used in a current addition operation, an integrator
could be created. As integrators are the basic building blocks of filters, many different filter
topologies are possible. This is the basic concept of the switched current (SI) integrator found in
Fig. Id. The storage element of an SI filter is the gate capacitance of a MOSFET. The MOSFET
is diode connected as the signal current is passed through it. The gate voltage required to pass this
current is smpled on the gate-to-source capacitance (Cg,) when a switch is thrown to isolate the
stored voltage on the gate. The MOSFET will continue to conduct the stored current which can
be used for other purposes including addition to a previous sample, thereby performing the
integration operation. By virtue of its operation, SI integrators are inherently discrete-time.
There are two main advantages of the SI integrator. No op-arnp is required, thus the
difficult task of constnicting a high-frequency op-amp is avoided. Being a current mode device,
the SI integrator is inherently less sensitive to parasitic capacitance, thus speeding its operation.
However, the serious problem of charge injection exists. W e the errors caused by charge
injection can be reduced with the use of dummy transistor switches, there is still a reduction in
achievable accuracy. Thus while SI filtea c m operate at higher speeds than MOSFET-C and SC
filters, SI filtea typicaily have lower resolutions. The fastest SI filter surveyed possessed a -3 dB
frequency of 13.3 MHz [6] .
A fourth type of analog filter is the transconductance-C (g,-C) filter, seen in Fig. le. The
integrator of a g,-C filter consists of a transconductance amplifier, and a capacitor. This type of
filter is a continuous-time system that does not require an ideal op-amp as the active-RC filter
does. Therefore, g,-C fiiters are capable of achieving tremendous speeds. As most
transconductoa are based on the differential op-amp. they, and the g,-C filter itself, can be easily
tuned by adjusting the bias current of the transconductor. However, the poor linearity of
transconductors reduces the achievable resolution. The fastest g,-C filters found in the survey
were found to have a -3 dB frequency tunable from 30-450 MHz but only had a 40 dB dynamic
range [7].
1.3 Rade-offs: Speed versus Resolution There are many techniques available to the analog filter designer: switched capacitor,
switched current, MOSFET-C, and transconductance-C. These techniques c m be split into two
domains: the discrete-time domain and the continuous-time domain. Within both categories
there are trade-offs between the speed of the fiiter and its resolution. In the continuous-time
domain, g,-C filters are faster than MOSFET-C filters, yet MOSFET-C are capable of higher
resolutions. In the discrete-time domain, SI filters are faster than SC filters, but SC filters are
capable of much higher resolutions. In general, continuous-time filters are faster than discrete-
time filters, making them preferable for the design of high-speed analog filters.
1.4 The Future of Kigh-Speed Filtering Device dimensions are decreasing as digital designers continue to increase the number of
transistors per unit area of silicon. As aualog filters now share chip space with these digital
circuits, analog filter designers should also take advantage of the benefits offered by the smaller
transistors. This trend in device dimensions should affect different filters equally as the input
capacitance of a transistor falls. Hence, it is expected that g,-C filters will stiU be the fastest
filters available. Though it-is possible for a new filter topology to exceed even the speed of the
g,-C filter, such filters are still in the experimental stage and are not suitable for commercial
fabrication.
Unfortunately, as channel lengths shnnk, g,-C filters lose sorne of their flexibility. As
mentioned earlier, gm-C filters are normally tuned by altering the bias current of the
transconductor, thus altering the small signal transconductance of the device. Short channel
transistors cannot be tuned in a similar manner. Whereas g,,, was previously dependent on the
square-mot of the bias current, it is now a constant depending only on the device dimensions [8],
[9]. This lack of tunability in shortchannel gm-C filters reduces their attractiveness for high-
frequency filtenng applications.
1.5 Purpose: To Explore Alternative Techniques The purpose of this thesis is to examine alternative methods for tuning short-channel g,-C
filters, and thus restore their effectiveness for high-frequency filtering applications. These
techniques should not require special processes thereby maintainhg fabrication compatibility
with digital CMOS circuits.
Two methods of tuning short channel g,-C filten will be exarnined. The first of these is
that if one cannot tune g, in a g,-C filter, can capacitance be tuned instead? The second method
of tuning is to use the transconductance of a triode transistor as the tuoing element. After an
extensive search, tunable capacitors are believed to be a new technique. The trioded
transconductor technique h a been used before [IO], [Il], [12]. [13], but rareiy has the regulated
cascode k e n used in conjunction with the transconductor [14], [15].
For both techniques, the necessary concepts of the MOSFET mode1 are reviewed and a
method of creating a tunable device is explained. Two circuit designs for each technique are
presented, a first-order filter section, and a biquad filter section. Simulations and test results are
shown for the designs. Finally, a cornparison between these two- methods of tuning short channel
CMOS are explained and compared with other existing techniques. The theoretical Lirnits of these
techniques are also examined. These comparisons are summarized and conclusions about the
future of high-frequency anaiog filtenng are presented.
2.0 The Tunable Capacitor 2.1 Why do we Need 'lùnable Capacitors?
G,-C filters are the filters of choice if a high-fiequency filter compatible with digital
CMOS processes is desired. Uniike other filtering methods g,-C füters do not require op-amps,
and since they are continuous time they do not require complicated clocking structures.
Additionally, g,-C filters are easily tunable by adjlisting the bias current of the transconductor,
thus aitering g, and the frequency response of the circuit.
As technology enables ever smaller channel lengths to be used, gm-C filters [ose some of
their attractiveness. White short-channel devices are required to create g,-C filters of very high-
frequency, the tuning of short channel g,-C filters is no longer possible. In long channel
transconductors, g, is proportional to the square root of the current and thus c m be altered by
adjusting the bias cunent [16]. However, when submicron channel lengths are used,
MOSFET square-law relationship no longer applies. Indeed, for short channel lengths,
MOSFET .drain current, ID, and gate-to-source voltage, VGS, become linearly related by
following equation [8]
the
the
the
ID = U S ~ ~ O X * ('(3s - 'T - V ~ ~ a t ) (2.1)
where v,,, is the saturation canier drift current, Co, is the oxide capacitance per unit area, W is the
device width, VT is the threshold voltage, and Vm, is the saturation drain voltage. Since gm is
defined as aIo/aVGs, g, becomes constant and equal to u,C,,W. Hence, it is not possible to
tune traditional g,-C filters once the circuit is fabricated.
While a number of solutions to this problem of how to tune short channeled
transconductors have been examined already, this chapter focuses on an alternative question. Is it
possible to tune capacitors in short channel CMOS? Such a capacitor, if digitally compatible,
would enable the tuning of short channel g,-C filters. It could also enhance the tuning of any
filter in which a capacitor is used, such as SC or MOSFET-C. In addition to creating tunable
filters, trimming could also be performed with tunable capacitors, thus aiiowing the creation of
high accuracy capacitors for use with analog circuits.
One form of the tunable capacitor aiready exists, the binary-weighted pardlel-comected
capacitor array, as seen in Fig. 2a. This circuit element consists of a number of binary weighted
capacitors, connected via switches to a single node. By selectively opening and closing switches,
the capacitance at the central node can be altered. The drawback of this circuit is the coarse
tuning it offen, especially at the lower end of the capacitance range. If a continuously tunable
capacitor, tunable over a 2:l range, were added equal to the srnailest capacitor in the circuit,
resulting in the circuit shown in Fig. 2b, continuous tuning over the complete range would be
possible.
2.3 The Structure of a MOSFET The MOSFET transistor is the fundamental building block for most digital and many
analog circuits today. While MOSFETs are simple to fabricate and possess well understood
models, the fundamental advantage of MOSFETs is their low cost. While newer fabrication
technologies, such as BiCMOS and GaAs, offer faster performance, the cost increase associated
with these processes will likely ensure that CMOS will be the technology of choice for many
years to corne.
The cross-section of an n-channel MOSFET is shown in Fig. 3a. It consists of 2 doped n-
wells in a p-type substrate. Contacts of meial connected to these wells form the source and drain
terminais. The surface between the two wells is isolated from the gate with an insulating oxide.
Figure 2. A Switched Tunable Capacitor (a) binary-weighted parallel connected capacitor array, tunable from 1/8 C to 15/8 C in steps of 118 C; @) proposed continuously tunable capacitor. C/8. C/4, C/2. and C are switched to achieve the closest step value to the desired capacitance. and a second C/8 is then continuously tuned to achieve the exact value.
Gate
Gate Source Drain
p-su bs trate
Drain
Q
Figure 3. The MOSFET Transistor (a) cross section of the physical structure of a N-FET; (b) dominant parasitic capacitances at the gate of a MOSFET: (c) small signal mode1 of the device.
and a metal contact to this oxide fo& the gate terminal. A contact to the substrate complete this
4 terminal device. As this device is physically symmefrical, the source and drain are determined
strictly by the direction of current flow. As the substrate is normally held at a fixed potenîiai to
avoid problems with latch-up, it is not usually available for use and will not be considered beyond
the body effect.
The MOSFET transistor is a complicated device, and many different models for its
behavior exist. The simplest model is that of a voltage controlled current source. When a voltage
is applied to the gate of an n-MOS device which exceeds the threshold voltage, electrons are
attracted from both the source and drain to form a conductive channel beneath the gate between
the source and drain, connecting them electncally. There are two distinct operating modes for a
MOSFET: saturation, and triode. In saturation. the source-drain current is proportional to the
square of the gate-source voltage less the threshold voltage, and is also proportional to the Widthi
Length ( W L ) ratio of the channel area. In triode, the source-drain current is also proportional to
the drain-source voltage, in addition to those factors rnentioned for saturation. The equations
which describe the current-voltage relationship of MOSFET transistors for both long- and short-
channel devices can be found in Table 2 [8] 1161. A small signal model of the transistor is shown
in Fig. 3c. Thus different models of a MOSFET transistor can Iead to different predictions of its
behaviour and one m u t always ensure that the mode1 king used is valid.
2.3 Parasitic Capacitances of the MOSFET While this mode1 is acceptable for conceptual designs, it must be irnproved to be truly
representative of a MOSFET. Parasitic capacitance between the gate and source, and gate and
drain, must be added. While these parasitic capacitances are normaliy hindrances to circuit
designers, they offer the tools needed to build a tunable capacitor from a MOSFET. Studies
gate-source voltage,
drain-source voltage,
threshold voltage,
saturation drain voltage,
carrier mobili ty,
oxide capacitance per unit area.
width of the channeI,
length of the channel.
effective channel-Iength between the source and the drain,
effective c h e r mobility,
saturation carrier drift velocity,
critical longitudinal channel field strength at which the carrier rnobility alten from a
constant to a variable dependent on the longitudinal channel field strength.
Table 2: Current-Voltage Relationships for Short- and Long-Channel MOSFETs 181 1161 .
Saturation
Long Channel Devices
ID= KWGS - VT ) 2
Short Channel Devices
ID = 'satCoxW ( V ~ s - 'T - ',a)
which examined these parasitics found interesting variations in capacitance with the bias
conditions [ 171. If these variations were hamessed, a tunable capacitor could be constructed.
When considering the creation of a tunable grounded capacitor from a MOSFET, the gate
terminal is of primary interest. The gate terminal conducts no D.C. current, and as it physically
resembles a capacitor, it is the ideal starting point. At the gate of a FET there are three primary
capacitances available; the gate-substrate capacitance Cgb, the gate-drain capacitance Cgd, and the
gate-source capacitance Cg,, as seen in Fig. 3b. Within each region of operation, these
capacitances Vary with both VGs and VDs in a complex rnanner. Empincal formulas, which
characterize the capacitances with respect to VGS and VDs are shown in Table 3 [17]. The broad
characteristics of these formulas are shown in Fig. 4a & 4b.
Table 3: Appmximate Expressions for MOS Gate Capacitances
Parameter L
- - -
O (fini te for short
channe1 devices)
Off
1 I a 1s a circuit parameter indicating the degree of triode operation (see section 2.3). 61 is a transistor parameter indicating short channel effects (see section 2.5).
Of the three parasitic capacitances under consideration, Cgb is the least useful since it is
- --- -
Triode
only signifiant in the off state, and is quite smali within the triode and saturation regimes. As
well, it is very difficult to separate this capacitance from the other gate capacitances without
special well technologies and techniques. Additionally, the low capacitance per unit area
- - - - --
Saturated
Saturation t +t
Figure 4. Smail Signai Capacitances of a MOSFET (a) vs. the gate-source voltage VGS; (b) vs. the drain-source voltage Vos.
Triode
1 Triode
(4
+4 Saturation
(b)
precludes the creation of a compact circuit. Consequently oniy Cg, and Cgd remain to be
considered. Cg, is a sizable capacitance that exists in bath saturation and triode modes. ui
saturation, theoretical predictions and simulation resulü both confirm that Cg, can be tuned by
about 10% of its nominal value [17]. Unfominately, to achieve this nining range, preliminary
work showed that a variation in the bias current of three orders of magnitude (i-e. 1 pA - 1000
PA) is required. While tunability of this size may be useful in error correction and trimmulg of
highly sensitive circuits, the high power consumption and low tunable range severely limits its
usefulness in tunable filter applications.
While the merits of Cg, do not improve in triode, dramatic changes in Cg, can be found for
relatively small changes in the bias current if the device is operating in weak inversion. In weak
inversion the value of Cg, varies frorn effectively zero to its nominal value of k,, with the 3
application of a very small bias current. The tunability and power consumption of this circuit
would make it ideal but for one flaw - signal swing. For the transistor to remain weakly inverted,
the signal must be kept very srnall (4 mV). Additionally, such small signals are necessary to
maintain linearity. Given the difficulties of ampliQing high-frequency signals, and potential
noise problems, weak inversion does not appear useful for high-frequency applications.
While Cg, W ~ S found to be unsuitable, the use of Cgd remains a viable option. Theoretical
predictions show that in saturation Cga is small and constant, while in triode, a large capacitance
2 change occurs from close to zero to the nominal value of -Cm as was illustrated in Fig. 4a & 4b. 3
This capacitance change occun over the complete triode region, dius avoiding the sharp
capacitance changes displayed by Cg, in weak inversion. Also. the capacitance per unit area is
much Larger than Cgb, thereby allowing the construction of a compact circuit. The potential
problem with using Cgd in triode mode is the parasitic path formed by the triode resistance Rds
and Cg, However, as discussed below, this problem can be controlied with careful design.
2.4 Using the Gate-tomDrain Capacitance I f a tunable capacitor is to be designed using Cgd, it is required to be able to estimate its
capacitance and tuning range. The maximum Cgd capacitance is easily estimated by using the
conventional equation for the gate capacitance of a MOSFET in triode [18]
where eo is the permittivity of free space, &Sioz is the relative permittivity of Sioz, to, is the gate
oxide thickness, and Coi is the overlap capacitance per unit width. As this equation does not
include depletion or routing capacitance, the actual capacitance is expected to be slightly higher
than this calculation would indicate.
While (2.4) is sufficient for estimating maximum capacitance, it fails to take into account
the changes in capacitances with bias conditions. A better estimate of the capacitance can be
obtained using the following expression from Table 3
where
WS~O, Co,= - W - L
and a is a parameter measuring the degree of triode operation. Alpha varies between O and 1,
with O indicating the boundary between triode and saturation, and 1 the boundary between triode
and cutoff. The transistor-should never be brought further into saturation than the boundary
between triode and saturation, as no additionai capacitor tuning range is gained.
f i v,, - v~ 6 - 6 , = Y ~ V T
v~~ = = - = constant i + 6 2 4-i d V s ~
Alpha is also used as a measure of efficiency of the nining circuit. Ideaily the circuit
would allow a to swing through its complete range, maxùnizing the change in capacitance.
However, as a approaches 1, large cutoff distortions appear in the signal. A value of a = 0.7 was
found to offer an excellent uade-off between low distortion and large capacitance changes, and
results in a practical maximum Cg, = 0.44 Co, , as opposed to the theoretical maximum
Cg = 0.5 . Co, . Thus most of the capacitance change is obtained while the circuit remains far
enough from cutoff to avoid signal distortion.
2.5 A 'Iiinable Capacitor Cell As Cgd appears in parallel with Cg,, with Cg, largely untunable, Cgd must be isolated from
the other parasitic capacitances, lest the overall tuning range be substantially reduced. To
constmct a tunable grounded capacitor at the gate of a MOSFET using Cgd, the drain of the
transistor must be a srnail signal ground. Similarly, in order to isolate Cg,, small signai isolation
must be provided at the source. It should be noted that if perfect source isolation is achieved, a
2 1
parasitic path to ground through Cg, and 5, wiil still exist and any design must take this path into
account. A circuit which meets both these requirements is shown in Fig. 5.
To provide the srnail signal ground at the drain of the triode mode MOSFET MI, a
regulated cascode circuit [19] consisting of transistors M2 and Mg. and current source IB2. was
used. The regulated cascode's feedback loop maintains a constant voltage at aode X. As the bias
current IB2 sets the cumnt for M3 and thus the VGs of M3, it controls the voltage to which node X
settles. As this bias current also controls the gain of the feedback loop of the regulated cascode
through transistor M3, tuning IB2 also affects the quality of the smaU signal ground at node X.
Transistor M3 was made large so that the gain of the transistor would keep the ripple at node X
small for changing cumnts.
To provide the small signal isolation at the source of the triode mode MOSFET transistor.
current source IB1 consisting of a long saturated transistor was used. A long saturated transistor
was used to maintain the high output impedance of a cument source. This current source was
biased to provide a current of 5 rnA. This was to ensure that the transistor remained in an 'on'
state, regardless of how VDs was tuned.
2.6 Design of a Tunable Capacitor Filter The first step in the design of a tunable capacitor filter is the establishment of the filter
specifications. The goal of this initial design was to create a tunable Iow-pass filter with a
maximum -3 dB frequency of 100 MHz. while maximizing the tuning range. Choosing a
frequency much larger than LOO MHz would serve no purpose. as the testing equipment available
cannot accurately obtain results at frequencies above 150 MHz. 100 MHz is a challenging
Figure 5. A Tunable Capacitor CeII
frequency for digitally compatible CMOS circuits, and allows for possible applications with
digital radio and other high-speed communications devices.
To further shplify the initial design, a passive resistor-capacitor (RC) low-pass filter
structure was chosen. As the tunable capacitor is an experimentai circuit, the fewer additional
complications. the more Iikely the circuit is to perform as designed. Together, the triode mode
MOSFET transistor, the regulated cascode, and the current source IB form the tunable capacitor.
By adding triode mode transistor MR, which behaves as a resistor, a first-order RC filter. as seen
in Fig. 6a, is created. The complete small-signal equivalent circuit is shown in Fig. 6b. Its
approximative transfer function, neglecting Csb, is given by (2.8). By varying IB2, Cgd in (2.8)
can be varied, yielding a tunable filter.
In order to be able to design the tunable capacitor, a capacitance value must be chosen.
However, as a passive RC filter is to be used, R must be known before C can be fixed. In order to
niaintain digital compatibility, a triode mode transistor was used as a voltage controlled resistor,
with the resistance dependent on both the bias voltages and the device dimensions. However, the
value of R must be chosen carefully. Too srnail a value will cause other on-chip circuits difficulty
in driving the filter. Too large a value cannot be accurately fabricated, as small changes in bias
voltage and device dimensions will cause large changes in the resulting resistance. Thus, an
intermediate value of 25 kR was selected for R.
Once R has been chosen, a value for C can be detemiined. Preliminary work has indicated
that, using ideal components. a tuning ratio of 3:l is achievable. As the lowest frequency of the
Figure 6. A First-Order Tunable Capacitor Filter (a) schematic design; (b) small signal mode1 with node X as signal ground.
tuning range detemiines Cm,, a tuning ratio of
MHz. Cm, can then be calculated using (2.9).
3:l results in a lowest -3 dB frequency of 33
= 190fF (2.9)
Once the desired transfer function has established the required capacitance, the design of
the tunable capacitor can be completed. Equation (2.4) c m be used to determine the required gate
area. As the design of the prototype tunable capacitor is using NorTel's 1.2 p CMOS4s process,
2 a Cm, of 190 ff requires 280 pm of gate area.
As the desired capacitance determines the size of the triode mode transistor, so too does
the size of the triode mode transistor determine the dimensions of the biasing network and
regulated cascode. There are rnany ways in which to design a transistor with a gate area of 280
9
pm- . from a long, nmow 1.2 pin by 233 p. to a square design 16.7 pm a side. However. when
rnaximizing the tuning range of the tunable capacitor, the shape of the transistor is restricted.
A single long narrow transistor has severai problems associated with it. A long, narrow
strip of polysilicon, typically used to form the gate connection, has a substantial resistance. This
R combined with the inherent C of the gate, could potentially interfere with the filter.
Additionally, it was found to be extremely difficult to properly control and bias such a large
transistor using the regulated casode network. Better performance was achieved when modestly
sized transistors were used. Thus, the tunable capacitor was constmcted out of parallel connected
tunable capacitor ceiis.
An advantage of using many cells for the tunable capacitor is the ease of altering the
design. To change the total capacitance. one needs only to add or subuact cells to achieve the
desired capacitance. One rnight argue that by simply scaling the triode mode transistor, a similiar
effect could be achieved without distmbing the biasing network. However, such scalings are not
linear if the scaiing changes the operating region of the device between the short channei region
( L c 1.5 p) and the long-channel region ( L > 1.5 p). Thus, 2 transistors of identical ratios
will not necessarily be interchangable.
The final step in the design of a tunable capacitor cell is the design of the transistors
themselves. The W L ratios shown in Fig. 6a were found to be useful as a starting point. HSPICE
[20] simulations could then be performed to adjust these ratios, to account for short channel
effects, process parameters, and layout parasitics, al1 of which affect the final design.
Any circuit dealing with srnail capacitances is vulnerable to parasitic capacitances and the
tunable capacitor is no exception. It is especially vulnerable at the gate of triode mode transistor
M I as any additional fixed capacitance would directly reduce the tuning range of the device. To
minimize this extra routing capacitance, the gate nodes of each ce11 were placed as closely as
possible to one another. This resulted in a long, narrow layout for each cell, as seen in Fig. 7. The
highest rnetal routing was used to connect the cells. which also helped to reduce the routing
capacitance. The layout of the complete filter is shown in Fig. 8.
2.7 A First-Order Test Filter. In the design of the prototype tunable capacitor cell, using NorTel's 1.2 p.m CMOS4s
process, a ratio of 12.511 for W L of the triode mode transistor Ml was found to meet the design
specifications. This resulted in a transistor gate area of 1.2 jîm by 15 p, with a Cgd of 12.5 fF, as
determined by (2.4). As this capacitance does not include depletion or routing capacitance, the
actual Cgd will be slightly higher than the calculated value. As low power operation is of great
importance, the tunable capacitor ce11 was designed to use a 3.1 volt power supply.
Transistor M3 (
Current Source IBl
C m n t Source IBZ
Transistor Mz
Triode Mode Transistor MI
Figure 7. Layout of a Unit Tunabie Capacitor Ce11
Triode Mode Transistor
Tunable Capacitor Grid Array
?-
Figure 8. Layout of the First-Order Tunable Capacitor Filter
With the hinable capacitor design complete, it is now possible to create a fint-order RC
test fiiter, using the tunable capacitor, and a triode mode transistor acting as a 25 kQ resistor.
Twelve tunable capacitor ceus are comected in parael to increase the total capacitance to 190 fF.
HSPICE simulations of the ideal tunable capacitor nIter indicated that, by a l t e ~ g the
current of IB2 from 3.3 pA to 33 pl, the -3 dB frequency was nined from 35 MHz to 97 MHz, a
2008 tunlng range. Once routing and other parasitic capacitances were taken into account, the -3
dB frequency was found to be tunable from 33 MHz to 67 MHz. a 100% tuning range. A lowest
frequency of 33 MHz with a resistance of 25 kS2 corresponds to a total maximum capacitance of
180 fF, or approximately 15 £F per cell. This value agrees quite closely with the calculated value
of 12.5 fF per cell, and also with the original design goal of 190 fF total. Fig. 9 shows the
relationship between the bias current IB2, and the capacitance of the filter. The dynarnic range of
a 1 MHz, 0.5 volt peak-to-peak test signal was 35 dB, indicating a linearity of 6 bits.
One final adjustment remains to alter the simulated results. To accurately predict the
behavior of this circuit, it is necessary to account for the distributed nature of the channel. Until
now. simulations have used a lumped element model, but a more accurate representation of the
channel is that of a transmission line. The transmission line channel rnodelling can be
approximated by a distributed series of resistoe and capacitors, as in Fig. 10. The greater the
number of discrete elements, the more accurate the approximation.
Two distributed transistor models were simulated; a 10 element model and a 20 element
model. The results of these simulations were compared to the results of a lumped element model,
so that the effect on the tunable capacitor cell could be calculated. The 10 element model was
found to have both the upper and lower -3 dB frequencies reduced by about 3.5% from the values
Capacitance vs. Current Bias for a 12 ceii Tunable Capacitor
200 L I I 1 I I 1
80 1 I I I I I l O 5 10 15 20 25 30 35
Bias Current (pi)
Figure 9. Simulated Capacitance Range vs. Bias Curent
Gate O
O Source
Figure 10. Six Element Lumped Mode1 of the MOSFET
predicted from the lumped model. The 20 element distributed model was found to have
negligibie differences from the 10 element model. These results are shown graphically in Fig. 11.
By combining the reductions in frequency with the eariier simulation results, a final
estimate of the tuning range c m be obtained. Reducing the simulated -3 dB values by 5% results
in a predicted tuning range fiom 3 1 MHz to 65 MHz for the first-order tunable filter.
2.8 Results from the First-Order Test Filter The multiple ceIl design philosophy was chosen so that extrapolations of the experimental
data to high frequencies by reducing the number of tunable capacitor cells would have greater
validity. Each tunable capacitor ce11 had a capacitance of 15 fF, according to HSPICE
simulations, agreeing closely with the calculated estimate of 12.5 fE
As the simulations indicated that the desired 100% tuning ratio was achievable, this filter
was submitted for fabrication. A digital 1.2 pm CMOS process was supplied by NorTel and 10
prototype chips were retumed for testing. A photomicrograph of the prototype circuit is shown in
Fig. 12.
Results from the fint-order test filter matched quite closely witb predicted results in one
regard, but differed substantially in another, as shown in Fig. 13. The expenmental results
revealed a first-order low-pass filter response tunable from 29 MHz to 36 MHz, indicating a 20%
tuning range, smaller than the predicted 100% tuning range. While the lower -3 dB frequency of
29 MHz agreed quiet closely with the predicted lower -3 dB frequency of 30 MHz, the measured
upper -3 dB frequency of 36 MHz differed quite substantiaily from the predicted value of
67 MHz. This nining range required a larger change in current in IBZ than was anticipated, closer
to 10- 1000 pA than the 3-30 pA predicted
tuning frequency does not scale by exactly
These results are sumrnarized below in Table 4. The
12 between the single ce11 and twelve ce11 simulations
Cornpanson of Filter Responses: Distributed vs. Non-distribued Channel
-
- - a t er, 3
a -
u 3 c. - c C3) CLI Zi -8- -
Distributed Modelling 4% difference at 100 MHz
O 10 20 30 40 50 60 70 80 90 100 Frequency [MHz]
Figure 11. Distributed vs. Non-Distributed Transistor Modeiling
Figure 12. Photomicrograph of the First-Order Tunable Capacitor Circuit ( 1.2 pm process)
35
Tuning Range of Filter
20 30 40 50 60
Frequency (MHz)
Figure 13. Measured and Simulated Results of the First-Order Tunable Capacitor Filter
due to the presence of parasitic routing capacitance. Simulations and test results were not well
matched. This is believed to be a combination of poor source isolation of the tunable capacitor,
and poor modeiiing of variable capacitance in integrated devices.
Table 4: Simulation and Test Results for First-Order h a b l e Filter.
Category Simulation (single ceU)
Simulation (twelve cells)
-- --
Measured Results (twelve cells)
1 Circuit Area 1 .71mm2 1 -98 mm2 I .98 mm2
~echnology 1.2 p.m CMOS
Power Supply
Power Consumption
Tuning Range (Hz)
1 Signal Swing 1 2 û û m ~ 1 200 mV I 200 mV
L
Tuning Range (%)
Linearity
2.9 'Iiinable Biquad Design
- - - - - - - - -
1.2 p CMOS
3.1 V
300 p W
217 - 300 MHz
The second design, and a goal of the tunable capacitor project, is the creation of a tunable
hiquad using the ninable capacitor. Biquad's are cascadable second-order filter elements, and
when cascaded, high order filters can be constructed. Biquads are comrnonly used in industry in
filter design, hence, the creation of a tunable biquad is highly desirable. So that the results of the
biquad filter may be comparable to the first-order design, a tuning range with a -3 dB frequency
tunable from 30- 1 10 MHz was selected.
The biquad circuit chosen for use with the tunable capacitor ce11 is shown in Fig. 14 and is
a comrnon design for g,-C biquad filten [21]. This second-order filter element consists of 4
transconducton and 2 capaciton, and is capable of both low-pass and band-pass operation. The
transfer functions of this circuit is shown below.
1.2 pm CMOS
138 %
30 dB
3.1 V
3.6 mW
31 -64MfIz
3.1 V
30 mW
29 - 36 MHz
206 %
30 dB
124 %
23 dB
Figure 14. The Tunable Capacitor Biquad Filter Design (a) schematic diagram of biquad circuit; (b) circuit diagram of transconductor.
To create a tunable biquad filter out of the design in Fig. 14a, the tunable capacitor cell,
first seen in the first-order test filter, was used again. There are wo differences between the ceus
used in the first-order filter, and the cells used here. The first difference is the technology used.
The tunable biquad was designed in NorTel's 0.8 pm BiCMOS process. This short channel
technology should display stronger short channel effects than the 1.2 pn technology used earlier
in the first-order filter. Only CMOS circuits were used with this design, so that compatibility with
digital CMOS processes was maintained. The second difference between the cells from the first-
order design and the tunable biquad cells is the number of cells per capacitor. As the gate area of
transistors shnnks with the smaller technology used, a greater number of cells must be used to
achieve the sarne capacitance. A ratio of 8.3/1 was chosen for W/L of MI, resulting in a transistor
gate area of 1.2 pn by 10 p, with a Cgd of 12 fF, as determined by (2.4). T m - s i x tunable
capacitor cells were used in parallei to increase the total capacitance to 430 fE
This tunable capacitor ce11 is vulnerable to parasitic capacitances at the gate in the same
way as the earlier design, and a similar, long, narrow layout was used to minimize routing
capacitances. As the width of the routing connections are smaller with the BiCMOS process, and
the highest routing metal is m e r above the substrate, routing capacitances are expected to be
substantially smdler than the earlier CMOS design. A capacitor with more cells is expected to
have a larger total fixed parasitic capacitance. However, the ratio of tunable capacitance to fixed
capacitance is expected to nse. This is because the fixed capacitance consists of two components,
one associated with the individual capacitor cells, and the other associated with routing to and
from the capacitor itself. While the first component will increase lineady with the number of
cells, the second wiU rernain fixed.
The transconductor design chosen is based on a modified differential pair and is known to
be linear with long channel devices and fast with short chamel.devices [7] [22]. This circuit is
that of a differential pair with no current source and is shown in Fig. 14b. As the intended
purpose of this uansconductor is to test the usefulness of the tunable capacitor, short channel
devices were used. 0.8 x 3.8 pm transistors were used for the current rnirror Mg, and 0.8 x 1.5
pm transistors for the differential pair M4. Simulations predict a transconductance of 80 pA/V.
With no current source to adjust, no g, tuning is possible in the traditionai manner of adjusting
the bias current and thus this transconductor is a good choice to test the tuning ability of the
tunable capacitor. The distonion of this device was measured to be 30 dB, indicating a linearity
of 5 bits. Any measurement of the linearity of the tunable capacitor is Iimited by the linearity of
the transconductors, and thus higher values are not expected.
To counter possible problerns with circuit mismatch due to the different values of g,
required, transconductor cells of a fixed size- were created. Integer values of these cells were
connected in parallel to obtain the required transconductance. Thus any mismatch in fabrication
should affect al1 transconductors simultaneously. The layout of the biquad circuit is shown in Fig.
HSPICE simulations of the low-pass output of the tunable biquad indicated that, by
altering the current of Is2, the -3 dB frequency was tuned from 40 MHz to 110 MHz, a 175%
tuning range. A lowest -3 dB frequency of 40 MHz with a transconductance of 80 pA/V
Figure 15. Layout of the Biquad Tunable Capacitor Filter
corresponds to a total maximum capacitance of 550 fF, or approximately 15.5 fF per cell. This
value agrees quite closely with the hand-calculated value of 12 fF. The dynamic range of a 1
MHz, 0.5 volt peak-to-peak test signal was 32 dB, indicating a linearity of 5 bits. These
simulations are summarized in Table 5 and plotted in Fig. 16.
As the simulations indicated that a 275% tuning ratio was achievable, this filter was
subrnitted for fabrication. A 0.8 pn BiCMOS process was supplied by NorTel and 5 prototype
chips were returned for testing. A photomicrograph of the prototype circuit is shown in Fig. 17.
Unfortunately, an error in the buffer prevented testing of this design.
Table 5: Simulation Results for Second-Order Biquad Filter.
Category Simulation
(single cell) Simulation
(thirty six cells)
--
Circuit Area
l
Technology
- -
Power Consurnption I 120 p W I 4.3 m W
Tuning Range (Hz) 1 520-580- 1 40- 11OMHz
0.8 p BiCMOS
Tuning Range (5%) 1 112 % 1 275 %
0.8 jun BiCMOS
Signal Swing I 200 mV I 200 mV
2.10 Summary on Tunable Capacitor Based Filter Structures Chapter 2 has focused on the use of integrated tunable capacitors in high-speed filters.
Short channel g,-C filters, in particular, could benefit from tunable capacitors, as they are not
tunable using traditional methods. An introduction to the use of a tunable capacitor was
presented, the parasitic capacitances of the CMOS transistor were exarnined, and it was shown
that Cgd had the greatest promise for the creation of a tunable capacitor.
Tuning Range of Filter
Frequency (MHz)
Figure 16. Simulated Tuning Range for the Biquad Filter
Figure 17. Photomicrograph of the Biquad Tunable Capacitor Circuit (0.8 pm process)
A design of a tirst-order low-pass filter was presented. A - 3 dB frequency tunable from
33- 100 MHz was selected for the initial design. The transfer function of the filter was denved and
the required transistor sizes .were determined. 12 tunable capacitor cells were used in this circuit
design, which used NorTel's 1.2 p CMOS4s process. Simulations showed that careful layout
technique is needed to reduce parasitic capacitances. and even then, some reduction in the upper -
3 dB frequency is expected. Simulations and test results were also presented.
A g,-C biquad filter was designed in the final section of chapter 2. A tuning range
similiar to the first filters was selected. A transconductor of 80 pA/V was fint designed, then
the required size of the tunable capacitor was determined. 36 tunable capacitor celis were used in
the circuit design, which used NorTelTs 0.8 jun BiCMOS process. Simulations showed that by
increasing the number of cells, the overall tuning range could be improved at the expense of the
upper -3 dB frequency. Simulations results were presented.
The results of investigating the tunable capacitor's suitability for tuning short channel g,-
C filiers showed that it is possible to tune g,-C filters using the tunable capacitor. Measurements
from the low end of the -3 dB frequency tuning range matched quite closely with predicted
values, confirming that the correct formulas and assumptions were used. A substantial difference
was found between the predicted and measured upper -3 dB frequency tuning range. These
simulations and results were summarized in Tables 4 & 5.
3.0 The Trioded ïkansconductor 3.1 Why do we Need Trioded 'hansconductors?
G,-C filten are ideally suited for high-speed analog filtering, especiaiiy applications
where tuning is required. These filters are able to operate at frequencies into the hundreds of
MHz and are tunable by simply adjusting a current source. Many corporations are examining this
type of filter as a possible replacement for switched capacitor filters. However, as technology
improves, and device dimensions shnnk, tuning g,-C filters becomes more difficult. As was
mentioned in section 2.1, g, in saturation is proportional to the square root of the bias current for
long channel devices [L 2 lSpm), but is a constant dependant only on device parameters for
short channel devices (L 5 LSprn). This makes it impractical to tune g, by the traditionai
method of adjusting the bias current, and alternative methods are needed for shon channei
transconductors.
A number of solutions to this problem of how to tune short channel transconductors have
been exarnined, among them the tunable capacitor concept from Chapter 2. While the previous
chapter has shown that tunable capaciton are possible, the experimental results indicate that this
technique, due to modelling problerns, currently possesses a small tuning range. An alternative
technique which has shown promise is the use of a triode mode transistor as a transconductor. A
number of recent publications [IO], 11 Il, [12], 1131 have focused on the triode mode transistor.
The low power consumption and compact circuit size of this technique offen a prornising
solution for the tuning of shortchamel g,-C fiiters. In triode mode, ail terrninals of a MOSFET
transistor affect g,. The regulated cascode, used eariier to control VDs of a triode mode
MOSFET, c m be used again for a similar purpose, ailowing the signai to use the v, terminal.
3.2 Transconductances in MOSFETs MOSFETs exhibit a number of transconductances available for tuning. While the simpler
model of transconductance show in Fig. 17 was sufficient for the tunable capacitor design, a more
detailed model of transconductance is required in a trioded transconductor design.
The transconductance of a MOSFET transistor in both triode and saturation mode cm be
broken into 3 components, with the overaii effect determllied by superposition. In triode, the
equations given by the gate transconductance g,, the substrate transconductance gmb, and the
drain transconductance gd are (161 1171
Drain p
l l
Substrate O
cg: 0 Source
Figure 17. Simple Transconductance Mode1 of a Transistor
The equations (3.1), (3.2), and (3.3) are the long Channel transconductance equations. A small
signai mode1 of a MOSFET in viode is shown in Fig. 18a. and a plot of their broad characteristics
is shown in Fig. 18b.
Of the three transconductances under consideration. g,b is the least useful since it is quite
small in the triode and saturation region, precluding the creation of a compact circuit.
Additionaily, as most CMOS processes make use of a comrnon substrate, it is impossible to use
the substrate as a signal input. Some advanced processes could isolate each transistor
individually, allowing the use of the substrate as an input. but only at additional cost and
complexity. Consequently, only g, and gd are worthwhile candidates. Both exist in triode, and
exhibit a large change with bias conditions. Unfortunately, (3.3) is only an approximate
characterization. It is known that gd is typically poorly modelled [17]. As g, has a
straightfonvard linear relationship, it is a more attractive option.
While gd was found to be unsuitable, the use of g, remains a viable option. Theoretical
predictions show that in saturation g,
! 1 Cox ( W/L) (VGS - VT) , while in triode the
is a constant at its maximum value of
transconductance smoothly varies from O to the
maximum. This change is transconductance is much larger than the corresponding change in g,b.
This allows the construction of a more compact circuit, as multiple parallel g,b transconductors
would be required to equal the transconductance of a single g, transconductor. The linear
equation which describes g, is much simpler than the numerical approximations required for an
accurate determination of gd.
Source
Figure 18. MOSFET Transconductances (a) irnproved transconductance mode1 of MOSFET transistor, including governing equation; (b) small signal transconductances of a MOSFET vs. VDs.
1 Triode Saturation b 4
(b)
3.3 Using the Gate Tramconductance if a trioded transconductor is to be designed using g,, it is necessary to be able to estimate
its transconductance and tuning range. While (3.1) is sufficient for predicting g, in most cases, it
fails to take into account the changes in g, as channel lengths shri.uk. A better estimate of the
transconductance can be derived from the shon channel triode MOSFET equations shown below
B I .
~IDS - peff con - - - - - 1 gm -
%s Le f f v ~ s - v~~
l + Ec . k f f
Thus it is shown that g, rernains solely dependent on VDs in boih long- and short-channel
devices. This dependance on VDs is linear in the long channel case. While g, is no longer
linearly proportional to VDs for short channel devices, VDs can still be used to alter the
transconductance. However, it should be noted that the change in g, is not as great for a given
change in VDs for short channel devices. This is graphically shown in Fig. 19. Equation (3.5)
was used to calculate short-channel transconductance. The parameter (pen. C, W) /Le, was
normalized to 1 and Ec = 2 . v,,/peR, with Len = 0.6 pm, v,, = 150,000 d s , and p , ~ = 577 cm2/
I I I 1 1 I 1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
v~~ Figure 19. Relative Cornparison of Transconductances
3.4 A 'kioded 'Ikansconductor Cell As g, is dependent on VDs in both long and shon channel transistors, VDs must be held
constant while allowing Ids to exit the transistor unaltered, which requires a cun-ent buffer. The
regulated cascode, used previously to control Vos for the tunable capacitor design in Chapter 2,
can again be used for controlling Vos. A circuit which combines the triode mode transistor with
the regulated cascode is shown in Fig. 20.
To control VDs of MI, a regulated cascode circuit consisting of transistors M1, Mg, and
current source IB2 was used. The regulated cascode's feedback loop maintains a constant VDs
voltage across transistor Ml. As the bias current IBZ sets the current for M3, and thus the VGS of
M3, it controls the VDs of MI. The current output of Ml can pass out of the transconductor ce11
through M2 for use elsewhere.
Figure 20. Inverting Tnoded Transconductor
To enable the trioded transconductor ce11 to handle both positive and negative signals, a
bias current is required. Ieia allows the output current to change symmetrically between +AI and
-AI. To set IBias a PMOS transistor with an extemal bias voltage was used.
3.5 Design of a Woded lkansconductor Filter To explore the feasibility of a trioded transconductor filter, a tunable first-order low-pas
filter was selected as an initial design. As the trioded transconductor is an experimental circuit,
the fewer additional complications introduced, the more likely the circuit is to perform as
expected. Together, the triode mode MOSFET transistor, the regulated cascode, and the current
source IBias in Fig. 20 form the trioded transconductor. A common kt-order g,-C filter design is
shown in Fig. 21. Note that g,~ performs the function of a darnping resistor of value R= l/gmz.
By vwing IB2 in (3.71, g,l and g,l in (3.6) can be varied, yielding a tunable filter.
where
Equation (3.7) was caiculated using the long channel equations from Table 2. A closer estimate
cm be found using the short channel equations fiom Table 2:
Figure 21. A First-Order g,-C Filter
To implement the g,-C filter, values for g, and C should be chosen. However, as a
trioded transconductor is to be used, g, must be known before C can be fixed. For comparative
purposes, circuitry was re-used from earlier designs. Both the regulated cascode and the triode
mode transistor were taken from the tunable capacitor filter. One change made to the regulated
cascode was to reduce the size of the feedback transistor M3 to match MI and M2. There is not as
great a need for the high feedback gain as that required in the tunable capacitor circuit. Equation
(3.1) was used to produce an maximum estimated transconductance of g,= 250 j.lA/V. This value
was later refined via cornputer simulation. For continued cornparison with the tunable capacitor,
the trioded transconductor ceii was designed to use a 3.1 volt power supply.
Once g, has been determined, a value for C can be established by the design's bandwidth
goals. Given the difficulties which occurred in the design of a high-speed buffer for the tunable
capacitor filter, a more modest maximum frequency of 5 MHz was chosen. Simulations indicated
that a tuning ratio of 10:l could be achieved. As the lowest frequency of the tuning range
determines CI, a tuning ratio of 10: 1 results in a lowest -3 dB frequency of 500 kHz. With g, and
the desired transfer function, CI can then be calculated and is 6 pF using (3.6).
Once the desired ~ansfer function has determhed the required capacitance, the design of
the trioded transconductor filter c m be completed. The required capacitance area can be found
from C = ~~a ,A/ t , , . As the design of the prototype trioded transconductor uses NorTel's 0.8
prn BiCMOS process, where b,= 17.5 nm, a capacitance of 6 pF requires 5200 of
polysilicon. To avoid polysilicon cracking, this large capacitor was sub-divided into four smaller
capacitors connected in parallel. This completes the design of the trioded transconductor filter,
and the layout is shown in Fig. 22.
3.6 Simulations of the First-Order Test Filter Spice simulations of the trioded transconductor filter indicated that. by altering the current
of IB2 from 18 pA to 30 PA. the -3 dB frequency was tunable from 500 lcHz to 5 MHz, a 10: 1
tuning range. A lowest -3 dB frequency of 500 kHz with a capacitance of 6 pF corresponds to a
g, tunable from 20 ~LA/V to 2 10 PAN. The upper transconductance value agrees closely with the
calculated estimate of 250 CIAN. The upper limit is set by the transistor approaching saturation.
vhile the lower limit is set by the desired minimum output signal swing. Fig. 23 shows the
relationship between the bias cunent IB1 and the transconductance of the filter. The dynamic
range of a 1 MHz, 0.2 volt peak-to-peak test signai was 22 dB, indicating a linearity of 4 bits. As
rnodels for the triode mode transistor behaviour are expected to match the actual behaviour better
than the tunable capacitor models, it is expected that the simulations will more accurately reflect
the actual tuning range.
3.7 Results from the First-Order FiIter A photomicrograph of the prototype circuit, which was fabncated in a 0.8 pm BiCMOS
process supplied by NorTel, is s h o w in Fig. 24. Of the five chips returned for testing, one was
Filter Transconductors y Test Transconductor
Quad Capacitor
Output B uff&
Figure 22. Layout of the First-Order Tnoded Transconductor Filter
Transconductance vs. Bias Current for the Fint Order Fiter
1 I 1 1 1 I 1 I
Calculated (long channel) Simulated
Bias Current (M)
Figure 23. Simulated Transconductance Range of the First-Order Trioded Transconductor Filter
57
Figure 24. Photomicrograph of the First-Order Trioded Transconductor Filter (0.8 pm process)
58
found to function poorly for one day, and then ceased to function entirely. 3 were fouod to
perform identicaily, with a -3 dB frequency tunable from 3 - 8.5 MHz, a 283% tuning range. The
simulated and measured frequency responses of these t h circuits are summarized in Table 6
and plotted in Fig. 25. The hearity of the output signal was found to Vary fiom 18-22 dB among
these three devices. The fifth circuit behaved abnormally, possessing both a higher, srnaller
tuning range, and a substantialiy higher iinearity. The -3 dB frequency was found to be tunable
from 7-10 MHz, a 142% tuning range. The simulated and measured kquency response is shown
in Fig. 26. The linearity of the output signal was measured at 33 dB. The simulations and
measured results did not match exactiy. There are two possible explanations for this. The fist is
a non-flat frequency response of the output buffer. The second is that process variations may have
increased g, above that predicted by simulations.
Table 6: Simulation & Test Results for First-Order Riodecl Tkansconductor Filter.
Category
Technology
Simulation
Circuit Area
Power Supply
1 Tuning Range (Hz) ( 0.5 -5 .0MHz ( 3 - 8.5 MHz 1 7 - 10 MHz 1
0.8 p n BiCMOS
Power Consumption
- - - - -
Measured Results (normal)
0.43 mm2
3.1 V
-
Measured Results (abnormal)
0.8 pm BiCMOS
105 p W
Tuning Range (96)
To measure the hearity of the circuit, a sine wave was applied to the input, and a
specuum analyzer was used to measure the resulting output spectrum. By normalizing the
0.8 pn BiCMOS.
0.43 mm2
3.1 V
Linearity
Signal Swing
0.43 mm2
3.1 V
<1mW
1000 %
< l m W
22 dB
200 mV
283 % 142 9%
18-22d.B
200 mV
33 dB
200 mV
- Simulated Tuning Envelope - - - -3 dB Level
X Test Measurements (low tuning) * Test Measurements (high tuning)
m
m -15-
Frequency (MHz)
Figure 25. Transfer Function of the Fint-Order Trioded Transconductor Filter (chips #2, #3, and #4)
- Simulated Tuning Envelope - - - -3 dB Level x Test Measurements (Iow tuning)
* Test Measurements (hi& tuning) '
Frequency (MHz)
Figure 26. Transfer Function of the First-Order Trioded Transconductor Filter (Chip #5)
61
Multiples of the Fundamental Frequency
(a)
Multiples of the Fundamentai Frequency
0)
Figure 27. Output Spectrum of the First-Order Trioded Transconductor Filter (a) normal circuit; (b) abnormal circuit.
spectrum, and looking at the relativesizes of the second, third, and higher order te-, an estimate
of the linearity c m be obtained. The normalized spectnims for the fmt-order trioded
transconductor filters is shown in Fig. 27.
3.8 A 'Iiinable Biquad Filter The second design, and a goal of the trioded transconductor project, is the creation of a
tunable biquad using the triode mode transistor. Given the range and variety of filter topologies
which can be created, the creation of a tunable biquad would greatly enhance their capabilities
[23] [24]. So that the results of the biquad filter may be easily compared to the first-order filter
design, an identical tuning range, from 0.5 - 5 MHz, was chosen as the design goal.
The biquad circuit chosen for use with the trioded transconductor ceii is shown in Fig. 28
and is a common design for g,-C biquad filters [21] [22]. This second-order filter element
consists of four transconductors, three negative and one positive, and two capacitors. This biquad
design is capable of both low-pass and band-pass operation, and its transfer function, which is
Figure 28. The Tnoded Transconductor Biquad Filter Design
identical to the biquad used in the tunable capacitor biquad. is given by (2.10) and (2.1 l), while
g, can be evaluated via (3.7). This is the basic filter structure.
3.9 Design of a Biquad Woded 'Ikansconductor CeIl. To create a tunable biquad filter out of the design in Fig. 28, the trioded transconductor
cell, first seen in the first-order test filter, was used again. There are three differences between the
cells used in the first-order filter, and the cells used here. The - k t difference is the technology
used. The tunable biquad was designed in Mitel's 1.5 pm CMOS process. This longer channel
technology should display weaker short channel effects than the 0.8 p n technology used earlier in
the first-order filter. It was necessary to scale the circuit to account for this change in minimum
channel length.
The second difference between the first-order design and the tunable biquad is the addition
of a current mirror to allow both positive and negative transconductors. As the biquad filter
design requires both positive and negative ansc con duc tors, it was necessary to add an inverting
current mirror to the basic transconductor design. The positive transconductor ia shown in
Fig. 29.
The third and final difference between the first-order design and the tunable biquad is the
masterlslave auto-biasing circuit The transconductor cells are designed to accept a signal with a
particular dc bias. To ensure that a cascade of these structures operates comctly, it is necessary to
ensure that the output voltage bias is identical to the required input bias. As the output voltage
bias changes with the tuning current 13.3'2, a correction mechanism is required.
To automatically bias a dummy transconductor cell, a differential amplifier can be used.
The dummy ce11 is identical to a normal ce11 in every respect. except no signal is applied to it. The
output voltage of the d u m y ce11 was sampled by the differential op-amp and the corrective
O- vin
Figure 29. Non-Inverting Trioded Transconductor Cell
feedback signal produced was then applied to both the dummy ce11 and the other transconductor
cells of the same type. As the dimensions of the dummy cell are identical to those of the real
cells, the same corrective signai should function for all ceiis. Since both positive and negative
transconductors exist, two feedback loops are required. A dummy transconductance ceU, with
feedback amplifier, is shown in Fig. 30.
3.10 Simulations and Results for the Trioded Ttansconductor Biquad Spice simulations of the low-pass output of the tunable biquad indicated that, by altering
the current of IBZ from 0.6 pA to 28 pl, the -3 dB frequency was tuned from 1.65 MHz to 6.9
MHz. a 320% tuning range. Again, as this transconductor makes use of current signals, routing
and other parasitic capacitances have a negligible effect on the transfer function. A lowest -3 dB
frequency of 1.65 MHz with a 6 pF capacitor corresponds to a g, tuoable from 50 pA/V to 205
PAN. The simulated fiansfer function is shown in Fig. 31. Fig. 32 shows the relationship
between the bias current IBZ and the transconductance of the filter. The dynamic range of a
1 hIHz, 0.2 volt peak-to-peak test signal was 32 dB, indicating a linearity of 6 bits.
The layout of the circuit is shown in Fig. 33. A 1.5 pm process was supplied by Mitel and
five prototype chips were retumed for testing. A photomicrograph of the prototype circuit is
shown in Fig. 34. Unfortunately, no test results are available from this filter'.
However, the test buffer was found to be operational and was successfully tested. Pre-
fabrication simulations indicated that the -3 dB frequency of the buffer is 15 MHz. The measured
1 . A process error occurred during this fabrication run. The biquad filter coufd not be successfulIy tested. While some evidence of tuning could be seen on a spectrum analyzer, no meaningfu1 measurements could be taken.
Feedback Amplifier
Inverting Transconductor
Figure 30. Dummy Transconductor Cell with Feedback Amplifier
Frequency (MHz)
Figure 31. Simulated Transfer Functions of the Biquad Trioded Transconductor Filter
Transconductance vs. Current Bias for Tunable Biquad Transconductor
Bias Current (jA)
Figure 32. Simulated Transconductance Range of the Biquad Trîoded Transconductor Filter
Ampli fiers
Output Signal Buffers
Positive / Transconduc tors
b
Negative Transconductors
/ I I I J
L 0 r 5 b
\ Capacitor Ci i' - = -D
L
9 Capacitor C2
Figure 33. Layout of the Tnoded Transconductor Biquad Filter
Figure 34. Photomicrograph of the Trioded Transconductor Biquad Filter ( 1 -5 pm process)
-3 dB frequency was found to be 9 MHz. The sixriulated and measured frequency responses are
summarized in Table 7 and is plotted in Fig. 35.
Table 7: Simulation Results for the Biquad 'Ihoded 'Ikansconductor Filter.
Category Biquad Simulation
Circuit Area 1 1.07mm2 1 Technology 1.5 pm CMOS
1 Tuning Range (%) ( 420 % 1
Power Supply
Power Consumption
- -
3.1 V
430 pW
3.11 Summary on Trioded Transconductor Based Filter Structures Chapter 3 has focused on the concept of the triode mode transistor transconductor, and
how they are useful to high-speed filten. Short channel gm-C filters, in particular, could benefit
from trioded transconductors, as they are not tunable by traditional methods. A first-order low-
pas filter was designed in the first section of chapter 3. A -3 dB frequency tunable from 0.5 - 5
MHz was designed. The transfer functicin of the filter was derived and the required transistor
sizes were determined. The circuit was fabricated, tested, and the results presented. The results
did not exactly match with simulations, but variations in the fabrication process cm account for
the differences.
A gm-C biquad filter was designed using the trioded transconductor with a -3 dB
frequency tunable from 1.65 - 6.9 MHz. The similarity between the biquad filter's tuning range
and the firstsrder filter's tuning range aided in the cornparison and analysis of the results. A
Linearity
Signal Swing
- - -
32 dB
200 mV
- Simulation Results - -3 dB Level X Test Measurements
5 10 15 20
Frequency (MHz)
Figure 35. Transfer Function of the Buffer
process error during fabrication prevented testing of this circuit. It is possible to uine g,-C filters
using triode mode MOSFETs. While the tuniag range does not match simulations exactly, they
are approximately the sarne.
4.0 Cornparison and Discussion 4.1 Introduction
TWO different filter- techniques have k e n described in earlier chapters: the tunable
capacitor filter and the trioded transconductor filter. These tunable elements, shown in Fig. 36,
look similar on the surface, and perforin similar functions, yet each accomplishes tuning in a very
different fashion. The mnable capacitor technique makes use of bias controlled changes in the
parasitic capacitances of a triode mode MOSFET to perform its tuning, while the trioded
transconductor technique makes use of bias controlled changes in transconductance. Both
techniques have been simulated, implemented, and tested. In the following sections, the
advantages and pitfalls of each will be examined with particular attention to architecture,
numerical results, relative merits, and design steps. Finally, some thoughts about the future of
high-frequency analog filtering are presented.
4.2 Architecture and Layout For both structures, controlling VDs of a triode mode device was used to control the
tunable element. For the tunable capacitor, varying VDs controls the shape of the inverted
channel formed beneath the gate terminal. AS the shape of the channel changes, it, in tum, alters
the parasitic capacitances of the MOSFET as seen from the gate. For the trioded transconductor,
varying VDS controls the transconductance of the transistor. For a short channel saturated
MOSFET, the transconductance is constant, therefore to allow tuning, a triode mode device must
be used. One restriction of using a triode mode device is that VDs must be controlled in such a
way as it does not interfere with ID. This implies that a current buffer is required to control VDs
Figure 36. Tunable Fil ter Cells (a) tunable capacitor ceii; (b) trioded transconductor cell.
For both circuits, VDs was controiled with a current buffer based on the regulated cascode
structure.
The tunable capacitor design consisted of a collection of subceils connected in parallel.
This was done to allow easy addition or subtraction of cells to change the total capacitance. To
minimize the routing capacitance between ceils, each ceil was designed to be very narrow.
However, reducing the routing capacitance between ceils does not elirninate it. These
interconnections adversely affect the tuning range by adding a fixed untunable capacitance to the
circuit. The routing capacitance is dependent on the technology used. The tunable capacitance is
linearly proportional to the number of cells, while the routing capacitance is dependent on the
technology and layout used and is not proportionai to the number of cells used. Therefore the
greater number of cells used, the larger the tuning range. However, as the number of cells
increases, the total capacitance increases, and the frequency of operation drops. Additionally,
with a greater number of cells cornes a correspondingly iarger power consumption. Thus the
tunable capacitor circuit is unusual in that the frequency of operation is inversely proportional to
the power consumption.
Both circuits make use of the regulated cascode to conuol VDS of a trioded transistor. The
regulated cascode is well suited for this task. A feedback loop though M2 and Mg in Fig. 36 holds
node X at a constant voltage. The voltage level to which X is held can be altered by adjusting
current source Is2, which, in hm, sets VGS of M3. AS the regulated cascode is used for both
maintaining a signal ground at node X, and as the primary tuning element via current source IBZ, a
conflict occurs. In order to maximize the stability of the signal ground at node X, and thus
maintain a high linearity, it is desirable to maximize the gain of transistor Ms However, current
source IB2, which sets the current in transistor M3, is simultaneously used as a tuning element,
and as such. is altered in value. To ensure a large tuning range, it is necessary to allow IBZ to
assume values as low as 1 pA and as high as 200 pA, which reduces the linearity of the circuit.
The size of transistor M3 was enlarged to compensate for this effect but did not eliminate it.
4.3 Cornparison and Discussion of Results Test results from both filter types are summarized in Tables 8 & 9 below. While the results
for the trioded transconductor came close to the simulated values, the same cannot be said of the
tunable capacitor. Whiie the tunable capacitor's lower range closely matched the simulations, the
overall tuning range was smaller than expected. One explmation which accounts for the tunable
capacitor test results is Cg, capacitive nining. The characteristics of Cg, tuning, tint mentioned in
section 7.3, are a 10% tuning range and an increase in power consumption by three orders of
magnitude. Both a smaller tuning range and higher power consumption were observed in the test
results surnmarized in Table 8. These results show a 20% tuning range, and an increase in power
consumption by two orden of magnitude. A likely cause is that the isolation of Cg, was not
complete, and the tuning observed was a result of a combination of Cg, and Cgd tuning.
Table 8: Simulation & Test Results for First-Order h a b l e Capacitor Filter.
Category Measured Results
(twelve celis) Simulation (single ceIf)
Simulation (twelve ceUs)
Maximum Frequency
The results for the trioded transconductor filter were much closer to the sirnulated
- -
Minimum Frequency
Power Consumption (minimum frequency)
predictions, but not an exact match. The size of the nining range remained approximately the
300 MHz
same, but was shifted 3 MHz higher in frequency. There are two possible explanations for this
217 MHz
300 p W
64 MHz 36 MHz -
31 MHz
3.6 m W
- --
29 MHz
120 m W
behaviour. It is possible that the high-speed buffer did not have a flat response, but rather pushed
the -3 dB frequency higher than expected. It is also possible that the transconductance was
underestimated by the models used. Either of these events could account for this shift
frequency. More details about the normal and abnormal results can be found on pg. 59.
Table 9: SimuIation & Test Resuït. for First-Order TIioded Ti.ansconductor Filter.
Category Simulation Measured Results Measured Results (abnormal)
Maximum Frequency
4.4 Relative Filter M d t s
Minimum Frequency
Power Consumption (minimum frequency)
There are a number of fundamental differences between the tunable capacitor and the
5.0 MHz
trioded transconductor filters. The important characteristics of these two filtering techniques are
0.5 MHz
105 pW
sumrnarized in Table 10, and are discussed in detail below.
8.5 MHz
The first fundamental difference between filter types is total circuit area. The tunable
10 M H z
3 M H z
d m W
capacitor requires a larger total circuit area than the trioded transconductor. The tunable capacitor
filter requires a gate area comparable to an equally sized capacitor of the lowest frequency desired
7 M H z
< 1 mW
in the tuning range. If the capacitor is divided into subcells, or retained as a single large
transistor, the required gate area remains constant. This area also changes as the desired
frequency of operation changes, with less area required at higher frequencies. The trioded
uansconductor filter requires a smaller total circuit area at the frequencies that have been
explored, and this area generally remains constant. The capacitance C, from Figure 36a, can be
altered if a shifi in the operating frequency is desired. As there are certain noise restrictions on
how srnail C can become, g, can also be shifted by altenng the size of the transconductor.
Table 10: The Relative Merits of the &able Capacitor and the IIiioded 'Ikansconductor.
Parame ter
Total Circuit Area:
Power:
Device Models:
Maximum Frequency: (simulated)
Tuning Range:
Figure of Ment: m w m 1
Modified FoM: [m WIMHz]
The Tunable Capacitor
Larger
Larger
Insufficient
580 MHz
124 %
4.14
19.2
The Trioded Transconductor
Smailer
Smaller
Sufficient
300 MHz
283 %
3.33
3.49
However t h i s size change is generally srnall. Even if the transistor doubled or tripled in size, it
would result in a srnail change in the total circuit area of the trioded transconductor filter.
The second distinction between filter types is power consumption. For the tunable
capacitor filter, power consumption is proportionai to die area. As more cells are added to
increase the capacitance, more area is used, and power consumption increases. Thus, the tunable
capacitor consumes more power than the trioded transconductor filter and as the operating
frequency of the tunable capacitor rises, its power consumption drops. The power consumption
of the irioded vansconductor is lower than that of the tmable capacitor and remains relatively
constant as the operating frequency changes. This is because the operating frequency is changed
by altering devices in the circuit, rather than adding more devices.
The third distinction between filter types is the suitability of the device models. The
device models used for the trioded transconductor filter have proven accurate enough to
reasonably rneet the design specifications. m e the test results did not match the design exactly,
there was enough overlap that with ody modest adjustments to the device models, very accurate
results should be achievable. The device models used for the tunable capacitor filter require a
greater adjustment. While the lowest frequency in the tuning range matched closely with
predictions, the overall tuning range was smder than simulations predicted using current device
models. Both analog and digital designers are interested in the maximum worst-case parasitic
capacitance, and not in changes in capacitance. The models currently available for parasitic
capacitance reflect these pnonties. If the models were altered to account for changes in
capacitance, a more accurate tuning range prediction would result.
The founh distinction between filter types is the maximum frequency of operation. In
both filters, the maximum frequency is reached by reducing the available capacitance. For the
tunable capacitor filter, the capacitance was reduced by eliminating capacitor cells from the
design. until only one remains. Simulations have shown a single ce11 tunable capacitor can
operate at 580 MHz. For the trioded transconductor filter, the capacitance was reduced by
reducing the size of a fixed passive capacitor operating in conjunction with the trioded
transconductor. %y reducing its nominal size from 6 pF to 100 fE the maximum frequency of
operation rose to 300 MHz.
The fifth distinction between filter types is the tuning range. For the ninable capacitor
filter, nining range and maximum frequency are inversely proportionai. This is primarily due to
the presence of fixed parasitic capacitance. As the operating frequency increases, the tunable
capacitance is reduced and the parasitic capacitance assumes a greater percentage of the total. As
the ratio of tunable to parasitic capacitance shifts in favour of the parasitics, the tuning range of
the filter is reduced. The trioded transconductor filter does not suffer from this effect because al1
capacitances are fixed. The parasitic capacitance can be safely lumped into the total capacitance.
To compare different circuits a figure of merit is ofien used. The most common figure of
ment for filters is power/(poles x frequency ) and is typically expressed in the units rnWWpole
[25]. As low power, high order, and high-frequency operation are desirable, the lower the figure
of merit, the better the design. The figure of ment for both the tubable capacitor filter and the
trioded transconductor filter compare favourably to those filters surveyed in Table 1.
However, this figure of merit does not account for any tuning range of the filter. Witb al1
else equal, a filter tunable from 101 MHz to 105 MHz has a much better figure of merit than a
filter tunable from 1 MHz to 5 MHz. Yet a filter tunable over 500% of its base frequency should
be compared more favourably against a filter tunable over 5% of its base frequency. To better
reflect the rnerits of tunable filters, this figure of merit was modified by a dimensioniess constant
(center frequencykunable range). This preserves the standard figure of ment, including its units,
but also considers the ratio of the operating frequency to the tunable range.
The trioded transconductor filter has a lower, and thus better, figure of ment for both the
standard and rnodified cases when compared to the tunable capacitor filter. A single order of
magnitude separates the standard figures of merit, whüe two orden of magnitude separate the
rnodified figures of rnerit. This indicates that both the power consurnption and tunini rapge of the
tunable capacitor filter must be improved before it cm be considered as a substitute for the trioded
transconductor filter.
4.5 Design Steps This section addresses the need for analog integrated circuit designers to be able to create
filter designs based on the two techniques described in this work. To foïmalize the design of both
the tunable capacitor and the trioded transconductor filters, design equations and procedures are
established below.
4.5.1 The Tunable Capacitor The tunable capacitor filter described in this work is a first-order passive RC
configuration. Once the desired filter specifications are known, the fint step in the design process
is to obtain the required R and C values. The value of C is normally determined first. For
minimum power consumption a small C is preferred. However, C cannot be made arbitrarily
small. The thermal noise power associated with a capacitor is inveaely proportional to the
capacitance [26]. The equation for the thermal noise power is given in (4.1):
where k is Boltzmann's constant (
Thus, the smallest value of C can be
1.38 x l ~ - ~ ~ joule l~) and T is the temperature in Kelvin.
determined from the desired signaIlnoise ratio of the filter.
Knowing C and the desired -3 dB frequency F3'3dB, R can then be determined:
Using a triode mode MOS to obtain R places constraints on the values R. Low values of R are
best avoided as this would result in a larger than necessary C, and an appropriately higher power
consumption. Additionally, the signal source may have difficulty driving the filter if a Iow value
is chosen. Another concem for small resistors is their matching. In general, as the uncertainty in
the dimensions of W and L are of a fixed length, the larger the transistor, the better the matching
[27]. However, as chip area is always at a premium, this is not an ideal solution. The value of R
can be estimated knowing the device dimensions and the bias voltages:
1
Now that both R and C have k e n detennined, the design of the tunable capacitor sub-cells
can begin. A good starting design is available with the circuit illustrated in Fig. 36a. The Cgd
capacitance per ceIl can be estimated via (4.4) using the device dimensions of MI and some
process parameters.
The number of cells required can be calculated by C/Cgd. It may be necessary to adjust W and L
of M I slightly to allow an integer number of cells.
This completes the initiai design of the tunable capacitor filter. Computer simulations are
necessary beyond this point. These simulations are used to confirm that MR provides the correct
R, and that the CToT of the sub-ceUs equals C, so that the filter specifications are met. To
maximize the tuning range of the filter, it is also necessary to ensure that a. a mesure of the
degree of triode operation determined by (4.5), varies from O to 0.7. The value of a should not be
greater than 0.7 as distortion wil1 quickly reduce the dynamic range of the filter. Alpha can be
calculated using (4.5):
vos = ' G S - v~ 6 5 6 , = Y - dV, i + 6 - - = constant
2JG-E d V s ~
4.5.2 The Trioded 'ILansconductor The trioded transconductor fiiter described in ihis work is a first-order active g,-C
configuration. Once the desired filter specifications are known, the first step in the design process
is to obtain the required g, and C values. The value of C is normally determined first, and can be
estimated using the same thermal noise calculations used for the tunable capacitor filter.
With C and the desired -3 dB frequency, g, cm be determined using (4.6) for a first- order
filter, or (4.7) for a biquad filter.
Once g, has been determined, the trioded transconductor ce11 can be designed. Equation
(4.8) is used to determine the dimensions of M I .
Both M, and the regulated cascode structure (M2. M3) may need to be altered. Transistor M2 is
generaily matched to Ml. Mg can be altered to vade off between linearity and tuning range. The
larger W/L of Mg, the larger its gain, and thus the more stable node X is. increasing iinearity. The
smalier W/L of M3. the greater the effect ID has on it, and thus a small change in ID will produce
a larger change in the dc voltage oode to which X settles. This cornpletes the initial design of the
trioded transconductor fiiter. Cornputer simulations are necessary beyond ihis point. These
simulations are used to ensure that the correct values for C and g, have been achieved. The
parameter a should receive the same attention it did with the tunable capacitor filter, to ensure a
large tuning range.
One additional complication remains for the trioded transconductor design. For higher-
order filters, consisting of cascades of biquads and single order sections, it is necessary to ensure
that the output voltage bias of any stage is equal to the required input voltage bias of any stage.
The automatic bias structure shown in Chapter 3. performs this task. One feedback amplifier is
required for each unique tunable transconductor.
4.6 Summary At first glance, it appem that the trioded transconductor is a superior filtering technique
and should be used in place of the tunable capacitor technique. It consumes Iess power, occupies
less space, and has a larger tuning range when compared to the tunable capacitor filter. While this
may be m e today, it is by no means certain in the future.
Few methods of improvement are available for the trioded transconductor, while many
options are available for the tunable capacitor. The tunable capacitor can already operate faster
than the trioded transconductor, and possesses the potential to dramatically improve its
performance. h addition, device dimensions continue to shrink. Experimental channel lengths
are now at or below 0.25 pm [28], dramaticaiiy increasing short channel effects. As technologies
improve, and device dimensions continue to fidi, future tunable Miers may be required to rely on
their parasitic components, as the tunable capacitor does. Thus, while the uioded transconductor
may be the technolo~ of today, the tunable capacitor may be the technology of the hiture.
5.0 Conclusion 5.1 Summary
High-frequency filters are an important area of. investigation. Regardless of how far
digital circuitry and DSP spread, they will always need to interface with the real world, and
analog circuits, in particular analog Hters, will be required for this task. Analog-to-digital
converters use analog filters as anti-aliasing filters to eliminate signal distortions, while digital-to-
analog converters use analog filters as smoothing aters, to aid in the retonstniction of signals.
Analog filters are also used for phase equalization of high-speed signals sent though
communication channels.
An introduction to mixed signal IC's and the usefulness of high-frequency analog filters
was given in Chapter 1. Afier reviewing five filter topologies, the g,-C filter was shown to be the
fastest of the filter topologies, and it is easily tuned where other filters are not. However, its
ability to be tuned in the traditional fashion is Iost at high frequencies. Two potential solutions,
the integrated tunable capacitor and the triode mode transconductor, were introduced.
The tunable capacitor concept was described in Chapter 2. The structure of the MOSFET
transistor was examined, and particular attention was paid to the main parasitic capacitances. Of
these capacitances Cgd was found to be most usehl. It was found that, by altering the bias
conditions of the MOSFET, changes in the parasitic capacitance could be induced. A tunable
capacitor ce11 was designed, simulated, and incorporated into two filter designs. FinaMy, test
results from the fabricated filters were presented.
An alternative tuning technique, the trioded transconductor, was presented in Chapter 3.
The main transconductances of a MOSFET were inspected. While g, is untunable for a saturated
shon channel MOS transistor, it can be tuned over a large range for a triode mode MOS transistor.
It was shown that, by altering the bias conditions of a MOSFET, the transconductance could be
altered. A trioded transconductor ceii was designed, simulated and incorporated into two g,-C
filter designs. The need to control output voltage offset, and one technique for doing so, were
discussed. Finally. test results from the prototype filters were presented.
5.2 Original Work and Results This work investigated a new method of tuning short chànnel g,-C filters using a tunable
capacitor created from the parasitic capacitances of a triode mode MOSFET transistor controlled
by a regulated cascode. To aid in evaluating the effectiveness of the tunable capacitor filter, a
comparison was performed between the tunable capacitor and an equivalent trioded
transconductor filter tuning element also controlled by a regulated cascode. MOSFET transistors
were chosen because of their low cost and wide availability.
For each of the two types of tunable filters, a first-order filter section and a biquad filter
section were designed and fabricated. If higher order filten are desired, cascaded combinations of
these two filter sections c m be used. A first-order filter based on the tunable capacitor concept
was tunable from 29-36 MHz, with a dynamic range of 23 dB, aod a maximum power dissipation
of 30 mW. A biquad filter based on the tunable capacitor concept was designed. A first-order
filter based on the trioded transconductor concept was tunable from 3-8.5 MHz, with a dynamic
range of 22 dB, and a maximum power dissipation less than 1 mW. A biquad filter based on the
trioded transconductor concept was designed, including the onchip auto-biasing feedback circuit.
5.3 Suggestions for Future Work As with any prototype design, there are areas where further work would yield benefits.
Based on test data obtained from the tunable capacitor circuits, three steps could be taken to
improve results. The first improvement is the development of a transistor capacitance model
which emphasizes changes in capacitance with bias conditions. The second improvement to the
tunable capacitor design is to enhance the source isolation of the triode mode transistor. The test
results are more indicative of Cg, tuning rather than Cgd tuning. Consequently, enhanced source
isolation could simu1taneousIy reduce power consumption and increase the tuning range. Finally,
the developrnent of a high-speed buffer would allow higher frequency tunable capacitor filter
operation, but would require appropriate high-frequency testing equipment. Simulations indicate
that speeds could reach as fast as 580 MHz.
Based on test data obtained from the trioded transconductor circuits, the available signal
swing of the trioded transconductor is fairly small, and any improvement to this would reduce the
need for high-frequency amplification. Finally, as the regulated cascode circuit structure is the
heart of both the tunable capacitor and trioded transconductor filters, any improvement to it would
also improve both filten' performance.
Further work should increase the effectiveness of both the tunable capacitor and vioded
transconductor filters. Better models of transistor capacitance will allow a closer match between
simulatiork and test data. Improved source isolation of Cg, will increase the tuning range. @gh-
speed buffers and testing equipment will push the operating frequencies even higher. Increasing
the available signal swing will reduce the need for high-frequency amplification. Future advances
to the regulated cascode will both improve the tuning range and reduce the power consumption.
Based on the Mprovements mentioned above, it should be possible to create very high
performance tunable analog fiIters.
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Appendix A: Output B a e r Design Three different high- speed unity gain output buffer designs have k e n used by the four
filtea fabricated in this work. The design which produced useful test results was a variation on a
simple design [29]. A detailed schematic of this design is shown below. The size ratios of the
transistors are based on the minimum charnel length for the technology.
*C was set to 1 pF for the 1.2 jun CMOS process, and to 250 fF for the 0.8 pn BiCMOS process.
Figure 37. Unity Gain High Frequency Buffer
Table 11: Simulations of Aigh Speeà Buffen.
Category
Technology L
Active Area
Buffer #1
1.2 Irrn CMOS
Power Supply
Power Consumption
-3 dB Frequency
Buffer #2
0.8 p.m BiCMOS
-06 mm2
Resistive Loading
Frequency m]
.O13 mm2
5 V
27 m W
22 MHz
Capacitive Loading
Signal Swing
v ~ i a s
Figure 38. Simulated Transfer Functions of High Speed Buffers
SV ,
120 m W
- 66 MHz
50 G! 50 Q
7 PF
2.5 V
2.5
7 PF
2.5 V
2.5
Appendix B: Test Setup AU fabricated circuits were packaged in 68-pin PGA form. The CMC IC test head was
used to obtain test results from fabricated circuits. It consists of a Device Under Test (DUT)
board with a 256 pin Zero Insertion Force (ZIF) socket. A Signal Adaptor Board (SAB) provided
16 standard BNC coaxial connections to the test head. The SAB signal paths consist of 50 R
controiled impedance traces suitable for high frequency signals. Both the DUT board and the
SAB have a continuous ground plane directly beneath them. This setup enables testing at
frequencies up to 50 MHz. A schematic diagrarn of the test setup, including signal flow amows,
cm be seen below.
Figure 39. Schematic Diagram of Test Setup
Scope Power
esba-
The following list of equipment was used with this test setup: Hewlett-Packard E3610A D.C. Power Supply Hewlett-Packard 54504A Digitizing Oscilloscope Wavetek Mode1 166 Function Generator .
Hewlett-Packard 3588A Spectmm Analyzer
Function Generator S.A.B.
D.U.T
- v I -