a1.25–12.5gbpsadaptivectlewithasynchronousstatistic eye...

Research ArticleA 125ndash125 Gbps Adaptive CTLE with Asynchronous StatisticEye-Opening Monitor

Chen Cai 12 Jian-zhong Zhao 2 and Yu-mei Zhou 12

1Institute of Microelectronics of Chinese Academy of Sciences Beitucheng West Road Chaoyang DistrictBeijing 100029 China2University of Chinese Academy of Sciences Yuquan Road Shijingshan District Beijing 100049 China

Correspondence should be addressed to Yu-mei Zhou ymzhouimeaccn

Received 15 July 2018 Revised 17 October 2018 Accepted 1 November 2018 Published 15 November 2018

Academic Editor George S Tombras

Copyright copy 2018 Chen Cai et al -is is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

-e equalization of a large attenuation signal and multirate communication in high-speed serial interface is hard to balanceTo overcome this difficulty an adaptive equalization system with optimized eye-opening monitor is proposed -e designedeye-opening monitor is based on the asynchronous statistic eye diagram tracking algorithm and the eye diagram is obtainedby undersampling with the low-speed asynchronous clock With the eye-opening monitor into the adaptive loop an adaptiveequalization system combined with continuous-time linear equalization (CTLE) is completed And the inductor peakingtechnology is used to improve the capacity of compensation With SMIC 28 nm CMOS process to achieve the overall designthe power consumption and core chip area are 12mW 125 Gbps and 012mm2 respectively And postsimulation resultsshow that it can offer compensation from 6 to 21 dB for 125ndash125 Gbps range of receiving data which achieves a large range ofdata rate and channel loss and its power efficiency is 0046 pJbitdB for the worst case which is better than mostprevious works

1 Introduction

High-speed serial interface has become the inevitablechoice for high-speed data transmission However thenonideal factors of the wireline transmission channel willlead to channel noise and frequency attenuation andsignificantly reduce the quality of the received signalVarious equalization techniques had been used to com-pensate the loss among the most popular are decisionfeedback equalizer (DFE) and CTLE -e DFE can elim-inate intersymbol interference (ISI) effectively but it willincrease system complexity and for high-speed data thetime constraint is apparent On the contrary CTLE canrealize the compensation of the full-frequency band andhas simple structure and it does not need any clock signalFor that reason we choose the CTLE to realize the signalequalization

In addition a fixed preset equalizer may not work wellacross a large range of data rate it is imperative to have the

robust adaptation algorithm to achieve a well-behavedadaptive equalizer -e adaptive equalization algorithmbased on energy extraction proposed by Won et al [1] hadgood compensation effect on high-speed data but thecircuit complexity and power consumption were greatlyincreased through its algorithm Choi et al [2] used thefrequency filter to change low-frequency gain adaptivelyand the adaptive linear device had a simple circuit struc-ture but the frequency information shaped by the rectifierwas inaccurate and the stability still needed to be opti-mized -e data pattern information also had been used tochange the equalization coefficient in [3] which had betterarea and power efficient but the compensation capacitywas limited

As the optimal compensation for the high-frequencysignal and low-frequency signal is difficult to balance and itis even more difficult to cover a large range of channel lossIn order to overcome these obstacles we proposed anoptimized adaptive equalization system which is based on

HindawiJournal of Electrical and Computer EngineeringVolume 2018 Article ID 3095950 9 pageshttpsdoiorg10115520183095950

eye diagram tracking We use the asynchronous under-sampling method to obtain an on chip eye-openingmonitor And the proposed tolerance judgement in theadaptation algorithm could track the change of the datarate and it can avoid the over equalization results Besidesthe undersampling method alleviates the circuit timingconstraints and simplies the circuit design and we use theactive-inductor technology to improve the performance ofthe CTLE module e optimized CTLE combined with thedigital eye-opening monitor realizes the automaticequalization for channel changing and it also can achievethe optimal compensation results for di erent data ratese equalization system can compensate the data rate rangefrom 125Gbps to 125 Gbps and provide a wide equal-ization range from 6 dB to 21 dB And the power eciencyof the core circuit is only 0046 pJbitdB It achieves bothdesign exibility and stability also with lower powerconsumption

2 Nonideal Factors of Channel

e nonideal characteristics of transmission channelsmainly include skin e ect dielectric loss return losscrosstalk and all kinds of noises Among which the skine ect and dielectric loss are main reasons for high-frequencychannel losses [4 5] eir impacts can be expressed by

CS exp minushs lowast l( )(1 + j)fradic

[ ] (1)

Cd exp minushd lowast l( )f[ ] (2)

where hs and hd are the coecients of skin e ect anddielectric loss respectively f is the frequency and l is thetransmission distance It indicates that skin e ect loss anddielectric loss are both proportional to the channel lengthAnd when the signal frequency is relatively low thechannel attenuation is mainly resulted from the skin ef-fect With signal frequency increasing the attenuationcaused by the dielectric loss becomes more and moreobvious Taking these nonideal factors into account wecan get the frequency response trend of the actual channelshown in Figure 1 e actual channel shows low-passcharacteristics and suppresses the high-frequency signalsignicantly

3 Adaptive Equalization Algorithm

31 Asynchronous Statistic Eye Diagram Tracking AlgorithmFigure 2 shows two eye diagrams and their statistic resultsAccording to the actual eye diagram it can be concludedthat height of the eye-opening indicates the amplitude ofthe received signal In addition the thickness of the eyelidproves that if the loss signal gets an e ective and uniformcompensation after passing through the equalizationsystem With that observation the eye diagram can beobtained by two steps sampling and counting easynchronous undersampling technique is adopted toachieve eye diagram sampling [6] in which the sampling

clock is not synchronous with the periodic input signaland the sample clock is much slower than the data clockAs shown in Figure 3 the asynchronous clock is used tosample the high-speed input signal and the low-frequencyclock is sweeping the sample time across the period of theinput waveform After a certain number of samplingperiods the time domain waveform of input data can beobtained and the statistical result of sampling data rep-resents the information of input data In that way wewould realize an on-chip eye-opening monitor Andcertain eye characteristics can be extracted as long asa sucient number of samples are taken

However the adaptive algorithm in [6] has a defectthat the analysis of the statistic information is not com-prehensive enough Using comparison of Figures 2(a) and2(b) to explain that it seems that biggest sample numberof Figure 2(b) is much bigger than Figure 2(a) But whenwe focus on the compensation performance in factFigure 2(b) provides an over equalization and Figure 2(a)gets the optimal equalization result which proves thatsimply searching for the histogram that has the largestpeak value to choose the equalization coecient is notaccurate In others words not only the height of eyeopening shows the amplitude of the compensated signalthe reference voltage value corresponding to the maxi-mum value of statistics results provides useful informationtoo erefore we optimize the algorithm with a tolerancejudgement using the reference voltage to do the second-order decision e proposed optimized algorithm couldfurther improve the performance of the adaptation systemand gets the optimal equalization e ects

32 Architecture of Adaptive Equalizer Figure 4 presents thestructure of the proposed adaptive equalizer which mainlyconsists of a CTLE a full di erential dynamic comparatorand a DAC to provide reference voltage and Figure 5demonstrates the adaptation control ow chart Based onthe asynchronous undersampling technique we divide theamplitude of an eye diagram into 16 reference levels namedREFj (j 0 1 2 15) and the equalizer coecients arecalled EQi (i 0 1 2 15) which aims to provide a largerange of equalization capacities

Frequency

Am

plitu

de

ChannelEqualizerAer compensation

Figure 1 Channel frequency characteristic

2 Journal of Electrical and Computer Engineering

Number of samples0 800 1600 2400 3200

ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de

ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de (V

)

0 50 100 150 200Time (ps)

(a)


ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de

ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de (V

)

0 50 100 150 200Time (ps)

(b)

Figure 2 Eye diagrams and statistic bars (a) Optimal equalization (b) Over equalization

Input data

Asynchronousclock

Sampleddata

Figure 3 Asynchronous undersampling technique

ChannelCTLE

DACCMP

Adaptive eye monitor

SH

SH

CLK133M_b

EQ_OUT

VBGVREF

4bit

CS

REFi

EQjCLK133M

4bit

Figure 4 Proposed adaptive equalizer structure

Journal of Electrical and Computer Engineering 3

e operation process of the adaptive equalizationsystem is as follows Step 1 the adaptive eye-openingmonitor sets the original equalization coecient as EQ0the reference level is set to REF0 and then DAC outputs thecorresponding reference voltage VREF Step 2 the fulldi erential comparator compares equalized data EQ_OUTwith VREF in M (for example M 8192) CLK samplingperiods (k is the count number of sample clocks) And thecomparison result CS is transmitted to the eye-openingmonitor Step 3 the eye-opening monitor moves the ref-erence value to next level (j j + 1) and repeats samplingoperation in Step 2 until j 15 and the whole eye diagramcorresponded to EQ0 is sampled Step 4 change theequalization coecient to EQ1 and repeat operation in Step2 and Step 3 and those processes are repeated for eachequalization coecient (i 0 1 2 15) en the eye-opening monitor obtains the counting results in order tocomplete the eye diagram Step 5 the eye-opening monitorselects the optimal coecient of the equalizer and com-pletes the adaptive process

e algorithm provides a full consideration of asyn-chronous statistic eye diagram tracking In Step 5 the eye-opening monitor rstly selects the biggest and secondarypeaking value of eye diagram statistical results which are Saand Sb respectively And they both correspond to a ref-erence voltage (called vrefa and vrefb) which indicate theamplitude of eye diagram If the di erence value of Sa andSb is less than the tolerance value then it compares thereference voltages vrefa and vrefb and chooses the equal-ization coecient corresponding to the bigger referencevoltage e tolerance value is depends on comparator andsampler errors and we did the simulation of those circuitsto set the tolerance value

e settle time of the proposed adaptation process iscalculated by M (sample number) times 16 (reference voltagelevel number) times 16 (equalization coecient number) times75 ns (asynchronous clock period)sim15ms

4 Implementation of Equalizer System

e system consists of a CTLE with the active inductor a fulldi erential dynamic comparator and a DAC We usea digital circuit to achieve the algorithm to improve designexibility and meanwhile promote system performance andalgorithm eciency

41 CTLE e common structure of conventional CTLE iscapacitive degenerated di erential pair [7] as shown inFigure 6(a) e transfer function is given by

H(s) gmRd( ) 1 + sRsCs( )

1 + sRsCs + gmRs2( )( ) 1 + sRdCd( ) (3)

where gm is the transconductance of input di erence pairsAnd the expressions for the locations of zero and poles canbe deduced as wz 1(RsCs) wp1 (1 + gmRs2)RsCs wp2 1(RdCd)

is topology however su ers from limited band-width and consequently insucient compensation at highfrequencies It is because wp1 exceeds wz by a factor of(1 + gmRs2) and the DC gain drops by the same amountof factor In other words gmRs must stay low so as to avoidlarge DC loss (otherwise the interposed bu ers su er)is issue limits the maximum achievable boost in mag-nitude and phase To expand the bandwidth of CTLE theinductor peaking technology is introduced shown inFigure 6(b) e transfer function of CTLE with the in-ductor load is given by

H(s) gmRd

1 + gmRs2( )middot1 + swz1( )1 + swp1( )

middot1 + swz2( )

1 + 2ζwn( )s + s2w2n( )

(4)

where wz2 2ζwn ζ (Rd2)(CdLp)12 wn 1(Cd middot Lp)

12

and wz1 and wp1 are unchanged

Start

j=0 k=0

If CS=0 Qj=Qj+1k++

Si=Qj maxk=0 Qj=0

j+1

kltM

i+1

If |Sa ndash Sb| lt tolerance valueeq_final = max(vrefavrefb)

elseeq_final = Sa

End

i=0

jlt16

ilt16

Max value of Si ge Sasecondary value of Si ge Sb

corresponding to VREF = vrefaand VREF = vrefb respectively

Y

Y

N

NY

N

Figure 5 Proposed adaptive equalizer structurersquos adaptation control ow chart


Since a passive inductor may take large area we in-troduce an optimized structure of CTLE called the activeinductor to realize the inductive termination [8 9] whichaims to extend the output bandwidth in the presence of largecapacitive loads and save chip area A PMOS-based active-inductor circuit is used as the load of CTLE in Figure 6(c)

which enhances the compensation ability for high-speeddata It uses a MOS resistor (M2 which operates in deep-triode region) through which the output node is coupled tothe gate of the PMOS transistor M1 A level shifter con-sisting of a source follower M3 and a current source M4 isinserted between M1 and M2 to allow a lower gate bias

A0

A1

fwz wp1 wp2

Av

OUTP OUTN

INPINN

VB

Rd Rd

Rs

Cs

Cd Cd

(a)

fwz1

wp1 = wz2

wn

Av

OUTP OUTN

INPINN

IB

Rd Rd

Rs

Cs

Cd Cd

Lp Lp

(b)

OUTN OUTP

SC1 SC1

SC2 SC2

SCn SCn

SR1 SR1SR2 SR2

SRn SRn

R1

R2

Rn

C1

C2

Cn

INP INNR

C

IB

IB

VBVBRx

L

Cp

Zt

M2M1

M3

M4 IB

20

15

10

5

0

ndash5

ndash10

ndash15

107 108 109

Frequency (Hz)

Mag

nitu

de (d

B)

1010 1011

SCSR = 0000SCSR = 0011SCSR = 1100

(c)

Figure 6 CTLE circuit (a) Conventional CTLE circuit and frequency-response curve (b) CTLE with inductor peaking (c) Designed CTLEcircuit and frequency-response curve


voltage for M1 -e termination impedance of presentedCTLE is given by the following equation

Zt 1 + jωCgsR2

gds + gm( 1113857minusω2R2CdsCgs + jω Cgs + Cds + R2Cgsgds1113872 1113873

(5)

L R2Cgs11113872 1113873

gds1 + gm1( 1113857

Cp Cds1

Rx 1

gds1 + gm1( 1113857

(6)

where Cds Cgs gds and gm are the parameters of M1 andR2 is the equivalent resistor And the termination impedancecan be represented as (6)

-e inductive peaking facilitates the equalizing filterdesign and the 20 dB compensation for data rate above10Gbps becomes feasible Besides for a single transmissiondata rate as the equalizer is designed for a fixed frequencypoint the adjusting of the equalization coefficient onlydepends on the channel change While the data rate ischanging it could not achieve an optimal compensation bya coefficient fixed equalizer -erefore the RC values bothneed to be changed through the switches SR and SC toprovide different DC gains and peaking frequency-ere are4 resistance values (SR is 2 bit) and 4 capacitance values (SCis 2 bit) and they can combine out 16 sets of differentequalization coefficients -e frequency response ofdesigned active-inductor CTLE is shown in Figure 6(c) Itcan realize a compensation range of 6ndash21 dB in the effectivefrequency band the DC gain can change from minus10 dB to5 dB and the peaking frequency can scan from 125ndash125GHz (at Nyquist frequency) which can provide an area-efficient alternative for passive inductive terminations andwell satisfy the equalization ability

42 Full Differential Comparator and DAC -e full differ-ential comparator consists of the SA in the first stage and theslave set-reset (SR) latch in the second stage is shown inFigure 7(a) and Figure 7(b) is the DAC circuit using partialpressure resistance structure and hot code control switch toreduce switch number

5 Postsimulation Results

-e equalizer layout in SMIC 28 nm CMOS technology isdemonstrated in Figure 8 core circuit power consumptionand area are 12mW 125Gbps and 012mm2 respectivelyand the digital implementation is included

-e postsimulation results are shown in Figure 9 -eS-parameter curve of a 563mm PCB channel with 181 dBloss at 5 GHz is shown in Figure 9(a) and the eye diagramof the 10 Gbps receiving signal is shown in Figure 9(b) itcan be seen that the eye diagram is closed totally -eacquired eye diagram after the adaptive equalizer of 456593 336 and 1355mm PCB channels are shown in

Figures 9(c)ndash9(f ) and according channel loss are minus214 dB 625 GHz minus223 dB 5GHz minus12 dB 5GHz andminus8 dB 620MHz respectively According data rates are125 Gbps 10 Gbps 10 Gbps and 125 Gbps respectivelyBy comparing Figure 9(d) with Figure 9(e) it shows thatfor the fixed data rate while the channel length ischanging the equalization system can realize wellequalization And by comparing Figures 9(c) and 9(d) withFigure 9(f ) it demonstrates that although the data ratesare different the loss data can achieve the optimal com-pensation results after the equalization system and thechanging of signal frequency can be well tracked by theproposed adaptation algorithm And the final equalizationcoefficients for Figures 9(c)ndash9(f ) are SRSC 0000 00010110 1111 respectively On the one hand it proves thatthe equalizer can provide large compensation range on theother hand it shows that the adaptation algorithm canavoid the over equalization results with the proposed eye-opening monitor As seen from the results receiving losssignal can be well compensated after equalization and eyediagrams open well

Compared with other recent work given in Table 1 theadvantages of this design can be displayed intuitivelyComparing with the eye-openingmonitor in [15] our designcan compensate the bigger loss and the adaptation part isrealized on the chip A proposed FOM is calculated by

FOM total power

data rate lowast channel loss (7)

-e proposed figure of merit normalizes the power con-sumption transmission data frequency and channel loss whichcompares the system performance under the same evaluationindex and canmake amore comprehensivemeasurement Andas shown in the comparison table thanks to digital eye-openingtracking monitor and the asynchronous sampling techniquethe FOM of proposed adaptive equalizer is clearly superior toother designs which means that this design achieves bettercompensation ability for the same data rate and it also hasobvious advantage in power efficiency -e active-inductorpeaking technology expands the compensation ability of theequalizer which can achieve the signal frequency range from125Gbps to 125Gbps and channel losses range from minus6dB tominus21dB In the meantime the proposed optimized asynchro-nous statistic eye diagram tracking algorithm also ensures toobtain the appropriate compensation effects and avoids overequalization for the different data rate

6 Conclusion

An adaptive equalization system based on the asynchronousstatistic eye diagram tracking algorithm was realized on SMIC28nm CMOS technology As the height of eye diagram andthe concentration of statistical data are taking into account theoptimized adaptive algorithm provides a tolerance judgementto track equalized eye opening so that the equalization systemcan avoid under equalization or over equalization of differentsignal frequencies -e active-inductor peaking technologyalso enhances CTLE capacity to provide a wide equalizationrange -e adaptive equalization system can offer


Figure 8 Layout of the chip

VP VNRP RN

CLK

OUTN OUTP

(a)

R R R RVbg

Vrefp

S16 S1S2

R

S15

Vrefn

S1 S2 S15 S16

(b)

Figure 7 Circuit of full di erential comparator and DAC

Loss

0

ndash10

ndash20

ndash30

ndash40

108 109 1010

Frequency (Hz)

ndash181dB5GHz

S21

(a)

ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

0 100 200

(b)

0 40 80 120 160ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(c)

Figure 9 Continued


a compensation from 6dB to 21 dB for 125ndash125Gbps of thereceiving signal and its power eciency is 0046 pJbitdB forthe worst case It has low power consumption and strongadaptive capacity so as to greatly optimize the high-speedinterface analog front-end design As the adaptation judge-ment is realized by the digital controller it achieves a reusabledesign of the adaptive equalization system as well

Data Availability

e data used to support the ndings of this study areavailable from the corresponding author upon request

Conflicts of Interest

e authors declare that there are no conicts of interestregarding the publication of this paper

Acknowledgments

is work was supported in part by the National Science andTechnology Major Project of China (2014ZX02302002)

References

[1] HWon J Y Lee T Yoon et al ldquoA 28-Gbs receiver with self-contained adaptive equalization and sampling point controlusing stochastic sigma-tracking eye-opening monitorrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 64no 3 pp 664ndash674 2017

[2] J S Choi M S Hwang and D K Jeong ldquoA 018-μm CMOS35-gbs continuous-time adaptive cable equalizer using

enhanced low-frequency gain control methodrdquo IEEE Journalof Solid-State Circuits vol 39 no 3 pp 419ndash425 2004

[3] S Shahramian C Ting A Sheikholeslami et al ldquoA pattern-guided adaptive equalizer in 65 nm CMOSrdquo in Proceedings ofIEEE International Solid-State Circuits Conference pp 354ndash356 San Francisco CA USA February 2011

[4] J Liu and X F Lin ldquoEqualization in high-speed communi-cation systemsrdquo IEEE Circuits and Systems Magazine vol 4no 2 pp 4ndash17 2004

[5] L Tang W Gai L Shi et al ldquoA 32Gbs 133mW PAM-4transceiver with DFE based on adaptive clock phase andthreshold voltage in 65nm CMOSrdquo in Proceedings of IEEEInternational Solid-State Circuits Conference-(ISSCC)pp 114ndash116 San Francisco CA USA September 2018

[6] W S Kim C K Seong and W Y Choi ldquoA 54-Gbitsadaptive continuous-time linear equalizer using asynchro-nous undersampling histogramsrdquo IEEE Transactions onCircuits and Systems II Express Briefs vol 59 no 9pp 553ndash557 2012

[7] C H Lee M T Musta a and K H Chan ldquoComparison ofreceiver equalization using rst-order and second-ordercontinuous-time linear equalizer in 45 nm process technol-ogyrdquo in Proceedings of International Conference on Intelligentand Advanced Systems pp 795ndash800 Kuala Lumpur MalaysiaJuly 2012

[8] J Song S Hwang HW Lee et al ldquoA 1-V 10-Gbspin single-ended transceiver with controllable active-inductor-baseddriver and adaptively calibrated cascaded-equalizer forpost-LPDDR4 interfacesrdquo IEEE Transactions on Circuits andSystems I Regular Papers vol 65 no 1 pp 331ndash342 2018

[9] Y S M Lee S Sheikhaei and S Mirabbasi ldquoA 10Gbsactive-inductor structure with peaking control in 90nmCMOSrdquo in Proceedings of IEEE Asian Solid-State Circuits

Table 1 Performance comparison

Reference [10] [11] [12] [13] [14]lowast [15]lowast [6]lowast is workTechnology 65 nm 65 nm 180 nm 130 nm 110 nm 90 nm 130 nm 28 nmEqualization DFE CTLE + DFE CTLE DFE CTLE + DFE DFE CTLE CTLEAdaptation YES YES YES NO YES YES YES YESData rate (Gbs) 10 10 5 625 115 10 54 125ndash125Channel loss (dB) 162 25 68 18 217 88 6ndash16 6ndash21Supply (V) 12 mdash 18 12 13 12 mdash 0918Core area (mm2) 001 mdash mdash mdash 0014 001 018 012Power (mW) 24 66 18 1875 2535 11 3499 12FOM (pJbitdB) 0148 0264 053 0167 0102 0125 0405 0046lowastMeasurement data and others are based on simulation

ndash02

02

ndash01

01

0

0 50 100 150 200

Am

plitu

de (V

)

Time (ps)

(d)

0 50 100 150 200

ndash02ndash03

0203

ndash01

010

Time (ps)

Am

plitu

de (V

)

(e)

ndash02

00 04 08 12 16

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(f )

Figure 9 Postsimulation results of adaptive equalization for di erent data rates and channel losses


Conference pp 229ndash232 Fukuoka Japan November2008

[10] S Yuan Z QWang X Q Zheng et al ldquoA 10Gbs speculativedecision feedback equalizer with a novel implementation ofadaption in 65nm CMOS technologyrdquo in Proceedings of IEEEInternational Conference on Electron Devices and Solid-StateCircuits pp 1-2 Chengdu China June 2014

[11] M Dolan and F Yuan ldquoAn adaptive edge decision feedbackequalizer with 4PAM signallingrdquo in Proceedings of IEEE 60thInternational Midwest Symposium on Circuits and Systems(MWSCAS) pp 535ndash538 Boston MA USA August 2017

[12] S Agarwal and V S R Pasupureddi ldquoA 5-Gbs adaptiveCTLE with eye-monitoring for multi-drop bus applicationsrdquoin Proceedings of IEEE 57th International Midwest Symposiumon Circuits and Systems (MWSCAS) pp 410ndash413 CollegeStation TX USA August 2014

[13] X L Zhang Y Wang J C Cao et al ldquoA 625-Gbps 4-tap low-power decision feedback equalizer in 013microm CMOS tech-nologyrdquo in Proceedings of IEEE International Conference ofElectron Devices and Solid-state Circuits pp 1-2 Hong KongChina June 2013

[14] Y Kim Y Kim T Lee and L Kim ldquoAn 115 Gbs 14th baud-rate CTLE and two-tap DFE with boosted high frequency gainin 110-nm CMOSrdquo IEEE Transactions on Very Large ScaleIntegration Systems vol 23 no 3 pp 588ndash592 2015

[15] C Seong J Rhim and W Choi ldquoA 10-Gbs adaptive look-ahead decision feedback equalizer with an eye-openingmonitorrdquo IEEE Transactions on Circuits and Systems II Ex-press Briefs vol 59 no 4 pp 209ndash213 2012


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eye diagram tracking We use the asynchronous under-sampling method to obtain an on chip eye-openingmonitor And the proposed tolerance judgement in theadaptation algorithm could track the change of the datarate and it can avoid the over equalization results Besidesthe undersampling method alleviates the circuit timingconstraints and simplies the circuit design and we use theactive-inductor technology to improve the performance ofthe CTLE module e optimized CTLE combined with thedigital eye-opening monitor realizes the automaticequalization for channel changing and it also can achievethe optimal compensation results for di erent data ratese equalization system can compensate the data rate rangefrom 125Gbps to 125 Gbps and provide a wide equal-ization range from 6 dB to 21 dB And the power eciencyof the core circuit is only 0046 pJbitdB It achieves bothdesign exibility and stability also with lower powerconsumption

2 Nonideal Factors of Channel

e nonideal characteristics of transmission channelsmainly include skin e ect dielectric loss return losscrosstalk and all kinds of noises Among which the skine ect and dielectric loss are main reasons for high-frequencychannel losses [4 5] eir impacts can be expressed by

CS exp minushs lowast l( )(1 + j)fradic

[ ] (1)

Cd exp minushd lowast l( )f[ ] (2)

where hs and hd are the coecients of skin e ect anddielectric loss respectively f is the frequency and l is thetransmission distance It indicates that skin e ect loss anddielectric loss are both proportional to the channel lengthAnd when the signal frequency is relatively low thechannel attenuation is mainly resulted from the skin ef-fect With signal frequency increasing the attenuationcaused by the dielectric loss becomes more and moreobvious Taking these nonideal factors into account wecan get the frequency response trend of the actual channelshown in Figure 1 e actual channel shows low-passcharacteristics and suppresses the high-frequency signalsignicantly

3 Adaptive Equalization Algorithm

31 Asynchronous Statistic Eye Diagram Tracking AlgorithmFigure 2 shows two eye diagrams and their statistic resultsAccording to the actual eye diagram it can be concludedthat height of the eye-opening indicates the amplitude ofthe received signal In addition the thickness of the eyelidproves that if the loss signal gets an e ective and uniformcompensation after passing through the equalizationsystem With that observation the eye diagram can beobtained by two steps sampling and counting easynchronous undersampling technique is adopted toachieve eye diagram sampling [6] in which the sampling

clock is not synchronous with the periodic input signaland the sample clock is much slower than the data clockAs shown in Figure 3 the asynchronous clock is used tosample the high-speed input signal and the low-frequencyclock is sweeping the sample time across the period of theinput waveform After a certain number of samplingperiods the time domain waveform of input data can beobtained and the statistical result of sampling data rep-resents the information of input data In that way wewould realize an on-chip eye-opening monitor Andcertain eye characteristics can be extracted as long asa sucient number of samples are taken

However the adaptive algorithm in [6] has a defectthat the analysis of the statistic information is not com-prehensive enough Using comparison of Figures 2(a) and2(b) to explain that it seems that biggest sample numberof Figure 2(b) is much bigger than Figure 2(a) But whenwe focus on the compensation performance in factFigure 2(b) provides an over equalization and Figure 2(a)gets the optimal equalization result which proves thatsimply searching for the histogram that has the largestpeak value to choose the equalization coecient is notaccurate In others words not only the height of eyeopening shows the amplitude of the compensated signalthe reference voltage value corresponding to the maxi-mum value of statistics results provides useful informationtoo erefore we optimize the algorithm with a tolerancejudgement using the reference voltage to do the second-order decision e proposed optimized algorithm couldfurther improve the performance of the adaptation systemand gets the optimal equalization e ects

32 Architecture of Adaptive Equalizer Figure 4 presents thestructure of the proposed adaptive equalizer which mainlyconsists of a CTLE a full di erential dynamic comparatorand a DAC to provide reference voltage and Figure 5demonstrates the adaptation control ow chart Based onthe asynchronous undersampling technique we divide theamplitude of an eye diagram into 16 reference levels namedREFj (j 0 1 2 15) and the equalizer coecients arecalled EQi (i 0 1 2 15) which aims to provide a largerange of equalization capacities

Frequency

Am

plitu

de

ChannelEqualizerAer compensation

Figure 1 Channel frequency characteristic



ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de

ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de (V

)

0 50 100 150 200Time (ps)

(a)


ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de

ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de (V

)

0 50 100 150 200Time (ps)

(b)


Input data

Asynchronousclock

Sampleddata


ChannelCTLE

DACCMP


SH

SH

CLK133M_b

EQ_OUT

VBGVREF

4bit

CS

REFi

EQjCLK133M

4bit










1 + sRsCs + gmRs2( )( ) 1 + sRdCd( ) (3)



H(s) gmRd


middot1 + swz2( )

1 + 2ζwn( )s + s2w2n( )

(4)


12


Start

j=0 k=0

If CS=0 Qj=Qj+1k++

Si=Qj maxk=0 Qj=0

j+1

kltM

i+1


elseeq_final = Sa

End

i=0

jlt16

ilt16



Y

Y

N

NY

N





A0

A1

fwz wp1 wp2

Av

OUTP OUTN

INPINN

VB

Rd Rd

Rs

Cs

Cd Cd

(a)

fwz1

wp1 = wz2

wn

Av

OUTP OUTN

INPINN

IB

Rd Rd

Rs

Cs

Cd Cd

Lp Lp

(b)

OUTN OUTP

SC1 SC1

SC2 SC2

SCn SCn

SR1 SR1SR2 SR2

SRn SRn

R1

R2

Rn

C1

C2

Cn

INP INNR

C

IB

IB

VBVBRx

L

Cp

Zt

M2M1

M3

M4 IB

20

15

10

5

0

ndash5

ndash10

ndash15

107 108 109

Frequency (Hz)

Mag

nitu

de (d

B)

1010 1011

SCSR = 0000SCSR = 0011SCSR = 1100

(c)




Zt 1 + jωCgsR2


(5)

L R2Cgs11113872 1113873

gds1 + gm1( 1113857

Cp Cds1

Rx 1

gds1 + gm1( 1113857

(6)









FOM total power



6 Conclusion




VP VNRP RN

CLK

OUTN OUTP

(a)

R R R RVbg

Vrefp

S16 S1S2

R

S15

Vrefn

S1 S2 S15 S16

(b)


Loss

0

ndash10

ndash20

ndash30

ndash40

108 109 1010

Frequency (Hz)

ndash181dB5GHz

S21

(a)

ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

0 100 200

(b)

0 40 80 120 160ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(c)

Figure 9 Continued



Data Availability




Acknowledgments


References













ndash02

02

ndash01

01

0

0 50 100 150 200

Am

plitu

de (V

)

Time (ps)

(d)

0 50 100 150 200

ndash02ndash03

0203

ndash01

010

Time (ps)

Am

plitu

de (V

)

(e)

ndash02

00 04 08 12 16

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(f )













RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de

ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de (V

)

0 50 100 150 200Time (ps)

(a)


ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de

ndash03

ndash02

ndash01

0

01

02

03

Am

plitu

de (V

)

0 50 100 150 200Time (ps)

(b)


Input data

Asynchronousclock

Sampleddata


ChannelCTLE

DACCMP


SH

SH

CLK133M_b

EQ_OUT

VBGVREF

4bit

CS

REFi

EQjCLK133M

4bit










1 + sRsCs + gmRs2( )( ) 1 + sRdCd( ) (3)



H(s) gmRd


middot1 + swz2( )

1 + 2ζwn( )s + s2w2n( )

(4)


12


Start

j=0 k=0

If CS=0 Qj=Qj+1k++

Si=Qj maxk=0 Qj=0

j+1

kltM

i+1


elseeq_final = Sa

End

i=0

jlt16

ilt16



Y

Y

N

NY

N





A0

A1

fwz wp1 wp2

Av

OUTP OUTN

INPINN

VB

Rd Rd

Rs

Cs

Cd Cd

(a)

fwz1

wp1 = wz2

wn

Av

OUTP OUTN

INPINN

IB

Rd Rd

Rs

Cs

Cd Cd

Lp Lp

(b)

OUTN OUTP

SC1 SC1

SC2 SC2

SCn SCn

SR1 SR1SR2 SR2

SRn SRn

R1

R2

Rn

C1

C2

Cn

INP INNR

C

IB

IB

VBVBRx

L

Cp

Zt

M2M1

M3

M4 IB

20

15

10

5

0

ndash5

ndash10

ndash15

107 108 109

Frequency (Hz)

Mag

nitu

de (d

B)

1010 1011

SCSR = 0000SCSR = 0011SCSR = 1100

(c)




Zt 1 + jωCgsR2


(5)

L R2Cgs11113872 1113873

gds1 + gm1( 1113857

Cp Cds1

Rx 1

gds1 + gm1( 1113857

(6)









FOM total power



6 Conclusion




VP VNRP RN

CLK

OUTN OUTP

(a)

R R R RVbg

Vrefp

S16 S1S2

R

S15

Vrefn

S1 S2 S15 S16

(b)


Loss

0

ndash10

ndash20

ndash30

ndash40

108 109 1010

Frequency (Hz)

ndash181dB5GHz

S21

(a)

ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

0 100 200

(b)

0 40 80 120 160ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(c)

Figure 9 Continued



Data Availability




Acknowledgments


References













ndash02

02

ndash01

01

0

0 50 100 150 200

Am

plitu

de (V

)

Time (ps)

(d)

0 50 100 150 200

ndash02ndash03

0203

ndash01

010

Time (ps)

Am

plitu

de (V

)

(e)

ndash02

00 04 08 12 16

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(f )













RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia









1 + sRsCs + gmRs2( )( ) 1 + sRdCd( ) (3)



H(s) gmRd


middot1 + swz2( )

1 + 2ζwn( )s + s2w2n( )

(4)


12


Start

j=0 k=0

If CS=0 Qj=Qj+1k++

Si=Qj maxk=0 Qj=0

j+1

kltM

i+1


elseeq_final = Sa

End

i=0

jlt16

ilt16



Y

Y

N

NY

N





A0

A1

fwz wp1 wp2

Av

OUTP OUTN

INPINN

VB

Rd Rd

Rs

Cs

Cd Cd

(a)

fwz1

wp1 = wz2

wn

Av

OUTP OUTN

INPINN

IB

Rd Rd

Rs

Cs

Cd Cd

Lp Lp

(b)

OUTN OUTP

SC1 SC1

SC2 SC2

SCn SCn

SR1 SR1SR2 SR2

SRn SRn

R1

R2

Rn

C1

C2

Cn

INP INNR

C

IB

IB

VBVBRx

L

Cp

Zt

M2M1

M3

M4 IB

20

15

10

5

0

ndash5

ndash10

ndash15

107 108 109

Frequency (Hz)

Mag

nitu

de (d

B)

1010 1011

SCSR = 0000SCSR = 0011SCSR = 1100

(c)




Zt 1 + jωCgsR2


(5)

L R2Cgs11113872 1113873

gds1 + gm1( 1113857

Cp Cds1

Rx 1

gds1 + gm1( 1113857

(6)









FOM total power



6 Conclusion




VP VNRP RN

CLK

OUTN OUTP

(a)

R R R RVbg

Vrefp

S16 S1S2

R

S15

Vrefn

S1 S2 S15 S16

(b)


Loss

0

ndash10

ndash20

ndash30

ndash40

108 109 1010

Frequency (Hz)

ndash181dB5GHz

S21

(a)

ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

0 100 200

(b)

0 40 80 120 160ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(c)

Figure 9 Continued



Data Availability




Acknowledgments


References













ndash02

02

ndash01

01

0

0 50 100 150 200

Am

plitu

de (V

)

Time (ps)

(d)

0 50 100 150 200

ndash02ndash03

0203

ndash01

010

Time (ps)

Am

plitu

de (V

)

(e)

ndash02

00 04 08 12 16

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(f )













RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia




A0

A1

fwz wp1 wp2

Av

OUTP OUTN

INPINN

VB

Rd Rd

Rs

Cs

Cd Cd

(a)

fwz1

wp1 = wz2

wn

Av

OUTP OUTN

INPINN

IB

Rd Rd

Rs

Cs

Cd Cd

Lp Lp

(b)

OUTN OUTP

SC1 SC1

SC2 SC2

SCn SCn

SR1 SR1SR2 SR2

SRn SRn

R1

R2

Rn

C1

C2

Cn

INP INNR

C

IB

IB

VBVBRx

L

Cp

Zt

M2M1

M3

M4 IB

20

15

10

5

0

ndash5

ndash10

ndash15

107 108 109

Frequency (Hz)

Mag

nitu

de (d

B)

1010 1011

SCSR = 0000SCSR = 0011SCSR = 1100

(c)




Zt 1 + jωCgsR2


(5)

L R2Cgs11113872 1113873

gds1 + gm1( 1113857

Cp Cds1

Rx 1

gds1 + gm1( 1113857

(6)









FOM total power



6 Conclusion




VP VNRP RN

CLK

OUTN OUTP

(a)

R R R RVbg

Vrefp

S16 S1S2

R

S15

Vrefn

S1 S2 S15 S16

(b)


Loss

0

ndash10

ndash20

ndash30

ndash40

108 109 1010

Frequency (Hz)

ndash181dB5GHz

S21

(a)

ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

0 100 200

(b)

0 40 80 120 160ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(c)

Figure 9 Continued



Data Availability




Acknowledgments


References













ndash02

02

ndash01

01

0

0 50 100 150 200

Am

plitu

de (V

)

Time (ps)

(d)

0 50 100 150 200

ndash02ndash03

0203

ndash01

010

Time (ps)

Am

plitu

de (V

)

(e)

ndash02

00 04 08 12 16

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(f )













RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



Zt 1 + jωCgsR2


(5)

L R2Cgs11113872 1113873

gds1 + gm1( 1113857

Cp Cds1

Rx 1

gds1 + gm1( 1113857

(6)









FOM total power



6 Conclusion




VP VNRP RN

CLK

OUTN OUTP

(a)

R R R RVbg

Vrefp

S16 S1S2

R

S15

Vrefn

S1 S2 S15 S16

(b)


Loss

0

ndash10

ndash20

ndash30

ndash40

108 109 1010

Frequency (Hz)

ndash181dB5GHz

S21

(a)

ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

0 100 200

(b)

0 40 80 120 160ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(c)

Figure 9 Continued



Data Availability




Acknowledgments


References













ndash02

02

ndash01

01

0

0 50 100 150 200

Am

plitu

de (V

)

Time (ps)

(d)

0 50 100 150 200

ndash02ndash03

0203

ndash01

010

Time (ps)

Am

plitu

de (V

)

(e)

ndash02

00 04 08 12 16

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(f )













RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



VP VNRP RN

CLK

OUTN OUTP

(a)

R R R RVbg

Vrefp

S16 S1S2

R

S15

Vrefn

S1 S2 S15 S16

(b)


Loss

0

ndash10

ndash20

ndash30

ndash40

108 109 1010

Frequency (Hz)

ndash181dB5GHz

S21

(a)

ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

0 100 200

(b)

0 40 80 120 160ndash02

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(c)

Figure 9 Continued



Data Availability




Acknowledgments


References













ndash02

02

ndash01

01

0

0 50 100 150 200

Am

plitu

de (V

)

Time (ps)

(d)

0 50 100 150 200

ndash02ndash03

0203

ndash01

010

Time (ps)

Am

plitu

de (V

)

(e)

ndash02

00 04 08 12 16

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(f )













RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



Data Availability




Acknowledgments


References













ndash02

02

ndash01

01

0

0 50 100 150 200

Am

plitu

de (V

)

Time (ps)

(d)

0 50 100 150 200

ndash02ndash03

0203

ndash01

010

Time (ps)

Am

plitu

de (V

)

(e)

ndash02

00 04 08 12 16

02

ndash01

01

0

Time (ps)

Am

plitu

de (V

)

(f )













RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia












RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia


a1.25–12.5gbpsadaptivectlewithasynchronousstatistic eye...

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