A TH-UWB Transmitter and its Pulse Generation Circuit for Intra/Interchip Wireless Interconnection

Pran Kanai Saha, Nobuo Sasaki and Takamaro Kikkawa

Research Centre for Nanodevices and Systems, Hiroshima University Phone: +81-824-24-6265, Fax: +81-824-22-7185, Email: sahapk@sxsys.hiroshima-u.ac.jp

respectively. The Hspice simulation is done from extracted view of the layout and results are shown in Fig, 4. The performance of the transmitter is given in table 1.

1. Introduction Steady downscaling of semiconductor device dimensions has been the main stimulus to achieve higher speed and performance of integrated circuits over the past decades. Unfortunately scaling has a reverse effects on interconnect delay associated with the parasitic R, L and C of conventional wiring. The introduction of low resistivity copper and low-permittivity (k) dielectrics can mitigate this problem. But the integration of these materials into integrated circuit fabrication is a complex task requiring material process and new techniques. Moreover it has also material limits due to chip area and minimal power requirements. New technology such as RF wireless interconnect using integrated antenna, transmitter and receiver is proposed for intra/interchip clock and data distribution [1, 2]. This future wireless interconnection essentially will form a local area network (LAN) as shown in Fig. 1 on a chip or among different chips. For high data transmission rate and multiple access capability of this wireless interconnection system, it requires wideband characteristics of each component [3]. A fully integrated time-hopped (TH)-UWB transmitter and its pulse generation circuit for wireless interconnection in future ULSI is developed and presented in this paper.

3. Monocycle pulse measurement

2. TH-UWB transmitter The circuit schematic of time hopped UWB transmitter is shown in Fig. 2. TH-UWB transmitter first generates a typical time shifting or time hopped with pulse position modulation pulse and this pulse is then used to generate UWB signal. A typical UWB signal generated by the kth transmitter (i.e. kth user or kth chip) is given as [4] (1) )()( )(

]/[)( k

Njck

jftrk

sdTcjTtwts ∆−∑ −−=

The measurement system consists of Agilent 81134A pulse pattern generator, infiniium digital oscilloscope and dc power supply. The SRP of width 0.1ns and GCP of width 0.5ns as shown in Fig. 7 are applied to MCP generator by using pulse pattern generator. Both applied pulses has equal rise and fall time of 70ps with a repetition rate of 400 MHz. The monocycle pulse is measured by infiniium digital oscilloscope and is shown in Fig. 8. The fig. 8 shows that the measured monocycle pulse is not symmetric because of low amplitude of negative part which may be due to the effect of high distributed parasitic resistance. The simulation also confirms this effect as shown in Fig. 9 where the black curve is the simulated monocycle pulse for the same inputs and without considering the effect of output pad buffer. The measured monocycle pulse width (1.13ns) as shown in fig. 8 differs from the desired pulse width of 0.5ns. This is due to the effect of low frequency buffer of the TSMC output pad. To investigate this effect, the monocycle pulse generator along with low frequency output buffer instead of TSMC output pad buffer is simulated. The simulation result as shown in red curve of fig. 9 depicts the same effect as found in measurement. The absence of asymmetric in this case is due to not considering the output buffer parasitic effect.

The test chip of monocycle pulse (MCP) generator shown in Fig. 5 is designed and fabricated by using TSMC 0.18 µm CMOS mixed signal process. The die microphotograph of the circuit is shown in Fig.3. The MCP generation circuit occupies an area of 0.19mm2. The fabricated chip is bonded on a test PCB as shown in Fig. 6.

Where, wtr(t) represents the transmitted Gaussian monocycle, Tf is the frame time, cj

k is the hopping number, Tc is the chip rate, ∆ is the modulation time and dj

k is data (0 or 1). Here the time shifted pulse train is generated from the frame clock. The multiplexer selects the time shifted frame clock which is generated by the voltage controlled oscillator( VCO), divider and delay line, according to PN (pseudorandom) sequence with three hopping bits (i.e hopping number cj

k varies from 0 to 7). Here, eight channels are considered for initial investigation of the proposed system. Linear feedback shift register which consists of four clocked D-type Flip-Flop along with an exclusive-or logic as feedback is used to generate such PN sequence. The time shifting due to pulse position modulation (PPM) to encode data is done by the fine delay line which provides a delay of approximately the modulation time (0.05ns). Two to 1 multiplexer finally selects the time shifted pulse train due to PN sequence and PPM according to data symbol (“0” or “1”). The time shifted pulse train is then used to produce monocycle pulse with wide bandwidth by monocycle pulse (MCP) generator. It consists of RLC network with RC filter, pass gate and pulse generation circuit for generating the short rectangular pulse (SRP) and gate control pulse (GCP) [5]. The chip is fabricated using TSMC 0.18µm CMOS mixed signal process. The die microphotograph and chip layout is shown in Fig. 3a and Fig. 3b

4. Conclusion We developed and fabricated a single chip TH-UWB transmitter by using 0.18 µm CMOS technology and its performance is analysed by simulation. UWB transmitter pulse generator circuit which generates monocycle pulse is tested and measurement result is presented. The measurement results show that the monocycle pulse can be generated from RLC network along with RC filter and pass gate from the time hopped signal. References [1] A B M H Rashid, S Watanabe and T. Kikkawa, IEEE EDL,

Vol.23, No.12, Dec 2002, p. 731-733. [2] Brian A. Floyd, Chih-Ming Hung and Kenneth K.O. IEEE

JSSC, vol 37, No. 5, May 2002, p. 543-552. [3] P.K. Saha, N. Sasaki and T. Kikkawa, Proc. of IEEE

ISSSTA’2004, Australia, p. 962-966. [4] Moe Z Win and Robert A. Scholtz, IEEE Transactions on

communications, vol 48, No. 4, April 2000, p. 679-691. [5] P.K. Saha, N. Sasaki and T. Kikkawa, Extended Abstract of

SSDM’ 2004, Japan, p. 394-395.

8 to 1 Multiplexer output

Fig. 1 Wireless interconnect system for future ULSI (a) Intrachip and (b) Interchip.

0 5 10 15 200

0.51.01.5

0

2 to 1 Multiplexer output

Volts

Time(ns)

0 10 15 200

0.51.01.5

0 Frame 2.5ns 5.0ns 7.5 ns 10.0ns 12.5ns 15ns 17.5ns

Volts

Time (ns)

0 10 15 200

0.51.01.5

0

Volts

Time (ns)

0 5 10 15 20

-0.10.00.10.2

MC

P(vo

lts)

Time (ns)

0 1 2 3 4 5 6 7 8 9 100

-30-20

00

dB

Frequency (GHz)

0 5 10 15 200.00.51.01.52.0 Hopping bit 0

Hopping bit 1 Hopping bit 2

Volts

Time (ns)

0 2 4 6 8 10

-0.10-0.050.000.050.100.150.20

Before output pad buffer After output pad buffer

MC

P (V

olts

)

Time (ns)

0.

2.

0. 2.

0.

-1

-4

Fig. 4 Simulation output: (a) Delayed frame; (b) Three hopping bits; (c) RZ data [ 1 1 0 0 0] ; (d) Multiplexers output (e) Monocycle Pulse (MCP) train and (f) FFT of monocycle pulse.

Time shifted frame 800 MHz VCO

Ring oscillator MCP generator

400 MHz Chip Impedance

Matching ckt

RX RXTH-UWB transmitter

Initial Shift data

TX 50 MHz Frame ÷2 RX RX

Delay lines UWB Pulse Generator RX =Receiver TX= Transmitter ÷2

(a) LFSR D1 D7 D0 (a) ÷2 Differential output analog buffer

8 to 1 Multiplexer

Monocycle pulse generator IC1 IC2 PN Seq. ÷2

TX Tx Antenna RX 2 to 1 MultiplexerTime shifting for PPM

Data (b) (b)

Fig. 2 TH-UWB Transmitter Schematic. Fig. 3 (a) Die Microphotograph; (b) TH-UWB transmitter layout.

Table I: Transmitter performance data

UWB system Time hopping Impulse Carrier Frequency No carrier Transmitter Signal bandwidth

3.3 GHz

Data rate 50 Mbps Single Channel datarate

400 Mbps

Modulation Pulse position modulation

Average power consumption

12.5 mW

Architecture All digital except pulse generator

Technology TSMC 1.8v, 0.18 µm CMOS mixed signal process

Implementation Single chip Circuit Size 0.729 mm2 (excluding

antenna) Application Short distance (on chip

wireless interconnection for future ULSI)

Bond wire 2.SRP

Bonded Output pad5(a) Bond wire

Buffer MCP Bond wire GCP

SRP= Short Rectangular Pulse, GCP=Gate Control Pulse MCP= Monocycle Pulse

Fig. 5 Monocycle pulse generator with bonded wire and output pad buffer.

(b)

5(c) SRP GCP

volts Pulse pattern Generator

Digital Oscilloscope

SRPGCP MCP (d) DC Power Supply

Time (ns) Vdd PCB

Fig. 7 Input pulses from pulse pattern generator to generate MCP.

(e)

P

Fig . 6 Test setup for monocycle pulse generator. CB

(f)

1.13ns

Fig. 9 Simulated monocycle pulse (considering bonded wire and outputpad buffer).

Fig. 8 Measured Monocycle pulse.

0 1 2 3 4-25

-20

-15

-10

-5

0

5

FFT

Am

plitu

de (d

B)

Frequency (GHz)

0 2 4 6 8 10

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20 Before output pad buffer After output pad buffer

MC

P (V

olts

)

Time (ns)

A THA TH--UWB Transmitter and its Pulse Generation Circuit for UWB Transmitter and its Pulse Generation Circuit for Intra/Inter Chip Wireless InterconnectionIntra/Inter Chip Wireless Interconnection

Pran Kanai Saha , Nobuo Sasaki and Takamaro KikkawaPran Kanai Saha , Nobuo Sasaki and Takamaro Kikkawa

　　　　Research Research CenterCenter for for NanodevicesNanodevices and Systems, Hiroshima Universityand Systems, Hiroshima University11--44--2 2 KagamiyamaKagamiyama, Higashi, Higashi--Hiroshima, 739Hiroshima, 739--8527 Japan 8527 Japan

EE--mail: sahapk, nsasaki, kikkawa@sxsys.hiroshimamail: sahapk, nsasaki, kikkawa@sxsys.hiroshima--u.ac.jpu.ac.jp　　　　　　

MOTIVATIONAdvanced wireless interconnect system could be a solution for interconnect delay problem due to parasitic Resistance, capacitance and inductance in future ULSI

Tx

RxRx

RxRx

Rx

Rx Rx

Rx

Rx

RxAntenna

Subcircuit

Subcircuit

RxTx

IC2IC1

IntraChip

Wireless Interconnection

Interchip

Requirement High Data rate

Multiple access

+=

NSBC 1log 2

Shannon’s channel Capacity theorem REQUIRE WIDEBAND

Transmitter and Receiver

TH- UWB TRANSMITTER

Data and Clock PPM

Programmable Time Delay

Frame Clock

PN SequenceGenerator

UWB Pulse Generator

UWB Antenna

[ ]( )∑ ∆−−−=j

kNjc

kjf

ks

dTcjTtwts /)(

)( ][kNjc

kjf s

dTcjTt ∆−−−δ)( fjTt−δ

kNj s

d ][∆kjc

Total time shifting (cj

kTc+∆dk[j/Ns]) must be

less than Tf

cjkTc <Tf where 0

≤cjk < Nh For 3 bit

hopping Nh varies from 0 to 7 (23-1) Tc <Tf/Nh

Frame-1 Frame-2

Tc=2.5ns

Tf=20ns

0 1 2 3 4 5 6 7

∆=0.06ns

0 1 2 3 4 5 6 7

τ=0.3ns

Tf=20ns

Tc=2.5nsTc=2.5ns

UWB PULSE2

284456.5)(

−

= τπ

τ

t

etAtwMonocycle pulse τ- Pulse Width

A –Amplitude

3rd Hiroshima International Workshop on Nanoelectronics for Terabits Information Process

December 6, 2004. Hiroshima, JAPAN.

Time Hopped Signal (THS)=

Tx=Transmitter, Rx=Receiver

TH-UWB TRANSMITTER CIRCUIT SCHEMATIC

Spiral Inductor

Multiplexer

VCOLFSR

Delay

MCP

Pulse generator

Simulation output: (a) Delayed frame; (b) Three hopping bits; (c) RZ data [ 1 1 0 0 0] ; (d) Multiplexers output (e) Monocycle Pulse (MCP) train and (f) FFT of monocycle pulse.

(a)

(b)

(c)

(d)

(e)

(f)

CHIP MICROPHOTOGRAPH AND LAYOUTHSPICE SIMULATION TRANSMITTER PERFORMANCE DATA

Short distance (On chip wireless interconnection for future ULSI)

Application0.729 mm2 (excluding antenna)Circuit SizeSingle ChipImplementation

TSMC 1.8V, 0.18 µm CMOS Mixed Signal Process

Technology

All digital except pulse generation circuit

Architecture 12.5 mWAverage Power ConsumptionPulse Position ModulationModulation400 MbpsSingle Channel Data rate

50 MbpsData Rate (Considering Eight Channel)

3.3 GHzTransmitter Signal BandwidthNo CarrierCarrier FrequencyTime Hopping ImpulseUWB System

MCP MEASUREMENT SETUPPulse pattern Generator Agiilent 81134A

SRPGCP

Agilent Infiniium digital Oscilloscope (1.5GHz)

MCP

DC Power Supply

Vdd

MONOCYCLE PULSE GENERATOR

TH-UWB TransmitterVCO

Divider DelayLFSR Monocycle Pulse

Generator 8 to 1 Multiplexer2 to 1 Multiplexer

PG

VddInput pad Output pad

InputpadGND

Pass gateGCPSRP

Time (ns)

Volt

SRP= Short Rectangular Pulse GCP= Gate Control Pulse MCP= Monocycle Pulse

RLC network with RC filter produces damped sinusoidal signal (Vosc) from SRP

RLC network start oscillation for

2

2

41

LR

LC>

−= 2

2

41

21

LR

LCf

π

Frequency of Oscillation

FFT of MEASURED MCP

Time (ns)

Volt

MEASURED MCP FOR A GIVEN INPUT PULSES

CONCLUSIONSMCP FROM SIMULATION

GCPSRP

Without Timehopped

With Time Hopped

Monocycle Pulse Generator outputMonocycle Pulse Generator Inputs

GCP- Pulse width 0.5ns, Rise and fall time ~70 ps

SRP-Pulse width 0.1ns, Rise and fall time ~70 psMeasured Monocycle Pulse width=1.13 ns Peak to peak amplitude 0.6V

Low amplitude of negative part of measured monocycle pulse may be due to the effect of high distributed Parasitic resistance .

Increase of pulse width and asymmetric waveshape change the monocycle pulse center frequency to 0.8GHz.

Increase of pulse width maybe due to low frequency buffer of the output pad and ground inductance.

SRP and GCP are generated from Time hopped signal (THS) which contains information by pulse generator (PG) consisting of voltage controlled delay circuit, exclusive-or (XOR), NAND and inverter.

SRP AND GCP GENERATION CIRCUIT

Delay Buffer SRP

Delay Buffer

THS

GCP

Pulse Generator (PG)

XOR

XOR

NAND

Vn1

Vn2

Two identical circuit are used to produce SRP and GCP from THS

Number of transistors required to generate SRP and GCP are same

Thus delay due to parasitics RC will be same in both SRP and GCP generation

No delay between SRP and GCP, rising time of both the pulses will be same.

Technology: TSMC 0.18 µm mixed signal process

UWB Transmitter 0.729 mm2

Monocycle pulse Generator: 0.19mm2

Area

1.13ns

R L

C

R1

C1

R2

C2

GCP

MCP

Bonding Wire

Bonding Wire

RB LB

CB

Output pad Non Inverting Buffer Amplifier

Bonding Wire

50Ω

SRP

Frame clock is generated from voltage controlled ring oscillator which consists of Five stage current straved inverter with transmission gate in series at each stage and divider .

Frame clock is delayed through delay circuits.

PN sequence is generated by Linear feed back shift register with Exclusive-or (XOR) as Feedback logic.

Multiplexers is implemented using combinational logic gates.

MCP generator along with non-inverting output buffer instead of TSMC output pad buffer is simulated.

Simulation confirms that output pad buffer change the pulse width as found in measurement.

FFT of MCP

This work is supported by the Ministry of Education, Culture, Sports, Science and Technology, Japan under the 21st Century COE program at Hiroshima University.

ACKNOWLEDGEMENT

FFT of measured MCP is obtained from Infiniium digital oscilloscope

Monocycle pulse can be generated from RLC network with RC filter and Pass gate. The circuit can be implemented by using the current CMOS technology which led us to implement the UWB transmitter in a single chip.

TH-UWB transmitter is designed and fabricated . Time hopped signal due to PN sequence and PPM is generated from time shifted frame. Time shifting is performed by delay circuit. Thus it is only necessary to keep constant delay with any variation of Vdd and substrate voltage.

Pulse width of generated monocycle limits data rate of UWB transmitter because data rate is inversely proportional to the monocycle pulse width. Data rate can be increased by generating short monocycle pulse. This can be done by using low value of inductance in RLC network of MCP generator.

VCO Ring oscillator

Divider 2:1

Divider 2:1

Divider 2:1

800 MHz signal

Delay lines D1

8 to 1 Multiplexer

D7

D0 Linear Feedback Shift register (LFSR)

400 MHz clock for PN Sequence

Time shifted frame due to PN sequence

Fine Delay line for Additional Time shifting for PPM

Data In

2 to 1 Multiplexer

Total Time shifted frame clock for a data

Impedance Matching network

UWB Pulse Generator

Divider 2:1

Single input dual output analog buffer

Tx Antenna

50 MHz Frame clock

Initial shift

[1 0 0 0]

[ ]( )∑ ∆−−−=j

kNjc

kjf

ks

dTcjTtwts /)(

)( ][kNjc

kjf s

dTcjTt ∆−−−δ

)( fjTt−δ

Hopping bits

0 5 10 15 200.0

0.5

1.0

1.5

2.0 8 to 1 Multiplexer output 2 to 1 Multiplexer output

Volts

Time(ns)0 5 10 15 20

0.0

0.5

1.0

1.5

2.0

Frame 2.5ns 5.0ns 7.5 ns 10.0ns 12.5ns 15ns 17.5ns

Volts

Time (ns)

0 5 10 15 200.0

0.5

1.0

1.5

2.0

Volts

Time (ns)

0 5 10 15 20

-0.1

0.0

0.1

0.2

MC

P(vo

lts)

Time (ns)

0 1 2 3 4 5 6 7 8 9 10-40

-30

-20

-10

0

FFT

Am

plitu

de (d

B)

Frequency (GHz)

0 5 10 15 200.0

0.5

1.0

1.5

2.0 Hopping bit 0 Hopping bit 1 Hopping bit 2

Volts

Time (ns)

(a)

(b)

(c)

(d)

(e)

(f)

-3dB

BW=3.3 GHz

Due to PPM and circuit delay

Due to circuit delay

P-19