a systematic topology evaluation methodology for high-density

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008 2665

A Systematic Topology Evaluation Methodology forHigh-Density Three-Phase PWM AC-AC Converters

Rixin Lai, Student Member, IEEE, Fei (Fred) Wang, Senior Member, IEEE, Rolando Burgos, Member, IEEE,Yunqing Pei, Member, IEEE, Dushan Boroyevich, Fellow, IEEE, Bingsen Wang, Senior Member, IEEE,

Thomas A. Lipo, Life Fellow, IEEE, Vikram D. Immanuel, Member, IEEE, and Kamiar J. Karimi, Member, IEEE

Abstract—This paper presents a systematic evaluation approachof three-phase pulsewidth-modulated (PWM) ac–ac convertertopologies for high-density applications. All major components andsubsystems in a converter are considered and the interdependenceof all the constraints and design parameters is systematically stud-ied. The key design parameters, including switching frequency,modulation scheme, and passive values, are selected by consider-ing their impacts on loss, harmonics, electromagnetic interference(EMI), control dynamics and stability, and protection. The com-ponent selection criteria as well as the physical design proceduresare developed from the high-density standpoint. The concept ofusing the same inductor for harmonic suppression and EMI filter-ing is introduced in the design. With the proposed methodology,four converter topologies, a back-to-back voltage source converter(BTB-VSC), a nonregenerative three-level boost (Vienna-type) rec-tifier plus voltage source inverter (NTR-VSI), a back-to-back cur-rent source converter (BTB-CSC), and a 12-switch matrix con-verter, are analyzed and compared for high specific power usingSiC devices. The evaluation results show that with the conditionsspecified in this paper, BTB-VSC and NTR-VSI have considerablylower loss, resulting in higher specific power than BTB-CSC andthe matrix converter. The proposed methodology can be applied toother topologies with different comparison metrics and can be auseful tool for high-density topology selection.

Index Terms—High density, SiC devices, switching frequency,three-phase ac–ac converter.

I. INTRODUCTION

I T IS OFTEN desirable to reduce the size and weight ofa converter, while meeting performance and cost require-

ments. In some cases, such as in aircraft applications, small

Manuscript received December 1, 2007; revised May 3, 2008. First publishedNovember 25, 2008; current version published December 9, 2008. This workwas supported in part by The Boeing Company and in part by the National Sci-ence Foundation—Engineering Research Center under Award EEC-9731677.Recommended for publication by Associate Editor B. Wu.

R. Lai, F. Wang, R. Burgos, and D. Boroyevich are with the Center forPower Electronics Systems, Virginia Polytechnic Institute and State Univer-sity, Blacksburg, VA 24061 USA (e-mail: [email protected]; [email protected];[email protected]; [email protected]).

Y. Pei is with the School of Electrical Engineering, Xi’an Jiaotong University,Xi’an 710049, China (e-mail: [email protected]).

B. Wang is with the Department of Electrical Engineering, Arizona StateUniversity, Tempe, AZ 85287-9309 USA (e-mail: [email protected]).

T. A. Lipo is with the Department of Electrical and Computer Engi-neering, University of Wisconsin, Madison, WI 53715 USA (e-mail: [email protected]).

V. D. Immanuel and K. J. Karimi are with The Boeing Com-pany, Seattle, WA 98124 USA (e-mail: [email protected];[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2008.2005381

size and lightweight is a must. The power stage is the main sizeand weight contributor in a converter, including power semicon-ductor device packages, cooling systems, energy storage, andfilter passive components [1]. The power stage design clearlydepends on the converter circuit topology. Therefore, to achievea high-density design, it is a logical and necessary step to carryout the systematic design and evaluation for the topologies thatmeet the application requirements, and select among them themost suitable candidate.

For three-phase ac–ac converters, such as industrial mo-tor drives, the two-level pulsewidth-modulated (PWM) voltagesource inverter (VSI) with six-pulse diode front-end rectifier hasbecome the topology of choice, due to its simplicity and rela-tively low cost. One drawback of the diode front-end topology isthe low-order, low-frequency harmonics on the dc link and ac in-put line, which, consequently, requires a bulky dc-link capacitorand inductor (ac or dc) filters. In order to improve converter per-formance and achieve higher power density, many topologiesfor three-phase ac–ac converters or motor drives with activefront-end rectifiers have been proposed and studied [2]–[11].These topologies can generally operate with reduced passivecomponents and an improved input current waveform. On theother hand, they may have increased loss and electromagneticinterference (EMI) noise, requiring additional cooling and fil-tering [12]. Different active front-end topologies have differentloss, harmonics, and EMI characteristics, which often have con-tradictory impact on the size and performance of the converter.To achieve a high power density design for a specific application,comprehensive analysis and evaluation are needed to obtain anoptimal converter topology selection.

There has been considerable work on ac converter topolo-gies evaluation and high-density design [13]–[20]. The previ-ous work generally focused on specific aspects of the converterdesign. For instance, the steady-state current and voltage wave-forms as well as the harmonics injected to the grid for twoinverter topologies were compared in [13]; device losses, inputfilter, and cost for three-level voltage source converters (VSCs)were discussed in [14]; different converter systems were evalu-ated in terms of the grid-side power quality and loss distributionin [15]–[17]; the efficiency of the current source and the volt-age source drive systems was compared in [18], the minimumenergy storage requirement on the dc link was studied in [19]and [20]. However, when developing a new converter for high-density applications, all aspects contributing to the convertersize and weight must be examined in the design, which requiresthat the correlation between all major design parameters be

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2666 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

Fig. 1. Key components for an ac–ac converter.

clearly established. There is a clear need then for a systematicevaluation methodology considering the strong interdependenceof all design variables and constraints. For example, increasingswitching frequency generally helps to reduce the passive size,but it also increases the converter switching loss, and there-fore, heatsink size. As will be shown later in the paper, eventhe relationship between the filter size and switching frequencyis not monotonous, as a result of changing loss characteristicsand attenuation requirements of harmonic and EMI standards.Generally speaking, operation conditions and constraints havegreat influence on the component and converter size and weight.The constraints can be physical ones as well as performanceand system related. The examples of physical constraints are:maximum junction temperature for devices, acceptable temper-ature rise for magnetic and dielectric components, and voltageand current stress limits; the examples of performance- andsystem-related constraints include: power ratings, power qual-ity, and EMI requirements, etc. The auxiliary circuits, such asinrush current control, protection, and sensors, can also impactconverter size and vary for different topologies, and therefore,should be considered in the topology evaluation as well. Finally,the selection of semiconductor devices, components, materials,and packaging also affects topology choice.

This paper presents a systematic evaluation methodology ofac–ac converter topologies for high-density applications withemphasis on topologies with active front-end rectifiers. Theevaluation approach and selection criteria are first developedand described. The evaluation examines all aspects of the de-sign that contribute to the size and weight of the converter,including control, switching frequency, semiconductor deviceloss and cooling, harmonic and EMI filters, and component de-sign and selection. Compared to previous works, the impact ofthe switching frequency on the input filter is carefully studiedin this paper, culminating with some favored operating pointsfrom the EMI standpoint. The concept of using the same induc-tors for both harmonics and EMI filtering is also introduced.Following the evaluation approach, a comparison study is car-ried out for four exemplary active front-end topologies: back-to-back VSC (BTB-VSC) [3], the nonregenerative three-levelboost (or Vienna-type) rectifier plus VSI (NTR-VSI) [4]–[6],the back-to-back current source converter (BTB-CSC) [7], [8],and the 12-switch matrix converter [9]–[11]. Not only are thesefour well-known topologies for three-phase ac–ac converters,

but they also represent a broad category of implementations(two-level, three-level, voltage-source, current-source, matrix,etc.). For each topology, a least-weight design is sought underthe same design conditions. The state-of-the-art SiC devices areassumed in this study.

A main objective of this paper is to provide a useful tool forpracticing engineers for selecting a high-density topology for agiven application. While the methodology applies to both sizeand weight, the focus will be on the lowest weight design in thecomparison study, owing to the complexity involving systemlayout in determining the volume of a converter.

II. EVALUATION APPROACH

Fig. 1 shows a generic three-phase ac–ac converter diagramwith active front-end. All key size and weight contributors areshown, including the input filter, dc link (filter and auxiliary cir-cuits), output filter, switching devices, and heatsink, and needto be considered in the high-density design. It should be notedthat not all of these elements are needed for all topologies, or forall applications. The basic evaluation and comparison approachis formulated similarly to a design optimization problem [39].Design conditions and constraints are first identified, includ-ing performance constraints, such as power quality and EMIstandards, and physical conditions and constraints, such as am-bient temperature, maximum device junction temperature, andpassive component thermal and electrical limits. With a givendesign objective (in this case, size or weight), key design pa-rameters can then be varied and determined, including switchingfrequency, control/modulation strategy, minimum L and C val-ues for both energy storage and filter passives, device losses,and cooling system thermal impedances.

The flowchart in Fig. 2 shows the evaluation procedure for alow-weight topology selection. 1) First, the type of devices arespecified, whether it is insulated-gate bipolar transistor (IGBT),MOSFET, gate-turn-OFF (GTO), or SiC switches. 2) For a candi-date topology, the semiconductor devices with proper datasheetrating are preliminarily selected according to the operation con-ditions, such as operating voltage and current. 3) Select the con-trol and modulation scheme, which impacts passive and thermaldesign. 4) Choose a preferred switching frequency within afeasible range that is determined by the device characteristics.The “preferred” switching frequency concept will be explained

LAI et al.: SYSTEMATIC TOPOLOGY EVALUATION METHODOLOGY 2667

Fig. 2. Topology evaluation procedure.

later in this section. 5) With chosen modulation and switchingfrequency, the harmonic and EMI noise spectrum can be de-termined as functions of passive components, based on whichminimum L and C parameters are designed to meet the sys-tem standards. In parallel, the device loss can be determined.6) Carry out physical design and selection for inductors andcapacitors for the least weight, and carry out thermal analysisand design for heatsink with given temperature conditions andthermal impedances. 7) Evaluate the total weight of the con-verter, including the passives, heatsink, semiconductor devices,and the auxiliary circuit. Note that iterations should be expectedin the design process, such as selection of a different modula-tor, varying the switching frequency, and adjustment of devicerating selection as a result of thermal design. For clarity, theiteration processes are omitted in the Fig. 2 flowchart. All can-didate topologies can be evaluated and compared with the sameprocedure. Some of the key steps of the evaluation approach aredescribed in detail in this section as follows.

A. Modulation Scheme

The ac active converters are PWM controlled. Modulationschemes affect switching loss, as well as voltage and currentripple spectrum, and therefore, the filter design. Modulationschemes are topology dependent. In general, there are no clear“optimal” modulators since some are better for loss, while oth-ers may be better for ripple or for dynamics. Selection of themodulator is a key design choice. At least, two types of modu-lation schemes should be evaluated in high-density design, thecontinuous PWM scheme, which usually generates lower ripple,

Fig. 3. Spectrum of the PWM voltage for BTB-VSC.

and the discontinuous PWM, which results in lower loss. Forsome topologies, the modulator has extra functions, which haveto be considered, e.g., the modulator of a multilevel converteroften performs dc-link neutral-point control.

B. Preferred Switching Frequency

Switching frequency is a key design parameter. In general,increasing switching frequency is an effective way to reducepassive components and increase power density, until the in-creased loss in switching devices and in passive componentsoutweigh the benefit of the increased frequency. Therefore, fora specific application, there can be an “optimal” switching fre-quency, which depends on the system, modulator, and com-ponents. In principle, the switching frequency selection couldinvolve a search for the optimal frequency. Generally speak-ing, increasing switching frequency can reduce the size of theharmonics filter until the further size reduction becomes phys-ically limited (thermal and electrical); at the same time, it alsoincreases the heatsink size due to increased switching loss. How-ever, when considering the EMI filter, the relationship betweenthe switching frequency and the size may not be monotonousdue to the noise spectrum and the standard requirement [21].Therefore, determining the favored switching frequencies fromthe EMI standpoint is an important step for the system switch-ing frequency selection. It can help narrow down the frequencyselection range, from which we seek the “optimal” point, con-sidering all design parameters, including other passives thanEMI filters, as well as cooling systems.

Fig. 3 shows the per-unit (p.u.) spectrum of the rectifier inputvoltage for a 40-kHz switching frequency case of a BTB-VSCusing 60 discontinuous PWM (DPWM). One p.u. voltage cor-responds to half of the dc-link voltage. From this spectrum,we can extract the differential-mode (DM) and common-mode(CM) noise, and then design the input EMI filter parametersbased on the requirements of the EMI/electromagnetic compat-ibility standard [21]. Assuming 1 p.u. voltage of 325 V (i.e.,dc voltage of 650 V), Fig. 4 shows the relationship obtainedbetween the required filter corner frequency (a two-stage filterwith 80 dB attenuation is assumed) and the switching frequency


Fig. 4. Corner frequency versus switching frequency.

based on the DO-160E standard [22], which defines the maxi-mum power line noise current as 53 dB·µA at 150 kHz. A higherfilter corner frequency is desirable since it indicates a smallerfilter. The nonmonotonous relationship in Fig. 4 indicates thathigher switching frequencies do not necessarily lead to higherfilter corner frequencies, unless the switching frequencies arebeyond 300−500 kHz. Clearly, there are some preferred switch-ing frequencies, from the standpoint of input EMI filters, as canbe seen in Fig. 4: below 40-, 70-, 140-, or above 300–500 kHz.Similar relationships can be established for other voltage levels,other topologies, or different filter structures. In final switchingfrequency determination, the impacts on the harmonics filterand the loss should also be included. The result will vary withthe given specifications, and will also depend on which factorplays the dominant role. As can be seen in the later sections, theimpact of the EMI filter is dominant compared to the harmonicsfilter under the conditions studied in this paper.

C. Loss Calculation and Heatsink Design

With the selected modulation scheme and switching fre-quency, the power stage design can be carried out, particularly,design of the major weight/size contributors of heatsink and pas-sives. The key to the heatsink design is power semiconductordevice losses, which are highly dependent on the device charac-teristics. There are many device characterization methods. Fortopology evaluation study, it is appropriate to use a linear ap-proximation device model in (1)–(4) for the loss calculation.The conduction voltage drop of the devices is given by (1) and(2), where Vf T and RON are the threshold forward voltage andthe ON-resistance of the switching device, Vf D and RD are theforward voltage and the ON-resistance of the diode, and vT , iTand vD , iD are the voltages and currents of switch and diode,respectively. The switching loss energy eT ON(OFF) and eD revfor the switch and diode at operating point v(t) and i(t) can bemodeled in (3) and (4), where eT ON(OFF) r and eD rev r are theswitching energy and the reverse-recovery energy at the mea-sured operating point vr and ir , which can be obtained fromeither the datasheet or experiments. Note that the device param-eters Vf T , RON, Vf D , RD , eON(OFF) r , and erev r are all significant

Fig. 5. Device thermal structure illustration.

Fig. 6. Thermal equivalent model.

functions of junction temperature. For the evaluation, the appro-priate temperature should be assumed, usually corresponding tothe peak junction temperature

ON-state voltage drop of switch: vT = Vf T + RONiT (1)

ON-state voltage drop of diode: vD = Vf D + RD iD (2)

Switching energy of switch: eT ON(OFF) = eT ON(OFF) r

× v(t)i(t)vr ir

(3)

Switching energy of diode: eD rev = eD rev r

× v(t)i(t)vr ir

. (4)

Given the semiconductor devices and operating conditions,the power loss for any given topology and modulation schemecan be found with (1)–(6). Examples of loss calculations willbe given for selected topologies and devices in Section III.

Knowing the loss, thermal calculation can be performed. Fortopology evaluation, a 1-D equivalent thermal model, consistingof equivalent thermal impedances of device package, heatsink,and other thermal interface materials, should be sufficient. Fig. 5shows an example of the thermal interface structure and Fig. 6shows the corresponding 1-D steady-state thermal equivalentcircuit, where Qc is the power loss generated by the device, R1is the thermal resistance from junction to case, R2 represents thethermal resistance of the thermal interface between the case andthe heatsink, and R3 is the thermal resistance of the heatsink tothe ambient. Tj , Th , and T0 are temperatures of the semicon-ductor device junction, heatsink, and ambient, respectively. Thethermal resistances can be obtained from the datasheet, mea-surements, or simulation. If there is transient overload, thermalcapacitances should also be considered. In the case without tran-sient overload, the junction temperature of the kth device canbe obtained as in (5), where Tj k and Qc k correspond to the


Fig. 7. (a) LC–LC filter for VSC; (b) CL--CL filter for CSC.

junction temperature and power losses for the kth device, andTlimit is the upper limit for the operating junction temperaturefor that device (e.g., 125 C for many commercial Si devices)

Tj k = Qc k (R1 + R2) + Th ≤ Tlimit . (5)

With (5), the acceptable upper limit of the heatsink temper-ature corresponding to that particular device may be readilyfound. For an ac converter with multiple devices, this valuecould vary with device, and the lowest one should be chosen asthe upper temperature limit for the whole heatsink. Then, therequired thermal resistance for the heatsink is given in (6). Witha given ambient temperature and cooling method/conditions,heatsinks can be selected or designed to meet the requirementof (6) and the corresponding size and weight of the coolingsystem can be determined

R3 = (Th − T0)/Qc. (6)

D. Passive Component Parameter Minimizationand Physical Design

Depending on topologies, the passives in an ac–ac convertercan include a dc-link capacitor and/or dc-link inductor, and anac input line inductor or capacitor, as well as an input and/oroutput filter for suppressing harmonics, EMI, and dv/dt. Theoutput filters are generally application dependent and will notbe considered in this paper. The approach used here should beapplicable to output filters for specific applications.

1) Energy Storage Capacitance and Inductance Minimiza-tion: For energy storage passives, i.e., dc-link and ac-line ca-pacitors and inductors, minimum parameters should first be de-termined according to a number of performance and system re-quirements. The parameter selections are topology dependent.In general, for a dc-link capacitor (for voltage source topology)or inductor (for current source topology), their selection needsto consider the following requirements.

1) Energy storage: The dc-link voltage variation (for voltagesource topology) or current variation (for current sourcetopology) caused by the instantaneous energy unbalanceshould be limited to an acceptable level. The energy unbal-

ance can be caused by a sudden change in load or sourceconditions.

2) Stability: Impedance characteristics of the dc link deter-mine the stability of the converter system [23].

For an ac-line inductor (for boost topology) and capacitor (forbuck topology), their selection needs to consider the followingrequirements.

1) Harmonics: This is often in terms of total harmonic dis-tortion (THD).

2) Peak ripple current: The peak ripple current as resultsof switching or others will impact the inductor flux, andtherefore, their sizes.

3) Inrush: High current peak will occur in voltage sourcetopologies during startup or recovery from a voltagenotch, which will impact inductor design and the capacitorselection.

2) Filter Passive Minimization: The ac input filters shouldalso be designed to meet EMI standards requirements. For com-parison discussion, this paper uses a two-stage LC–LC filter forvoltage source topologies, as shown in Fig. 7(a), and a CL–CLfilter for current source topologies, as shown in Fig. 7(b). Thedesign objective is to minimize the L and C values while com-plying with the EMI standard. Given the standard requirementand the noise spectrum, which can be obtained through anal-ysis, such as double Fourier analysis, the required attenuationand then the filter corner frequency can be determined. Whiledamping design for high-frequency resonance is an integral partof filter design, it is omitted here since damping componentscontribute little to weight and size and they can be common forall topologies. Both passive [24] and active [25], [26] damp-ing schemes can be used. Note that the EMI filter passives andenergy storage passives can be combined or integrated in thedesign for further reduction of size and weight, which meansthat the input filter can be designed as one entity to achieve har-monic and EMI filtering functions as well as for energy storage.Examples of such a design will be shown in Section III.

3) Capacitor Design and Selection: In most practical con-verter designs, the capacitors are selected based on availablecommercial parts. For high density and lightweight design, thesmallest and lightest capacitors should be selected that alsomeet the capacitance, voltage, current, and thermal require-ments. Commercial film capacitors are selected in this paper for


Fig. 8. Design variable for the three-phase EE core.

Fig. 9. Design variables for the toroid core.

comparison purposes. The section examples are demonstratedin Section III.

4) Inductor Design: Toroid cores are assumed for the CMchoke, and EE cores for ac-line and dc-link inductors. The de-sign constraints are: required inductance and physical limitssuch as saturation, window area, insulation, and maximum tem-perature rise [27]. The leakage inductance of the CM choke [28]is also considered as a design constraint in order to achieve therequired DM attenuation. In this paper, ferrite (R material) fromMagnetics is used for the ac-line and dc-link inductor design,and nanocrystalline (FT-3M) material for the CM choke design.The core losses under sinusoidal excitation are given by (7) [29]and (8) [30], where the core loss is in watts, f is the frequencyin kilohertz, dB is the peak flux density change in kilogauss,and Vcore is the core volume in cubic centimeters. Based on (7)and (8), the improved generalized Steinmetz equation [31] canbe used to calculate the core loss of the inductors.

Loss of ferrite (R material):

Pcore = 7.4 × 10−5f 1.43 dB2.85 Vcore (7)

Loss of nanocrystalline (FT-3M material):

Pcore = 8.34 × 10−5f 1.621 dB1.982 Vcore . (8)

An optimization function (FMINCON) in Matlab is used todetermine the physical dimensions to achieve minimum weight.The design variables are the core dimensions (as shown in Figs. 8and 9), air gap, and the number of turns. All the design con-straints mentioned earlier are considered and the total weightis the objective function for both inductors. Based on this algo-rithm, the optimal inductor design and the corresponding weightcan be obtained under the given operating conditions and thedesigned inductance value.

E. Auxiliary Circuits, Design Variation, and Iteration

In addition to cooling and passive components, the other rel-atively important topology-dependent weight contributors in-

clude power device packages and auxiliary circuits, such asinrush control and protection circuits. Together, the total weightof the converter can be determined and compared with the resultof a different design or topology.

Clearly, for each given topology, there can be different designswith different converter weights, with all meeting the perfor-mance requirements and design constraints. In principle, everykey parameter can have its design range. In practice, designvariation and iteration should be performed to achieve the leastweight design. For example, there are several preferred switch-ing frequencies observed in Fig. 4, and the most suitable oneneeds to be selected through design iteration. The device ratingselection should be traded off with losses, thermal impedance,and heatsink. The design variation can be systematically carriedout following the flowchart process in Fig. 2 and even automatedwith computer programming or optimization.

III. TOPOLOGY COMPARISON

Based on the proposed approach, four three-phase ac–ac ac-tive front-end topologies, as shown in Fig. 10, are evaluated andcompared. While these candidate topologies cover a range ofcircuits often used in high-density converter design and study,their selection is not meant to be exhaustive and is intendedonly to demonstrate the effectiveness of the evaluation pro-cedure, which should also be applicable to other topologies.Table I lists the sample system specifications and requirementsused in this comparison study. SiC devices are selected in thecomparison since they offer the advantages of low loss, highswitching frequency, and high operating temperature [32]. Thecommercial SiC diode C2D20120 (1200 V/20 A) and a 1200V/5 A JFET from SiCED are selected in this study. The diodeparameters are available from the datasheet. At 175 C, the JFEThas ON-resistance of 0.8 Ω and switching energy of 155 µJ (at400 V/10 A) [33]. The number of paralleling devices requiredvaries with the topologies according to the current and thermalrequirement. For comparison purposes, all candidate topologieskeep the same total number of devices (a total of 72 devicesincluding the diodes and JFETs).

As explained in Section II, switching frequency is a key de-sign parameter. There are preferred switching frequencies forthe front-end rectifier based on input EMI filter requirements.In principle, for the inverter, the switching frequency can be sep-arately selected based on output filter requirements and the loadspecifications. Since the output filter is very application depen-dent, and therefore, omitted in this paper, the inverter switchingfrequency is chosen to be the same as the rectifier for comparisonpurposes. In the comparison study, four switching frequenciesare used, 40-, 70-, 100-, and 140 kHz, and the correspondingdesigns are obtained and compared.

A. BTB-VSC

As shown in Fig. 10(a), BTB-VSC is a popular topology inmany applications. A 60 DPWM is implemented in this paperfor better EMI noise performance and lower semiconductor losscompared to continuous PWM [34]. In Fig. 11, the simulationwaveforms of ac-line currents and PWM line-to-line voltage


Fig. 10. (a) BTB-VSC. (b) Nongenerative three-level boost rectifier plus VSI. (c) BTB-CSC. (d) 12-switch matrix converter.

TABLE ISYSTEM SPECIFICATIONS

Fig. 11. Simulation results for BTB-VSC: (a) ac-line currents; (b) PWM line-to-line voltage.

are shown (circuit parameters: Lin = 100 µH, Cdc = 10 µF,fSW = 40 kHz).

1) EMI Filter: The double Fourier integral transform is ap-plied to determine the harmonic spectrum of the phase-leg pul-sating voltage. The harmonic components of the phase-leg volt-age for the BTB-VSC are given by (9) [34], where Vdc is thedc-link voltage, ωs is the angular switching frequency, and ω0is the angular fundamental frequency. The outer integral limityf and yr and the inner integral limit xf and xr are determinedby the modulation scheme. For 60 DPWM, they are shown inTable II, where M is the modulation index defined as the peak

phase voltage over half of the dc-link voltage.

Cmn =1

2π2

∫ yf

yr

∫ xf

xr

Vdcej (mωs t+nω0 t)d(ωst) d(ω0t). (9)

Fig. 3 in Section II shows the spectrum analysis results for a40-kHz switching frequency case with 60 DPWM scheme, andthe EMI filter parameters based on the DO-160E requirementsare shown in Fig. 4, which lead to the determination of preferredswitching frequencies, of below 40-, 70-, 140 kHz or beyond 300kHz. For comparison purposes, the capacitors Cx and Cy areselected to be 1 µF and 6.8 nF, respectively, for all the topologies,and then the inductances vary to meet the corner frequency.For the 40 kHz case, the common-mode and differential-modeinductances are 11.5 mH and 110 µH, respectively.

2) AC-Line Inductor: The design of ac-line inductance con-siders: 1) harmonics; 2) instantaneous current peak; 3) EMI; and4) inrush current. For harmonics, the requirement is often spec-ified for each individual component. For example, in DO-160E,the limit of the even current harmonic with the order higher thanfour (up to 40) is 0.25% of the fundamental current. Since thephase-leg voltage harmonic is the source of the current ripple,we can determine the required line inductance with the result ofthe spectrum analysis and the corresponding harmonic require-ment for a given switching frequency. For the two-stage inputfilter structure, the relationship between the current harmonicand the filter parameters is given by

Ih =uh

ωL |2 − ω2LC| (10)

where uh is the amplitude of the harmonic voltage achieved bythe spectrum analysis, and ω is the corresponding frequency.If the switching frequency is within the range defined by theharmonic current requirement, then the input inductance shouldalso be designed to limit the relatively low-frequency currentharmonic based on (10). For instance, if the switching frequencyis 32 kHz, the required inductance of each stage is 336 µH (as-suming 1 µF for the capacitance). The required inductance is


TABLE IIOUTER AND INNER DOUBLE FOURIER INTEGRAL LIMITS FOR DPWM (PHASE A)

about three times the value designed based on the EMI require-ment. Although the lower switching frequency can improve theefficiency and reduce the heatsink, the total system size increasesdue to the tremendous increase of the inductors. Therefore, thelow switching frequency boundary is selected to be 40 kHz toavoid relatively low-order harmonics, given the 400–800 Hz fun-damental frequency range. For a different design specification,a lower or higher switching frequency range may be selected.

The input current THD is also often used as a constraint fora converter design. The THD limit is chosen to be 20% in thispaper. Both harmonic spectrum and THD limits are consideredin the design, with the spectrum limits playing the dominant role.

In addition to the harmonics requirement, the instantaneouscurrent peak should be limited within a reasonable range toguarantee the proper control and protection of the circuit. Oneimportant impact of the current peak is on the inductor core peakflux density. The peak ripple current is given by (11), where Ts

is the switching cycle, Vp is the peak phase voltage, and L is theac-line inductance. In this paper, the ripple limit is chosen to behalf of the peak fundamental current, and then, the required lineinductance is 80 µH

∆i =12

(1 − 3

4M

)TsVp/L. (11)

The ac-line inductor should also consider the inrush condi-tion. During the startup, the current is usually best limited byother schemes (such as precharge or current limiting circuit) ina high-density converter, and therefore, is not a concern. On theother hand, the recovery from a voltage notch could lead to highcurrent peak, which should also be accounted for. The relationbetween the peak current and the voltage notch is given by (12),where Vline is the line-to-line voltage, and Vinitial is the initialvoltage of the dc-link cap when the inrush occurs

Li2peak =12C(VLine − Vinitial)2 . (12)

Actually, the ac-line inductor can also be a part of the EMIfilter. So, the total input inductance should be the larger one be-tween the two values designed for the DM inductor and the lineinductor, respectively. In this case, the EMI filter DM inductanceof 110 µH is dominant, which can be the leakage inductance of

the CM choke. Based on the designed parameters and operatingconditions, the optimization algorithm shown in the previoussection is used to design the actual inductor (physical unit). Theapproach has been validated in simulation and experiments.

3) DC-Link Capacitor: The capacitor is a topological re-quirement of voltage source converters to maintain the dc-linkvoltage. The dc-link voltage variation is generally caused bythe front-end and inverter power unbalance. The notable condi-tions to cause power unbalance include sudden load and sourcechanges. The extreme case would be that in one switching cycle,the rectifier input power drops to zero while the inverter keepsthe maximum output power, or vice versa. In this case, the rela-tionship between the capacitance and the voltage ripple is givenby (13), where Pmax is the maximum output/input power, Vdc isthe dc-link voltage, and ∆U is the allowed voltage change (50V in this paper). In practical applications, there could be longerterm power loss requiring the converter to ride-through, whichwould need more capacitance than the value in (13). In thiscomparison study, we assume the ride-through is not required.

C =Pmax

(Vdc∆U ± 12 ∆U 2)fsw

. (13)

Another consideration regarding the dc-link capacitance, se-lection is the converter stability. The rectifier and the inverterare two cascaded subsystems, as shown in Fig. 12(a). In or-der to avoid the instability, the output impedance Zout of therectifier should be lower than the input impedance Zin ofthe inverter [23]. This is illustrated in Fig. 12(b) showing theimpedance relationship in a magnitude Bode plot. The invertercan be considered as a constant power load below the controlbandwidth frequency fBW . On the other hand, Zout can beassumed to be very low below the control bandwidth, and isdominated by the dc-link capacitance impedance 1/ωC beyondfBW . Then, the constraint for the dc-link capacitance is givenby (14), where Pout is the rectifier output power and Zm is theimpedance margin (6 dB in this case). Then, we can select theminimum capacitance of (13) and (14) as

20 log(

V 2dc

Pout

)− 20 log

(1

2πfBW C

)≥ Zm . (14)


Fig. 12. (a) Cascaded subsystem diagram. (b) Impedance Bode plot.

Fig. 13. Vector synthesis in sector I of the space vector diagram.

Fig. 14. Pulse pattern for the top switches in the first 30.

Based on the previous discussion, the dc-link capacitance isselected to be 10 µF for 40-kHz switching frequency. Four 400V/10-µF film capacitors are chosen in the design to form theequivalent 10-µF dc-link capacitor bank to meet the voltage andthe ripple current requirement.

Although (9)–(14) are derived for the BTB-VSC, the designfor all the other topologies can follow the same approach andprocedure.

4) Cooling System: For loss calculation in topology eval-uation, the dc-link voltage ripple and ac input–output currentharmonics can be neglected. Under the assumption, the currentthrough each device is only determined by the switching patternand the duty cycle. With the three-phase symmetrical system,for the loss calculation, we can just consider the losses in one-sixth of the line cycle. Fig. 13 shows the voltage vector synthesisin sector I of the space vector diagram [34]. The duty cycles d1 ,d2 , and d0 for voltage vectors V1 , V2 , and V0 are given by (15).Fig. 14 shows the pulse patterns of the top switches for the first30 in sector I. With (15), the duty cycles for phase legs are

given by (16).

d1 =√

32

M sin(π

3− ωt

)

d2 =√

32

M sin ωt

d0 = 1 − d1 − d2 .

(15)

da = 1

db = d2 + d0 = 1 −√

32

M cos(ωt +

π

6

)

dc = d0 = 1 −√

32

M cos(ωt − π

6

).

(16)

The switching loss of SiC diodes is ignored as they haveexcellent reverse recovery performance [35]. With the linear as-sumption, the power losses of the SiC JFET and diode in thephase leg of the rectifier at the jth switching cycle are given by(17) and (18), where Ir (t) is the instantaneous rectifier input cur-rent, dr (t) is the instantaneous duty cycle of the correspondingphase leg of the rectifier given by (16), Vdc is the dc-link volt-age, and Nr T and Nr D are the numbers of parallel JFETs anddiodes in the rectifier, respectively. Nr T = 4 and Nr D = 2for the BTB-VSC

Pr JFET j = (1 − dr (t)) ×RON

Nr T× Ir (t)2 + eT ON(OFF) r

× VdcIr (t)vr ir

× fsw (17)

Pr Dio j = dr (t) ×[Vf D × Ir (t) +

RD

Nr D× Ir (t)2

]. (18)

The power losses in the inverter are given by (19) and (20),where Ii(t) is the instantaneous inverter output current, di(t)is the instantaneous duty cycle of the corresponding phase legof the inverter, and Ni T and Ni D are the numbers of parallelJFETs and diodes in an inverter phase leg, respectively. Ni T =5 and Ni D = 1 in this case

Pi JFET j = di(t) ×RON

Ni T× Ii(t)2 + eT ON(OFF) r

× VdcIi (t)vr ir

× fsw (19)

Pi Dio j = (1 − di(t)) ×[Vf D × Ii(t) +

RD

Ni D× Ii(t)2

].

(20)

Assume sinusoidal Ir (t) and Ii(t); then (17)–(20) are usedto calculate the average losses of the semiconductor deviceson the phase leg. The same procedure is used to obtain thelosses of the other phase legs and the sum of the phase-leglosses yields the total converter loss. And then, with (5) and (6),the required thermal impedance for the heatsink can be deter-mined. The aluminum heatsink OS080 from Aavid Thermalloyis selected in this paper. The width and the height are 135 mmand 25 mm, respectively, and the length is varied to achievethe required thermal resistance. The rectifier and inverter used


TABLE IIIDETAILED CALCULATION RESULTS FOR BTB-VSC FOR 40-KHZ SWITCHING FREQUENCY

TABLE IVDESIGN RESULTS FOR BTB-VSC

separate heatsinks due to the different loss dissipation and dis-tribution. And the minimum length of the heatsink is 50 mm.Two fans (614 F series from ebm-papst, Inc.) are assumed for allthe topologies. The weights of the inductors are calculated bythe designed core dimensions and the number of winding turnswith the material density. A nanocrystalline toroid core andcopper wire are utilized for the inductor design. The weights ofthe other components are obtained from the datasheet. Table IIIshows some detailed design results for 40-kHz switching fre-quency. The loss calculation results and the weight distributionfor different switching frequencies are shown in Table IV laterin this section.

B. NTR-VSI

The topology is shown in Fig. 10(b). In comparison to theBTB-VSC, the two-level active front-end is replaced in thiscase by a nonregenerative three-level boost rectifier, which of-fers the advantages of lower voltage stress to the devices andlower harmonic distortion. But, it does not provide the regen-erative capability. Three-level continuous space vector PWM isused for the rectifier [36] and DPWM is implemented for theVSI as the BTB-VSC. Fig. 15 shows the simulation waveforms(Lin = 100 µH, C1 = C2 = 20 µF, fSW = 40 kHz). The spec-trum analysis for the PWM voltage is shown in Fig. 16 for40-kHz switching frequency. Since the nonregenerative three-level rectifier is a voltage source rectifier, the input filter designand the dc-link capacitor selection can follow the same approach

Fig. 15. Simulation results for NTR-VSI: (a) ac-line currents; (b) PWM line-to-line voltage.

Fig. 16. Spectrum of the PWM voltage for NTR-VSI.

as the BTB-VSC. For the 40 kHz case, the common-mode anddifferential-mode inductances are 7.8 mH and 97 µH, respec-tively. The dc-link capacitors are 20 µF each so that the totaldc-link capacitance is 10 µF.

For the rectifier, the power losses of the JFET and the mainbridge diode have the same expressions as (17) and (18) exceptthat 0.5 Vdc should be utilized instead of Vdc for the JFETswitching energy calculation in (17). The loss of the neutral


TABLE VDESIGN RESULTS FOR NTR-VSI

Fig. 17. Simulation results for BTB-CSC: (a) ac-line source currents;(b) rectifier input current.

bridge diode is given by (21), where Nr Dn is the number ofparallel diodes in the neutral bridge. Nr T , Nr D , and Nr Dn

are 4, 2, and 1, respectively, in the design

Pr Dio neu j = 2 × (1 − dr (t))

×[Vf D I(t) +

RD

Nr Dn× Ir (t)2

]. (21)

The VSI is modulated using DPWM, and therefore, its lossesare determined by (19)–(20). Similar to the BTB-VSC, theheatsink design is then carried out based on the loss calcula-tion. Table V shows the design results for NTR-VSI.

C. BTB-CSC

Fig. 10(c) shows the topology of BTB-CSC. The energy stor-age component in the dc link is an inductor instead of a capacitor.Both input and output filters are required to smooth the ripplecurrent. The DPWM scheme is implemented [34] in the design.Figs. 17 and 18 show the simulation results and pulse currentspectrum for the case with 40-kHz switching frequency (cir-cuit parameters: Lin = 100 µH, Cin = 1 µF, Ldc = 1 mH, andfSW = 40 kHz).

For the filter design, the same procedure as BTB-VSC isfollowed while the Fourier analysis is carried out for the pulsat-ing current instead of the voltage at the rectifier input terminal.As mentioned in Section II, a CL–CL input filter is used forthis topology. For the 40-kHz switching frequency case, the

Fig. 18. Spectrum of the PWM current for BTB-CSC.

required inductance is 162 µH with 1 µF capacitance. This dc-link inductor should also meet the stability and energy storagerequirements, expressed by (22) and (23), where Idc is the dc-link current, and ∆I is the maximum ripple current (7 A in theexample design)

L ≥ Pmax

fsw (Idc∆I ± 12 ∆I2)

(22)

and

20 log(2πfBW L) − 20 log(

Pout

I2dc

)≥ Zm . (23)

With (22) and (23), the dc-link inductor is designed to be1.27 mH for a 40-kHz switching frequency case with a 6-dBimpedance margin and 4-kHz control bandwidth. In BTB-CSC,the output capacitors are usually required to smooth the out-put waveform, especially for the motor load. In this paper, thevoltage THD requirement is used to determine the output ca-pacitance. Assuming all ripple components of the output currentgo through the output capacitors, the relationship between theoutput capacitance and the voltage THD can be achieved withthe spectrum analysis result for the output current. For a 30%THD requirement, the capacitance is designed to be 1 µF whenthe switching frequency is 40 kHz.

For BTB-CSC, the losses of the power devices have the sameexpressions for the rectifier and inverter, which are given by(24) and (25), where d(t) is the instantaneous duty cycle, VL (t)is the instantaneous line-to-line voltage, and NT and ND arethe numbers of parallel FETs and diodes, respectively. NT = 5and ND = 1 for this case. With (24) and (25), the losses of eachindividual device and the total system can be achieved, and then,the heatsink can be readily designed. The design results for theB2B-CSC are shown in Table VI

P JFET j = d(t) × RON

NT× I2

dc + eT ON(OFF) r

× VL (t)Idc

vr ir× fsw (24)

P Dio j = d(t) ×(

Vf D × Idc +RD

ND× I2

dc

). (25)


TABLE VIDESIGN RESULTS FOR BTB-CSC

Fig. 19. Simulation results for 12-switch matrix converter: (a) source currents;(b) PWM line current.

D. 12-Switch Matrix Converter

The 12-switch matrix converter, as shown in Fig. 10(d), con-sists of a cascaded connection of two bridge converters withoutany dc-link energy storage components. The converter at theinput terminal has the same structure as the front-end rectifierof the BTB-CSC, which is treated as the current source bridge(CSB); and the converter at the output terminal is treated as thevoltage source bridge (VSB) since it has the same structure as theinverter of BTB-VSC. A carrier-based modulation scheme [37]is implemented and the corresponding noise spectrum is usedfor the filter parameter design. The simulation results and thespectrum analysis for the phase-leg pulsating current for the40-kHz switching frequency case are shown in Figs. 19 and20, respectively (Lin = 100 µH, Cin = 4 µF, fSW = 40 kHz).Since the pulsating current is the noise source in the 12-switchmatrix converter, the CL–CL structure is chosen for the inputfilter and the design follows the same way as the BTB-CSC. Forthe case of 40-kHz switching frequency, the inductance is 128µH with the capacitance selected to be 1 µF.

Losses are determined in the following way: for CSB, theswitching loss is zero under the modulation scheme used, andthe conduction losses are given in (26) [38], where I0 is theamplitude of the output current, M0 is the modulation index,and φ0 is the output power factor angle, which is assumed tobe 0 for all the sample designs. The numbers of parallel JFETs

Fig. 20. Spectrum of the PWM current for matrix converter.

TABLE VIIDESIGN RESULTS FOR 12-SWITCH MATRIX CONVERTER

Nr T and diodes Nr D in CSB are 5 and 1, respectively, for thesample design

Pc CSB =92π

×Vf D M0I0 cos(φ0)+3√

32π2 ×

(RON

Nr T+

RD

Nr D

)

× M0I20 × (1 + 4 cos(φ0)2). (26)

For VSB, the conduction and switching losses are given in(27) and (28) [38], where Vs is the amplitude of the input phasevoltage and φi is the input power factor angle (0 for the sampledesigns). The numbers of JFETs Ni T and diodes Ni D in VSBare 5 and 1, respectively

Pc VSB = 6

Vf D I0

2π+

(RON

Ni T+

Rf D

Ni D

)× I2

0

8

− 38π

×Vf D I0M0 cos(φ0)+(

RON

Ni T− Rf D

Ni D

)

× I20

π2 × M0 cos(φ0)

(27)

Psw VSB =27π2 × fsweT ON(OFF) r ×

VsI0

vr ir× cos(φi). (28)

With (26)–(28), the losses for the devices can be obtained, andthen, the heatsink can be selected. Table VII shows the designresults for the 12-switch matrix converter.


Fig. 21. Weight comparison of four topologies under consideration.

Fig. 22. Formulation of the converter optimization.

E. Topology Comparison Results and Discussions

Fig. 21 shows the total weight comparison of the four differenttopologies under consideration for four switching frequencies.From the results, it can be seen that the BTB-CSC has thehighest losses and also the heaviest passive components. TheNTR-VSI and the BTB-VSC present comparable weights, withthe latter having slightly lower loss, but a slightly larger filter.The 12-switch matrix converter requires the least passives butits higher loss makes it inferior to the BTB-VSC and NTR-VSItopologies. It can also be seen that 40-kHz switching frequencyis the best choice for all topologies due to the dominance ofheatsink weight, except for BTB-CSC. It should be emphasizedthat these conclusions are based on specific design conditionsand component characteristics. For a different design, the same

procedure can be applied and different conclusions on topologyselections may arise.

As mentioned earlier, auxiliary circuits, such as inrush controland protection circuits, also contribute to the converter weightand should be considered in topology evaluation. They are topol-ogy dependent. Among the four studied topologies, BTB-VSCand NTR-VSI require extra inrush control and dc-link over-voltage protection [40]. Their estimated weights are includedin Tables IV and V. Since the weights are relatively small, thedetailed design descriptions are omitted here.

Note that in Tables IV–VII, the weights of the power de-vices are the same for all topologies with the comparison con-dition that all topologies use the same number of devices withthe same packages. Because of the commercial package limita-tions for SiC devices, the device weights constitute an unusually


high percentage in the converters. With better packaging, deviceweights should be significantly reduced. In this case, the deviceweight does not change the comparison results of the topologiesas a common factor. The same cooling fan is also assumed indifferent designs due to its relatively small size.

Some interesting observations can be made based on thetopology comparison results. The matrix converter, which re-quires no dc-link capacitors, has often been considered a natu-ral choice for high-density design. In our case, the comparisonclearly shows that the matrix converter does not result in alower weight design due to its higher loss and correspondinglarger heatsink. The BTB-CSC would be a good topology thatsuits well the normally-ON characteristics of SiC JFET. Unfortu-nately, its high loss makes it the heaviest design among the fourcandidate topologies. These comparison results prove the valueof a systematic topology evaluation in high-density converterdesign.

As mentioned earlier, the presented topology evaluation ap-proach is formulated similar to an optimization problem. Thedesign conditions, constraints, and variables are defined forachieving a high-density design. The focus of the paper hasbeen on establishing the relationships between all these pa-rameters and on determining the preferred topology relative toothers. Although the presented designs may only be preferredrather than optimal due to limited iterations, the approach pro-vides insight on correlations of all key parameters, which canbe applied to any ac–ac converter. The proposed approach andanalysis can also form a basis for global optimization of anac–ac converter. Fig. 22 shows the conceptual formulation ofsuch an optimization. The key to the optimization is establish-ing the relationships, through models and equations, betweendesign conditions, constraints, variables, and objectives, whichhas been the main focus of this paper. The actual optimiza-tion can follow various standard algorithms including genericalgorithm [41], which is out of the scope of this paper.

IV. CONCLUSION

A systematic evaluation approach of three-phase PWM ac–ac converter topologies for high-density design has been de-veloped. All major components and subsystems in a convertersystem have been considered, including the switching devices,heatsink, energy storage and filter passive components, and aux-iliary circuits. A comprehensive list of design conditions, con-straints, and parameters, and their interdependencies on con-verter density have been considered. With the high-frequencycapability SiC devices assumed, the impact of the switchingfrequency was carefully studied by considering loss, passivesize, and EMI filter design, culminating with identifying anonmonotonous relationship and some preferred switching fre-quency ranges. The criteria for minimum passives were devel-oped based on control dynamics and stability, ripple, and pro-tection. The impact of modulation schemes on loss and passiveswas also considered, and it was found that lower loss modulationschemes do not necessarily lead to bigger passives. The conceptof using the same inductor for harmonic suppression and EMIfiltering was introduced in the design. In addition, auxiliary cir-cuits, such as protection circuits, can add to the total size and

weight. Based on the proposed approach, four active front-endconverters using SiC devices are quantitatively compared forlowest weight design. The comparison results show that theBTB-VSI and NTR-VSI topologies present lighter total weightfor the given specifications than BTB-CSC or matrix converter.The proposed methodology can be extended to other topologieswith different comparison metrics and can be a useful tool forhigh-density topology selection.

ACKNOWLEDGMENT

This study made use of the National Science Foundation En-gineering Research Center shared facilities.

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Rixin Lai (S’07) received the B.S. and M.S. degreesin electrical engineering from Tsinghua University,Beijing, China, in 2002 and 2005, respectively. Heis currently working toward the Ph.D. degree at theCenter for Power Electronics Systems, Virginia Poly-technic Institute and State University, Blacksburg.

His current research interests include passive fil-ters design, electromagnetic interference modeling,and three-phase converters control and analysis forhigh power density applications.

Fei (Fred) Wang (S’85–M’91–SM’99) received theB.S. degree from Xi’an Jiaotong University, Xi’an,China, in 1982, and the M.S. and Ph.D. degrees fromthe University of Southern California, Los Angeles,in 1985 and 1990, respectively, all in electrical engi-neering.

He was a Research Scientist at the Electric PowerLaboratory, University of Southern California, from1990 to 1992. He joined the GE Power Systems Engi-neering Department, Schenectady, NY, as an Appli-cation Engineer in 1992. From 1994 to 2000, he was

a Senior Product Development Engineer with GE Industrial Systems, Salem,VA. During 2000 to 2001, he was the Manager of the Electronic and PhotonicSystems Technology Laboratory, GE Global Research Center, Schenectady, andShanghai, China. In 2001, he joined the Center for Power Electronics Systems(CPES), Virginia Polytechnic Institute and State University, Blacksburg, VA,where he is currently the CPES Technical Director and an Associate Professor.His current research interests include power electronics, power systems, con-trols, electric machines, and motor drives.

Rolando Burgos (S’96–M’03) received the B.S. de-gree in electronics engineering, the Electronics En-gineering Professional degree, and the M.S. andPh.D. degrees from the University of Concepcion,Concepcion, Chile, in 1995, 1997, 1999, and 2002,respectively.

In 2002, he joined as Postdoctoral Fellow the Cen-ter for Power Electronics Systems (CPES), VirginiaPolytechnic Institute and State University (VirginiaTech), Blacksburg, where, since 2005, he has been aResearch Assistant Professor. His research interests

include multiphase power conversion, stability of ac and dc power electronicssystems, hierarchical modeling, control theory, and the synthesis of power elec-tronics conversion systems for sea, air, and land vehicular applications.

Dr. Burgos is a member of the IEEE Power Electronics, Industrial Electron-ics, Industry Applications, and Power Engineering Societies, and is currentlythe Secretary of the Committee on Simulation, Modeling, and Control of thePower Electronics Society.

Yunqing Pei (M’96) received the B.S. and M.S. de-grees in electrical engineering in 1991 and 1994,respectively, from Xi’an Jiaotong University, Xi’an,China, from where he also received the Ph.D. degreein power electronics in 1999.

Currently, he is an Associate Professor at Xi’anJiaotong University. His current research interests in-clude high-power inverters and switch-mode powersupply.


Dushan Boroyevich (S’81–M’82–SM’03–F’06) re-ceived the Dipl. Ing. degree from the University ofBelgrade, Belgrade, Serbia, in 1976, the M.S. degreefrom the University of Novi Sad, Novi Sad, Serbia,in 1982, and the Ph.D. degree from Virginia Poly-technic Institute and State University (Virginia Tech),Blacksburg, in 1986.

From 1986 to 1990, he was an Assistant Professorand Director of the Power and Industrial Electron-ics Research Program at the Institute for Power andElectronic Engineering, University of Novi Sad, and

later, Acting Head of the Institute. He then joined the Bradley Department ofElectrical and Computer Engineering at Virginia Tech as an Associate Professor.He is currently the American Electric Power Professor at the Department andCo-Director of the National Science Foundation Engineering Research Centerfor Power Electronics Systems. His current research interests include multi-phase power conversion, power electronics systems modeling and control, andmultidisciplinary design optimization.

Prof. Boroyevich received the 2007 IEEE William E. Newell Power Elec-tronics Technical Field Award “for the advancement of control, modeling, anddesign of switching power converters.”

Bingsen Wang (S’01–M’06–SM’08) is a native ofChina. He received the M.S. degrees from ShanghaiJiao Tong University, Shanghai, China, and the Uni-versity of Kentucky, Lexington, in 1997 and 2002,respectively, and the Ph.D. degree from the Univer-sity of Wisconsin, Madison, in 2006, all in electricalengineering.

From 1997 to 2000, he was with Carrier Air Con-ditioning Equipment Company as an Electrical Engi-neer in Shanghai, China. He joined General Electric(GE) Global Research Center in New York as a Power

Electronics Engineer. While with GE, he was engaged in research in power elec-tronics, mainly in the high-power area. Since 2008, he has been on the facultyof the Department of Electrical Engineering, Arizona State University, Tempe.He is the author or coauthor of more than ten technical articles in peer-reviewedconferences and refereed journals. He holds one Chinese patent. His currentresearch interests include power conversion topologies, in particular, multilevelconverters and matrix converters, dynamic modeling and control of power elec-tronic systems, application of power electronics to renewable energy systems,power conditioning, flexible ac transmission systems (FACTS), and electricdrives.

Dr. Wang is a member of Sigma Xi. He received the Prize Paper Award fromthe Industrial Power Converter Committee of the IEEE Industry ApplicationSociety in 2005.

Thomas A. Lipo (M’64–SM’71–F’87–LF’04) wasborn in Milwaukee, WI. He received the B.E.E. andM.S.E.E. degrees from Marquette University, Mil-waukee, in 1962 and 1964, respectively, and the Ph.D.degree in electrical engineering from the Universityof Wisconsin, Milwaukee, in 1968.

From 1969 to 1979, he was an Electrical Engineerin the Power Electronics Laboratory of CooperateResearch and Development of the General ElectricCompany, Schenectady, NY. He became a Professorof electrical engineering at Purdue University, West

Lafayette, IN, in 1979. In 1981, he joined, as Professor, the University of Wis-consin, Madison, where he is currently the W. W. Grainger Professor for powerelectronics and electrical machines.

Prof. Lipo was the recipient of the Outstanding Achievement Award fromthe IEEE Industry Applications Society, the William E. Newell Award of theIEEE Power Electronics, and the 1995 Nicola Tesla IEEE Field Award fromthe Power Engineering Society. He has served the IEEE in various capacities,including as President of Industrial Applications Society. He is a Fellow of theInstitute of Electrical Engineering (London), a member of the Institute of Elec-trical Engineering (Japan), a Fellow of the Royal Academy of Great Britain,and a Fellow of the National Academy of Engineering (USA).

Vikram D. Immanuel (M’05) received the B.E. de-gree in electronics and electrical engineering fromKarunya Institute of Technology, Coimbatore, India,in 2002, and the M.S. degree in electrical engineer-ing from Illinois Institute of Technology, Chicago, in2004.

Since 2005, he has been with The Boeing Com-pany as a Design Engineer. He is currently involved inthe testing and validation of the 787 electrical powersystem. He is also the Principal Investigator for re-search projects in the field of power electronics. His

current research interests include power electronics, control systems, powersystems, and electric machines.

Kamiar J. Karimi (S’81–M’81) received the B.S.,the Master of Engineering, and the Ph.D. degreesfrom Cornell University, Itaca, NY, in 1981, 1982,and 1986, respectively, all in electrical engineering.

From 1986 to 1989, he was with Landis and GyrSystems, San Jose, CA, where he was engaged inresearch in the area of energy management systems.Since 1989, he has been with The Boeing Company,Seattle, WA. He is a Boeing Senior Technical Fel-low. From 1989 to 1992, he was the Lead of SystemAnalysis and Modeling for the Space Station Power

System. Since 1992, he has been engaged in research on power system design,power electronics research, power quality issues, and simulation of various air-plane power systems. Currently, he leads the development of power systemdesign and power quality requirements, and power system test and simulationfor the 787 power system. He also leads several research projects in the areas ofpower system architecture, simulation methods, and power electronics.

a systematic topology evaluation methodology for high-density

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