a study of schematic entry tool - vidyarthiplus

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A STUDY OF SCHEMATIC ENTRY TOOL – TANNER

1. To launch S-Edit in PC, go to START > PROGRAMS > TANNER > S-EDIT

2. Click on Module > Symbol Browser or click on to launch the symbol browser

window. Choose your device and click on Place.


3. Once the main parts are in place, it is time to add I/O pins and wire the parts together.

Select and place an Input Pad and an Output pad on the schematic and give the pads a

unique name.

4. Now using the wiring tool make appropriate connections


5. Output – Transient Analysis

1. Once Design Entry is over, Click and open T-Spice, then open Insert Command Dialog and select

Transient Enter the time step and length -> Click Insert

2. Select Files Include Files Browse for ml2_125 and open. Click Insert


3. Select Transient Result by expanding Output Enter the node to be traced

4. Select Voltage Sources and Enter the values for inputs stream


5. Select Constant from Voltage sources and enter the constants

6. Finally all the Commands are entered in Module0 Window


7. Save and run Simulation. Expand Chart to view the output


CIRCUIT DIAGRAM - S-EDIT


Ex.No:11 CMOS INVERTER

AIM

To design a CMOS inverter using the Schematic entry tool, Tanner and verify its

functioning.

APPARATUS REQUIRED:

1. Tanner tool

2. PC

THEORY:

CMOS Inverter consists of nMOS and pMOS transistor in series connected

between VDD and GND. The gate of the two transistors are shorted and connected to the

input. When the input to the inverter A = 0, nMOS transistor is OFF and pMOS transistor

is ON. The output is pull-up to VDD. When the input A = 1, nMOS transistor is ON and

pMOS transistor is OFF. The Output is Pull-down to GND.

PROCEDURE

1. Draw the schematic of CMOS Inverter using S-edit.

2. Perform Transient Analysis of the CMOS Inverter.

3. Obtain the output waveform from W-edit.

4. Obtain the spice code using T-edit.


WAVEFORM


OUTPUT

TSPICE - Tanner SPICE

Version 7.10

Copyright (c) 1993-2001 Tanner Research, Inc.

Parsing "C:\Tanner\S-Edit\Module011.sp"

Including "C:\Tanner\TSpice70\models\ml2_125.md"

Device and node counts:

MOSFETs - 2 MOSFET geometries - 2

BJTs - 0 JFETs - 0

MESFETs - 0 Diodes - 0

Capacitors - Resistors - 0

Inductors - 0 Mutual inductors - 0

Transmission lines - 0 Coupled transmission lines - 0

Voltage sources - 2 Current sources - 0

VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0

V-control switch - 0 I-control switch - 0

Macro devices - 0 Functional model instances - 0

Subcircuits - 0 Subcircuit instances - 0

Independent nodes - 1 Boundary nodes - 3

Total nodes - 4

Parsing 0.01 seconds

Setup 0.00 seconds

DC operating point 0.00 seconds

Transient Analysis 0.04 seconds

-----------------------------------------

Total 0.05 seconds

RESULT

Thus the design & simulation of a CMOS inverter has been carried out using S-Edit of

Tanner EDA Tools


CIRCUIT DIAGRAM - S-EDIT( NAND)

( NOR)


Ex.No:12 CMOS NAND & NOR

AIM

To design a CMOS NAND and NOR gates using the Schematic entry tool, Tanner and

verify its functioning.

APPARATUS REQUIRED:

1. Tanner tool

2. PC

THEORY:

NAND and NOR gates are known as universal gates as any function can be

implemented with them

NAND functionality can be implemented by parallel combination of PMOS and

series combination of NMOS transistor. When any one of the inputs is zero, then the

output will be one and when both the inputs are one the output will be low.

NOR functionality can be implemented by parallel combination of NMOS and

series combination of PMOS transistor. When any one of the inputs is one, then the

output will be one and when both the inputs are zero the output will be low.

PROCEDURE

CMOS NAND

1. Draw the schematic of CMOS NAND using S-edit.

2. Perform Transient Analysis of the CMOS NAND.



CMOS NOR

1. Draw the schematic of CMOS NOR using S-edit.

2. Perform Transient Analysis of the CMOS NOR.




WAVEFORM NAND

WAVEFORM NOR


OUTPUT - NAND


Version 7.10


Parsing "F:\tanner\TSpice70\Module0.sp"

Including "F:\tanner\S-Edit\models\ml2_125.md"

Warning T-SPICE : DC sources have non-unique names. "vin".



BJTs - 0 JFETs - 0


Capacitors - 0 Resistors - 0




VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 6

*** 1 WARNING MESSAGES GENERATED


Setup 0.00 seconds



-----------------------------------------

Total 0.04 seconds


OUTPUT – NOR


Version 7.10




Warning T-SPICE : DC sources have non-unique names. "vin".



BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 7


Warning T-SPICE : The vrange voltage range limit (5.5) for diode tables has been exceeded.

Warning T-SPICE : The vrange voltage range limit (5.5) for MOSFET tables has been exceeded.

Warning T-SPICE : The vrange voltage range limit should be set to

at least 7.11984 for best accuracy and performance.


Setup 0.01 seconds



-----------------------------------------

Total 0.07 seconds


RESULT

Thus the design & simulation of a CMOS NAND and NOR gates have been carried out

using S-Edit of Tanner EDA Tools


Ex.No:13 TRANSMISSION GATE

AIM

To design a transmission gate logic using the Schematic entry tool, Tanner and verify its

functioning.

APPARATUS REQUIRED:

1. Tanner tool

2. PC

THEORY:

It’s a parallel combination of pmos and nmos transistor with the gates connected

to a complementary input. The disadvantages weak 0 and weak 1 can be overcome by

using a TG instead of pass transistors. Working of transmission gate can be explained

better with the following equation. An important advantage of TGs is that the reduction

in the resistance because two transistors will come in parallel.

When phi =’0’ n and p device off, Vin=0 or 1, Vo=’Z’

When phi =’1’ n and p device on, Vin=0 or 1, Vo=0 or 1 , where ‘Z’ is high impedance.

PROCEDURE

1. Draw the schematic of Transmission gate Inverter using S-edit.

2. Perform Transient Analysis of the Transmission gate Inverter.




WAVEFORM


OUTPUT


Version 7.10




Warning T-SPICE : Node vdd is attached to only one device



BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 8






Setup 0.00 seconds



-----------------------------------------

Total 0.04 seconds

RESULT

Thus the design & simulation of a transmission gate has been carried out using S-Edit of

Tanner EDA Tools


Ex.No:14 PASS TRANSISTOR LOGIC

AIM

To design a pass transistor logic using the Schematic entry tool, Tanner and verify its

functioning.

APPARATUS REQUIRED:

1. Tanner tool

2. PC

THEORY:

When an nMOS or pMOS is used alone as an imperfect switch, then it is called a pass transistor.

An nMOS transistor is an almost perfect switch when passing a 0 and thus we say it passes a

strong 0. However, the nMOS transistor is imperfect at passing a 1. The high voltage level is

somewhat less than VDD. We say it passes a degraded or weak 1. A pMOS transistor again has

the opposite behavior, passing strong 1s but degraded 0s. The disadvantage with the pass

transistors is that, they will not be able to transfer the logic levels properly.

PROCEDURE

1. Draw the schematic of pass transistor using S-edit.

2. Perform Transient Analysis of the Pass transistor.




WAVEFORM


OUTPUT


Version 7.10




Warning T-SPICE : DC sources have non-unique names. "v1".

Warning T-SPICE : unused model "pmos"



BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 5



Setup 0.00 seconds



-----------------------------------------

Total 0.01 seconds

RESULT

Thus the design & simulation of a nMOS pass transistor has been carried out using S-Edit

of Tanner EDA Tools.


Ex.No:15 DOMINO LOGIC – AND GATE

AIM

To design an AND gate in Domino logic using the Schematic entry tool, Tanner and


APPARATUS REQUIRED:

3. Tanner tool

4. PC

THEORY:

The monotonicity problem can be solved by placing a static CMOS inverter

between dynamic gates. This converts the monotonically falling output into a

monotonically rising signal suitable for the next gate. The dynamic-static pair together is

called a domino gate because pre-charge resembles setting up a chain of dominos and

evaluation causes the gates to fire like dominos tipping over, each triggering the next. A

single clock can be used to pre-charge and evaluate all the logic gates within the chain.

PROCEDURE

1. Draw the schematic of Domino AND gate using S-edit.

2. Perform Transient Analysis of the Domino AND gate.




WAVEFORM


OUTPUT


Version 7.10






BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 9


Setup 0.00 seconds



-----------------------------------------

Total 0.19 seconds

RESULT

Thus the design & simulation of a Domino AND has been carried out using S-Edit of

Tanner EDA Tools


Ex.No:16 CMOS D-LATCH

AIM

To design a CMOS D-Latch using the Schematic entry tool, Tanner and verify its

functioning.

APPARATUS REQUIRED:

1. Tanner tool

2. PC

THEORY:

Latches are sequential circuits capable of storing the values given until the value

changes. Being a sequential circuit the working of the circuit is controlled by a clock

signal. Latches are level triggered devices which tracks the change in input along the

level of the clock signal. A D-latch is capable of tracks the value given in D-input along

the positive level of clock and holds the value during negative level of clock.

PROCEDURE

1. Draw the schematic of CMOS D-Latch using S-edit.

2. Perform Transient Analysis of the CMOS D-Latch.




WAVEFORM


OUTPUT


Version 7.10






BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 11






Setup 0.00 seconds



-----------------------------------------

Total 0.15 seconds

RESULT

Thus the design & simulation of a CMOS D-Latch has been carried out using S-Edit of

Tanner EDA Tools


SCHEMATIC DIAGRAM

DIFFERENTIAL AMPLIFIER


Ex.No:17 DIFFERENTIAL AMPLIFIER

AIM

To design a CMOS Differential Amplifier using the Schematic entry tool, Tanner and


APPARATUS REQUIRED:

1. Tanner tool

2. PC

THEORY:

A differential amplifier is a type of electronic amplifier that multiplies the difference

between two inputs by some constant factor (the differential gain). Many electronic

devices use differential amplifiers internally. The output of an ideal differential amplifier

is given by:

Where Vin+ and Vin- are the input voltages and Ac is the differential gain. In practice,

however, the gain is not quite equal for the two inputs. This means that if Vin+ and Vin-

are equal, the output will not be zero, as it would be in the ideal case. A more realistic

expression for the output of a differential amplifier thus includes a second term.

Ac is called the common-mode gain of the amplifier. As differential amplifiers are often

used when it is desired to null out noise or bias-voltages that appear at both inputs, a low

common-mode gain is usually considered good.

The common-mode rejection ratio, usually defined as the ratio between differential-mode

gain and common-mode gain, indicates the ability of the amplifier to accurately cancel

voltages that are common to both inputs. Common-mode rejection ratio (CMRR):

PROCEDURE

1. Draw the schematic of CMOS Inverter using S-edit.

2. Perform Transient Analysis of the CMOS Inverter.




WAVEFORM


OUTPUT


Version 7.10


Parsing "C:\Tanner\S-Edit\Module0.sp"

Including "C:\Tanner\TSpice70\models\ml2_125.md"



BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 9


Setup 0.01 seconds



-----------------------------------------

Total 0.09 seconds


WAVEFORM


RESULT

The design and simulation of Differential Amplifier has been performed using Tanner

EDA Tools.

a study of schematic entry tool - vidyarthiplus

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