a self-aligned double poly-si process utilizing non-selective

ESSDERC 2002 Microelectronics24-26 September 1

A self-aligned double poly-Si process utilizing non-selective epitaxy of SiGe:C for intrinsic base

and poly-SiGe for extrinsic base

J. PejneforsRoyal Institute of Technology (KTH)

Sweden

T. Johansson, J. Wittborn, A. Santos, H. Norström and U. Smith

Ericsson Microelectronics AB, KistaSweden

A. Cheshire Applied Materials UK Ltd.

Scotland

T. Buschbaum, C. Rosenblad and J. Ramm

Unaxis Balzers Ltd.Liechtenstein


Outline

• Introduction

• Intrinsic Base Module - Non-selective epitaxy of SiGe:C

• Extrinsic Base Module - Bi-layered stack of poly-Si/SiGe

• A transistor with the intrinsic and extrinsic modules implemented

• Summary


Introduction• Modular base concept - add on to existing I/I process to achieve improved HF performance

Concept used in I/I RF ProcessConcept for Epitaxial Base Process

Si Substrate

Resist

PETEOSPoly-Si

+++++++++Implanted Base

Poly-SiGe

SiGe:C Base Epitaxy

Si Substrate

Poly-Si


Schematic cross-section of the transistor

p

n-

n+

p

p+

E

n+

BC

p+

n

n+

STI

Non-selective epitaxyPoly-SiGe (30%)

DTI

Extrinsic base

Intrinsic base


Outline

• Introduction




• Summary


Intrinsic base module - NSEG of SiGe:C

• UHV/CVD Unaxis SIRIUS System• Higher growth rate on epitaxial regions

than on field areas =>planarization of the device

• Temperature: 550 °C• Pressure: 1 mTorr


SIMS profile of the as-grown epitaxy

0 5 00 1 0 0 0 15 0 0 20 0 01 0 1 7

1 0 1 8

1 0 1 9

1 0 2 0

1 0 2 1

C

Con

cent

ratio

n (c

m-3)

D e p th (Å )

0

5

1 0

1 5

G e

B

Ge

(%)

• Two-step Ge profile (5 % and 12 %)

• Carbon peak level at 1020 cm-3

• Boron peak level of 1019 cm-3

• Carbon peak at interface between epitaxy and Si-substrate


Outline

• Introduction




• Summary


Extrinsic base module - stack of poly-Si/SiGe

• UHV/CVD Unaxis SIRIUS System• Poly-SiGe (30 %), 500 Å • No epitaxial realignment

• Additional LPCVD poly-Si, 600 Å • Why bi-layer of poly-Si/SiGe?

– Prevent the poly-SiGe from oxidation

– Facilitating the formation of TiSi2

AFM picture of active areas


Etching of the extrinsic base• Applied Materials DPS poly chamber

using HBr/Cl2 based chemistry• Selectivity > 2:1 between SiGe:Si

• No loading effects

NitrideSiO2

SiGe (30%)

Resist

PETEOS

Mono Si Substrate

Poly-SiPoly-SiGe

Intrinsic base

• 3040 Å emission line used to indicate the interface between poly-Si and poly-SiGe


Etching of the poly-Si/SiGe extrinsic base

Etch ended at the rise of the end-point signal

Etch ended after a timed over-etch


Verification of the extrinsic base module

PETEOS

Resist

Poly SiGe

+++++++Implanted Base

Poly Si

• Implementation of the SiGe extrinsic base module in a standard implanted transistor process

Ib (A)

R B(Ω

)

Si Substrate

• Standard poly-Si => Rb,Ext.= 9.4 Ω

• Poly-Si/SiGe => Rb,Ext.= 4.8 Ω


Outline

• Introduction




• Summary


A transistor with the intrinsic and extrinsic modules implemented

Rb,Ext.= 7.2 Ω (Std process 9.4 Ω)


Effects of different emitter drive-in temperatures

Large Boron diffusion at 1075 ºC

No Boron diffusion at 1050 ºC

0 1 000 2 000 3 000 4 000 5 0001015

1016

1017

1018

1019

1020

1021

1022

Con

cent

ratio

n (c

m-3)

Depth (Å)

103

104

105

106

Cou

nts

(c/s

)

0 1 000 2 000 3 000 4 000 5 0001015

1016

1017

1018

1019

1020

1021

1022

Con

cent

ratio

n (c

m-3)

Depth (Å)

103

104

105

106

Cou

nts

(c/s

)


Electrical measurements

• Single device– ideal collector and base

currents– peak current gain of 140

• Array of 3040 transistors– ideal collector current

indicate dislocation free epi

0.2 0.4 0.6 0.8 1.010-13

10-11

10-9

10-7

10-5

10-3

10-1

Single transistorAE=0.6 x 3.0 µm2

Array of 3040 transistorsAE=0.6 x 3.0 µm2

Base

, Col

lect

or C

urre

nt (A

)

Base-Emitter Voltage (V)


Electrical measurements

• Emitter area 0.4x10 µm2

– fT = 53 GHz– fmax = 80 GHz

0.1 1 10 1000

5

10

15

20

25

30

35

40

45

Vce =3 V

Le = 10 µmWe = 0.4 µm

Uh21

Smal

l sig

nal c

urre

nt g

ain

(h21

), an

dU

nila

tera

l pow

er g

ain

(U) [

dB]

Frequency [GHz]


Summary

• Planarization of device topology using UHV/CVD epitaxy

• Calibration of first intrinsic SiGe:C base profile

• Development of poly-SiGe extrinsic base etch

• Demonstration of process concept, resulting in a self-aligned extrinsic base combined with NSEG epitaxy

a self-aligned double poly-si process utilizing non-selective

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