A Robust Pulse-triggered Flip-Flop A Robust Pulse-triggered Flip-Flop and Enhanced Scan Cell Designand Enhanced Scan Cell Design

Tarun SoniTarun SoniRajesh KumarRajesh KumarSunil P. KhatriSunil P. Khatri

Department of Electrical and Computer Engineering,Department of Electrical and Computer Engineering,Texas A&M University, College StationTexas A&M University, College Station

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OutlineOutline

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MotivationMotivation Scan DesignScan Design At Speed Scan TestingAt Speed Scan Testing

Launch on Shift (LOS)Launch on Shift (LOS) Launch on Capture (LOC)Launch on Capture (LOC) Enhanced Scan DesignEnhanced Scan Design

Pulse Flip Flops (PFFs)Pulse Flip Flops (PFFs) Our Robust PFFOur Robust PFF Our Pulse based Enhanced Scan Flip Flop (PESFF)Our Pulse based Enhanced Scan Flip Flop (PESFF) Experimental ResultsExperimental Results ConclusionConclusion

MotivationMotivation Decreasing process feature sizes increase the Decreasing process feature sizes increase the

probability of defects during the manufacturing probability of defects during the manufacturing processprocess A single faulty transistor or wire can result in a faulty ICA single faulty transistor or wire can result in a faulty IC Testing required to guarantee fault-free productsTesting required to guarantee fault-free products

Design for testability (DFT)Design for testability (DFT) Addresses testing issues during the design stage itself so Addresses testing issues during the design stage itself so

that testing after implementation becomes easierthat testing after implementation becomes easier

Scan design Scan design is the most popular DFT methodology is the most popular DFT methodology used for sequential circuitsused for sequential circuits

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Scan DesignScan Design Replace all selected storage elements with scan cellsReplace all selected storage elements with scan cells

Connect scan cells into scan chainsConnect scan cells into scan chains Operated in three modes:Operated in three modes:

Normal modeNormal mode All test signals are turned off (i.e. SE is held low)All test signals are turned off (i.e. SE is held low)

Shift modeShift mode To shift data into and out of the scan cells (SE held high)To shift data into and out of the scan cells (SE held high)

Capture modeCapture mode To capture test response into scan cells (SE is held low)To capture test response into scan cells (SE is held low)

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CLK

1

SECLK

QD D Q0D

SIQD Q

Scan design (continued)Scan design (continued)

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CLK

D

Q001

SE

Combinational Logic

SC

AN

IN

SCANOUT

CLK

D

SI

Q101

SE

CLK

D

SI

Q201

SE

SCANIN = 111Expected Output = 000

Shift Shift Shift Capture Shift Shift Shift

CLK

SE

Q0

Q1

Q2

D Q

SI

D Q

D Q

SCANOUT

At Speed Scan TestingAt Speed Scan Testing Identifies transition delay fault by applying two vectors Identifies transition delay fault by applying two vectors VV11

andand V V22 VV11 is used to initialize internal logic values of the circuit under is used to initialize internal logic values of the circuit under

testtest VV22 is used to launch transitions into the combinational circuit is used to launch transitions into the combinational circuit

Propagated output is captured in the scan chain by the Propagated output is captured in the scan chain by the system clock after launching system clock after launching VV22

Three ways to perform at speed scan testingThree ways to perform at speed scan testing Launch on ShiftLaunch on Shift Launch on CaptureLaunch on Capture Enhanced Scan DesignEnhanced Scan Design

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Launch on Shift (LOS)Launch on Shift (LOS)

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CLK

SE

V1

V2 Launch Edge

Capture Edge

Scan-in cycle

Scan-in cycle

Launch cycle is last scan-in cycle

Capture cycle

Scan-out cycle

Launch on Capture (LOC)Launch on Capture (LOC)

Uses two consecutive functional clocks to launch the Uses two consecutive functional clocks to launch the transition and capture the output test responsetransition and capture the output test response

Vector Vector VV22 is the response of the circuit under test to vector is the response of the circuit under test to vector VV11

Lower fault coverage in comparison to LOS [Lower fault coverage in comparison to LOS [Xu et. al. ‘07Xu et. al. ‘07]]

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CLK

SE

V1

V2 Launch Edge

Capture Edge

Scan-in cycle

Scan-in cycle

Launch cycle

Capture cycle

Scan-out cycle

Enhanced-scan cell stores two bits of data per input of Enhanced-scan cell stores two bits of data per input of the circuit under testthe circuit under test

Achieved by adding a D latch to a muxed-D scan cell Achieved by adding a D latch to a muxed-D scan cell

No restriction on vector No restriction on vector VV22

High fault coverage but with some area overheadHigh fault coverage but with some area overhead

Enhanced Scan DesignEnhanced Scan Design

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Q

SE

SI

0

CLK

SCAN IN

D D Q

D Q 1

Our ContributionOur Contribution Design of a Design of a robust PFFrobust PFF

Lower area and better timing than previous Lower area and better timing than previous approachesapproaches

Modify this PFF for use in a Modify this PFF for use in a pulse based pulse based enhanced scan flip-flopenhanced scan flip-flop Better timing than DFF based ESFFBetter timing than DFF based ESFF

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Consists of a pulse generator and a latchConsists of a pulse generator and a latch The pulse is derived from system clock The pulse is derived from system clock

edgeedge

Hence data can arrive even after the clock Hence data can arrive even after the clock edge (therefore Tedge (therefore Tsusu may be negative) may be negative)

Pulsed Flip-flops (PFF)Pulsed Flip-flops (PFF)

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Data

Pulse

Clk

Latch

D

Clk

QData

PulseGenerator

Clk Pulse

Figure of Merit for a Flip-flopFigure of Merit for a Flip-flop

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D Q

CLK

Combinational circuit

D Q

Time Period Time Period T ≥ TT ≥ Tcq cq + T+ Tsusu + d + d

where where dd – delay of the combinational circuit – delay of the combinational circuit

TTsusu – setup time of the flip-flop– setup time of the flip-flop

TTcqcq –– clock to Q delay of the flip-flopclock to Q delay of the flip-flop

Since Since dd is circuit-dependent, is circuit-dependent, TTcq cq + T+ Tsu su is the figure of is the figure of

merit for a flip-flopmerit for a flip-flop

Previous WorkPrevious Work Fast PFF (Fast PFF (Venkatraman et al. 2008Venkatraman et al. 2008))

Pulse generation circuit is fasterPulse generation circuit is faster Static power dissipation when CLK is highStatic power dissipation when CLK is high

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D

CLK

CLK

CLKB

pulse

pulseb

pulse

pulseb

Pulse generator

Pulsed latch structure

Previous Work (continued)Previous Work (continued) Explicit PFF (Explicit PFF (Zhao et al. 2002Zhao et al. 2002))

Uses dynamic pulse generator circuit and a static latch to achieve good setup timeUses dynamic pulse generator circuit and a static latch to achieve good setup time Layout area is large and also power consumption is highLayout area is large and also power consumption is high

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CLK

CLKB

pulse

D

Q

Previous Work (continued)Previous Work (continued) Improved hybrid latch flip-flop (Improved hybrid latch flip-flop (Goel et al. 2006Goel et al. 2006))

Modified dynamic master stage of Explicit PFF to reduce power consumption Modified dynamic master stage of Explicit PFF to reduce power consumption High clock to Q delayHigh clock to Q delay

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CLK

D

Q

CLK

Proposed PFFProposed PFF

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CLK

pulseb pulse

pulseb

pulse

D Q

Pulse generator

Latch

pulse

CLKB

CLK

CLKB

Pulse based Enhanced Scan Pulse based Enhanced Scan Flip-flop (PESFF)Flip-flop (PESFF)

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D Q

PULSEB

PULSE

SCAN

SCANB SCAN

SCANB

SCAN IN SI

PULSEB

PULSE

SEB

SE

SE

SI

0

CLK

SCAN IN

D D Q

D Q 1

Q

PULSEB

PULSE

D

Our robust PFF

PESFF (continued)PESFF (continued)

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SCANB

SCAN

PULSE

SEB

SEB

CLK

PULSE

SE

SCAN

SEB SE

V1

V1V2 Launch Edge

Capture Edge

V2

Experimental SetupExperimental Setup Implemented our PFF and PESFF in BPTM 100nmImplemented our PFF and PESFF in BPTM 100nm Compared PFF with existing designsCompared PFF with existing designs

Fast Robust Pulsed Flop (Fast Robust Pulsed Flop (Venkatraman et al. 2008Venkatraman et al. 2008)) Explicit Flip-Flop (Explicit Flip-Flop (Zhao et al. 2002Zhao et al. 2002)) Improved hybrid pulsed Flip-Flop (Improved hybrid pulsed Flip-Flop (Goel et al. 2006Goel et al. 2006)) Traditional D Flip-FlopTraditional D Flip-Flop

Compared PESFF with traditional DFF based ESFFCompared PESFF with traditional DFF based ESFF Performed Monte Carlo simulations for all designs listed Performed Monte Carlo simulations for all designs listed

above above Varied supply voltage, channel length, threshold voltageVaried supply voltage, channel length, threshold voltage 33σσ = 10% of the nominal value = 10% of the nominal value 200 Monte Carlo simulations 200 Monte Carlo simulations

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Experimental Results - PFFExperimental Results - PFF

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Flip-flopsFlip-flops TTcqcq

(ps)(ps)TTsusu

(ps)(ps)TTcqcq + T + Tsusu

(ps)(ps)PowerPower

(µW)(µW)Area Area

(∑ (∑ WWiiLLii)) (um(um22))

µµ σσ µµ σσ µµ σσ

ProposedProposedPulsed FFPulsed FF 134.6134.6 13.813.8 -78.7-78.7 9.29.2 54.254.2 8.68.6 5.85.8 0.4300.430

FastFastPULSED FFPULSED FF 163.7163.7 23.723.7 -68.6-68.6 10.110.1 79.179.1 20.720.7 6.76.7 0.5100.510

HYBRID HYBRID LATCHLATCH

PULSED FFPULSED FF117117 14.714.7 -34.4-34.4 1.91.9 82.682.6 11.811.8 8.48.4 0.4100.410

EXPLICIT EXPLICIT PULSED FFPULSED FF 120.4120.4 29.329.3 -54.2-54.2 4.54.5 65.865.8 7.37.3 14.614.6 0.3900.390

TraditionalTraditionalD-FFD-FF 69.969.9 1.51.5 21.421.4 2.52.5 91.291.2 8.78.7 7.67.6 0.2400.240

Experimental Results - PESFFExperimental Results - PESFF

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EnhancedEnhancedScan Flip-Scan Flip-

flopflop

TTcqcq

(ps)(ps)TTsusu

(ps)(ps)TTcqcq + T + Tsusu

(ps)(ps)PowerPower

(µW)(µW)Area Area

(∑ (∑ WWiiLLii)) (um(um22))

µµ σσ µµ σσ µµ σσ

PESFFPESFF 157.7157.7 16.316.3 -82.6-82.6 6.56.5 75.175.1 13.413.4 10.110.1 0.8800.880

ESFF using ESFF using traditional DFFtraditional DFF 43.143.1 5.25.2 43.743.7 3.63.6 86.686.6 5.85.8 7.57.5 0.5400.540

Pulse generator has been shared among 10 latches to Pulse generator has been shared among 10 latches to reduce area and power overheadreduce area and power overhead

PESFFPESFF

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D Q

PULSEB

PULSE

SCAN

SCANB SCAN

SCANB

SCAN IN SI

PULSEB

PULSE

SEB

SE

ConclusionConclusion The performance of our PFF design is better than existing The performance of our PFF design is better than existing

PFF designsPFF designs 18% 18% better better TTcq cq + T+ Tsu su than explicit PFFthan explicit PFF 14%14% lower power dissipation than Fast PFF lower power dissipation than Fast PFF 60%60% lower standard deviation of lower standard deviation of TTcq cq + T+ Tsu su compared to Fast PFFcompared to Fast PFF

16%16% lower area in compared to Fast PFF lower area in compared to Fast PFF

No earlier PFF based enhanced scan designNo earlier PFF based enhanced scan design 14%14% better better TTcq cq + T+ Tsu su than traditional DFF based ESFFthan traditional DFF based ESFF 105% area overhead compared to traditional DFF based ESFF105% area overhead compared to traditional DFF based ESFF Selective replacement gives considerable coverage improvement with Selective replacement gives considerable coverage improvement with

small area overheadsmall area overhead

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Thank YouThank You

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