A Novel Si Tunnel FET with 36mV/dec Subthreshold Slope Based on Junction Depleted-Modulation through Striped Gate Configuration

Qianqian Huang, Ru Huang*, Zhan Zhan, Yingxin Qiu, Wenzhe Jiang, Chunlei Wu, Yangyuan Wang

Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing 100871, China

Phone: 86-10-62757761, Fax: 86-10-62757761, *E-mail: ruhuang@pku.edu.cn

Abstract

In this paper, a novel junction depleted-modulation design to achieve equivalently abrupt tunnel junction of Si Tunnel FET (TFET) is proposed. By changing the gate layout configuration, the new Junction-modulated TFET can reliably and effectively achieve much steeper switching behavior and higher ON current without area penalty and special fabrication compared with traditional TFET. Further junction optimization by introducing the self-depleted doping pocket with much relaxed process requirements is also experimentally demonstrated based on the bulk Si substrate. With traditional Si CMOS-compatible process, the fabricated device shows a minimum substhreshold slope of 36mV/dec within one decade of drain current.

Introduction

Tunnel FETs (TFETs) have attracted much attention currently as one of promising candidates of MOSFET for low power applications due to its steep substhreshold slope (SS) of sub-60mV/dec and low IOFF [1-4]. It has a gated p-i-n structure switched by band-to-band tunneling (BTBT) at the source/channel (S/C) interface. However, for experimental realization of TFETs, it is difficult to form abrupt doping profile to achieve the expected sharp band bending (or equivalently high tunnel electric field) at the tunnel junction when devices turn on. Thus it may result in low tunneling efficiency and small gate modulation in the BTBT current, leading to relatively low ION and large SS of experimental demonstrations compared with the ideally theoretical expectations, especially for Si TFETs. By introducing additional Schottky tunneling mechanism with effectively suppressed leakage we proposed in [5], high ION of Si TFET can be achieved, yet further SS improvement is still expected. One of the critical points for ultra-steep SS is the realization of abrupt doping profile. Some extensively discussed methods for SS improvement in Si TFETs include inserting a fully-depleted doping pocket at the tunnel junction [6] and using advanced annealing technologies [7], yet stringent process control is required, such as sufficiently small pocket

width for fully depletion, as well as strict annealing condition for steep doping gradient.

In this paper, we propose a novel Si Junction-modulated TFET (JTFET) with the equivalent function to achieve ideally abrupt doping profile. Compared with traditional TFET of the same fabrication process, by merely introducing a striped gate, JTFET can effectively achieve sharper band bending at the tunnel junction when switching on due to the junction depleted-modulation action, resulting in much steeper switching behavior, and the ION is also enhanced due to the higher tunneling efficiency, as well as larger tunneling area with the same footprint. Moreover, an additional self-depleted pocket with much relaxed width requirement can further modulate the tunnel junction with steeper SS and larger ION.

JTFET structure and junction depleted-modulation

The structure of proposed Si JTFET is schematically shown in Fig. 1a. Compared with traditional TFET (Fig. 1b), JTFET has a striped gate stretched into the P+ source region with the induced larger tunneling area. The built-in potential of adjacent tunnel junctions in JTFET can fully deplete the LSWG region with the gate of narrow WG, which can be considered as a kind of self-depletion effect.

Fig. 2 shows the simulated transfer characteristics of JTFET and traditional TFET using Sentaurus device simulator [8] with a calibrated dynamic non-local tunneling model. JTFET exhibits much steeper SS, higher ION, and a little larger VBTBT (VBTBT defined as the voltage at which BTBT occurs) due to the junction depleted-modulation action. Fig. 3 compares the surface energy band along the tunnel direction of JTFET and traditional TFET with the increased VG. It shows that at the same VG, JTFET can get higher conduction band energy (EC) in the channel than TFET which is modulated by the self-depletion effect, yet with the unchanged band bending at the S/C interface due to the same dopants distribution. For the off-state (Fig. 3a), no BTBT occurs at the tunnel junction for both JTFET and TFET because of the higher EC in the channel than the valence band energy (EV) in the source. The IOFF are both very low. However, when the BTBT of traditional TFET

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Acknowledgement: This work was partly supported by the 973 Projects (2011CBA00601), NSFC (60625403), and National Science & Technology Major Project 02 under Grant 2009ZX02035-001. The authors would like to thank the staff of National Micro/Nano Fabrication Laboratory of Peking University for their assistance in the device fabrication and Dr. Weihai Bu for the discussion. References: [1] A. M. Ionescu et al., IEDM, p. 378, 2011; [2] G. Dewey et al., IEDM, p. 785, 2011; [3] F. Mayer et al., IEDM, p. 163, 2008; [4] S. H. Kim et al., VLSI, p. 178, 2009; [5] Q. Huang et al., IEDM, p. 382, 2011; [6] R. Jhaveri et al., IEEE TED, vol. 58, p. 80, 2011; [7] J. T. Smith et al., IEEE TED, vol. 58, p. 1822, 2011; [8] Sentaurus TCAD, vE-2011.09, Synopsys, 2011.

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Fig.2 Simulated transfer characteristics of JTFET and TFET; JTFET shows steeper SS, higher ION and larger VBTBT due to the junction depleted- modulation. (Inset) top view of JTFET and TFET.

Fig.1 Schematic structure and surface top view of (a) proposed Si Junction-modulated TFET (JTFET) with a striped gate and (b) traditional TFET; larger tunneling area can be achieved in JTFET than traditional TFET.

Fig.3 Simulated surface energy band along the tunnel directions (shown in the dash line in inset of Fig. 2) of JTFET and traditional TFET with increased gate voltage.

Fig.4 Extracted tunneling barrier width as a function of VG-VBTBT in JTFET and traditional TFET. Reduced can be achieved in JTFET.

Fig.5 Surface electric field E of JTFET and TFET along the tunnel directions when devices turn on. JTFET has the higher E for switching.

Fig.6 Subthreshold slopes of JTFET and traditional TFET as a function of drain current. JTFET shows much steeper SS below 10mV/dec.

Fig.7 (a) Experimental process flow of JTFET based on the bulk silicon substrate; (b) top view SEM image of typical JTFET structure; (c) cross-section SEM image of the striped gate along AA in (b).

Fig.8 (a) Measured transfer characteristics of Si JTFET with steep SSmin and SSavg (extracted over 3 decades of ID from IOFF); (b) compared with traditional TFET in the same die, JTFET demonstrates much steeper switching behavior and higher ION.

Fig.9 Measured output characteristics of the fabricated JTFET and traditional TFET in the same die. Better saturation and lower parasitic resistance can be achieved in JTFET compared with TFET.

Fig.10 Measured ION dependence on temperature of JTFET and traditional TFET with different VDS; the similar positive dependence with TFET indicates the dominant BTBT current in JTFET.

Fig.11 Comparison of measured transfer characteristics of JTFET with different WG in the same die; JTFET with larger WG shows weaker junction depleted-modulation action, but still larger ION than traditional TFET.

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