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A Novel Metric for Interconnect Architecture Performance

Parthasarathi Dasgupta, Andrew B. Kahng,Swamy V. Muddu

Dept. of CSE and ECEUniversity of California, San Diego

La Jolla, California 92093

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Outline

• Interconnect Architecture (IA)

• Interconnect Architecture Metric - Rank• Dynamic Programming for Exact Rank Computation

• Experimental Results and Conclusions

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Interconnect Architecture• An Interconnect Architecture (IA) is a collection of

pairs of wiring layers, with all wires in a given layer pair having uniform width (w), height (h), spacing (s) and thickness (t)

Repeater

Repeater

Layer-pair (j+1)

Repeater

Layer-pair j

via Schematic of an IA

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Interconnect Architecture Metrics• Traditional IA metrics

– Delay, bandwidth, crosstalk noise margin, #layers• Conventional metrics do not effectively capture

design constraints and process parameters– How does interconnect delay vary with ILD-k ?– How does #layers needed to route a design change

with wire width?• An evaluation metric should consider

– Design parameters– Process parameters– Process constraints– Routability subject to performance constraints

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• [Bohr95], [Moll93]

• Study effects on delay, crosstalk of changing geometric parameters and technology constraints

• [Venkatesan01] • Method to minimize delay, #layers and area• Shows dependence of die area on repeater insertion

• Previous works do not explicitly consider semi-global, local layers

• These layers significantly impact routability due to via blockage Motivates search for new IA quality metric

• Simple and efficiently computable• Sensitive to design parameters such as frequency, WLD• Sensitive to process parameters such as ILD permittivity• Aware of layout issues such as repeaters, via blockage

Previous Work

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Performance-, WLD-Aware Routing Model• All connections (wires) are two-pin, L-shaped• Each segment of an L is assigned to one layer of a tier• For a given WLD, longer wires always routed on upper

tiers; shorter wires always routed on lower tiers• Every wire has a target delay (proportional to clock period)• Repeaters inserted as needed to meet delay targets

• Starting from longer wires first• All repeaters used in wires of a tier are of same size

• Repeater resource (maximum available repeater area) is specified as fraction of total die area

•Repeaters inserted until repeater area budget exhausted

Layer-pair (j+1)

Layer-pair j

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Outline

• Interconnect Architecture (IA)

• Interconnect Architecture Metric - Rank• Dynamic Programming for Exact Rank Computation

• Experimental Results and Conclusions

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The Rank Metric for IA

• Determines IA quality in terms of how completely target performance is met while embedding all wires

• Definition 1. The rank of a wire is its index in the WLD, where wires have been arranged in order of non-increasing length

• Definition 2. The rank of an IA is the index of the highest-rank wire in the WLD that meets its target delay, subject to the constraints:

– The given repeater area budget is not exceeded– All lower-rank (= longer) wires in the WLD meet target delays– All wires in the WLD can be assigned to the IA

• The rank of an IA is zero if not all the wires of the WLD can be assigned to the IA, even without meeting any delay targets

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Rank of IA: Dependencies

Via blockage

IA:number of layer pairs

W, H, S and T, tech node, gate count and

gate parameters

Repeater area budget

AR

Target DelaysRank of the IA

TWirelength

Num

ber o

f wire

s

WLD

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The Rank Computation Problem• Given

– IA with fixed number of layer-pairs with fixed geometry– WLD W with n wires– Available repeater area AR

– Upper bound di = target delay for each wire

• Find– An assignment of wires from the WLD to the IA

• using repeater insertion within the repeater area budget• to meet target delays of wires

– such that rank of first wire failing to meet target delay is maximized

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• Heart of IA evaluation: meeting target delay• Target delays of wires are met with repeater insertion• Delay computation

Length of wire i = li; Maximum wire-length = lmax;

Clock frequency = fc,

cp = Parasitic capacitance; CL = load capacitance

rj, cj = resistance, capacitance per unit length of layer-pair j

ro, co = output resistance, capacitance of min-sized repeater

ActualDelay of wire i = f(cp,cl,ri,ci,ro,co)

TargetDelay of wire i = di = (li/lmax) x (1/fc)

OptimumRepeaterSize in wires of tier j = Sj =

• Repeater insertion performed if ActualDelay < TargetDelay

Delay Computation and Repeater Insertion

oj

oj

rccr

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Rank Computation…(2)• Rank of an IA is computed by assigning maximum

number of wires from the WLD to tiers of the IA – by making ActualDelay TargetDelay– within AR

• Maximizing the Rank requires optimum combination of– wires assigned to tiers– repeaters assigned to wires

• Exhaustive search over wires, tiers and repeaters is infeasible

• How to compute Rank efficiently?– Greedy approach or Dynamic Programming (DP)

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Can Greed Correctly Compute Rank?• Rank(IA) calculation: make ActualDelay TargetDelay for max #wires, within AR budget– Assign wires to tiers; assign repeaters to wires – Example: Four wires, each requiring 4 repeaters to meet target

delay in layer-pair j, but only 1 repeater in layer-pair j+1; repeater budget = 8 repeaters Greed is not optimal

Wires in layer-pair j meet target delay

Wires in layer-pair j+1 fail to meet target delay

Wire in layer-pair j meets target delay

Wires in layer-pair j+1 meet target delay

Greedy solution. Rank = 2

Optimum solution. Rank = 4

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Outline

• Interconnect Architecture (IA)

• Interconnect Architecture Metric - Rank• Dynamic Programming for Exact Rank Computation

• Experimental Results and Conclusions

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DP formulation• In DP formulation, Rank computation is considered as a

collection of sub problems• Sub problem characteristics

– number of wires to be assigned (i)– number of tiers used for wire assignment (j)– repeater area used to satisfy delay requirements (r)– number of wires already assigned, that meet target delay (i’)

• A Boolean array M[i,j,r,i’] indicates the feasibility of wire assignment in successive stages of the DP

• M[i,j,r,i’] is 1 if – i wires can be assigned to – j tiers– with i’ wires meeting target delays– within r repeater areaWith all remaining n-i wires assigned to m-j tiers even without

meeting target delay

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DP Formulation…contd.• The DP populates cells of M[i,j,r,i’] according to

• The DP has three main components– A means of preserving partial solutions of assignment– A method, testing feasibility of assigning some wires to tiers

satisfying delay constraints within repeater budget– A method, testing feasibility of assigning all remaining wires to

remaining tiers without delay considerations

M[i, j+1, r, i’] = M[i1’, j, r1, i1’] ^ …1

M’(i1’, j+1, zr1, r-r1, r2, i2’, i) ^ …2

M’’(n, i, m, j+1, zr1+zr2) …3

s.t. r1 + r2 < r, i1’ + i2’ = i’

m = total # of tiers, n = total # of wires, i, i’, i1’, i2’ = wire indices, j = layer-pair index, r, r1, r2 = repeater area, zr1,zr2 = # repeaters

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Components of the DP Algorithm• Component (1) of the DP, M[i, j+1, r, i’] checks the feasibility

of assigning wires 1,…,i in layer-pairs 1,…, j+1 using at most r repeater area s.t. i’ wires meet target delay

• Component (2) of the DP, M’(i1’, j+1, zr1, r-r1, r2, i2’, i) checks feasibility of assigning i2’ (out of i’) wires in layer-pair j+1 using at most r-r1 repeater area, where total set of wires assigned is 1,..i in layer-pairs 1,…,j+1

• Component (3) of the DP, M’’(n, i, m, j+1, zr1+zr2) checks feasibility of assigning wires i+1,…, n in layer-pairs j+2, …, m without any delay constraint

• Wire assignment for rank computation is performed by DP components (2) and (3)• (2) performs wire assignment by meeting target delay• (3) performs wire assignment greedily without delay

considerations after repeater area is exhausted

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Wire Assignment to the IA• Wire assignment to the IA is performed by (2), (3) of the DP• Wire assignment in (2) takes in to account

– delays of wires and repeater insertion– area occupied by wires– via blockage due to wires from

higher tiers and repeater vias• In (3), greedy bottom-up wire assignment is performed to

check: – feasibility of assigning n-i wires to m-j tiers– with via blockage from wires above– without any delay considerations

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Outline

• Interconnect Architecture (IA)

• Interconnect Architecture Metric - Rank• Dynamic Programming for Exact Rank Computation

• Experimental Results and Conclusions

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Experimental Setup• DP algorithm for Rank computation is implemented in C• Rank computation is performed for

– 1M / 4M / 20M gate designs in the 180nm/130nm/90nmtechnology nodes respectively

• IAs are specified in tech files based on industry design rules• Coarsening of WLD for speedup of rank computation

– Binning– Bunching

• Study of variation of Rank with– ILD permittivity (K)– Miller Coupling Factor (MCF)– Repeater area fraction (R)– Target clock frequency (C)

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Experimental Results

Variation of Rank with K, MCF, C and R for 130nm, 1M gate design

K Rank MCF Rank C Rank R Rank

3.9 0.397 2 0.397 500MHz 0.397 0.1 0.117

3.6 0.413 1.85 0.412 800MHz 0.386 0.40 0.397

3.3 0.430 1.7 0.429 1.1GHz 0.309

2.9 0.458 1.5 0.456 1.5GHz 0.309

2.5 0.491 1.3 0.488

•Rank • increases with decreasing K – ILD permittivity• increases with decreasing MCF – Miller Coupling Factor• decreases with increasing C – Target Clock Frequency• increases with increasing R – Repeater Area budget

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Conclusions and Future Work• Performance impact of ILD permittivity reduction can be

matched by reduction in MCF• For high-rank embeddings of future WLDs, material

improvements alone are not sufficient• Need to co-optimize design and process parameters• On-going work includes

– Alternative models of target delay requirements– Direct optimization of IA using Rank as the metric– Comparison of optimized IA’s with foundry, ITRS IA’s