J Electron Test (2013) 29:697–714DOI 10.1007/s10836-013-5410-z

A Novel Formalism for Partially Defined AsynchronousFeedback Digital Circuits

Gurkan Uygur · Sebastian M. Sattler

Received: 27 March 2013 / Accepted: 4 September 2013 / Published online: 19 October 2013© Springer Science+Business Media New York 2013

Abstract In contrast to combinational logic and masterclocked sequential logical, asynchronous feedback circuitsare partially defined due to analogous meta-stabilities. Wepresent a novel formalism to exactly explore this digitallyassisted analog phenomenon in order to build up a repre-sentative test bench that is able to enforce race constraints(meta-stable behavior) for non-deterministics, instabilitiesas well as for oscillations in feedback structures. Further, weintroduce our definitions for consistently modeling understate transition graphs, we provide all entities for modelingasynchronous feedback structures and state our proposedmethodology with an exemplary asynchronous circuitry.The given example is explained at a high level of abstrac-tion, all data for revision is provided, too. The approachseems to be capable to test for meta-stabilities, analogbehavior in feedback digital structures.

Keywords Asynchronous · Feedback · Digital · Circuit ·Meta-stability · Partial · Automaton

1 Introduction

Digital circuits can be considered in several views, e.g., inblock-view, nand-view, net-view, and in structure-view. Thestructure-view consists of nodes and directed edges betweentwo nodes. The nodes represent a timeless function, and

Responsible Editor: S. Ray

G. Uygur (�) · S. M. SattlerChair of Reliable Circuits and Systems,University of Erlangen-Nuremberg, 91052 Erlangen, Germanye-mail: uygur@lzs.eei.uni-erlangen.de

S. M. Sattlere-mail: sattler@lzs.eei.uni-erlangen.de

the edges define the signal flow backwards from the sourcenode (output pin) to the target node (input pin). Connectingall of the edges by name exhibits a directed graph. This isa most abstract structural view of an arbitrary circuit. Oneof its advantages is that it provides a topological approachto distinguish between combinational logic and sequentiallogic: a digital structure implements a combinational logic,if the structure does not contain any simple cycle, to say ele-mentary circuit [23]. On the other hand, the structure hasto contain at least one simple cycle1 for feeding-back itsstate information to realize a sequential logic. Of course,looking more precisely, we need to factor in more criteriato differ between combinational and sequential logic; e.g.it is to be checked, whether and when an elementary cir-cuit is alive, so to say, whether and when its gates are open,such that the circuit is in a position to change its logicalinformation content depending on the input information aswell as the feedback situation. In fact, there are divers tech-niques and technologies for opening and closing the gates;particularly, employing a master clock is a very well estab-lished and accepted concept. Different topologies—RS-FF,JK-FF and so on—for opening a gate at a “specific logi-cal state” of a master clock and at a “specific logical edge”of a master clock, respectively, are well studied. Powerfulstandard technologies realizing master clocked architec-tures are successfully deployed. At this point, it is worth tonotice, that a simple “four valued” digital (logical) seman-tics is used, namely digitally high (1), digitally low (0),rising edge (↗) and falling edge (↘), for designing specificstate triggered and edge triggered sequential logics. Thecombinational and the master clocked sequential digital cir-cuits are scientifically and technologically well understood.

1In topological manner of speaking, a topological hole [45]

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A non-ambiguous relationship between theory and applica-tion in mathematics and electrical engineering is ensuredby technologically isolating hazardous and analogue phe-nomenon; for this, in state of the art research and in standardliterature [37, 43, 44], powerful theoretical frameworks—e.g., dead-time modeling, Boolean differential calculus,worst-case approximation and so on—are well-established.

1.1 Synchronous vs. Asynchronous Digital Circuit

A sequential circuit can be classified as synchronous orasynchronous. Synchronous means that the circuit is pro-vided with a master clock which has a sufficiently longperiod of time regarding to worst case scenarios. Hence,per definition, a synchronous circuit is free of any hazardcaused by analog signal racing conditions. But, it is sub-ject to a single point of failure, so if the clock fails then thecomplete functionality fails, too. Even though the class ofsynchronous circuit systems is well understood and formsthe base of almost all modern microcomputers, there is arenewing and increasing interest in asynchronous design,because asynchronous circuits are a promising type of digi-tal circuits with lots of potential benefits of improved systemperformance, modular design, low power consumption andreduced electro-magnetic emission. Further essential char-acteristics of asynchronous circuits are, that asynchronouscircuits show no problems with clock skew and related sub-tle issues, and are fundamentally more tolerant of voltage,temperature and manufacturing process variation [24, 32,35]. And, it is remarkable, that the international technologyroadmap for semiconductors (report on design [21]) predictsthat up to 40 % of the designs will be driven by ‘handshakeclocking’ (i.e., asynchronous) in 2020 [24].

1.2 Focus of the Paper

What we are interested in is a theoretical modeling con-cept for discrete event based modeling, verification and testof asynchronous feedback digital circuits. This means inparticular that the formalism has to cover partially defineddigital system behavior, whereby the partiality is caused byanalogous signal races in asynchronous feedbacks. The rea-son is, that asynchronous feedback circuits—as opposed tosynchronous feedback circuits—are instantaneously under-lying analogue principles. Hence, analogue conditionedsignal racing and meta-stability [15, 19, 38] and furtherrelated electrical influences are playing a crucial role inasynchronous circuits [16, 27]. The task formulation in thispaper is to provide a formalism for handling with partiallyspecified asynchronous digital automata. To reduce com-plexity for large automata, the theory also has to be totallyfeatured to divide arbitrary structure into sub-structures, andrecompose the generated sub-models again into an overall

structure model. There exists lots of related and importanttechniques, which should be taken into consideration:

Petri nets are one famous general purpose modeling tech-nique for discrete event and hybrid systems, with lots ofderivatives for special applications [29]. As a big advan-tage, Petri nets naturally support simultaneous behavior.But, there exist too many composition techniques for Petrinets [8]. Therefore there are researches for putting themunder a unified framework. Chen et al. [8] presents sucha framework investigation by classifying into feedback andnon-feedback composition. However, as mentioned above,we are interested in a formalism, which covers feedback,simultaneity as well as asynchronicity, and also being totally(without any constraints) closed under (de-)composition.

Signal Transition Graphs (STG) are a widely usedinterpreted Petri net based formalism with transitionslabeled with rising and falling edges for the descriptionof asynchronous feedback circuits, with several existingapproaches to their synthesis [35]. However, STG have todeal with the state space explosion problem, so there areseveral approaches like STG decomposition strategies andPetri net unfoldings for efficient implementations [24], [1].Unfortunately, these strategies again are handicapped todeal with the serious Complete State Coding (CSC) prob-lem some times leading to so called irreducible conflicts[42]. So as to remember again, we seek a formalism forasynchronous feedback digital circuits (thus asynchronousfeedback transitions), which is closed totally under (de-)composition.

In recent times, Transaction Level Modeling (TLM)together with the modeling language SystemC become moreand more relevant in system design [7, 20, 41]. Both,TLM as modeling concept and SystemC as software lan-guage build a powerful tool for system simulation, syn-thesis and verification. However, [7] points at the lack ofclear definition of TLM, which leads to (re-)usage prob-lems in modeling, validation, refinement, exploration andsynthesis.

Contrary to TLM, there exist diverse precisely definedautomata based modeling and composition techniques instate of the art, which are hierarchic (not associative) [2],or associative [17], or commutative and associative by con-straint, or both associative and commutative [29] takingsingle events into account. The associative and commuta-tive one is preferred to provide non-hierarchical and scalabledivide-and-conquer. The problem is, that automata theory isan universal concept, and not specifically designed for mod-eling asynchronous circuitry and supporting simultaneousbehavior. Thus, appropriate composition operation and datastructures (entities) are needed.

In an abstract view feedback asynchronous and syn-chronous circuitries can be considered as a dynamic hybridsystem by nature [39], as they exhibit continuous and

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discrete components which are embedded in continuous anddiscrete physical environment instantaneously interactingwith each other. They are provided with lots of heteroge-neous units, which themselves are being hybrid subsystems,as they are dealing and interacting continuously and dis-cretely using analog and digital signals. The analog anddigital system components (modules, integrated systems[34]) exhibiting continuous and discrete state transitions [3]are coupled over directed data flows (interfaces). Particu-larly the interfaces between heterogeneous system classesof sensors and actuators and the specification of data flowsare vitally important [11, 33]. There exist diverse model-ing techniques for particular system classes. The continuousstate transitions can be described using algebraic and dif-ferential equations [30], and the discrete state transitionsare generally represented by (partial) truth tables (transitiongraphs, automata). Hybrid automata—finite state machinesequipped with a set of real-valued variables—are a for-malism to compose both continuous and discrete worlds[3]. Timed automata [31] and Timed Petri nets [25] areimproved modeling technique for studying such dynamichybrid systems also including concurrency. Since concur-rent task behavior can hazardously lock the system, par-ticular investigations are needed for optimal (profinite andinfinite) schedule modeling [5] involving real-time aspects[9] and precisely task system definitions [22, 26]. Thus,to avoid locally valid and isolated methods and ad hocproofs [28] which then may are leading to failing globalresults, mathematical abstractions and overall formalismswith unified framework are needed for powerful and consis-tent modeling and verification. Such a candidate is the tracetheory [28], which has been applied to Petri nets and devel-oped for mathematically exactly describing the behavior ofconcurrency on distributed and parallel systems providingadditional features, e.g. locally description of synchroniza-tion [13, 14]. Particularly, the trace theory—also known ashistory monoid, as referred in computer science and orig-inally has been claimed as the free partially commutativemonoid for combinatorics on words—together with wordreplacement systems [4] provide a powerful simulationframework for optimized dynamically parallel processingwhich additionally can be improved by adding further suit-able replacement rules. One should also mention, that tracesare also interesting for the serialization problem in dis-tributed databases [12]. Thus, traces involving algebraictopology and statistics are powerful tools for analysis andverification of stored data [10, 18] captured from diverseconcurrent dynamic hybrid systems.

1.3 Organization of the Paper

We start with preliminaries in Section 2 and introductinto the state-diagram-driven formalism for automata-based

modeling of asynchronous sequential circuits. In Section 3we exhibit the partial behavior of asynchronous feedbackdigital circuits, and hence point out to the non-realistictotally specified digital automata calculated by the state ofthe art formalism in Section 2. In Section 4 we present anovel categorial co-algebraic Automata Based Composition(ABC) and the application of the formalism for partiallyspecified asynchronous digital automata. In Section 5 weshow experimental results which are proving the consis-tency of the new approach, and finally the paper closes witha conclusion in Section 6.

2 Preliminaries

In the following, we introduct into the state-diagram-drivenformalism for design of digital automaton and for automata-based modeling of asynchronous sequential circuits. Theinterested reader may find further information in [43].

2.1 Digital Automaton

A generic digital automaton is a 5 tuple A = (z, x, y, δ,

λ) with input vector x = (· · · , x1, x0), state vector z =(· · · , z1, z0), output vector y = (· · · , y1, y0), (asynch-ronous) state transition function δ : (z, x) �→ z and outputfunction λ : (z, x) �→ y, see Fig. 1. As the output functionλ depends on state variables and input variables (z, x) =(· · · , z1, z0, · · · , x1, x0), this type of automaton is termedas Mealy (Fig. 1a). If the output function only depends onthe state variables, then the automaton is termed as Moore(Fig. 1b). And, if the output is the same as the state, then theautomaton is termed as Medwedew (Fig. 1c).2

2.2 Automata Based Modeling of Asynchronous SequentialCircuits

Let us consider a simplest non-trivial3 feedback cir-cuit structure, the low-active RS latch, with input vectorx = (S, R) and state vector z = (z1, z0), see Fig. 2. Wewant to derive the corresponding digital automaton fromthe circuit structure. For this, we open (cut) the feedbackwires into two parts and synchronize the unidirectional dataflow using synchronization points (doors). We abbreviatethis operation, “to open a wire and to control the data flowusing a timed synchronization point”, with the symbol τ , seeFig. 3. This means, that the feedback wires are divided intotwo parts: the one part is “connected” to the corresponding

2If the automaton acts independent of input, then we say that it is anautonomous one.3A trivial one is e.g. an OR gate which is feedback with itself, hencerealizing a monotonically increasing function.

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a b c

Fig. 1 Digital automaton: input vector x = (· · · , x1, x0), state vector z = (· · · , z1, z0), output vector y = (· · · , y1, y0), (asynchronous) statetransition function δ : (z, x) �→ z, output functions λ : (z, x) �→ y (Mealy) and μ : z �→ y (Moore), and trivial output y = z (Medwedew)

NAND gate output, hence it is (instantaneously) assignedwith the new value (nz = δ(az, x)), and the other part is“synchronized behind the door τ”, hence keeping the oldinformation until τ lets pass the new information such thatthe synchronized part becomes assigned with the new valueafter τ , az := nz. This procedure allows to formally derivethe following Boolean equations and timed (τ ) assignments(Fig. 3):

az1 := nz1 = S ∧ az0

az0 := nz0 = R ∧ az1

The set of states Z is encoded by the state vector z, Z =[z] = {Z0, Z1, Z2, Z3} = {az1

az0,az1

az0,az1

az0,az1

az0} ={[00], [01], [10], [11]}. Thus, for each state Zi the sub-transition graph of transitions leading to Zi is determinedby the Boolean algebra:

Z0 = [00] := Z3SR

Z1 = [01] := Z3SR ∨ Z1S

Z2 = [10] := Z3SR ∨ Z2R

Z3 = [11] := SR ∨ Z2R ∨ Z1S ∨ Z0

The superposition of all sub-transition graphs derived abovethen determines the transition graph of the low-active RSlatch, see Fig. 4.

Fig. 2 Low-active RS latch with input vector x = (S, R) and statevector z = (z1, z0) = (Q, Q)

2.3 Epilogue: Digital Automaton with Output

Previous section shows, that for formally deriving the tran-sition graph, it is necessary to open and synchronize (τ ) thefeedbacks. However, this leads to ambiguous output func-tions, which we term type-new and type-old, respectively.In the following we explain the two types on the basis ofthe Mealy automaton (Fig. 1a): type-new says that the out-put y depends on the new state value nz and the input x,y = λ(nz, x); on the other hand, type-old says that theoutput y depends on the old state value az and the inputx, y = λ(az, x), see Fig. 5. Thus, the type determines theoutput for each state in the transition graph.4

3 True Digital Behavior of Asynchronousfeedback Circuits

In this section, we deal with the vital problem, how muchthe transition graph (Fig. 4) of the RS latch (Fig. 2) complieswith the “true” digital behavior regarding asynchronousfeedback.

3.1 Digital Truth Table of the Low-Active RS Latch

In digital-view, we adopt the position that the gates are notmathematical-logical functions. The output of a functioncan not be evaluated infinitely fast, and it is depending onphysical reality such as driving strength of the gates, propa-gation delay and races between several signal edges. As anexample, we consider the following initial situation [0001]for t = (aQ1,

aQ0, S, R), see Fig. 6. It is to note, that aninitial situation means, that on each (feedback) wire theelectrical potential is equal. Hence, the assignment [00] for(nQ1,

nQ0) implies—due to galvanic coupling—the sameassignment [00] for (aQ1,

aQ0). Now, with R = 0, it arises

4Obviously, to observe outputs is essential for testability. Considerthat any observation point is marked with τ . Thus τ divides a wireinto two pars, one part is assigned with new analog signal informationbefore observation and test resp., and the other part is assigned withold information after observation and test.

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Fig. 3 Low-active RS latch (Fig. 2) with synchronized (τ ) feedback.τ means “to open (cut) the feedback wires into two parts and tosynchronize the unidirectional data flow using timed synchronizationpoint (door)”. nz = n(· · · , z1, z0) = (· · · , nz1,

nz0) means “state vec-tor assigned with new value δ(az, x)” formally termed as the equationnz = δ(az, x). az = a(· · · , z1, z0) = (· · · , az1,

az0) means “state vec-tor assigned with old value after τ” formally termed as the timedassignment az := nz. Equations and timed (τ ) assignments in detail:az1 :=nz1 = S ∧ az0; az0 := nz0 = R ∧ az1

nQ0 = 0 → 1, and the new voltage level is propagatingon the wire Q0, see Fig. 7. At this point, in physical-view,two different scenarios are possible, which—as we willdiscover—are leading to “digital” contrariness:

3.1.1 Scenario: aQ0 is Still Acting

In this scenario, the electrical potential nQ0 = 1, whichis just created, is not able to cover the electrical potentialaQ0 = 0 in due time. In this case, a glitch (nQ1 = 0 → 1)could be triggered, see Fig. 8.

3.1.2 Scenario: aQ0 is in Time Covered

In this scenario, the electrical potential nQ0 = 1, which isjust created, is able to cover in due time (aQ0 = 1). In thiscase, no glitch (nQ1 = 0 → 1) will be triggered, see Fig. 9.

Fig. 4 Transition graph of the low-active RS latch (Fig. 3) determinedby the sub-transitions:Z0 = [00] := Z3SR

Z1 = [01] := Z3SR ∨ Z1S

Z2 = [10] := Z3SR ∨ Z2R

Z3 = [11] := SR ∨ Z2R ∨ Z1S ∨ Z0

a

b

Fig. 5 Timed Mealy automaton

3.1.3 Conclusion

To sum up, we state that the initial situation [0001] fort = (aQ1,

aQ0, S, R) is leading to contradictory (abbrevi-ated as ∗) behavior. Hence, in digital-view, we register theassignment [∗∗] for (nQ1,

nQ0). Table 1 presents the com-plete “digital” truth table of the low-active RS latch. It saysthat the state [00] becomes non-reachable (Fig. 10). The rea-son is given in analog-view. Namely, at stable state [11],if inputs simultaneously change from SR to SR, a signalracing on the wires Q and Q gets triggered. This can leadto a win-win situation, too, which then triggers a new raceagain causing an (unstable) oscillation on the feedback. Butagain, as this is an analog destructive phenomenon, at theend one, either Q or Q, will win. This then is stated as a

Fig. 6 Initial situation [0001] for t = (aQ1,aQ0, S, R)

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Fig. 7 nQ0 = 0 → 1, and the new voltage level is propagating on thewire Q0

non-determined (contradictory) digital behavior in the cor-responding transition graph (Fig. 11, dashed arrows). Thus,in analog view, we say that the state [00] is an analog meta-stable state occurring during the win-win phase. It doesn’tshow up in digital view.

3.2 Logical vs. Digital vs. Analogue

In logic-view, each combination of old state and inputis uniquely determining the next specific new state. Therespective z-equations and assignments, respectively, aretotally defined combinational functions. Table 2 contraststhe logical truth table with the digital truth table.

In digital-view, the meta-stable states, which are the start-ing points for analogue signal races, are “not accepted asdigital states”. In particular, for the low-active RS latch, thisis the case for the meta-stable state (Q1, Q0) = [00] andregular input (S, R) = [00], which triggers a “logical” oscil-lation, but is “digitally” not determined, because the nextstate could be [10], [11] or [01].

Fig. 8 Scenario: nQ0 = 1 is not able to cover aQ0 = 0 in due time;risk of glitch (nQ1 = 0 → 1)

Fig. 9 Scenario: nQ0 = 1 is able to cover aQ0 in due time; no risk ofglitch

In analog-view, changes of input signals can triggerraces, which then can lead to non-deterministic (contra-dictory) state transitions and are neither existing in thelogic-view nor in digital-view.

3.3 Use Case: Edge Triggered RS-FF

Let us consider the low-active positive edge triggered RS-FFin Fig. 12. For the sub-structure on the right we did alreadydiscuss its behavior in Section 2 (Fig. 4). Now, we derivethe z-equation from the sub-structure on the left:

y1 = az2hS

y2 = az3hR

az2 := nz2 = y1Caz3 = az2hSCaz3 = (az2 ∨ hS)Caz3

az3 := nz3 = y2Caz2 = az3hRCaz2 = (az3 ∨ hR)Caz2

After deriving the corresponding transition graph, we syn-thesize the transition graphs of the sub-structures on theleft and the right, which then obviously lead to the overalltransition graph, see Fig. 13 with the overall state encoding(

z2 Q

z3 Q

).

Let us explore the meta-stability. For this, we regularly

setup the RS-FF into the stable state[

1 01 1

]and then hold

(Fig. 13 at the top left). As long as the clock signal islow (C), the input (hS, hR) is allowed to change with-out any effect. We setup the input variables into high-level((hS, hR) = [1, 1]) and hold, hence the signals on the inputwires (hS, hR) are put into low-level ((hS, hR) = [0, 0]),and so the signals (y1, y2) are stably hold in high-level((y1, y2) = [1, 1]) (Fig. 12 on the left). During this situa-tion, let the clock signal switch from low to high (positiveedge, C = [↗]), which then enforces the state signals(z2, z3) to switch from high to low ((z2, z3) = [↘, ↘]), see

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Table 1 Truth table of thelow-active RS latch Combination Digital Comment

aQ1aQ0 S R nQ1

nQ0

0 0 0 0 * * Input [00] ⇒ meta-state [00]

0 0 0 1 * * Input [01] ⇒ meta-state [00]

0 0 1 0 * * Input [10] ⇒ meta-state [00]

0 0 1 1 1 1 Stable state

0 1 0 0 0 1 Stable state

0 1 0 1 0 1 Stable state

0 1 1 0 1 1 Transient state

0 1 1 1 1 1 Stable state

1 0 0 0 1 0 Stable state

1 0 0 1 1 1 Transient state

1 0 1 0 1 0 Stable state

1 0 1 1 1 1 Stable state

1 1 0 0 * * Input [00] ⇒ meta-state [11]

1 1 0 1 0 1 Stable state

1 1 1 0 1 0 Stable state

1 1 1 1 1 1 Stable state

The symbol * means here dig-itally not determined, metameans meta-stability potentiallyleading to (hazardous) insta-ble, oscillating and transienttransitions, respectively

Fig. 14. At this point, z2 and z3 start a race from Vdd (supplyvoltage) to VTH (threshold voltage). The first signal, whichachieves VTH, continues to decrease, and feeds back andenforces the other signal to increase. In this view, the winneris not determined. Obviously, the final outcome, (z2, z3) =[0, 1] and (z2, z3) = [1, 0], respectively, is biased by thetechnology parameters and environmental conditions, butthe parameters and conditions may also vary. The signals(z2, z3) act as master; as a consequence, the digital behaviorof the RS-FF considered is not determined at all.

3.4 Trade-Off Between Ideality and Reality

The use case above contrasts with different views and eval-uations: in logical view, the state

[0 10 1

]is reachable.

[0 10 1

]

Fig. 10 Partial state transition graph of digital RS latch with the fol-lowing reliably reproducible states: stable at [01], stable at [10], andstable and transient at [11], respectively. The state [00] is not reachable(Table 1)

triggers the successor state[

1 01 0

]in any case, so—in terms

of observability, controllability and testability—the state[1 01 0

]is reliably and reproducibly reachable. In analog

view, however, the state[

1 01 0

]is meta-stable, so far away

from reliability and reachability, even its predecessor state[0 10 1

]is not reliability reproducible. Hence, the trade-off

seems to say that, starting from a stable state([

1 01 1

]), if

a race gets triggered ((z2, z3) = [↘, ↘]), then this will

(ideally) lead to the intermediate state([ ↘ 0

↘ 1

]), but then

the (real) successor state is not defined any more:[

1 01 1

]�→[ ↘ 0

↘ 1

]�→ ∗.

Fig. 11 Totally (non-partially) specified state transition graph of log-ical RS latch extended with non-deterministic analog behavior, inparticular with the meta-stable state [00] provided with contradictorytransitions

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Table 2 “Logical” vs. “digital” truth table of the low-active RS latch:the formalism explained in Section 2 generates a total deterministicbehavior model which does not comply with the digital behavior of thestructure

Combination Logical Digital

aQ1aQ0 S R nQ1

nQ0nQ1

nQ0

0 0 0 0 1 1 * *

0 0 0 1 1 1 * *

0 0 1 0 1 1 * *

0 0 1 1 1 1 1 1

0 1 0 0 0 1 0 1

0 1 0 1 0 1 0 1

0 1 1 0 1 1 1 1

0 1 1 1 1 1 1 1

1 0 0 0 1 0 1 0

1 0 0 1 1 1 1 1

1 0 1 0 1 0 1 0

1 0 1 1 1 1 1 1

1 1 0 0 0 0 * *

1 1 0 1 0 1 0 1

1 1 1 0 1 0 1 0

1 1 1 1 1 1 1 1

4 Theory for Partially Specified AsynchronouslyDigital Automata

The trade-off discussed in Section 3.4 motivates to“upgrade” the 2-valued Boolean algebra, such that the inter-mediate states get included into the behavioral model. Thismeans, that, besides the two digital signal levels high (1)and low (0), the intermediate signal levels “high to low”(↘) and “low to high” (↗) are needed to be respected,too. Hence, a 4-valued (2 × 2-valued) Boolean algebraseems to be reasonable. Further, we need a formalism,which is able to cope with partiality and de-composition.

Fig. 12 Low-active positive edge triggered RS-FF decomposed intothe left sub-structure (edge triggered master clocked latch) and theright sub-structure (low-active RS latch)

Fig. 13 Logical transition graph of the RS-FF in Fig. 12. Obvi-

ously, for the state encoding , the state in conjunction ofChRhS is meta-stable, hence we are not interesting for successor state

transitions after the state

Obviously, this is not the case for the Boolean algebra, sinceit is only capable of totally composing as seen in Section 2and discussed in Section 3. This motivates us to researchfor a co-algebraic categorial [6, 36] approach to cover a rea-sonable monomorphic5 de-composition kernel while totallybeing independent from deployed data structures (entities).

4.1 Automata Based Composition (ABC)

In this section, we define our automata based compositionusing co-algebraic categorial approaches as categories andfunctors are too convenient to avoid [6].

Definition 1 (Automaton) Let Ai = (Zi, 2�i , zi,0, ZFi)

be a 4-tuple with index i. Then, Ai specifies a possiblyincomplete (partial) deterministic finite automaton with setof states Zi , structured set of inputs (hyper events) 2�i ,initial state zi,0 ∈ Zi and set of final states ZFi ⊆ Zi . 2�i

denotes the power set of single events �i . Let Mi =(2�i \ {∅})∗ denote the corresponding free monoid over2�i \ {∅}. Let σi ∈ 2�i act on Zi by z′

i = ziσi , and ∅ actsas the identity on Zi . By sequential application Mi acts alsoon Zi .

Let the three automata Ai , Aj and A|| be given. Forthe corresponding monoids Mi , Mj and M|| we declare the(local) σ -Encoder ρ:

Definition 2 (σ -Encoder) ρ : M|| → Mi × Mj ,for generators σ of M|| we declare ρ : σ �→ (σi, σj ) withσi = σ ∩ �i and σj = σ ∩ �j . Furthermore, “ρ(σ) exists”if and only if (σi ∩ �j = σj ∩ �i). ρ−1 denotes the corre-sponding σ -Decoder.

5In short, to embed and operate partially uniquely

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Fig. 14 Simulation curves of the RS-FF (Fig. 12): race between thesignals (z2, z3) leading to meta-stability, (z2, z3) = [↘, ↘]

In the following we state the axioms for ρ−1 (we are, ofcourse, only interested in arguments at which ρ(σ) exists).The following formulae are to be understood as universallyquantified:

Axiom 1 (Invertibility) ρ(ρ−1(σi, σj )) = (σi, σj )

Axiom 2 (Associativity) ρ−1(ρ−1(σi, σj ), σk) =ρ−1(σi, ρ

−1(σj , σk)) =: ρ−1(σi, σj , σk) (herewith intro-ducing an abbreviated notation)

Axiom 3 (Commutativity) ρ−1(σi, σj ) = ρ−1(σj , σi)

Axiom 4 (Neutral Element) ρ−1(∅, σi)=ρ−1(σi, ∅) = σi

Axiom 5 (Idempotency) ρ−1(σi, σi) = σi forMi � σi∈ Mj

Fact (ρ-Monomorphism) ρ(′σ · ′′σ) = ρ(′σ) · ρ(′′σ) =′(σi, σj ) · ′′(σi, σj ) = (′σi ·′′σi , ′σj ·′′σj )

Definition 3 (Automata Based Composition) We definethe automaton A|| = Ai ||Aj = (Z||, 2�|| , z||,0, ZF ||) oftwo automata Ai and Aj with set of states Z|| = Zi × Zj ,set of hyper events 2�|| , set of single events �|| = �i ∪ �j ,initial state z||,0 = (zi,0, zj,0) and set of final statesZF || = ZFi × ZFj . Then, the following commuta-tive diagram defines the kernel for the ABC algorithm:

4.1.1 Formalism and Language Properties of the ABC

In the following we refer to some basic formalisms andproperties of the ABC. The monomorphic property of ρ

(Axiom 1, Fact) warrants the overall consistency of the

Fig. 15 A fingerprint code of the trace 0σ i · 1σ i · · · · · kσ i and theinduced behavioral scenario azi

1zi2zi · · · kzi

nzi in Ai

ABC. Imagine that n parallel system components are (asso-ciatively, see Axiom 2) composed to an overall componentsystem, A1||A2||...||An = A||, and let a scenario (actions,trace, scanning, sampling, sensing) of length m is specified(captured, stored). Then, the following formalism representsthis scenario, with σ(k) = σ(k − 1) · kσ and σ(−1) = ∅ :

a⎛⎜⎝

z1...zn

⎞⎟⎠

T⎛⎜⎝

σ1(0) σ1(1) · · · σ1(m − 1)

.

.

....

.

.

....

σn(0) σn(1) · · · σn(m − 1)

⎞⎟⎠ =

n⎛⎜⎝

1z12z1 · · · mz1

.

.

....

.

.

....

1zn2zn · · · mzn

⎞⎟⎠T

= az||(σ||(0), σ||(1), · · · , σ||(m − 1)) = n(

1z||, 2z||, · · · , mz||)

The transpose of the right side of the equation preserves thecomponent-wise transpose of the sequential data structure.z1, ..., zn are the particular states of the n parallel entities.σi(m − 1) = 0σ i · 1σ i · · · · · m−1σ i ∈ Mi is a word (trace)coding the sequence of m actions on Ai whereby eachaction consists of particular events which are simultane-ously occurring within the respective action. 0zi

1zi2zi · · · mzi

is the row vector of particular states of length m + 1 repre-senting the behavioral scenario of Ai on acting σi(m − 1).Correspondingly alike in case of A||. Obviously, the com-mutativity (Axiom 3) induces the isomorphism betweenAi ||Aj

∼= Aj ||Ai . Further, the neutral element (Axiom 4)induces the identical entity (identity) 1|| of the ABC upto isomorphism, 1||||Ai

∼= Ai ||1|| ∼= Ai . The idempotency(Axiom 5) even induces the idempotency up to isomor-phism, Ai ||Ai

∼= Ai .The properties of the ABC are also allowing to define

a rather topologically and statistically motivated behavioralrepresentation.6 For a given entity Ai , consider a (|Zi | +|�i |)-dimensional linear vector space. Then, the diagramin Fig. 15 represents a sequence 0σ i · 1σ i · · · · · kσ i andan induced behavioral scenario azi

1zi2zi · · · kzi

nzi in Ai ,which is in fact a trace in the corresponding linear vectorspace. With regard to the commutative diagram in Defi-nition 3 the ABC can be interpreted as the composition

6Like e.g., in case of the so called barcodes [10]

706 J Electron Test (2013) 29:697–714

and respectively decomposition of linear vector spacescomposing and respectively decomposing particular corre-sponding traces in each linear vector space. The fingerprintcode (FC) can be seen as a suitable histogram representa-tion for all kind of data based management, analysis andverification.

4.1.2 Complexity and Scalability

In the following, we discuss the properties of the formal-ism regarding to complexity. The monomorphic propertytogether with the associativity of the ABC warrant the ABCkernel to be realized as a non-hierarchic algorithm. Thisis an essential feature, since the algorithm can decide tostart to operate with favorable entities regarding to a costfunction, hence the ABC operation becomes easily tunablefor specific applications. In addition, the underlying com-mutativity is a big advantage, too, since the entities canalgorithmically get rearranged for the ABC such that theefficiency increases regarding to the specific quality struc-ture of the entities. The idempotency ensures the ABCto discard redundant information. Then again, the isomor-phism allows the entities to be designed for preservingsufficient information after de-composition.

4.2 Entity Design in Accordance with Test Principles

A test consists of the following principle: to setup the teststimuli and measure the outcome by meeting the conditionsfor testing, sourcing and further parametering. Evaluation ofthe measurement results has to be done with specified limits.

Table 3 4-valued logical operations

i a b b a ∧ b a ∨ b a∧b

0 0 0 1 0 0 1

1 0 ↗ ↘ 0 ↗ 1

2 0 1 0 0 1 1

3 0 ↘ ↗ 0 ↘ 1

4 ↗ 0 1 0 ↗ 1

5 ↗ ↗ ↘ ↗ ↗ ↘6 ↗ 1 0 ↗ 1 ↘7 ↗ ↘ ↗ 0 1 1

8 1 0 1 0 1 1

9 1 ↗ ↘ ↗ 1 ↘10 1 1 0 1 1 0

11 1 ↘ ↗ ↘ 1 ↗12 ↘ 0 1 0 ↘ 1

13 ↘ ↗ ↘ 0 1 1

14 ↘ 1 0 ↘ 1 ↗15 ↘ ↘ ↗ ↘ ↘ ↗

a

b

Fig. 16 Transition graph of input entity AS and AR

In view of the entity design, this principle leads to entitiesto be classified as resource, task and schedule. The resourcehas to generate test stimuli and to provide the unit undertest with stimuli. Hence, we need input entities classifiedas resource. The outcome depends on the internal task ofthe unit under test, hence we need output entities classifiedas task. Further, we need schedule entities, to specify theconditions.

In the following, we define the entities mentioned aboveand keep the data structures simple and sufficient to remainreasonable. For this, as a use case, we concentrate on thelow-active RS latch (Fig. 2).

4.2.1 4-valued NAND(∧)-Gates

Let B = {0, ↗, 1, ↘} be the set of the truth values for the4-valued logic. We declare 0, 1 as the (stable) extreme val-ues in the digital technology and ↗, ↘ as the (transient)intermediate values (called “from 0 to 1”, “from 1 to 0”).Thus, a sequence of assignments like 0 ↗ 1 ↘ 00 can

be represented as an impulse diagram

(...�

......�

......

)

J Electron Test (2013) 29:697–714 707

Table 4 State transition forAz1

az σaz,nz ⊆ 2�z1 nz

−{{

s1S, s1

z0, s0

z1, sall

}}0

−{{

s0S, s0

z0, s1

z1, sall

},{s0S, s1

z0, s1

z1, sall

},{s1S, s0

z0, s1

z1, sall

}}1

0{{

z10, z1s , z01, S1}}

0

0{{

z10, z1s , z0↘, S↘},{z10, z1s , z0↘, S1

},{z10, z1s , z01, S↘

}} ↗

↗ {{z1↗, z00, S0

},{z1↗, z00, S↗

},{z1↗, z00, S1

}, 1

{z1↗, z00, S↘

},{z1↗, z0↗, S↘

},{z1↗, z0↘, S↗

},

{z1↗, z0↗, S0

},{z1↗, z01, S0

},{z1↗, z0↘, S0

}}

1{{

z11, z1s , z00, S0},{z11, z1s , z00, S↗

},{z11, z1s , z00, S1

}, 1

{z11, z1s , z00, S↘

},{z11, z1s , z0↗, S↘

},{z11, z1s , z0↘, S↗

},

{z11, z1s , z0↗, S0

},{z11, z1s , z01, S0

},{z11, z1s , z0↘, S0

}}

1{{

z11, z1s , z0↗, S1},{z11, z1s , z0↗, S↗

},{z11, z1s , z01, S↗

}} ↘

↘ {{z1↘, z01, S1

}}0

exhibiting also the transient signal transitions. Hence, ↗↘means a 1-peak7 (�

...�), and ↘↗ means a 0-peak. Table 3shows the 4-valued logic operations NOT, AND, OR8 andNAND (∧).

4.2.2 Behavioral Principle for the Input and Output

For each input and output entity, respectively, it should beallowed to stay in the state 0 or 1 as long as possible.This means, that the states 0 and 1 have reflexive transi-tions. However, a change from high to low (↘) and fromlow to high (↗) has to be completed without delay. For asimple solution, this means, that the states ↘ and ↗ arenot provided with a reflexive transition. At this point, onecan consider non-symmetric transitions for ↘ and ↗, andfurther details, leading to more specific entity design.

4.2.3 Input Entities

In the following, we consider input entities, which canstay in 0 or 1 without any restriction. Further, the states↘ and ↗ have to be exited immediately (Fig. 16).For the input S this means, that the corresponding

7Which is observed e.g., by static 0-function-hazards8AND and OR are isomorphic to the Boolean lattice V = {0, p, q, 1}

entity AS has the reflexive transitions 0{S0} = 0 and1{S1} = 1, see Fig. 16a. The literals in {S0, S↗, S1, S↘} ={Sb|b ∈ B} are declared as “set S to b” with b ∈ B.If S exits 0, then the transition 0{Sc, S↗} =↗ is trig-gered. Sc means “value of S changes”, hence the hyperevent {Sc, S↗} says “S was in 0 and changes from 0to 1”. Then, S changes from ↗ into 1 immediately,↗ {S1} = 1. Correspondingly alike in case of 1 �→↘�→ 0:1{Sc, S↘} · {S0} =↘ {S0} = 0. Further, we provide theentity with an initial9 state − with two possible transitions

−{s0S, sall

}= 0 and −

{s1S, sall

}= 1. sall means “all vari-

ables are initialized”, s0S

means “set S initially to 0” and s1S

means “set S initially to 1”. Now, we have sufficient data tobuild the input entity AS = (

ZS, 2�S , zS,0, ZF S

)with ZS =

{−} ∪ B, �S ={sall , s

0S, s1

S, Sc, S0, S↗, S1, S↘

}, zS,0 = −

and ZFS = {0, 1}, see Fig. 16a. Similarly, the input entityof Boolean variable R is AR = (

ZR, 2�R , zR,0, ZFR

)with

ZR = {−} ∪ B, �R ={sall , s

0R, s1

R, Rc, R0, R↗, R1, R↘

},

zR,0 = − and ZFR = {0, 1}, see Fig. 16b. It shouldbe noticed, that the entity graphs of Fig. 16 are stronglylinked to their corresponding circuit structure of type-new(Fig. 5).

9Here, the literal - stays for the initial state, and should not be confusedwith the don’t care symbol.

708 J Electron Test (2013) 29:697–714

Fig. 17 Transition graph of taskentities Az1 and Az0 withhyper-edges (az, σ

az,nz, nz)

Table 5 State transition forAz0

az σaz,nz ⊆ 2�z0 nz

−{{

s1R, s1

z1, s0

z0, sall

}}0

−{{

s0R, s0

z1, s1

z0, sall

},{s0R, s1

z1, s1

z0, sall

},{s1R, s0

z1, s1

z0, sall

}}1

0{{

z00, z0s , z11, R1}}

0

0{{

z00, z0s , z1↘, R↘},{z00, z0s , z1↘, R1

},{z00, z0s , z11, R↘

}} ↗

↗ {{z0↗, z10, R0

},{z0↗, z10, R↗

},{z0↗, z10, R1

}, 1

{z0↗, z10, R↘

},{z0↗, z1↗, R↘

},{z0↗, z1↘, R↗

},

{z0↗, z1↗, R0

},{z0↗, z11, R0

},{z0↗, z1↘, R0

}}

1{{

z01, z0s , z10, R0},{z01, z0s , z10, R↗

},{z01, z0s , z10, R1

}, 1

{z01, z0s , z10, R↘

},{z01, z0s , z1↗, R↘

},{z01, z0s , z1↘, R↗

},

{z01, z0s , z1↗, R0

},{z01, z0s , z11, R0

},{z01, z0s , z1↘, R0

}}

1{{

z01, z0s , z1↗, R1},{z01, z0s , z1↗, R↗

},{z01, z0s , z11, R↗

}} ↘

↘ {{z0↘, z11, R1

}}0

4.2.4 Output Entities

The behavior of the output entity is subjected to the inputs

of the corresponding gate. As an example of ,

the behavior of z1 depends on (S, z0); e.g., (S, z0) =[↗, 1] assigns z1 = [↘] (Table 3). Hence, z1 stays in 0,if (S, z0) is assigned with [1,1]: 0{z10, z1s , z01, S1} = 0.z1s means “value of z1 is stable”, see Table 4. To changez1 from 0 to ↗ there are 3 possibilities for (S, z0):[↘, ↘] = {z10, z1s , z0↘, S↘} or [↘, 1] ={z10, z1s , z0↘, S1} or [1, ↘] = {z10, z1s , z01, S↘}.By this means, the transitions of z1 gets determined.Again, we provide the entity with an initial state−. Now, we have all data to build the output entityAz1 = (Zz1 , 2�z1 , zz1,0, ZFz1) with Zz1 = {−} ∪ B,�z1 = {

sall, s0z1

, s1z1

, z1s , z10, z1↗, z11, z1↘} ∪

{z00, z0↗, z01, z0↘, S0, S↗, S1, S↘}, zz1,0 = − andZFz1 = {0, 1}. Table 4 shows the state transitions accord-ing to σ ⊆ 2�z1 . Figure 17 shows its corresponding

transition graph. Similarly, the elementary circuit struc-

ture determines the corresponding output

entity Az0 = (Zz0 , 2�z0 , zz0,0, ZFz0) with Zz0 = {−} ∪ B,�z0 = {

sall , s0z0

, s1z0

, z0s , z00, z0↗, z01, z0↘} ∪ {z10,

z1↗, z11, z1↘, R0, R↗, R1, R↘}, zz0,0 = − andZFz0 = {0, 1}. Table 5 shows the state transitions accord-ing to σ ⊆ 2�z0 . Figure 17 shows its correspondingtransition graph. The entity graph of Fig. 17 is stronglylinked to its corresponding circuit structure of type-old(Fig. 5).

Table 6 State transitions of A|S|: −{z1s} = −, −{z0s} = −,−{z1s , z0s} = − and −�|S| = −az σ

az,nz ⊆ 2�|S| nz

−{{z1s}, {z0s}, {z1s , z0s}, �|S|

}−

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Table 7 State transitions of A|R|: −{z1s} = −, −{z0s} = −,−{z1s , z0s} = − and −�|R| = −az σ

az,nz ⊆ 2�|R| nz

−{{z1s}, {z0s}, {z1s , z0s}, �|R|

}−

4.2.5 Schedule Entities

The inputs (S, R) have to be set stable (0 or 1) aslong as at least one of the outputs (z1, z0) is not stable(↘ or ↗), and S and R are allowed to change (↘ or↗) if all the variables (z1, z0) are stable (0 or 1). Thiscondition is given by the hyper events {Sc, z1s , z0s} and{Rc, z1s , z0s}, respectively. We provide the entity with theinitial state −, too. Thus, the schedule entity of variable

S is A|S| =(Z|S|, 2�|S|, z|S|,0, ZF |S|

)with Z|S| = {−},

�|S| = {Sc, z1s , z0s}, z|S|,0 = − and ZF |S| = {−}. Table 6

shows the state transitions according to σ ⊆ 2�|S| . The statespace consists of a single state − ∈ Z|S| and four reflex-ive transitions (edges) and accordingly only one hyper-edge

(−, σ−,−, −), so . Similarly, the schedule entity

of variable R is A|R| =(Z|R|, 2�|R| , z|R|,0, ZF |R|

)with

Z|R| = {−}, �|R| = {Rc,z1s , z0s}, z|R|,0 = − andZF |R| = {−}. Table 7 shows the state transitions according

to σ ⊆ 2�|R| .

4.3 Example: ABC of the RS Latch

Now, all the necessary entities are defined to generate theABC-model of the RS latch, ARS = A|S|||A|R|||AS ||AR||Az1 ||Az0 . ARS exhibits 23 reachable states, 29 literals, 31sets of literals for triggering a transition, and 45 transitions.

4.3.1 Meta-stability

The request for states ∗ ∈ Z∗RS ⊆ ZRS with-

out successor state in ARS , formally Z∗RS ={∗ ∈ ZRS |�σ ∈ (

2�RS \ ∅)(∗σ ∈ ZRS)

},10 returns the fol-

lowing intermediate (meta-)state (−, −, ↗, ↗, ↘, ↘) ∈Z∗

RS . It codes that S and R are in the transient state ↗, andz1 and z0 are in the transient state ↘. Then, the next requestfor these transitions, which lead to a state ∗ ∈ Z∗

RS , returnsthe transition (z, σ, ∗) ∈ (

ZRS × (2�RS \ ∅) × Z∗

RS

)from z = (−, −, 0, 0, 1, 1) with σ = {Sc, S↗, Rc,

R↗, z1s , z11, z0s , z01} to ∗ = (−, −, ↗, ↗, ↘, ↘). z

10Verbalized: the state ∗ is in Z∗RS , if there is no hyper event σ defined

to trigger a transition ∗σ

Table 8 FSM B with undefined transition at i = 1

i Old state Input Output New state

z1 z0 x0 q0 z1 z0

0 0 0 0 0 1 0

1 0 0 1 0 * * Undefined

2 0 1 0 0 0 1

3 0 1 1 0 1 0

4 1 0 0 1 1 1

5 1 0 1 1 0 1

6 1 1 0 1 1 1

7 1 1 1 1 0 0

codes that S and R are in the stable state 0, and z1 andz0 are in the stable state 1. The dynamic edge σ codes,that the value of S and R change from 0 to 1 while thevalue of z1 and z0 stably stay in 1. Thus, according to(z, σ, ∗), the instability given in RS latch occurs, when thestate variables are assigned with [11] and the input vari-ables are simultaneously (at the same time) changing from[00] to [11].

5 Experimental Results

This section covers the synthesis process of partial FiniteState Machines (FSM) using RS latches. Compared with[40], in this paper, we provide detailed structuring andexplanation for a better understanding. To achieve this goalwe need specifications or implicit equations that can besplit into a Setup phase and a Store phase. By Setup wemean the preparation of the internal RS latch states, alllatches in question must be forced into meta-stability, Storemeans that we try to conserve this meta-stability.11 Westart off with a specification for a FSM B in form of truthtable b(Z, X, Q, Z), with the encoded sets Z = [z1z0],X = [x0] and Q = [q0], respectively, as shown inTable 8.

The critical sequence here is the transition for state z =[11] and x0 = [1] into state z = [00]. If x0 stays at [1] theFSM should show undefined behavior, if x0 changes to [0]the FSM continues with normal operation. This means thatassignment i = 7 is the Setup state while i = 1 is the Store.The graph for this FSM is shown in Fig. 18. It is importantto note that if the circuit somehow enters the regular statez = [00] then input x0 = [1] will not cause any randomswitches. It just stays in z = [00] as x0 = [1] stores thecurrent state.

11Here, “to conserve a meta-stability” does not apply to an analogmeta-stable signal but a digital meta-stable state

710 J Electron Test (2013) 29:697–714

Fig. 18 Graph of FSM in Table 8

5.1 Generation of Control Signals

The generation of the control signals is done using regu-lar methods with the exceptions mentioned above. For thisexample we need two RS latches FF0 and FF1. The truthtable Table 8 suggests the use of NOR-type latches as in thiscase the critical transition is from state z = [11] to z = [00].The reflexive transitions (0 → 0) and (1 → 1) in the FSMcan be achieved with different RS latch codings, store orreset for (0 → 0), store or set for (1 → 1). This ambigu-ousness can be used to reduce the corresponding Booleanequations.

For i = 7, the Setup state z = [11], we have toenter the Store state z = [00], i = 1, by applying(S, R) = [11] to both latches. Once the Store state z =[00] is entered it differs from a regular z = [00] stateas the internal states ZRS of the latches are forced intometa-stability. The subsequent Store command fails andthe internal states are forced back into a balanced state,zRS = [01] or zRS = [10]. The meta-stability is resolvedbased on current operating conditions and can not be pre-dicted. In Table 9 we show the mapping of state transitions

Table 10 Control signals

i FF1 FF0

S1 R1 S0 R0

0 1 0 0 1

1 0 0 0 0

2 0 0 0 0

3 1 0 0 1

4 0 0 1 0

5 0 1 1 0

6 0 0 1 0

7 1 1 1 1

to the control signals S0, R0, S1 and R1 under considera-tion of the boundary conditions for the assignments i = 1and i = 7.

Picking reasonable values for ambiguous values weget the final coding for the control signals (Table 10).From that we derive the control equations as follows:S1 = R0 = z1z0x0 ∨ z0x0, S0 = z1 and R1 = z1x0. There-fore the final circuit for the specified FSM B in Table 8 canbe implemented as shown in Fig. 19.

5.2 Instability and Oscillation Exhibited by the GivenCircuit Structure in Fig. 19

First the circuit in Fig. 19 has to be converted to NAND-onlyprimitives. Table 11 shows the elementary circuit struc-tures using NAND(∧)-gates, which after linking by namerealize the NAND representation of the given circuit inFig. 19.

As shown in Section 4, these elementary circuit struc-tures determine entities for input variable (Ax0 ), out-put variables (Ax0 , Az0 , Az1 , Ay5 , Ay1 , Ay3 , Ay4 , Ay5 , Ay2 ,

Ay7 , Ay6 , Ay8 , Az1 , Az0 ) and scheduling (A|x0|).

Table 9 Synthesis of controlsignals for FF0 and FF1 i Old state Input New state FF1 FF0

z1 z0 x0 z1 z0 S1 R1 S0 R0

0 0 0 0 1 0 1 0 0/0 1/0

1 0 0 1 * * 0 0 0 0 Store

2 0 1 0 0 1 0/0 1/0 0/1 0/0

3 0 1 1 1 0 1 0 0 1

4 1 0 0 1 1 0/1 0/0 1 0

5 1 0 1 0 1 0 1 1 0

6 1 1 0 1 1 0/1 0/0 0/1 0/0

7 1 1 1 0 0 1 1 1 1 Set

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Table 11 Elementary circuitstructures for realizing thecircuit in Fig. 19 usingNAND(∧)-gates

Table 12 State sequence inAB leading to instability x0 x0 z0 z1 y5 y1 y3 y4 y5 y2 y7 y6 y8 z1 z0

0 1 0 0 1 1 1 1 0 0 1 0 1 1 1

↗ ↘ 0 0 1 ↘ ↘ 1 0 0 1 0 1 1 1

1 0 0 0 1 0 0 1 ↗ ↗ 1 0 1 1 1

1 0 0 0 ↘ 0 0 1 1 1 ↘ 0 1 ↘ 1

Table 13 States sequence inAB leading to oscillation x0 x0 z0 z1 y5 y1 y3 y4 y5 y2 y7 y6 y8 z1 z0

0 1 0 1 1 1 1 1 0 1 0 0 1 0 1

↗ ↘ 0 1 1 1 ↘ 1 0 1 0 0 1 0 1

1 0 0 1 1 1 0 1 ↗ 1 0 0 1 0 1

Table 14 One oscillationperiod in AB

x0 x0 z0 z1 y5 y1 y3 y4 y5 y2 y7 y6 y8 z1 z0

1 0 0 1 1 1 0 1 ↗ 1 0 0 1 0 1

1 0 0 1 ↘ 1 0 1 1 1 0 0 1 0 1

1 0 0 1 0 1 0 1 1 1 ↗ ↗ 1 0 1

1 0 0 1 0 1 0 1 1 ↘ 1 1 ↘ 0 ↘1 0 ↗ 1 0 1 ↗ 1 1 0 1 1 0 ↗ 0

1 0 1 ↘ 0 ↘ 1 1 ↘ 0 1 1 0 1 0

1 0 1 0 ↗ 0 1 1 0 ↗ 1 1 ↗ 1 0

1 0 1 0 1 0 1 1 0 1 ↘ ↘ 1 ↘ 0

1 0 1 ↗ 1 ↗ 1 1 0 1 0 0 1 0 ↗1 0 ↘ 1 1 1 ↘ 1 0 1 0 0 1 0 1

1 0 0 1 1 1 0 1 ↗ 1 0 0 1 0 1

712 J Electron Test (2013) 29:697–714

5.2.1 Automata Based Composition (ABC)

To synthesize the overall circuit structure, termedB, the elementary circuit structures in Table 11 arecomposed using the composition operator || (Definition 3):AB = Ax0 ||Ax0 ||Az0 ||Az1 ||Ay5 ||Ay1 ||Ay3 ||Ay4 ||Ay5 ||Ay2 ||Ay7 ||Ay6 ||Ay8 ||Az1 ||Az0 ||A|x0|. AB exhibits 32 reachablestates, 106 literals, 36 sets of literals for triggering atransition, and 36 transitions.

5.2.2 Instability

Using the formalisms in Section 4.3 successively return thesequence of states in AB (Table 12) leading to instability inB by occurring of the last assignment row of variables inTable 12. Thus, according to Table 12, the instability givenin the circuit in Fig. 19 occurs, when the state variables areassigned with [11] and the input variable is changing from[0] to [1].

5.2.3 Oscillation

An oscillation in AB means a non-trivial cycle(zo

0, ..., zoi , ..., z

on

)whereas each state zo

i ∈ ZB \ ZFB inthe cycle is a non-final state. The request for such cyclesreturns an oscillation which is given in B. Table 13 showsthe state sequence leading to this cycle. Table 14 shows oneperiod of this cycle. Thus, according to Tables 13 and 14,the oscillation given in the circuit in Fig. 19 occurs, whenthe state variables are assigned with [01] and the inputvariable is changing from [0] to [1], which leads the statevariables periodically change from [01] to [10] and thenfrom [10] to [01], realizing an infinite sequence, while theinput variable is assigned with [1].

Fig. 19 Feedback circuit structure B for Table 8 with three intercon-nection networks, two function blocks and FF bank

Fig. 20 Simulation Results of the circuit in Fig. 19:Sequence until 60 ns, no oscillation (Fig. 18):

. At 60 ns weslightly change the voltage conditions and repeat theprocess: Sequence after 60 ns, oscillation (Fig. 18):

5.3 Simulation

The circuit in Fig. 19 has been designed and simulated ina 350 nm technology to verify that it features the unde-fined states we included during the synthesis process. Toachieve different operating conditions during simulation thesupply voltage domain for the feedback has been split up.This allows the modeling of different delays in the feed-back logic, resulting in different behavior during the Storeevent of the meta-stable state z = [00]. The simulation startswith a regular state z = [00], see Fig. 20. Input x0 = [1]keeps the circuit there until we create an x0 = [0] event at20 ns. This forces the circuit to step into state z = [10] andas we keep x0 = [0] even further into state z = [11]. At40 ns we force our circuit into the important state z = [00]by setting x0 = [1], which causes the unstable internalRS latches states zRS = [00]. With the applied voltagesduring this transition we get a new stable state z = [00] at46.6 ns which corresponds to the stable internal RS latchstates zRS = [01]. At 60 ns we slightly change the voltageconditions and repeat the process. At 120 ns we are againin state z = [11] however the circuit does not decide forz = [00] this time but for z = [01] at 126.7 ns, which corre-sponds to zRS = [01] for the first RS latch and zRS = [10]for the second latch. The circuit then proceeds normal oper-ation with cycling between z = [10] and z = [01] becausex0 stays at [1].

J Electron Test (2013) 29:697–714 713

6 Conclusion

With this work we have shown that it is possible to imple-ment a partially defined function—feedback digital circuitstructures—by utilizing the undefined analog behavior ofthe RS latch. We have presented the entities for modelingthese structures in a state transition graph and provided theunderlying methodology to compose graphs consistently atall. Results are given and show that we are able to detectinstabilities and oscillations inherent in digital feedbackstructures. Our novel formalism obviously allows for exten-sive investigations of this analog behavior in digital domain.In the computed example circuitry, we interestingly showthat one RS latch structure exhibits an instability while theother RS latch structure is responsible for maintaining anoscillation across part of the complete circuitry. Therefore,it should be possible to generate dedicated test sequences tocheck if these analog effects in digital design can be usedto digitally sensitize feedback structures and monitor analogparameters.

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Gurkan Uygur received his diploma degree in Computer Science(Diplom Informatik) from the University of Erlangen-Nuremberg in2006. He is a research assistant at the Institute for Reliable Circuitsand Systems, University of Erlangen-Nuremberg since 2006. Fieldsof activities include analysis and synthesis of discrete-event modelingfor hybrid, dynamic, asynchronous, concurrent systems, and optimiza-tion methods and resource management for verification and test ofintegrated circuits and systems.

Sebastian Sattler received the Dipl.-Ing. and Dr.-Ing., both in electri-cal engineering and computer science, from the Munich University ofTechnology in Germany, in 1989 and 1994, respectively. From 1996 to2009, he was at Infineon Semiconductor AG (former Siemens Semi-conductor AG) as CAD/CAT Engineer, Manager for Analog DesignFor Test, and Manager for Aquisition of Public Funding in Testing.Since 2009 he is head of the Institute for Reliable Circuits and Systemsat the University of Erlangen-Nuremberg, Germany.

He has been engaged in research and development on Analog &Mixed- Signal Design for Test applications and techniques, integratedinto SOC/SIP for communication and automotive systems. In thesefields, he has published about 60 papers and formed more than 30patents. In 2005, he received the German EDA Achievement Award.

His fields of activities include verification, production testing andlife time diagnosis for analog, mixed-signal and digital circuits andsystems.