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A NOVEL APPROACH FOR SYNTHESISING SINUS WAVEFORMS AT

POWER LEVEL

A THESIS SUBMITTED TO

THE GRADUATE SCHOOL OF NATURAL AND APPLIED SCIENCES

OF

THE MIDDLE EAST TECHNICAL UNIVERSITY

BY

SERKAN PAKİ ŞEDELE

IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF SCIENCE

IN

THE DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

JANUARY 2004

Approval of the Graduate School of Natural and Applied Sciences

________________

Prof.Dr. Canan ÖZGEN

Director

I certify that this thesis satisfies all the requirements as a thesis for the degree of

Master of Science.

___________________

Prof.Dr. Mübeccel DEMİREKLER

Head of Department

This is to certify that we have read this thesis and that in our opinion it is fully

adequate, in scope and quality, as a thesis for the degree of Master of Science.

_________________

Prof.Dr. H.Bülent ERTAN

Supervisor

Examining Committee Members

Prof. Dr. Muammer ERMİŞ (chairman) _____________________

Prof. Dr. H.Bülent ERTAN _____________________

Prof. Dr. Aydın ERSAK _____________________

Assist Prof. Dr. M. Timur AYDEMİR _____________________

Assist Prof. Dr. Ahmet M. HAVA _____________________

ABSTRACT

A NOVEL APPROACH FOR SYNTHESISING SINUS

WAVEFORMS AT POWER LEVEL

ŞEDELE, Serkan Paki

M.Sc., Department of Electrical and Electronics Engineering

Supervisor: Prof. Dr. H. Bülent ERTAN

January 2004, 142 pages

In variable speed motor drive and uninterruptible power supply (UPS)

applications, taditional method is to employ some kind of a modulation technique at

a high frequency typically 6 kHz to 20 kHz range. In these modulation techniques,

the switches are hard switched. The result is application of a series of pulses to the

load, and if the load is inductive, sine wave current flows into the load. Hard and

rapid switching causes a voltage waveform with a very high dv/dt (rate of change in

voltage) causing high EMI problems, reduced life expectancy of the motor and

additional losses. So a power supply generating pure sinusoidal voltage waveform is

very desirable. In industry some low pass filters called sinusoidal filters, are used at

the output of the inverters but this comes with additional cost and bulky filter

elements.

In this study, a novel approach for generating power level sinusoidal

waveforms is proposed. The basic structure is a DC-DC converter that produces a

iii

rectified DC-link at its output and an H-bridge inverter that inverts the rectified

sinusoids to form a sinusoidal voltage. Main advantages of the circuit are that the H-

bridge inverter switches have no switching stresses, they are switched at low

frequency so the reliability is increased.

Throughout the study different circuit topologies have been investigated and

the analysis of the chosen topologies is supported with computer simulations. The

system is then set up in the laboratory. In order to prove of the concept, only a single

phase inverter has been investigated at steady state conditions. Efficiency, distortion

level, magnitude error and device stresses have been obtained. The results indicate

that the proposed configuration is very promising.

Keywords: Pure Sinusoidal voltage waveform, complementary switching DC-DC

buck converter, rectified DC-link.

iv

ÖZ

GÜÇ SEVİYESİNDEKİ SİNÜS DALGA ŞEKİLLERİNİN

SENTEZLENMESİNDE YENİ BİR YAKLAŞIM

ŞEDELE, Serkan Paki

Yüksek Lisans, Elektrik Elektronik Mühendisliği Bölümü

Tez Danışmanı: Prof. Dr. H. Bülent ERTAN

Ocak 2004, 142 sayfa

Değişken hızlı motor sürücüleri ve kesintisiz güç kaynakları, kısaca “yüksek

frekanslı eviriciler”, çıkış gerilimini oluşturmak için hızlı anahtarlama yapabilen

transistörler (genellikle FET veya IGBT) kullanırlar. Bu anahtarlar çok ani açılıp

kapanırlar ve bu işlem açık ve kapalı olmak üzere iki durumdan oluşur ve ara

durumlar içermez. Bunun sonucu olarak bir dizi darbeden meydana gelen bir gerilim

oluşur ve de eğer yük endüktif ise motora sinüs dalga şekilli bir akım akar. Voltaj

geçişleri çok anidir. Bu ani anahtarlamalar çok yüksek dv/dt (gerilimdeki değişim

oranı) ye sahip olan bir gerilim dalga şekli meydana getirir ki bu da yüksek

elektromagnetik kirlilik, motor ömründe azalma ve ekstra kayıplara neden olur.

Bunlardan kurtulmak için motor sürücüleri ve güç kaynaklarının çıkışlarında saf

sinüs bir gerilim elde etmek gerekir.

Bu çalışmada sinüzoidal dalga şekilleri üretmek için yeni bir yaklaşım ortaya

atıldı. çıkışı saf sinüzoidal dalga şekilleri olan ve böylece yüksek frekanslı elemanları

v

ve dv/dt problemlerini ortadan kaldıran bir üreteç fikri ortaya atıldı. Önerilen devre

topolojisi iki bölümden oluşmaktadır. Giriş bölümü doğrultulmuş sinüs dalga

şekilleri üretmekte, çıkış ise bunları evirip sinüsoidal bir dalga şekli üretmektedir. Bu

tez çalışmasında değişik devre topolojileri araştırıldı ve seçilen topolojinin detaylı

dizyn prosedürü ve bilgisayar simülasyonu sunuldu. Ayrıca sistem labaratuvarda

kurularak çalıştırıldı ve teorik çalışmaların sonuçları deneylerle doğrulandı.

Anahtar Kelimeler: Saf sinüs dalga şekli, tamamlayıcı anhtarlayan DC-DC çevirici,

Doğrultulmuş Doğru Akım Barası.

vi

To My Family...

vii

ACKNOWLEDGEMENTS

I express sincere appreciation to my thesis supervisor Prof. Dr. H. Bülent

Ertan for his guidance throughout all stages of this study, which made it possible.

I would like to express my special thanks to Asst. Prof. M. Timur Aydemir

and Asst. Prof Ahmet M. Hava for their precious suggestions and for their

continuous encouragements during my studies.

I wish to thank to my roommates and my dear friends Cüneyt Karacan and

Tolga İnan for their deep understanding, suggestions and supports.

I also wish to thank Çağlar Hakkı Özyurt, Akın Acar, Erdal Bizkevelci, and

all Tübitak-Bilten Intelligent Energy Conversion Group staff for their support. My

special thanks also goes to Gökçen Baş for her deep support and possitivity.

Finally I thank to my father, mother, brother and grandmother for their

precious support and help against all difficulties.

viii

TABLE OF CONTENTS

ABSTRACT............................................................................................................... iii

ÖZ...............................................................................................................................v

ACKNOWLEDGMENTS..........................................................................................vii

TABLE OF CONTENTS............................................................................................ix

LIST OF TABLES.....................................................................................................xiii

LIST OF FIGURES...................................................................................................xiv

LIST OF SYMBOLS...............................................................................................xviii

CHAPTER

1 INTRODUCTION............................................................................................ 1

2 THEORETICAL STUDY................................................................................. 6

2.1 General Overview of the Proposed System................................................ 6

2.2 Output Stage (Inverter Stage).................................................................... 6

2.3 Input Stage ................................................................................................ 7

2.3.1 Determination of Suitable Topology for Input Stage..................... 7

2.3.2 DC-DC Converter Basics............................................................. 8

2.3.3 Step Down (Buck) Converter..........................................................9

2.3.3.1 Continuous Conduction Mode...................................... 10

2.3.3.1.1 Mode 1: switch is on....................................... 10

2.3.3.1.2 Mode 1: switch is off...................................... 11

2.3.3.1.3 Steady-State Analysis and Volt-Second Balance

on Inductor........................................................12

2.3.3.1.4 Output Voltage Ripple of Buck Converter for

Continuous Conduction Mode (Approximate

Analysis) .......................................................... 13

ix

2.3.3.2 Boundary between Continuous and Discontinuous

Conduction Modes...................................................... 15

2.3.3.3 Discontinuous Conduction Mode................................. 17

2.3.3.3.1 Subinterval 1: switch is on........................... 18

2.3.3.3.2 Subinterval 2: switch is off........................... 18

2.3.3.3.3 Subinterval 3: switch is off and inductor current

is 0.................................................................. 18

2.3.3.3.4 Steady-State Analysis and Volt-Second Balance

on Inductor..................................................... 19

2.3.3.3.5 Output Voltage Ripple of the Buck Converter

Operating in Discontinuous Conduction

Mode................................................................. 20

2.4 Combination of Input and Output Stages................................................... 23

2.4.1 Analysis of the Basic Topology In Terms of Operating

Conditions................................................................................... 24

2.4.2 Analysis of the Basic Topology In Terms of Load Types……….. 27

2.4.2.1 Feed Forward Control...................................................... 28

2.4.2.2 Closed Loop Control........................................................ 32

2.4.2.2.1 Determination of the Control Circuit Parameters

Used for Closed loop Operation………………………...32

2.4.3 Modified Circuit Topology........................................................... 39

3 DETERMINATION OF THE DC-DC CONVERTER PARAMETERS......... 43

3.1 Introduction................................................................................................. 43

3.2 Inductance Design....................................................................................... 44

3.2.1 Inductance Design Software........................................................... 46

3.2.2 Calculation of Lmax, Possible With the Selected Core and Specifying

the Inductance Value................................................................................ 50

3.2.3 Calculation of Winding Loss......................................................... 52

3.2.4 Calculation of Core Loss............................................................... 52

3.2.5 Thermal Analysis........................................................................... 53

3.2.5.1 Thermal Resistance Due to Radiative Heat Transfer….. 54

x

3.2.5.2 Thermal Resistance Due To Convective Heat Transfer. 55

3.2.5.3 Temperature Rise in the Inductor...........................….... 56

3.2.6 Specifying the Air gap Length....................................................... 57

3.3. Determination of the Capacitance (Value and type)…………………...... 60

4 HARDWARE AND SOFTWARE IMPLEMENTATION………………….. 62

4.1 Introduction………………………………………………………………. 62

4.2 Hardware…………………………………………………………………. 68

4.2.1 Power Stage of the Circuit……………………………………….. 69

4.2.2 Gate Driver and Protection Circuits……………………………… 71

4.2.3 Voltage Sensing Circuit…………………………………………. 74

4.2.4 The Controller .……………..…………………………………… 75

4.3 Software………………………………………………………………….. 77

4.4 Experimental Study and Verification of Theoretical Calculations………. 78

4.4.1 Experimental Results of Feed Forward Control Operation ……... 79

4.4.1.1 Experimental Results for No-Load Operation …............ 80

4.4.1.2 Experimental Results for Full load Operation ……........ 81

4.4.2 Experimental Results of Closed Loop Control Operation……….. 83

4.4.2.1 Experimental Results for No-Load Operation…………. 84

4.4.2.2 Experimental Results for Full load Operation…………. 85

4.4.3 Determination of the Level of the Minimum Achievable Voltage. 88

4.4.4 The Effect of Power Factor on Inverter Operation ……………. ..89

4.4.5 Stresses on the Semiconductor Switch……………………………92

4.4.6 Inductor Losses at 15000 Hz……………………………………...94

4.4.7 Sinusoidal Power Filters in the Market………………………….. 96

4.4.8 Conclusions………………………………………………………. 96

5 CONCLUSION……………………….……………………………………. 98

5.1 General……...…………………….……………………………………… 98

5.2 Experimental Results………………………………………………….. 100

5.3 Conclusion and Future Work…………………………………………… 101

xi

REFERENCES……………………………………………………………………103

APPENDIX A. DATA SHEETS OF THE COMPONENTS AND FULL PROGRAM

CODES…………………………………………………………..105

A.1 Flow Charts and Source Codes Written in C language..........................106

A.2 Source Code of The Inductor Design Software.......................................114

A.3 Data Sheets of the Components...............................................................115

A.4 Simulation model……………………………………………………….127

A.5 Determination of Suitable Topology for the Output Stage..................... 128

A.5.1 Full Controlled Bridge Inverters................................................. 128

A.5.1.1 Topology One of the Full Controlled Bridge Inverter.. 129

A.5.1.2 Topology Two of the Full Controlled Bridge Inverter..129

A.5.1.3 Topology Three of the Full Controlled Bridge Inverter130

A.5.1.4 Topology Four of the Full Controlled Bridge Inverter..131

A.5.1.5 Topology Five of the Full Controlled Bridge Inverter..134

A.6 Sinusoidal Filters Available in the Market…………………………….. 138

xii

LIST OF TABLES TABLE 3.1 Properties of Ferrite E shaped cores for medium power applications........ 44

3.2 Coefficients applied to core loss formula……………………………....... 52

4.1 Performance Analysis for Feed Forward Control Operation…………….. 83

4.2 Performance Analysis for Closed Control Operation……………………. 87

4.3 Performance Analysis at different Load power factor values…………… 92

4.4 Expected and Measured Efficiency Values for Closed Loop Control

Operation…............................................................................................ 95

4.5 Physical Dimensions of the filter Inductors……………………………… 96

xiii

LIST OF FIGURES FIGURES

1.1 Full-rectified sinusoids…………………………………………................4

1.2 Sinusoidal waveform inverted from full-rectified sinusoids…………….. 5

2.1 Full controlled H-Bridge inverter with back diodes (output stage)..……. 7

2.2 Output of the input stage……………………………………………….. 7

2.3 Step Down (Buck) converter…………………………………………… 9

2.4 Buck converter waveforms and circuit states………………………… 10

2.5 Equivalent circuit for switch is on……………………………………… 10

2.6 Equivalent circuit for switch is off……………………………………… 11

2.7 Inductor voltage........................................................................................ 13

2.8 Actual Output Voltage Waveform of a Buck Converter.......................... 13

2.9 inductor current ripple(stored charge)..................................................... 14

2.10 Inductor voltage and current waveforms at the boundary of continuous and

discontinuous conduction........................................................................ 15

2.11 Converter characteristics with duty-cycle and load.................................. 16

2.12 vL and iL waveforms with discontinuous conduction.............................. 17

2.13 Switch is on (discontinuous conduction).................................................. 18

2.14 Switch is off (discontinuous conduction)................................................. 18

2.15 Switch is off, Inductor current is 0 (discontinuous conduction)............... 18

2.16 Converter characteristics with discontinuous conduction........................ 20

2.17 Capacitor current waveform (stored charge)............................................ 20

2.18 Inductance current waveform for discontinuous conduction mode.......... 21

2.19 Basic circuit diagram of the overall system.............................................. 24

2.20 Circuit diagram for open loop analysis..................................................... 28

2.21 Output voltage for full resistive load with open loop control................... 29

xiv

2.22 Harmonic Spectrum of the output voltage (open loop control, resistive

load)......................................................................................................... 29

2.23 Output voltage for inductive load with open loop control........................ 30

2.24 Harmonic spectrum of the output voltage (open loop control, inductive

load)......................................................................................................... 30

2.25 Buck converter inductor current for inductive load (open loop).............. 31

2.26 Buck converter inductor current for inductive load (open loop,

magnified)................................................................................................ 31

2.27 Circuit diagram for closed loop analysis……………………………… 32

2.28 Type 2 compensated error amplifier (PI Controller)…............................ 33

2.29 Frequency response of the uncompensated system…………………….. 34

2.30 Output voltage for full resistive load with closed loop control………… 35

2.31 Harmonic Spectrum of the output voltage (closed loop control, resistive

load)…………………………………………………………………… 35

2.32 Output voltage for inductive load with closed loop control......................36

2.33 Output current for inductive load with closed loop control..................... 36

2.34 Harmonic Spectrum of the output voltage and current (closed loop

control, inductive load)………………………………………………… 37

2.35 Output voltage and gate signal of the buck converter...............................38

2.36 Modified Circuit Topology....................................................................... 39

2.37 Output voltage and load current for inductive load with closed loop

control...................................................................................................... 40

2.38 Harmonic Spectrum of output voltage and load current for inductive load

with closed loop control........................................................................ .. 41

2.39 Inductance current (modified topology)).................................................. 41

2.40 Inductance current (magnified version of Fig.2.60) (modified topology).42

3.1 Conventional Buck Converter.....................................................................43

3.2 Complementary Switching Buck Converter............................................... 44

3.3 Inductor current over one period.................................................................47

3.4 Saturation flux density vs. temperature for P Material............................... 48

3.5 Area Productand maximum inductance current vs.inductance................... 49

3.6 Area Productand maximum inductance current vs.inductance (magnified)49

xv

3.7 Area Product and Irms versus Inductance………………........................... 50

3.8 Fringing fields in the air-gap of an inductor (a), effective cross-sectional

area of the gap (b)………………..................................................................... 57

3.9 Double E-core, its bobbin and an assembled inductor ………………...... 58

3.10 Capacitance vs. Duty cycle for ∆Vo = 7V……………………………… 61

4.1 Block diagram of the hardware setup......................................................... 63

4.2 Input DC link and Filter Capacitors............................................................ 64

4.3.DC-DC Converter Power Stage (2MBI50N120 IGBT and Snubber

Capacitance)...................................................................................................... 64

4.4 Output Inverter Power Stage (IRF 740 Mosfets)........................................ 65

4.5 DC-DC Converter IGBT Gate Drivers and Protection Circuit…………... 65

4.6 Output Inverter Mosfet Gate Driver Circuit............................................... 66

4.7 Voltage Sensing Circuit……………………….......................................... 66

4.8 TMS320LF2407A DSP Controller Circuit................................................. 67

4.9 Experiment Setup........................................................................................ 67

4.10 Experiment Setup….................................................................................. 68

4.11 Power Stage of the Circuit........................................................................ 69

4.12 Circuit schematic of the protection and gate driver circuit...................... 73

4.13 Connection of the Voltage Sensing Circuit ……………………………. 74

4.14 Schematic of the voltage Sensing Circuit ……………………………… 75

4.15 Basic flow-chart of the software for feed-forward control …………….. 77

4.16 Basic flow-chart of the software for closed loop control ……………… 78

4.17 Rectified DC-link (upper waveform) and load voltages (lower waveform)

at 10 Hz. ……………………………………………………………….. 80


at 50 Hz ………………………………………………………………. 80


at 100 Hz……………………………………………………………… 81


at 10 Hz ……………………………………………………………… 81


at 50 Hz……………………………………………………………. 82

xvi


at 100 Hz ………………………………………………………………. 82


at 10 Hz.……………………………………………………………….. 84


at 50 Hz ………… ……………………………………………………. 84


at 100 Hz ………………………………………………………………. 85


at 10 Hz ……………………………………………………………… 85


at 50 Hz ……………………………………………………………….. 86


at 100 Hz …………………………………………………................... 86

4.29 Input DC-Link capacitor current……………………………………….. 87

4.30 Constant V/f operation for 5 Hz. Upper waveform is load voltage and the

lower one is rectified DC-link voltage ……………………………… 88

4.31 Constant V/f operation for 10 Hz.Upper waveform is load voltage and the

lower one is rectified DC-link voltage ………………………………. 88

4.32 Load Voltage and current at 1 kVA with pf = 0……………………… 90

4.33 Load Voltage and current at 1 kVA with pf = 0 …………………….. 90

4.34 Load Voltage and current at 1 kVA with pf = 0.8. ……………………. 91

4.35 Load Voltage and current at 1 kVA with pf = 1………………............ .. 91

4.36 Voltage and Current on the DC-DC converter IGBT ………………….. 92

4.37 IGBT Current for full load (1 kVA) at pf = 1…………………………... 93

4.38 IGBT Current for full load (1 kVA) at pf = 0.8……………………….... 93

4.39 Turn on and turn off characteristics of the DC-DC converter

IGBT ………………………………………………………………… . 94

A.1 Flow Chart of the main program for open loop control………………. 106

A.2 Flow Chart of the interrupt service routine for open loop control…….. 107

A.3 Flow Chart of the main program for closed loop control……………... 108

A.4 Flow Chart of the interrupt service routine for closed loop control…… 109

xvii

A.5 Simulation Model.................................................................................... 127

A.6 First topology consists of four tyristors ………………………………..129

A.7 Four anti-parallel diodes are added to topology one …………………...129

A.8 Third topology consists of two tyristors and two transistors ………….. 130

A.9 T1 and TR2 are turned on ………………………………………………130

A.10 Load current closes its path through D2……………………………….131

A.11 Fourth topology consists of four transistors………………………… 132

A.12 Anti-parallel diodes connected to topology shown in figure A.11…… 132

A.13 TR1 and TR4 are on……………………………………………………132

A.14 D2 and D3 are on…………………………………………………….. 133

A.15 TR2 and TR3 are on……………………………………………………133

A.16 D1 and D4 are on………………………………………………………134

A.17 Theoretical voltage and current waveforms indicating the operation

modes for inductive load …………………………………………….134

A.18 Fifth topology consists of two transistors, two capacitors at the input 135

A.19 TR1 is on……………………………………………………………….135

A.20 D2 is on……………………………………………………………… 136

A.21 TR2 is on……………………………………………………………….136

A.22 D1 is on……………………………………………………………… 136

A.23 Theoretical voltage and current waveforms indicating the operation

modes for inductive load……………………………………………..137

xviii

LIST OF SYMBOLS

Vd DC-DC Converter input voltage

Vo DC-DC Converter output voltage

VL DC-DC Converter inductance voltage

iL DC-DC Converter inductance current

ton Turn-on duration of the switch of the DC-DC Converter

toff Turn-off duration of the switch of the DC-DC Converter

Ts Switching period of the switch of the DC-DC Converter

fs Switching frequency

D Duty cycle

∆V DC-DC Converter output voltage ripple

∆Q Stored charge on DC-DC Converter output capacitor

fc Cut-off frequency

ILB Average inductor current at boundry

IoB DC-DC converter output current at boundry

L DC-DC Converter filter inductance

C DC-DC Converter ∧

I Maximum inductance current

N Number of turns ∧

Φ Peak flux in the inductor

kcu Winding factor

Aw effective winding area

Acu Conductor area.

Acore effective core area ∧

B Maximum flux density

xix

Irms rms value of the inductor current

Jrms rms current density

Zo DC-DC converter output impedance

AP Area Product

Bsat Saturation flux density

PCu Copper loss

Pcore Core loss

Vcore core volume

Rθsa Surface-to-ambient thermal resistance

Rθ,rad Radiative thermal resistance

Rθ,conv Convective thermal resistance

Prad Radiated power

Pconv Heat power lost via convection

lc Magnetic flux path length in the core material

Rm Total reluctance of the magnetic flux path

xx

CHAPTER 1

INTRODUCTION

In variable-speed ac drives which utilize voltage-fed inverters, control of the

voltage and frequency output of the inverter feeding the ac motor is essential for

torque and speed control of the motor. Similarly in ac power supplies which utilize

uninterruptible power supplies, again control of the output voltage and frequency of

the supply feeding the load is essential for supplying regulated voltage to the load

without any distortion. The early approach has been to use a voltage-fed square wave

inverter fed by a variable DC voltage source. Variable DC voltage is required since

the only way to change the fundamental voltage of a square-wave inverter is to

change its amplitude. The variable DC-link voltage is obtained from a phase-

controlled rectifier. This system has a big drawback. The output of a square-wave

inverter contains high-amplitude low frequency harmonics. Therefore, the losses of a

motor (in the case of a motor drive application) due to the resulting harmonic

currents tend to be high.

With the recent developments in power electronic devices and controller

circuits, different techniques have been developed called Pulse-Width Modulation

(PWM) techniques, which carry the harmonics of the output voltage to higher

frequency levels eliminating lower order harmonics. Also these techniques make

possible both voltage and frequency control within the inverter itself. There are some

advantages of these techniques. First, a variable DC-link is not essential. A PWM

1

inverter is usually fed by an uncontrolled diode bridge rectifier. Secondly, high

amplitude low frequency harmonics are eliminated.

Various PWM strategies have been introduced for controlling inverters. The

common principle in all these strategies is to introduce notches in the basic square-

wave pole voltage, such that the resulting periodic waveform has the desired

fundamental frequency and amplitude. [1]

PWM techniques can be classified into the following categories:

• Square-wave modulation

• The sampling method

• Optimized PWM

• Selected Harmonic Elimination

• Delta Modulation

• Space-vector based PWM

Beside the advantages of the PWM techniques, some drawbacks occur with

the increasing frequency levels. The switches in the inverter are rapidly switched and

are either turned hard ON or OFF with no in between state. The result is that the sine

wave current is generated if the load is inductive by using pulse width modulated

switching. However as discussed before the voltage wave form is a series of pulses

in the output of the inverter, and the voltage transitions are very rapid. This rapid

switching causes a voltage waveform with a very high dv/dt (rate of change in

voltage).

In recent studies it has been proven that these pulses introduce some

additional drawbacks to the system. First, the losses especially copper and core

losses are increased. Secondly, in motor drive applications motors have parasitic

capacitances of the electrically conducting components with respect to the ground

potential. If the available DC voltage is chopped in the inverter, then, during the

potential jumps of the voltage, considerable pulse currents flow across the parasitic

capacitance’s to the earth. If the grounding of the motor is inadequate, the potentials

2

at the parasitic capacitances increase sharply. The values of the bearing currents also

increase massively, and flow fully through the bearings to the earth. In that case, the

life expectancy of the ball bearings, and hence of the entire motor is reduced. Also

the insulation of the motor is affected by these pulses. Thirdly, even the load current

is sinusoidal, high dv/dt can cause high radiated energy causing EMC problems as

well.

Under these circumstances, synthesizing a pure sinusoidal waveform at the

output of the inverter seems to be an important concept and demand in order to

further increase the performance of inverter-load systems.

With the developments in power electronic devices and magnetic materials a

novel idea is proposed by the supervisor of this thesis in order to synthesize pure

sinusoidal waveform. Basic idea is a DC-DC converter which can track a high

frequency sinusoidal reference and create a DC bus of rectified sinusoids at desired

frequency as shown in figure 1.1. By inverting the rectified sinusoids at the DC-DC

converter’s output, a pure sinusoidal output voltage can be obtained as shown in

figure 1.2. An added advantage of this technique is that the input current can be also

made sinusoidal without additional cost. Hence, injection of harmonic currents to the

mains can be avoided.

Throughout this thesis study, proper topologies for DC-DC converter and

the inverter part are analyzed in detail. Necessary basic theoretical information is

given about the selected topologies. Some modifications made on topologies in order

to improve the performance. Also detailed design procedures are given for the

magnetic parts. Practical results are obtained in the laboratory environment.

Second chapter includes the choice of the best topologies necessary for the

proposed idea. In this section some candidate topologies are examined and the

chosen topologies are supplied with detailed theoretical background information.

Also this chapter includes the integration of chosen topologies and computer

3

simulations. The modifications on the topologies and further computer simulations

including different control approaches are given in chapter 2 as well.

In chapter 3, determination of DC-DC converter parameters are examined.

This is followed by an evoluation of how the output filter parameters L, and C should

be chosen.The inductance value and size minimization is specially emphasized,

which has a vital role in our application. A computer program is developed in order

to calculate the proper value of the inductor depending on the current and size

parameters. Then thermal analysis of the inductor is given in order to guarantee the

operation.

Chapter 4 includes the practical implementation of the proposed system. The

hardware and control software are introduced in this chapter. Also detailed

experimental results are given in this chapter.

Finally conclusions and proposals for future studies are given in chapter 5.

Fig.1.1 Full-rectified sinusoids

4

Figure.1.2 Sinusoidal waveform inverted from full-rectified sinusoids

5

CHAPTER 2

THEORETICAL STUDY

2.1 General Overview of the Proposed System

In chapter 1 the problem has been defined. As discussed in the introduction,

the overall system is supposed to be composed of two discrete stages that are the

input stage which generates rectified sinusoidal voltages in other words which

produces a DC- link has a voltage waveform of rectified sinusoids that can be called

as “Rectified DC-Link”. And the output stage that forms the sinusoidal output

voltage from the rectified sinusoids in other words inverts the rectified sinusoids of

the output of the first stage.

In this chapter, first of all the suitable circuit topologies for input and output

stages are reviewed and analyzed.

Subsequently, integration of two discrete stages will be analyzed. At that

section the drawbacks of the proposed basic circuit configuration will be given.

Consequently the modifications proposed on the circuit topology and their

effects on the performance are investigated. Also detailed computer simulations of

the resultant circuit will be examined.

2.2 Output Stage (Inverter Stage)

The inversion capabilities of different topologies, under two types of load

6

(purely resistive, inductive), are examined and detailed mode by mode analysis are

given in Appendix A5. The chosen topology is given below

Figure 2.1 Full controlled H-Bridge inverter with back diodes (output stage)

2.3 Input Stage

In this section, the best and feasible topology for the input stage is determined

and analyzed in detail.

2.3.1 Determination of Suitable Topology for the Input Stage

The input of the input stage is a constant DC bus voltage, and the output

should be rectified sinusoidal voltage as shown in figure 2.2. Also the frequency and

the magnitude of the output voltage should be variable. The output of this circuit is

called as “Rectified DC-Link”

Figure 2.2 Output of the input stage (Rectified DC-Link voltage)

7

The waveform shown in figure 2.2 is a variable DC voltage waveform. So it

can be said that both the input and the output of the circuit is DC quantities.

Consequently a DC-DC converter will be suitable for the application. But

contrary to conventional operation of a DC-DC converter which operates in steady-

state, the operation must be always in transient region for the proposed application.

In another words, DC-DC converter should be operated to track a rectified sinusoidal

reference voltage, but not a constant one as usual.

Due to its simplicity and linearity, in this thesis, a DC-DC step down (buck)

converter is chosen as the input stage of the overall topology. It has the advantage of

linear input output voltage relation and also has the ability of control the voltage

down to 0 volts as well. Detailed information about DC-DC converters focusing on

the step down (buck) type is given in the next section.

2.3.2 DC-DC Converter Basics

A DC-to-DC converter is a device that accepts a DC input voltage and

produces a DC output voltage. Typically the output produced is at a different voltage

level than the input.[2,3]

Two alternatives for delivery of electric power from a dc source to a load in a

controllable manner are linear and switched mode power conversion.

Linear power conversion relies on the presence of a series linear element,

especially a semiconductor device used in the linear region such that the total load

current passes through the linear element. Therefore, the greater the difference

between the input and the output voltages, the more power is lost in the element. So

this type of conversion is very dissipative and inefficient.

In switched mode power conversion, the controlling device is a switch which

is either closed or open. By controlling the duty cycle, the power flow to the load can

be controlled in a very efficient way. The only losses may be the element losses(

semiconductor, inductor and capacitor). However, the output voltage is not a pure dc

8

as in the linear case, and pulsed power is delivered to the load. The power flow to the

load may be easily smoothed out by implementing a low-pass LC filter.

2.3.3 Step Down (Buck) Converter

The basics of the single quadrant buck converter is given in [2,3] in detail. In

this section only brief information and necessary equations are given also some

equations which are not available in the literature such as output voltage ripple

equations for discontinuous conduction mode.

The simplest configuration of the converter is given in the figure 2.3 below.

Figure2.3 Step Down (Buck) converter

During 0 < t < ton, voltage across the inductor L is Vd – Vo; iL rises to ILmax.

During ton < t < Ts, voltage across the inductor L is –Vo, and iL falls to ILmin. In the

steady state, the inductor current must return to ILmin at the end of the switching

period Ts, and the integral of the inductor voltage (i.e., the dc voltage supported

across the inductor) must be zero. In the following we assume that the output voltage

ripple is negligible.

Depending on the inductor current waveform, the operation of the step down

(buck) converter will be examined in 2 different modes. These are:

• Continuous Conduction Mode

• Discontinuous Conduction Mode

9

2.3.3.1 Continuous Conduction Mode

For continuous conduction mode of operation, there are two circuit states as

shown in figure 2.4. The circuit is analyzed mode-by-mode for continuous

conduction mode.

Figure 2.4. Buck converter waveforms and circuit states

2.3.3.1.1 Mode 1: switch is on

The equivalent circuit diagram is shown in Figure2.5

Figure 2.5 Equivalent circuit for switch is on

10

Inductor voltage

vL(t) = Vd – vo(t) 2.1

Small ripple approximation

vL(t) ≈ Vd – Vo 2.2

Knowing the inductor voltage, now the inductor current can be found via

Faraday’s Law

( ) ( )dt

tdiLtv L

L = 2.3

Solve for the slope of the inductor current:

( ) ( )L

VVL

tvdt

tdi odLL −≈= 2.4

2.3.3.1.2 Mode 2: switch is off

The equivalent circuit diagram is shown in Figure2.6

Figure 2.6.Equivalent circuit for switch is off

Inductor voltage

vL(t) = – vo(t) 2.5

Small ripple approximation

vL(t) ≈ – Vo 2.6

Knowing the inductor voltage, we can again find the inductor current via

11

( ) ( ) ( )L

Vdt

tdidt

tdiLtv oLL

L −≈⇒= 2.7

2.3.3.1.3 Steady-State Analysis and Volt-Second Balance on Inductor

From Faraday’s law for the inductor voltage,

( ) ( )dt

tdiLtv L

L = 2.8

Integrating over one complete switching period:

( ) ( ) ( )∫=− sT

LLsL dttvL

iTi0

10 2.9

In periodic steady state, the net change in inductor current is zero

( )∫=sT

L dttv0

0 2.10

Hence, the total area (or volt-seconds) under the inductor voltage waveform,

shown in figure 2.7, is zero whenever the converter operates in steady state. An

equivalent form

( ) L

T

Ls

vdttvT

s == ∫010 2.11

The average inductor voltage for one cycle is zero at steady state. Using this

statement and figure 2.7

(Vd – Vo) D Ts = Vd (1-D) Ts ⇒ DVV

d

o = 2.12

Eq 2.12 equation is called the conversion ratio equation for continuous

conduction mode.

12

Figure 2.7. Inductor voltage

In ideal cases, voltage control range of a buck converter operating in

continuous conduction mode, is from 0 V to Vd.

2.3.3.1.4 Output Voltage Ripple of Buck Converter for Continuous

Conduction Mode (Approximate Analysis)

Actually the output of a buck converter is not a pure DC voltage. It has a

small ripple on a DC component as shown in figure 2.8. In order to calculate the

switching output voltage ripple ∆V, it is assumed that the inductor current ripple ∆iL

flows into the output capacitor to generate the voltage ripple. The total voltage ripple

∆V is obtained from the stored charge ∆Q, which is the area under inductor current

ripple as shown in figure 2.9

Figure 2.8. Actual Output Voltage Waveform of a Buck Converter

13

Figure 2.9. inductor current ripple(stored charge)

Hence,

∆Q = LL iTs

iTs∆=

∆81

2221 , 2.13

∆VO = CC

Q 1=

∆LiTs∆

81 , 2.14

∆iL = TsDL

Vo )1( − 2.15

OV∆ = TsDL

VoC

Ts )1(8

− ⇒ 2

2 )1(81)1(

81

s

O

LCfD

LCDTs

VoV −

=−

=∆

2.16

Eq. 2.16 can also be expressed in terms of switching and cut-off frequencies as,

22

)1(2

−=

∆fsfcD

VoVO π 2.17

where fs = 1/Ts and

LCfc

π21

= 2.18

14

The output voltage ripple can be minimized if fs >> fc. Also it is obviously

seen that the output voltage ripple of a buck converter operating in continuous

conduction mode, is independent from load. It is only a function of constant

parameters such as L, C, fs, and D.

2.3.3.2 Boundary between Continuous and Discontinuous Conduction Modes

In this section, the boundary condition for the inductor current is investigated.

Figure 2.10 shows this condition for inductor current and voltage.

Figure 2.10. Inductor voltage and current waveforms at the boundary of continuous

and discontinuous conduction.

From figure 2.10, average inductor current ILB, where subscript B refers to the

boundary, is found as a function of duty cycle as,

oBonOd

LLB ItL

VViI =

−==

21

21

max 2.19

( ) ( ) ( )L

DDVTDVV

LDT

VVL

DT dsdd

sOd

s

21

22−

=−=−= 2.20

ILB becomes maximum when D = 0.5 (this is found by differentiating ILB with

respect to D and equating the derivative to zero). For D = 0.5,

15

LVT

I dsLB 8max = 2.21

And,

( )DDII LBLB −= 14 max 2.22

Using Eq. 2.21 and 2.22 ILB loci for duty cycles between 0-1 can be plotted as

shown in figure 2.11

Figure 2.11.Converter characteristics with duty-cycle and load

During normal operation, ILB should be smaller than the lowest load current,

so that the converter operates in continuous conduction mode (i.e., in the linear mode

with Vo = DVd). The minimum inductance L and the switching frequency fs for this

condition of operation are obtained from the following consideration. In periodic

steady state, the net change in inductor current is zero

( )

( )0

00== ∫∫

ss TT L didtLv

2.23

( ) 01 =−−−

so

sod TD

LV

DTL

VV 2.24

The first term in Eq.2.24 is .iL (rise) and the second term is .iL (fall). For a given load

resistance R,

16

( ) sooLo

L TDL

VR

ViR

Vi −+=

∆+= 1

22max 2.25

( ) sooLo

L TDL

VR

ViR

Vi −−=

∆−= 1

22min 2.26

At the boundary of continuous-discontinuous conduction, iLmin = 0, so that

( ) ( )2

1min

RDLf s−

= 2.27

Hence, for continuous conduction,

( )2

1 RDLf s−

≥ 2.28

2.3.3.3 Discontinuous Conduction Mode

In practice load current may change over a wide range, from no load to full

load. Increase of load resistance leads to a decrease of load current. Hence a new

operation region is encountered, termed discontinuous conduction mode. The load

current and consequently the inductor current cheases before the next cycle begins.

Inductor current and voltage waveform is shown in figure 2.12.

Figure 2.12 vL and iL waveforms with discontinuous conduction.

17

For discontinuous conduction mode of operation, there are three circuit states

as shown in figure 2.13, 2.14, and 2.15.

2.3.3.3.1 Subinterval 1: switch is on

Figure 2.13 Switch is on (discontinuous conduction)

2.3.3.3.2 Subinterval 2: switch is off

Figure 2.14 Switch is off (discontinuous conduction)

2.3.3.3.3 Subinterval 3: switch is off and inductor current is 0

Figure 2.15 Switch is off, Inductor current is 0 (discontinuous conduction)

18

2.3.3.3.4 Steady-State Analysis and Volt-Second Balance on Inductor

The average inductor voltage for one cycle is zero at steady state. Using this

statement and Fig 2.12

( ) 01 =∆−− sosod TVDTVV 2.29

Thus input output voltage relationship becomes

1∆+=

DD

VV

d

o 2.30

Where . Now 11 <∆+D

so

L TL

V1max ∆=i 2.31

And,

s

sL

sL

o T

Ti

DTi

I

∆

+=

221

maxmax ( )2

1max

∆+=

DiL 2.32

Using Eq.2.31

21 1∆+∆=

DT

LV

so 2.33

Using Eq.2.30

21

11

∆+×∆×

∆+=

DT

DD

LV

sd 2.34

12∆= DT

LV

sd 2.35

Using Eq. 2.21

1max4 ∆= DI LB 2.36

DII

LB

o

max1 4=∆ 2.37

19

Using Eq.2.30

( )max2

2

/41

LBod

o

IID

DVV

+= 2.38

Figure 2.16 Converter characteristics with discontinuous conduction.

Note that Vo falls sharply with load when the inductor current is

discontinuous. Note also that with discontinuous conduction, the Vo/Vd ratio

becomes higher than D, implying loss of voltage gain of the converter.

2.3.3.3.5 Output Voltage Ripple of the Buck Converter Operating in

Discontinuous Conduction Mode

The same approach followed for Continuous Conduction mode of operation

is applicable for discontinuous conduction mode of operation. The total voltage

ripple ∆V is obtained from the stored charge ∆Q, which is the area under inductor

current ripple as shown in figure 2.17

Figure 2.17. Capacitor current waveform (stored charge)

20

∆Q = C ∆Vo = 2

)( Opeak IIt − 2.39

(Ipeak – Io) = ( ) ( )

LLIDTVV

IL

DTVV OOSO

Os −−=

−

− 2.40

Time t can be calculated from inductance current waveform given in figure 2.18

Figure 2.18 Inductance current waveform for discontinuous conduction mode

32 ttt += , 2.41

And

12 tDTt −= 2.42

By using the slope of the inductance current for t < t2

OOS It

LVV

=

−1 2.43

Yields,

−

=Os

O

VVLI

t1 2.44

Thus using Eq. 2.42

21

−

−=OS

O

VVI

DTt2 2.45

On the other hand using the slope of the inductance current waveform for t > t3,

OO

peak IL

VtI =− 3 2.46

Ipeak can be expressed as,

OOOS IL

VtDT

LVV

=−

−3 2.47

Therefore,

O

O

O

OS

VLI

DTV

VVt −

−=3 2.48

Using Eqs. 2.42, 2.44 and 2.48 in Eq. 2.41 yields,

( )O

O

O

OS

OS

O

VLI

DTV

VVVVLI

DTt −

−+

−

−= 2.49

Finally using Eq.2.49 in Eq.2.39 gives

( )[ ] ( ) ( ) ( )( )[ ][ ]( )

−

−−−+−−−−=∆

OSO

OOSOSOOOOSOOSO VVLV

LIVVDTVVVLIVVVDTLIVVDTVC

2 2.50

Thus the output voltage ripple is expressed as

( )[ ] ( ) ( ) ( )( )[ ][ ]( )

−

−−−+−−−−=∆

OSO

OOSOSOOOOSOOSO VVLCV

LIVVDTVVVLIVVVDTLIVVDTV

2 2.51

It is obviously seen from equations 2.38 and 2.51 that both buck converter’s

input output voltage relationship and output voltage ripple functions are depending

on load. This has some disadvantages in terms of both control of the converter output

22

voltage and also selection of the circuit parameters especially the output filter

capacitor for specific applications.

2.4 Combination of Input and Output Stages

In this section, the two discrete circuits, which are the buck converter and the

H-bridge inverter, are connected together to form a sinusoidal wave shape and the

performance of the resultant circuit will be investigated.

As discussed in previous sections, input stage will generate rectified sinusoids

and the output stage will invert this waveform. And also proper circuit topologies

have been determined that can separately do necessary operations. This section of the

study investigates the combinational operation of discrete stages and will analyze the

effects of each stage on the other. If necessary, modifications will be proposed.

Performance of the combined circuit will be investigated in terms of

• Operating conditions of the DC-DC converter filter inductance (continuous

and discontinuous conduction modes)

• Under load conditions (resistive and inductive load)

During the analysis of the DC-DC filter inductance operating conditions,

minimum inductance values will be calculated which satisfy the continuous

conduction mode of operation. With these values necessary comments will be done

for the performance of the system.

For the load analysis, first of all feed forward control for DC-

DC converter will be analyzed. Than if necessary closed loop control will be applied

to the system. For all load analysis, system performance will be evaluated by output

voltage FFT (Fast Fourier Transform) results and also THD (Total Harmonic

Distortion) of the output voltage.

23

During the analysis, the parameters that is calculated for the filter elements

(capacitor and inductor) in chapter 3, is used in foregoing analysis in this section.

L = 950 µH and C = 10 µF.

The basic proposed topology of the circuit is shown in figure 2.19. The

maximum output power and voltage of the system is desired to be 1kVA and 220

Vrms respectively. Full load current is approximately 4.5 A. So for full load, load

impedance is approximately 50Ω.

Figure 2.19 Basic circuit diagram of the overall system

2.4.1 Analysis of the Operating Conditions of the DC-DC Converter Filter

Inductance

In this section the operating conditions of the buck converter used in our

application will be examined. The circuit will be analyzed whether it operates in

continuous conduction mode or in discontinuous conduction mode.

As discussed before the output voltage of the DC-DC Converter used in this

thesis, is supposed to be rectified sinusoidal voltages. In other words, the amplitude

of this voltage is changing between 0 and Vout,peak. Thus, duty cycle is changing

between 0 and Dmax.

24

Boundary operation condition (boundary condition between continuous and

discontinuous inductor current) for a buck converter is given by equation 2.28

( )2

1 RDLf s−

≥

Maximum output power of the circuit is desired to be in the range 750VA - 1

KVA. Maximum Output Voltage is 311 Vpeak, 220Vrms. For an input voltage of 530

Vdc, Dmax ≅ 0.6, fs = 15.000 Hz.

So the minimum inductance that satisfies continuous conduction mode for an

output voltage of 310Vpeak and for full load impedance (50Ω) is

6.0,,min =DfullloadL ≅ ( ) HL µ67030000

506.01min ≅⇒

−

In our application, even if the circuit operates at full load, and at maximum

operating voltage, the inductance value is just satisfies the necessary condition for

continuous inductor current just for the higher instantaneous voltages of the sinus

curve. Because as it is said before the actual inductance value is 950 µH (calculated

in chapter 3).

As the output voltage is sinusoidal and in one cycle its magnitude already

changes between 0 and 310 at rated conditions. That mean duty cycle gets a value of

range 0-0.6.

For voltage values near 0, let’s say D ≅ 0.1, then again for full load, the

minimum inductance value necessary for continuous conduction operation is,

≅= 1.0,min, DfullloadL ( ) mHL 5.130000

501.01≅⇒

−

Consequently it is obvious that even if the output voltage is max (220 Vrms),

and the circuit operates at full load, the inductor current is essentially both

continuous and discontinuous in one period, in our application.

25

The equations for a buck converter show that, for discontinuous operation

mode, the system is nonlinear in terms of input-output voltage relationship as shown

in equation 2.30. As a result of this nonlinearity, two problems occur.

• Proper voltage regulation can not be achieved with linear control techniques

such as PI control. Because, as it is discussed in DC-DC buck converter

basics, for discontinuous conduction mode of operation, the circuit is out of

control of the switches as the inductor current vanishes, as was shown in

figure 2.36. There will be no switching in this period and the variation of the

output voltage is directly proportional with the time constant of the output

capacitor and the load. Thus the system is operates in this region

uncontrollably with its own nature.

• Secondly, the output voltage ripple relation with the converter operating

characteristics must be analyzed especially for determining the value of the

output filter capacitance of the DC-DC buck converter.

For continuous conduction mode of operation, the output voltage ripple is

given by Eq.2.16 as

OV∆ = ( )

281

s

O

CLfVD−

Solving Eq.2.16 for C gives,

( )28

1

sO

O

LfVVD

C∆

−=

For constant values of DC-DC converter input voltage, inductance, switching

frequency, and for a specified value of output voltage ripple, capacitance value can

be determined as a function of duty cycle, independent of the load and if the highest

possible value of the inductance is chosen, the desired low output voltage ripple level

will be guarantied.

26

On the other hand, for continuous conduction mode of operation, the output

voltage ripple is given by Eq.2.51 as

( )[ ] ( ) ( ) ( )( )[ ][ ]( )

−

−−−+−−−−=∆

OSO

OOSOSOOOOSOOSO VVLCV

LIVVDTVVVLIVVVDTLIVVDTV

2 2.51

Solving Eq.2.51 for C gives,

( )[ ] ( ) ( ) ( )( )[ ][ ]( )

−∆

−−−+−−−−=

OSOO

OOSOSOOOOSOOS

VVLVVLIVVDTVVVLIVVVDTLIVVDT

C2

2.52

As it is seen in Eq.2.52, capacitance value is dependent to the load. As a

result of this for specified circuit parameters it is impossible to obtain constant output

voltage ripple for dynamic loads. Such as in the application in this thesis, output

voltage is always varying to form rectified sinusoidal wave shape so it always

operates in transient region. Therefore discontinuous conduction mode is

undesirable.

2.4.2 Analysis of the Proposed Circuit under Load Conditions

The analysis is done with ORCAD’s PSpice version 9.2 [5]. Throughout the

simulations, non-ideal (actual) semiconductor switches and diodes are used for buck

converter and H-bridge inverter. In closed loop control case, an analog PI controller

is used composed of analog comparators. In order to prevent convergence problems

of the analysis, small series resistances added to the passive elements as discussed in

[5, 22]. Simulation model is given in appendix A.4

The system is first simulated using feed-forward control. A reference voltage

that is rectified sinusoids is applied to the buck converter and then the signal at the

output of the buck converter is inverted by the output stage.

27

Secondly the system is simulated using closed loop control by taking

feedback from the output of the buck converter. The output voltage of the buck

converter is compared with the reference and the error is applied to a PI controller.

The output of the controller is applied to the buck converter.

Load analysis is done at rated output voltage and at full load (Load

impedance = 50Ω) conditions.

2.4.2.1 Feed-Forward Control

The schematic of the simulated circuit with open loop control is shown in

figure 2.20 below. Firstly the resistive load and then inductive load is used in the

simulations.

Figure 2.20 Circuit diagram for open loop analysis

The input of the circuit is rectified line voltage of 530V DC. Output is desired

to be 220Vrms, 50 Hz, sinusoidal voltage without any low or high frequency

harmonics.

For a rectified sinusoidal reference voltage (feed-forward control) and for a

purely resistive load of 50Ω, the output voltage of the system for one period is shown

in figure 2.21

28

Figure 2.21 Output voltage for full resistive load with open loop control

It is seen from the figure that, for purely resistive load, the output voltage

tends to follow the reference sinusoidal input voltage. But it is obvious that the

response of the system is not very well at lower voltage regions depending on the

circuit dynamics. The harmonic diagram is shown in the figure 2.22. The

representation of FFT in PSpice 9.0 is in the form of triangles with only their peak

values indicate the amplitude of related harmonics. THD of the waveform shown in

figure 2.21 is calculated approximately 11.37%.

Figure 2.22 Harmonic Spectrum of the output voltage (open loop control, resistive

load).

The system shown in figure 2.20 is now simulated for inductive load. The

load is now a combination of resistance and an inductance and is specified as

during the simulations. o2050∠

29

The simulation has been run for inductive load and results are obtained.

Output voltage and harmonic spectrum of the system with open loop control and with

inductive load, is shown in Figs.2.23 and 2.24 respectively.

Figure 2.23 Output voltage for inductive load with open loop control

As it is seen in figure 2.23, the output voltage is far from being sinusoidal. As

the load becomes inductive, a distortion occurs on the output voltage of the buck

converter due to the inductive current flowing back to the capacitor. This

phenomenon was discussed in section A.5.1.4 (choosing the best topology for output

stage). Harmonic spectrum is shown in figure 2.24. THD of the waveform shown in

figure 2.23 is calculated approximately 19.5%.

Figure 2.24 Harmonic Spectrum of the output voltage (open loop control, inductive

load).

30

The inductor current for one period is shown in figure 2.25. Also a magnified

version of figure 2.25 is given in figure 2.26. These waveforms show that the

inductor current is both continuous and discontinuous in one period of operation.

Figure 2.25 Buck Converter Inductor current for inductive load (open loop)

Figure 2.26 Buck Converter Inductor current for inductive load (open loop)

Magnified.

Output voltages include lower order harmonics for both load types as seen in

figures 2.22 and 2.24 resulting from inadequate dynamic response and in addition the

distortion for inductive load case.

Another disadvantage of the open loop is poor voltage regulation capability

resulting from the voltage drops of the semiconductor switches.

31

2.4.2.2 Closed Loop Control

As a result of the feed-forward control technique gave unsatisfactory results,

closed loop control is decided to be used in order to regulate the output voltage.

Voltage feed-back is taken from the output filter capacitance of the DC-DC

converter. Circuit schematic is shown in figure 2.27. System is again first simulated

for resistive load and than for inductive load.

Figure 2.27 Circuit diagram for closed loop analysis

2.4.2.2.1 Determination of the Control Circuit Parameters Used for Closed loop

Operation

The buck converter output capacitor voltage, should track the reference

voltage which is full-rectified sinusoids. So the capacitor voltage and the reference

voltage are compared. Then the error is compensated by PI controller. An amplifier

circuit used as PI regulator is shown in figure 2.28. The control signal is then applied

to a PWM generator and the resultant signals become the switching signals of the

buck converter’s controllable switch. Determination of control circuit parameters for

32

a buck converter is discussed in [21] in detail. The foregoing analysis for the control

circuit design is taken from [21].

Vo

0

R2

1k

Vref

C21 2

3

2

84

1+

-

V+

V-

OUT

R1

C11 2

Figure 2.28 Type 2 compensated error amplifier (PI Controller)

In order to determine the controller parameters, transfer function of the

overall system must be obtained from the small signal averaged circuit. The transfer

function is given in [21, 2 by Eq.2.52

×+

++

×+

+××

=

CLLrr

CXss

CsrCLVp

VssVcsVo

Lc

L

c

11

1)()(

2

2.52

The crossover frequency can be calculated using the DC-DC converter

inductance and the capacitance values in Eq.2.18 as

Hzfc 16501010109502

166=

×××=

−−π

The frequency characteristics of the system is obtained with MATLAB as

33

shown in figure 2.29

Figure 2.29 Frequency response of the uncompensated system.

From the bode diagram it is seen that, the system gain at 1.65 kHz (10367

rad/s) is 4 dB with a phase angle of -120. The compensated error amplifier should

have a gain of -4 dB at 1.65 kHz in order to make the loop gain 0 dB. Also phase

margin is adjusted to be ≅ 46 in order to assure the stability [2, 21]

Therefore the resistance and the capacitance values of the compensated error

amplifier shown in figure 2.28 are obtained as, R1= 1kΩ, R2= 6kΩ, C1=8nF,

C2=1nF [21]

Using these parameters, the simulation has been run and results are obtained.

Output voltage and harmonic spectrum of the system with closed loop control and

purely resistive load is shown in Figs.2.30 and 2.31 respectively.

34

c

c

s

Figure 2.30. Output voltage for full resistive load with closed loop control

Figure 2.31 Harmonic Spectrum of the output voltage (closed loop control, resistive

load).

istive load, THD of the waveform shown in figure 2.30 is

alculated as 1.78%.

e load

f resistance and an inductance and is specified as during the

imulations.

For purely res

The system is now simulated for inductive load. Th is now a

ombination o o2050∠

35

The simulation has been run and results are obtained. Output voltage, output

current and harmonic spectrum of the system with closed loop control and with

inductive load, is shown in Figs.2.32, 2.33 and 2.34 respectively.

Figure 2.32 Output voltage for inductive load with closed loop control

Figure 2.33 Output current for inductive load with closed loop control

36

Figure 2.34 Harmonic Spectrum of the output voltage and current (closed loop

control, inductive load).

The distortion of the voltage is reduced but still exists in serious levels.

During reactive current flowing, the control circuit turns off the switch at the DC-DC

converter as shown in figure 2.35 but this could not be sufficient to suppress the over

voltage. In figure 2.35, upper waveform in blue is output voltage, and the lower

waveform in red is gate signals of the switch of the DC-DC converter.

THD of the waveform shown in figure 2.32 (output voltage), is calculated as

10%.

37

Figure 2.35 Output voltage and gate signal of the buck converter for closed loop

control and inductive load.

To sum up, the simulations show that the reactive current distorts the

sinusoidal shape of the output voltage. It was expected that, the closed loop control

circuit would solve this problem. But even with the feed-back control, the overcharge

could not be removed but decreased to a lower value than that obtained with open

loop control, as shown in figure 2.32.

The problem is the nonlinear reactive current flowing through the capacitor,

pumping up the capacitor voltage beyond the reference voltage.

The solution must be to provide an alternative path to the reactive current to

prevent the over voltage on the capacitor. This can be done by some modifications on

the conventional buck converter topology.

As conclusion, it is obvious that the proposed circuit topology is not

sufficient especially for inductive loads and also for control point of view it is

undesirable to operate the circuit in discontinuous conduction mode.

38

The inverter part works properly but DC-DC buck converter part fails. The

next section is devoted to solving this problem and a modified circuit topology for

the DC-DC converter is proposed.

2.4.3 Modified Circuit Topology

Two main drawbacks of the proposed system are defined in the previous

section.

• The distortion of the “rectified DC-link” voltage.

• Control Complexity for discontinuous conduction mode.

The circuit called complementary switching Buck Converter or two quadrant

Buck Converter or so-called Synchronous Buck Rectifier is supposed to solve these

two problems. The circuit schematic is shown in figure 2.36

3-Phase Bridge Rectifier

Synchronous Buck Converter

H-Brigde Inverter

PWM Generator

Figure 2.36. Modified Circuit Topology

The advantage of this circuit is the inductance current of the synchronous

buck rectifier will flow in both directions. So the circuit always operates in

continuous conduction region. If the voltage on the output capacitor of the input

39

stage tends to increase more then the reference voltage (as seen in previous sections)

due to the inductive current flowing through it, the additional switch turns on and

provides an alternative path for that current. So the distortion will be prevented

As a result of this, all conventional Buck Converter equations for continuous

conduction mode of operation are valid for complementary switching Buck

converter.

Since this circuit never operates in discontinuous region, the linear

relationship between the input and output voltages of the input stage is guarantied for

all type of loads.

Also the modified topology provides fast response to a load transient which is

demanded by this application. [12]

The modified topology is simulated for inductive load and the results are

given in the figures below. The output voltage and current waveforms are shown in

figure 2.37. Upper waveform is voltage and the lower one is current.

Figure 2.37 Output voltage and load current for inductive load with closed loop

control. (Upper waveform is voltage and the lower one is the current).

40

Figure 2.38 Harmonic Spectrum of output voltage and load current for inductive load

with closed loop control. (Upper waveform is voltage and the lower one

is the current).

The FFT results shown in figure 2.38 show that the fundamentals of both

voltage and current are at 50 Hz, beside these there are significantly small

(negligible) lower order harmonics. Also figure 2.37 proves that the modified

topology has solved the control complexity problem and the undesirable distortion on

the rectified DC-link is eliminated.

THD of the waveform shown in figure 2.32 (output voltage), is calculated as

10%.

Fig 2.39 shows the inductance current of the buck converter. Also a

magnified version of figure 2.39 is shown in figure 2.40.

Figure 2.39 Inductance current (modified topology)

41

Figure 2.40 Inductance current (magnified version of figure 2.60) (modified

topology)

The advantage of the new modified topology can be clearly seen from

figures.2.39 and 2.40. The inductance current can be bidirectional due to the

additional switch. As a result of this, the reverse inductive current pumped from the

output stage to the in put stage can be directed through this switch to either ground or

to the input DC-link instead of it flows into the DC-DC converter filter capacitance.

Thus the distortion is avoided.

42

CHAPTER 3

DETERMINATION OF THE DC-DC CONVERTER PARAMETERS

3.1 Introduction

In conventional buck converter (figure 3.1) design procedures, except for

special applications, the inductance value L is chosen such that the inductance

current is continuous. A minimum value of the inductance that satisfies the

continuous conduction mode of operation can be calculated and selected as the

criteria for the design, as discussed in section 2.3.3.2 and given by the formula

( )2

1 RDLf s−

≥ 3.1

Figure 3.1 Conventional Buck Converter

However in our application the system always operates in continuous

conduction mode as a result of the additional switch connected in parallel with diode

D in figure 3.1, thus providing a path for the inductance current to flow in both

directions as shown in figure 3.2 as discussed in section 2.4.3. So a “minimum

43

inductance value for continuous conduction mode” definition does not exist for the

case. Another criterion should be defined for the inductance value.

Figure 3.2 Complementary Switching Buck Converter

In this thesis study this criteria is defined as the physical volume of the

inductor. After determining the inductance value, the capacitance value will be

determined depending on the output voltage ripple specification.

3.2 Inductance Design

While starting the inductance design, the operating conditions of the circuit

should be considered. The inductance used in this thesis is operating at high

frequencies such as 15 kHz. In manufacturers application notes and data sheets [13,

14], ferrite E shaped cores are recommended for high frequency and medium power

inductance and transformer design applications. The properties of some of E shaped

ferrite cores that will be proper for our application are shown in table 3.1.

Table 3.1 Properties of Ferrite E shaped cores for medium power applications

44

In the last column of the table 3.1 a term defined as WaAc (cm4) is seen. This

term is called Area Product and is the basis of the design procedure for selecting the

proper core. In the foregoing analysis Wa is indicated as Aw and Ac is indicated as

Acore in the formulations in order to prevent complexity.

Design procedure is discussed in detail in [2]. The starting point of the

inductor design is the equation commonly termed stored energy relation defined as, ∧

Φ= NIL max 3.2

where L is inductance, Imax is maximum inductance current, N number of turns, and

is peak flux in the inductor. The number of turns N is given by, ∧

Φ

cu

wcu

AAkN = 3.3

where kcu is winding factor (0,3-0,6 depending on the insulation and the wire type),

Aw is effective winding area and Acu is conductor area. The flux in the inductor is,

3.4 ∧∧

=Φ BAcore

where Acore is effective core area and ∧

B is maximum flux density in Tesla. Conductor

area, Acu , is given by

rms

rmscu J

IA = 3.5

where Irms is the rms value of the inductor current and Jrms is the rms current density

in A/mm2. Using Equations. 3.3, 3.4 and 3.5 in equation 3.2 yields,

∧

= BAA

AkIL core

cu

wcumax 3.6

∧

= BA

JI

AkIL core

rms

rms

wcumax

45

3.7 ∧

= BAAkJIIL corewcurmsrmsmax

AwAcore is called AREA PRODUCT and given by

∧==BkJ

IILAAAP

curms

rmscorew

max 3.8

This equation is the basis for the inductor design procedure in this thesis. This

equation relates design inputs (L,Imax and ) to the material parameters (JrmsI rms and∧

B )

and geometric parameters (kcu, Aw, and Acore) of the core and winding. [2]

Design software is developed in MATLAB in order to determine the proper

inductance value depending on the Eq.3.8

3.2.1 Inductance Design Software

The software is developed particularly for a complementary switching buck

converter. Program code is given in appendix A2. With this software, Imax, Imin, Irms,

and AP values are calculated for a defined range of inductance values, where Imax is

maximum inductance current, Imin is minimum inductance current, Irms is rms value

of inductance current, and AP is Area Product of the core. Imax , and Imin are defined

and formulated in section 2.3.3.2 and shown by equations 2.25 and 2.26 respctively

also Irms is the rms value of the inductance current shown in figure 3.3 and calculated

simply by integrating the square of the waveform shown in figure 3.3 over one

period and taking its square root. The derived expression of Irms in terms of D, Imax,

and Imin is given in equation 3.9.

46

Figure 3.3 Inductor current over one period

+++

−+−−−

−= 2

minmin

2223

2

2 3)1()1()1(

3)1(1 IaIaDbDabDaD

I rms 3.9

where,

minmax IIa −= 3.10

minmax DIIb −= 3.11

( ) sooLo

L TDL

VR

ViR

Vi −+=

∆+= 1

22max 3.12

( ) sooLo

L TDL

VR

ViR

Vi −−=

∆−= 1

22min 3.13

By using equations 3.9, 3.10, 3.11, 3.12, and 3.13 in equation 3.8, Area

Product value is calculated in the software.

Program inputs are, kcu, Jrms, ∧

B , Zo, Vo, f, Vs, where kcu is winding factor,

Jrms is RMS value of current density in A/mm2, ∧

B is maximum flux density, Zo is

47

load impedance, Vo is output voltage, f is switching frequency, Vs is input voltage.

For the given values of input parameters, AP and Imax values are calculated

for inductance values between 25µH and 5mH in steps of 25µH. Load is assumed to

be full load as discussed in section 2.4.1 as Maximum output power of 750VA - 1

KVA. Maximum Output Voltage is 311 Vpeak, 220Vrms. fs = 15.000 Hz.

The input parameters are determined as,

kcu = 0.3, Jrms = 200 A/cm2, Zo = 50-70Ω, Vo = 220Vrms, f = 15000Hz, Vs = 530V.

∧

B value is determined with the aid of manufacturer’s data sheet. For our

application the most proper material which has the highest saturation flux density is

material P core of Magnetics Corporation.. For P type material, the saturation flux

density versus temperature curve is shown in figure 3.4.

Figure 3.4 Saturation flux density vs. temperature for P Material

This material has Bsat of 500 mT at 30 °C and 400 T at 90 °C. ∧

B is

determined as 0.35T in order to assure safe operation.

The outputs of the program, area product versus inductance value are shown

in figures.3.5, 3.6

48

Figure 3.5 Area product vs. inductance

It is obviously seen that at the neighborhood of 1mH, area product has its

minimum value as shown in figure 3.6. For greater values of inductance above 1mH,

area product increases to the values that are not feasible with the cores given in table

3.1.

Figure 3.6 Area product vs. inductance (Magnified)

In this design procedure, the standard commercially available inductor cores

are also taken into account while choosing the proper inductance value [13].

49

In figure 3.6 Area Product value for 900-1000 µH is approximately 14.2 –

14.3 cm4. Depending on that, the most proper core for our application is selected to

be 47228-EC material P core of Magnetics Corporation. This core has an Area

Product of 14.8 cm4 as shown in table 3.1. Also inductance value is determined to be

950 µH depending on figure 3.6. A number of samples of this core has been

manufactured in USA and sent by the manufacturer.

3.2.2 Calculation of Lmax, Possible With the Selected Core and Specifying the

Inductance Value

For the selected core, the maximum inductance value possible with must be

calculated in order to assure the selection of core. In the design, the winding material

will be Litz wire because it has the lowest eddy current loss of any conductor type at

high frequencies. For Litz wire kcu = 0.3. Jrms is chosen as 200A/cm2 in order to avoid

over temperature problems.

Irms, can also be calculated by the inductance design software. The result is

shown in figure 3.7. Irms for 950 µH is approximately 4.2 A.

Figure 3.7 Area Product and Irms versus Inductance

50

The required area of the copper conductor is given by Eq.3.4. Using Eq.3.4

and figure 3.3 required copper area is calculated as,

21.222.4 mmAcu ==

From data sheet of the core 47228-EC, Aw = 402 mm2. So the maximum

number of turns that is possible to wind to the selected core, with the conductor area

obtained above and with kcu = 0.3 is calculated using Eq.3.2 as,

TurnsN 601.2

3.0402max ≅

×=

The maximum inductance achievable with the specified core could then be

calculated. Combining Eqs.3.1 and 3.3 gives,

∧

∧

=I

BANL coremax

max

HmmTL µ9908.7

1068.335060 24

max =×××

=−

The possible inductance value will be an arbitrary value in the range of 900-

990 µH. however if the maximum achievable inductance value is chosen, the

minimum achievable inductance current values will be obtained. So inductance value

is chosen as 950µH, leaving a safety margin for the assembling process.

Number of turns necessary for 950 µH, can be calculated using Eqs.3.1 and

3.3 assuming that ∧

I is constant within a small interval of inductance value as,

TurnsNNL

NL

5710990

60109506

6

max

max ≅×

××=⇒= −

−

51

3.2.3 Calculation of Winding Loss

Specific power PCu,s dissipated per unit of copper volume in a copper winding

due to its resistance is given by

32

, )(22 cmmWJkP rmsCusw = 3.14

Winding volume is calculated approximately as Vw = 75 cm3. Thus total

power dissipated in the windings is

WPw 275)2(3.022 2 ≅××=

3.2.4 Calculation of Core Loss

All magnetic cores exhibit some degree of hysteresis in their B-H

characteristic. The area inside the B-H loop represents work done on the material by

the applied field. The work (energy) is dissipated in the material, and heat caused by

the dissipation raises the temperature of the material.

The hysteresis loss increases in all core materials with increases in ac flux

density Bac, and switching frequency f. The general form of the loss per unit volume

(specific loss), is given by Eq.3.10. d

acc

s BafP = 3.15

where P is in mW/cm3, Bac is in kiloGauss, and f is in kHz. Coefficients are given by

the manufacturer as shown in Table 3.1.

a c d

f < 100 kHz 0.158 1.36 2.86

100 kHz ≤ f < 500 kHz 0.0434 1.63 2.62

f ≥ 500 kHz 7.36 10-7 3.47 2.54

Table.3.2 Coefficients applied to core loss formula

52

AC core flux density Bac is calculated in [2] and given as

∧

∧ −=

I

IIBB dc

acmax

Imax, and Idc are calculated by the inductance design software by the given

formulas in section 3.2.1 for 950 µH as Imax = 7.9 A and Idc = 4.4 A

Thus Bac = 0.155 T = 1.55 kilo Gauss and for f = 15 kHz.

386.236.1 37.30155.015158.0 cmmWPs =××=

Total core loss is given by Eq.3.11 as,

corescore VPP = 3.16

where, Vcore is core volume, in cm3. Core volume of 47228-EC is 50.3 cm3

(from data sheet given in appendix A3. Thus max core loss is

WPcore 527.13.501.24 =×=

3.2.5 Thermal Analysis

In this section, thermal verification of the inductance design will be given.

Increases in the temperature of the magnetic core and winding materials

degrade the performance of these materials. The resistivity of the copper winding

increases with temperature and so the winding loss increases with temperature,

assuming a constant current density. In the magnetic materials, the core loss

increases with increasing temperature, assuming the frequency and flux density

53

remain constant. However the value of the saturation flux density becomes smaller

with increases in temperature. [2]

To keep the performance degradation within bounds, the temperature of the

core and windings must be kept below some maximum value. This value is

approximately 100°C for ferrite material [13, 14].

The internal temperature and surface temperature of the inductor is assumed

to be nearly the same. This assumption is made because the power dissipation is

approximately uniformly distributed throughout the volume of the core and the

windings. This leads a large cross-sectional area for heat conduction to the surface

and for relatively short path lengths. Moreover, the thermal conductivities of the

materials are large. Hence the thermal resistance of importance in determining the

temperature of the inductor is the surface-to-ambient resistance, Rθsa. The heat

transfer from a body to its surroundings is composed of two parallel mechanisms

which are heat transfer by radiation and heat transfer by convection. Thus surface-to-

ambient thermal resistance Rθsa, has two components, that are radiative, Rθ,rad, and

convective, Rθ,conv.

3.2.5.1. Thermal Resistance Due to Radiative Heat Transfer

Heat transfer via radiation is given by the Stefan-Boltzman law as,

)(107.5 448ssrad TTEAP −×= − 3.17

where Prad is the radiated power in watts, E is the emissivity of the surface, Ts is the

surface temperature in K, Ta is the ambient temperature in K, and A is the outer

surface area in m2. For dark objects, E = 0.9.

For black ferrite material, Eq.3.17 can be rewritten as

54

−

=

44

1001001.5 as

radTT

AP 3.18

The thermal resistance Rθ,rad is defined as

radrad P

TR ∆=,θ 3.19

Thus,

−

∆=

44,

1001001.5 as

radTT

A

TRθ 3.20

The surface area of the inductor for the selected core and winding configuration is

0.0112 m2. For an ambient temperature of Ta = 40°C and for maximum surface

temperature of Ts = 100°C, the thermal resistance due to radiation is calculated using

Eq.3.20 as

Rθ,rad,100°C = 10.75°C/W

3.2.5.2 Thermal Resistance Due To Convective Heat Transfer

If a vertical surface has a vertical height dvert less than about 1 m, it loses heat

energy via convection to the surrounding air [2] at a rate given by

( )( ) 25.0

25.1

34.1vert

conv dTAP ∆

= 3.21

where Pconv is the heat power lost via convection in watts, ∆T is the temperature

difference between the surface and ambient, A is the total surface area of the body in

m2, and dvert is the vertical height of the body in meters.

55

The thermal resistance Rθ,rad is defined as

convconv P

TR ∆=,θ 3.22

Combining Eqs.3.21 and 3.22, 25.0

, 34.11

∆

=T

dA

R vertconvθ 3.23

The surface area of the inductor for the selected core and winding configuration is

0.0112 m2 and dvert = 5.8 cm. For an ambient temperature of Ta = 40°C and for

maximum temperature of Ts = 100°C, the thermal resistance due to convection is

calculated using Eq.3.23 as

Rθ,conv,100°C = 13.88°C/W

These two thermal resistances are in parallel, and the total thermal resistance

of the inductor body to ambient when Ta = 40°C and Ts = 100 °C is

WCRR

RRR

convrad

convradsa

o06.6,,

,, =+

=θθ

θθθ

3.2.5.3 Temperature Rise in the Inductor

For a given total power dissipation of PT (Core loss + copper loss), max

surface temperature of the inductor is given by,

aTsas TPRT += θ 3.24

corewT PPP += 3.25

56

For our application the max surface temperature, at an ambient temperature of

40 °C, is

( ) 402527.106.6 ++×=sT

Ts = 61 °C

This result is in the safe operating region. Possibly, the current density will be

increased a little bit in order to increase the power.

3.2.6 Specifying the Air gap Length

The air-gap length must be specified in such a way that the gap must be

tailored to give the value of ∧

B when the inductor current is Imax . The total

reluctance, Rm, of the magnetic flux path is given in [2] by

gc

cgapmcorem

core

m Ag

Al

RRBA

INR

0,,

max

µµ∑+=+== ∧ 3.26

where lc is the magnetic flux path length in the core material. At every air-gap in the

magnetic core, there will be fringing flux as shown in figure 3.8a. However the total

flux in the air-gap must be the same as the total flux in the core, the flux density in

the air-gap is much smaller than the flux density in the core. The effect of the air-gap

is modeled as a rectangular block as shown in figure 3.8b having a gap length g and

cross-sectional area Ag.

Figure 3.8 Fringing fields in the air-gap of an inductor (a), effective cross-sectional

area of the gap (b)

57

Double E-core, its bobbin and an assembled inductor is shown in figure 3.9

Figure 3.9 Double E-core, its bobbin and an assembled inductor

Ag is given for a double-E core by,

( )( )gagaAg ++= 3.27

Mostly,

c

ccorem

ggapm A

lR

Ag

Rµµ

=>>= ∑ ,0

,

So that the gap length ∑ is given by g

∑ ∧==BA

INARAg

core

ggapmgmax

0,0 µµ 3.28

Eqs.3.27 and 3.28 give,

( )( gdgaBA

INg

core

++=∑ ∧max

0µ ) 3.29

Moreover, the double, E-shaped inductor does not have a single large air-gap

as shown in figure 3.9. In stead of one, three air-gaps (distributed air-gaps) are used

to keep the magnetic flux, which fringes into the copper windings to a minimum.

58

Thus the distributed air-gapped inductor has less eddy current loss than a single large

air-gapped inductor. If there is Ng such distributed air gaps each having a length g

then

∑ = gNg g 3.30

As the air-gap at the center leg of the E-shaped inductor is twice in width of

the gaps at the side legs, the center gap will be thought as two gaps. Thus in

calculations it is assumed that the inductor has four air-gaps.

Substituting Eq.3.29 into Eq.3.30 yields

+

+= ∑∑∑ ∧

ggcore

Ng

dN

ga

BA

INg max

0µ 3.31

Expansion of Eq.3.26 yields a quadratic equation in the desired

parameter . In practical designs involving distributed air-gaps, the individual gap

length g << a and d. Thus the quadratic terms in Eq.3.31 can be neglected in

comparison to the linear terms in

∑ g

∑ g to yield

( )∑

+−

≈ ∧

g

core

core

Nda

IN

BA

Ag

max0µ

3.32

In our application, Acore = 3.68 cm2 (from data sheet of 47228-EC core), ∧

B =0.35 T, µ0 = 4π*10-7 H/m, N = 57 (calculated and verified in section 3.2.4), ∧

I =7.9 A (calculated in section 3.2.1), a = d = 1.9 cm (from data sheet of core 47228-

EC), Ng = 4 (for a double-E core, two in series in each leg). Then

59

( ) ( ) mmg 78.1

4108.3

9.76010435.01068.3

1068.32

7

4

4

=×

−×××

×××

≈∑ −

−

−

−

π

The length of each of the four distributed air-gaps is

mmg 445.0478.1

==

3.3. Determination of the Capacitance (Value and type)

After specifying the inductance value, the capacitance value can be

determined by the output voltage ripple equation (Eq.2.16) derived in section 2.3.3.1.

OV∆ = ( )

281

s

O

CLfVD−

3.33

For the maximum possible output voltage Vo = 318 V, D = 0.6. f = 15000 Hz.

L = 950 µH. Then solving Eq.3.28 for C, for a specified output voltage ripple be ∆Vo

≅ 2.5 % yields

C = ( )( )

F626

1062.10150001095078

3186.01 −−

×=××××

−

This will be corrected as 10µF in order to match the standards.

Now whether the capacitance value calculated for max output voltage assures

reasonable output voltage ripple values for lower voltage levels is checked. In order

to do this, output voltage ripple equation 3.33 is expressed as a function of duty cycle

D and solved for ∆Vo as shown in Eq.3.27,

( )2

2

8 s

gO LfC

VDDV

−=∆ 3.34

60

where Vg = 530 V, L = 950 µH, fs = 15000 Hz and C = 10 µF. Remembering that the

linear input output voltage relationship Vo = VgD, equation 3.34 is said to be a

function of output voltage as well. Output voltage ripple values are calculated and

plotted for duty cycle values D = 0 - 0.8 as shown in figure 3.10.

Figure 3.10 Capacitance vs. Duty cycle for ∆Vo = 7V.

It is obviously seen in figure 3.10 that the calculated capacitance value C =

10µF provides reasonable % output voltage ripple for all values of duty cycle, and

output voltage values as well. Even if the output voltage value is minimum let’s say

D = 0.1 and Vo = 53V, output voltage ripple is calculated using figure 3.10 as

VVo 756.253052.0 =×=∆

At the frequency level of f = 15000 Hz, standard electrolytic capacitors may

have higher equivalent series resistances. As a result, capacitor losses may be

excessive. Instead of electrolytic, metalised poly-propylene film capacitors are

preferred in this application in order to reduce capacitor losses.

Also the voltage rating of the capacitor is important. Since the output voltage

of the synchronous buck converter is a DC quantity with a maximum value of Vo,peak

= 318 Vdc, at least two times of Vo,peak should be chosen as the capacitor rating

voltage.

61

CHAPTER 4

HARDWARE AND SOFTWARE IMPLEMENTATION

4.1 Introduction

The block diagram and pictures of the hardware setup used in this research is

given in figure 4.1. Description of each block and brief information about software is

given in the following sections. Also specifications of the components and the codes

written in C and assembly languages are given in appendix A1. Experimental results

obtained in laboratory are also given also in the following sections.

62

TMS320LF2407 DSP

CONTROLLER BOARD

GATE DRIVER and

PROTECTION CIRCUIT of DC-

DC CONVERTER

VOLTAGE SENSING CIRCUIT

GATE DRIVER CIRCUIT of H-

BRIDGE INVERTER

DC-DC CONVERTER INCLUDING

OUTPUT FILTER

H-BRIDGE INVERTER

LOAD

Figure 4.1 Block diagram of the hardware setup

63

Figure 4.2 Input DC link and Filter Capacitors

Figure 4.3 DC-DC Converter Power Stage (2MBI50N120 IGBT and Snubber

Capacitance)

64

Figure 4.4 Output Inverter Power Stage (IRF 740 Mosfets)

Figure 4.5 DC-DC Converter IGBT Gate Drivers and Protection Circuit

65

Figure 4.6 Output Inverter Mosfet Gate Driver Circuit

Figure 4.7 Voltage Sensing Circuit

66

Figure 4.8 TMS320LF2407A DSP Controller Circuit

Figure 4.9 Experiment Setup

67

Figure 4.10 Experiment Setup

4.2 Hardware

In the implementation phase of the study, as the aim is to proof of the concept

given in section 2, some critical components of the hardware are selected so that they

have 3-4 times rating values above the demanded ratings. Also some devices are

chosen so that they give perfect performance compromising the cost such as voltage

sensing LEM module.

As discussed in previous chapters the overall system has two basic functional

stages that are DC-DC converter and H-bridge inverter. The purpose of the DC-DC

converter is generating a rectified DC-link, and the inverter is to invert the rectified

DC-link to form a sinus waveform.

However experimental set up used may be investigated as having three parts.

The separation into parts is based on the functions.

68

• Power Stage of the Circuit

• Gate Drive and Protection Circuits

• Control Circuit

4.2.1 Power Stage of the Circuit

1 2 3

Power stage

is indicated with nu

1. Inpu

2. DC-

capa

3. Outp

In order to o

#1 in figure 4.11, li

3-phase uncontrolle

voltage ripples. Th

power semiconduc

voltage spikes on t

Figure 4.11 Pow

can be divided into

mbers.

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ut Inverter (includin

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d bridge diode recti

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three parts as shown in f

3-phase bridge rectifier)

uding 2 IGBT’s and F

g 4 power mosfet’s and lo

power stage of the overa

0 V is converted into DC

fier and a filter capacitor

nk between the input filte

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ctors. In order to reduce

69

igure 4.2 Each part

ilter inductor and

ad)

ll system shown by

by using a standard

is used to eliminate

r capacitor and the

ctances may cause

the effects of these

stray inductances the connection is kept as small as possible and filter capacitor of

the bridge rectifier is connected to the DC-DC converter switches as close as

possible.

In the DC-DC converter stage shown by #2 in figure 4.11, 2MBI50N-120

Dual IGBT module was used as the controlled switches as discussed in section 2.4.3

The basic specifications of the IGBT module are as follows

• 1200 V, 50 A

• Over current Limiting Function (4-5 Times Rated Current)

• Integrated Gate to Emitter protection zener diodes.

Detailed Information about the IGBT module is given in appendix A3.

In order to absorb the surge voltage on the DC link, a snubber capacitor is

also used in the DC-DC converter stage.

At the output of the DC-DC converter, there is a low-pass filter consists of an

inductor and capacitor as shown by #2 in figure 4.11. This filter inductor is designed

for high frequency application and detailed information about the core material is

given in the appendix A.3. The capacitor is polypropylene film type which is suitable

for high frequency applications. Detailed information about this capacitor is given in

appendix A3.

In the output inverter stage shown by #3 in figure 4.11, four IRF 740 power

mosfets were used in order to invert the signal at the output of the DC-DC converter

stage. This stage is operated at low frequencies and also the switching instants are at

the zero voltage crosses of the rectified DC-link voltage thus eliminating the

switching losses. Mosfets used here have rather higher turn on resistances. BJT’s can

be used to reduce the conduction losses of the output stage so the efficiency of the

system will be improved. Discussion on this topology was made in section 2.2.1.2.4

70

and shown in figure 2.11. The basic specifications of the each mosfet are given in the

following:

• 400V, 10A

• Typical RDS(on) = 0.46Ω

• Low gate charge

Detailed Information about the mosfet IRF 740 is given in the appendix A3.

4.2.2 Gate Driver and Protection Circuits

For proper operation of an IGBT, the gate signals are required to be +15V for

high state, and -5V for low state. EXB-840 of Fuji Corp. gate driver hybrid

integrated circuit is used in this application. Basic features of EXB-840 are given as:

• Up to 40 kHz operation

• Built-in photocoupler for high isolation voltage 2500V AC for 1 minute

• Single supply operation (requires +20V DC supply )

• Built-in over current protection circuit

• Over current detection output

Detailed Information about the gate driver hybrid EXB 840 is given in

appendix A3.

The over current detection output generates a signal if a short circuit fault

occurs on the IGBT. This signal of the EXB-840 must be processed to provide the

necessary protection for the gate drivers and the IGBT’s. A protection circuit is

designed based upon the over current detection output of the gate driver the circuit

diagram of the protection and gate drive circuit is shown in figure 4.12. the

protection circuit consists of two R-S latches, two optocouplers, and necessary logic

gates each for one IGBT. The operation of the circuit is discussed briefly below

71

In normal operation (no-fault), the output of the R-S latches are both high.

Each of these signals is applied to distinct AND gates with the gate signals coming

from the controller. Whenever a fault signal is generated by the gate driver hybrids,

the SET input of the R-S latch goes low and the output of the R-S latch goes low and

both gate signals are goes low immediately. Even if the fault situation cleared the

gate signals are not applied to the IGBT’s unless the RESET signal is applied to the

R-S latch thus providing a complete protection for both IGBT’s.

72

CB1

12

U9A

74LS08

1 23

U1A

74LS00

1 23

0

0-20 V Isolated Power

Supply

R2

U1A

74LS00

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out

puts

)

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HP 47071 2

3

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123456789101112131415

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2MBI

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-120

2MBI50N-120

0-20 V Isolated Power

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HP 4707

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Figure 4.12 Circuit schematic of the protection and gate driver circuit

73

In the output inverter stage, the same gate driver circuit used in DC-DC

converter stage is used to drive the mosfets.

4.2.3 Voltage Sensing Circuit

In order to obtain satisfactory operation of the system, the output voltage

must be controlled by taking samples from it and regulate depending upon the error

between the reference and the actual value as discussed in section 2.4.2.2. The output

voltage can be measured with a simple voltage divider but its accuracy may not be

satisfactory. In this thesis, a new circuit concept is analyzed so proving the concept is

more important then struggling with details. For this reason in order to get reliable

voltage measurement results (without any noise problems), a voltage transducer is

used in stead of a voltage divider as the sensing device. LEM LV-25P voltage

transducer is used in this project. Connection and schematic of the voltage sensing

circuit is shown in figures 4.13 and 4.14 respectively.

Voltage Sensing Circuit

Controller Circuit

Figure 4.13 Connection of the Voltage Sensing Circuit

74

Figure 4.14 Schematic of the voltage Sensing Circuit

Basic features of LV-25P are given below

• Closed Loop (compensated) voltage transducer using the Hall-Effect

principle.

• Ipn = 10mA, Vpn = 10..500V

• Galvanic isolation between the primary circuit (high voltage) and the

secondary circuit (electronic circuit).

Detailed Information about the LV-25P LEM voltage transducer module is

given in appendix A3.

4.2.4 The Controller

The controller used in this study is composed of a Digital Signal Processor. In

power electronics laboratory an application software development kit with digital

signal processor (DSP) of Texas Instruments TMS320LF2407A, of Technosoft Corp.

was available. The software has a user interface called DMC Developer Pro,

providing a code generation interface and built-in compiler, builder and debugging

tools. This development kit is used throughout the experimental studies although far

75

less sophisticated microcontrollers could be sufficient to do this task. Basic features

of the TMS320LF2407A are given in the following:

• TMS320LF2407 running at 30/40 MHz

• 64-kB 0-wait state external RAM

• 2x12-bit accuracy D/A outputs

• RS-232 and JTAG interfaces

• 16 channel,10 bit A/D converter. (400 ns conversion time)

• Six PWM outputs with internal dead-time generating register.

Detailed Information about the TMS320LF2407A DSP is given in appendix

A3.

The controller circuit used in this study has three basic functions. First, it

takes the analog voltage measurements of the voltage sensing circuit as shown in

figure 4.13 and converts them to digital quantities, using its built-in Analog-Digital

Converter. Second function is to generate necessary PWM signals for the gate drive

circuit of the DC-DC converter semiconductor switches (IGBT’s).. To do this the

measurement from the ADC converter is compared with the reference and applied to

a PI controller as mentioned in section 2.4.2.2.1. The third function of the controller

circuit is to detect the zero voltage cross of these rectified sinusoids, and generate

necessary gate signals for the semiconductor switches (mosfets) of the H-bridge

inverter.

The input to the DSP is the analog voltage measurement coming from LEM

module as discussed above and enters to the ADC pins. The output of the DSP is the

gate signals for both DC-DC converter IGBT’s and output stage mosfet’s. The output

signals are generated at the PWM pins of the DSP and goes to the related gate driver

integrated circuit.

76

4.3 Software

The purpose of the software is to realize all the control algorithms that are

mentioned in section 2.4.2.2.1. The reference voltage is defined in the software as a

look-up table. By this software the voltage measurement is converted to digital with

the DSP. The result is then compared with the reference and the error is processed by

the software within a PI loop. The reference is defined in a look-up table and at each

interrupt service routine the controller reads the necessary reference voltage from this

table as shown in Appendix A.1 Then the necessary initializations of the PWM ports

are done. Then the basic function of the software that is to generate the necessary

gate signals for the controlled switches is generated at the related PWM ports of the

DSP. The software is developed in DMC Developer Pro which is an interface

program between DSP card and user. It has a built-in C compiler and runs in the

Windows O.S. environment.

Two programs are developed during the course of this study, one is for open

loop operation (without feed back from output voltage of the DC-DC converter), and

the other for closed loop operation (taking feed back from the output voltage of the

DC-DC converter). The basic flow chart of the programs for two control strategies is

given in the next parts. The detailed flow charts and source codes written in C and

assembly are given in appendix A2.

Figure 4.15 Basic flow-chart of the software for feed-forward control

77

Figure 4.16 Basic flow-chart of the software for closed loop control

4.4 Experimental Study and Verification of Theoretical Calculations

In this section, results of the laboratory experiments are shown. As discussed

many times in the previous sections, the purpose of this thesis is to generate a

rectified DC-link and than invert the voltage at this link to generate pure sinusoidal

voltage. So at each step of the experiments, the load and the rectified DC-link

voltages are obtained under different conditions. A systematic experimental

procedure is followed. The purpose is to identify the open loop (feed forward) and

closed loop performance of the converter at steady state. In other words to determine

a) Whether the output follows the reference voltage, and the level of

minimum voltage achievable

b) The magnitude error

c) Distortion level (THD) of the output voltage and possible causes

78

d) Identify device stresses

e) Identify efficiency of the system and causes of the losses

f) Determine the effect of load power factor variations on the capability of

the converter to follow a specified reference voltage.

The experiments are carried out at 10 Hz, 50 Hz, and 100 Hz at no load and

full load (1kVA) conditions. In order to determine the level of minimum voltage

achievable, the voltage level of frequencies of 5 Hz and 10 Hz is adjusted to keep the

V/f level at 50 Hz (220V/50Hz). The effect of the load power factor variation on the

converter output is tested at 50 Hz.

All experiments are carried out at steady state conditions. In this work, input

power factor correction algorithms are not employed. Note that to achieve this

purpose only additional software is needed. Hardware modifications are minimal.

The results presented in the following sections are obtained with

TEKTRONIX TDS3400 digital phosphor oscilloscope.

4.4.1 Experimental Results of Feed Forward Control Operation

In this section the experimental setup is operated for feed forward control. In

feed forward control operation there is no feedback taken from the rectified DC-link

as mentioned in section 4.2.3. The reference voltage waveform available as a look-up

table in the controller software is directly applied to the IGBT’s. The experiments for

the feed forward control operation are done first for no-load case. Then a series

combination of adjustable resistances and inductances available in the laboratory are

connected as load. The system is then operated for full load case (1 kVA). Cos φ is

adjusted to 0.8. The measurements are taken for 10 Hz, 50 Hz, and 100Hz. At each

frequency level the rectified DC-link and load voltages are obtained with differential

voltage probes. For all steps, magnitude error between actual waveform and the

reference is obtained with the scope. Also THD levels of the waveforms are

calculated approximately by using the FFT property of the scope. Also input and

79

output powers of the system are measured and the efficiency of the system is

calculated. These quantities are given in tables at the end of the section.

4.4.1.1 Experimental Results for No-Load Operation

Figure 4.17 Rectified DC-link (upper waveform) and load voltages (lower

waveform) at 10 Hz.


waveform) at 50 Hz.

80


waveform) at 100 Hz.

4.4.1.2 Experimental Results for Full load Operation


waveform) at 10 Hz.

81


waveform) at 50 Hz.



82

Feed Forward Control Operation

No Load Full Load

10 Hz 50 Hz 100 Hz 10 Hz 50 Hz 100 Hz

Magnitude

Error (%) 0 0 0 14% 8% 4.5%

T.H.D (%) 7.76% 8.4% 8.32% 9.2% 9.48% 8.5%

Efficiency

(%) - - - 80% 85.6% 87%

Table 4.1 Performance Analysis for Feed Forward Control Operation

As it is seen from the waveforms and the performance table, the feed-forward

control gave unsatisfactory results. The output tends to follow the reference but with

oscillation. The frequency of the ripples on the voltage waveforms are approximately

1750 Hz. The cut-off frequency of the DC-DC converter filter is 1650 Hz. The

possible reason of these ripples is the high gain of the DC-DC converter filter at the

cut-off frequency in open loop case. The distortions on the waveforms are above the

acceptable limits.

4.4.2 Experimental Results of Closed Loop Control Operation

As the feed forward control gave unsatisfactory results, the voltage on the

rectified DC-link is regulated by a fed-back loop as taking voltage samples at each

switching cycle, comparing with reference, calculating the instant error, regulating it

in a PI control loop and then generating necessary switching signals. Same

measurements and analysis done in section 4.4.1 are applied for closed loop

operation experiments.

83

4.4.2.1 Experimental Results for No-Load Operation


waveform) at 10 Hz.


waveform) at 50 Hz.

84



4.4.2.2 Experimental Results for Full load Operation


waveform) at 10 Hz.

85


waveform) at 50 Hz.


waveform) at 100 Hz

86

Closed Loop Control Operation

No Load Full Load

10 Hz 50 Hz 100 Hz 10 Hz 50 Hz 100 Hz

Magnitude

Error (%) 0 0 0 1.9% 0.95% 0.95%

T.H.D (%) 1.21% 1.53% 1.93% 1.35% 1.71% 2.25%

Efficiency

(%) - - - 88.75% 89.7% 93.4%

.

Table 4.2 Performance Analysis for Closed Control Operation

The results for closed loop operation are much better then the ones obtained

for the feed forward operation. THD and magnitude errors are decreased to

acceptable levels. The existing small magnitude errors are caused by the voltage drop

on the output stage mosfets. Also the efficiency of the system operating in closed

loop mode is increased.

While calculating the input power, the current flowing into the input DC-link

capacitor is used. As the input DC-link capacitor is too big (2200 µF) the frequency

of the current is low and only flows whenever the input DC-link capacitor voltage

tends to drop. Such a current waveform is shown in figure 4.29

Figure 4.29 Input DC-Link capacitor current

87

4.4.3 Determination of the Level of the Minimum Achievable Voltage

In motor drive applications the output voltage is applied to the motor is

generally a linear function of the frequency. At lower frequencies voltage level must

be decreased to lower levels to preserve the V/f ratio. However going down to lower

voltage values is a problem for digital controllers. In order to determine the level of

minimum voltage achievable, the inverter is operated at 5 Hz and 10 Hz keeping the

V/f level at 50 Hz (220V/50Hz). The results are shown in figures 4.30 and 4.31

Figure 4.30 Constant V/f operation for 5 Hz and 22Vrms Upper waveform is load

voltage and the lower one is rectified DC-link voltage

Figure 4.31 Constant V/f operation for 10 Hz and 44 Vrms Upper waveform is load

voltage and the lower one is rectified DC-link voltage

88

As shown in the above figures the output voltage waveforms are distorted

even if closed loop control is applied. In order to understand the causes of the

distortion, actual PWM generating principle should be reviewed.

In theory, the maximum duty cycle of each switch in the DC-DC converter

can be unity. But in actual case (especially for two switches in one lag case), two

switches should never fired at the same time in order to prevent any short circuit

situation. To realize this time delay called “dead time” is injected between two

switching signals that is 4-5 µs thus reducing the achievable maximum and minimum

duty cycles.

In this study dead time is adjusted to be 2.6 µs also switching period is 66 µs

(for switching frequency of 15000Hz). So 5 µs of the period becomes useless.

Because there are two dead time durations in a switching period. Minimum

achievable duty cycle is then 5/66 = 0.075. The input DC link is 400 V so minimum

achievable output voltage level of the DC-DC converter is 30V. As the voltage

reference is reduced below 30 V the controller applies 0 signal to the IGBT’s. This is

clearly seen in figure 4.30 for 5 Hz and 22V operation. For 10 Hz, 44V operation the

system tends to follow the reference but as not good as higher voltage references.

Below 10V the output voltage can no longer follow the reference voltage.

For lower voltage values the switching frequency is to be decreased in order

to widen the switching period and so the ratio of dead time to switching period is

decreased providing smaller duty cycle values and much satisfactory results for the

lower voltage levels.

4.4.4 The Effect of Power Factor on Inverter Operation

In this section the system is operated at full load (1kVA) at different power

factors such as pf = 0, 0.3, 0.8 and 1 at 50 Hz. Results are as shown in figures 4.32,

4.33, 4.34 and 4.35 respectively.

89

Figure 4.32 Load Voltage and current at 1 kVA with pf = 0

Figure 4.33 Load Voltage and current at 1kVA with pf = 0.

90

Figure 4.34 Load Voltage and current at 1 kVA with pf = 0.8

Figure 4.35 Load Voltage and current at 1 kVA with pf = 1

91

Table 4.3 Performance Analysis at different Load power factor values

Effect of Load Power Factor Variations

pf = 0 pf = 0.3 pf = 0.8 pf = 1

Magnitude

Error (%) 0.64 % 0.64% 0.64% 1.29%

T.H.D (%) 2.55 % 2.16 % 1.65 % 1.39 %

As it is seen both from the figures 4.31, 4.32, 4.33, and 4.34, and table 4.3,

the inverter operation does not affected with the variation of the load power factor.

The worst case, pf = 0 has the highest distortion and as the pf decreases to 1

distortion also decreases. This is the result of increasing inductive current flowing

into the rectified DC-link capacitor.

4.4.5 Stresses on the Semiconductor Switch

The voltage and current level on the DC-DC converter IGBT is obtained and

given in figures 4.36, 4.37 and 4.38. The turn-on and turn-off characteristics of the

IGBT are given in figure 4.39. The problem is the voltage and the current rating of

the switches used in the DC-DC converter.

Figure 4.36 Voltage and Current on the DC-DC converter IGBT

92

Figure 4.37 IGBT Current for full load (1 kVA) at pf = 1

Figure 4.38 IGBT Current for full load (1 kVA) at pf = 0.8

93

Figure 4.39 Turn on and turn off characteristics of the DC-DC converter IGBT

As seen in figure 4.36 the maximum voltage level on the IGBT is input DC

link voltage and the maximum current level is approximately 9 A when the load is 1

kVA. The maximum voltage of the switches is the DC-link voltage, and as the input

capacitor is too big, there are no ripples or spikes on the switches. Also figures 4.37

and 4.38 shows the IGBT currents for full load (1 kVA) at pf = 1, and pf = 0.8

respectively. The maximum peak current is also approximately 9 A for pf = 1 and 8

A for pf = 0.8. rms values of these currents are 4.69A and 3.32A for pf=1 and pf=0.8

respectively which are proper values for the chosen power levels. The peak currents

are approximately two times of the rms currents. These results show that the switches

used in the DC-DC converter stage have ratings slightly higher than the ones used in

a conventional DC-AC inverter.

4.4.6 Inductor Losses at 15000 Hz

As discussed in chapter 3, the filter inductor in DC-DC converter stage is

designed using ferrite core, however in experimental study, since the ordered

inductor was not available on time, an air core conventional inductor is used. The

inductor has 60 turns with a solid conductor has an area of 2.5 mm2. As a result of

94

high frequency operation, a solid conductor inductor has higher resistance than a

bundled conductor. Thus the inductor losses are expected to be higher. The AC

resistance of the inductor is calculated at 15000 Hz and also knowing the rms

inductor current, the inductor loses will be calculated by the following formula

Pind = Irms2.Rac(15000 Hz)

The inductor loss is calculated for two extreme condition (pf = 0 and pf = 1)

at full load (1 kVA). For pf = 0 Irms = 5.1 A, and for pf = 1 Irms = 4.98 A and the

resistance is 2.35Ω so

Pind,pf=0 = 5.12x2.35 = 61.12W

Pind,pf=1 = 4.982x2.35 = 58.28W

If the actual designed inductor have been used, the inductor loss would have

been Pind = 3.527 W as calculated in sections3.2.5 and 3.2.6. The efficiencies for

closed loop operation than would be

Expected and Measured Efficiency Values for Closed Loop Control Operation

No Load Full Load

10

Hz 50 Hz 100 Hz 10 Hz 50 Hz 100 Hz

Efficiency

With Ideal

Inductor (%)

- - - 92.74% 93.73% 97.6%

Efficiency

Measured

with the

Existing

Inductor (%)

- - - 88.75% 89.7% 93.4%

Table 4.4 Expected and Measured Efficiency Values for Closed Loop Control

Operation

95

4.4.7 Sinusoidal Power Filters in the Market

Some passive sinusoidal filters are available in the industry. However they

have some disadvantages compared with the proposed method in this study. First of

all the size of the inductor used in that filters at the same power level is 7-20 times

greater in value then the one used in this study. For example the dimensions of one

such filter is as given in Table 4.5. Note that the volume of this filter is 4 times larger

than the filter used here. Also the frequency range of the commercial inductors is

often quite limited. The data sheets of two sinusoidal filters are given in Appendix

A.6

Filter

Inductance

Height

(mm)

Width

(mm)

Length

(mm)

Commercial

(DEO 100) 107 53 41

Used in this

thesis 56 19 59

Table 4.5 Physical Dimensions of the filter Inductors.

4.4.7 Conclusions

As shown in figures for feed forward control section, the output voltages both

for no load and full load (1 kVA) tend to follow the reference voltage but the

distortion of the waveforms is considerable. At no load the peak output voltage has

almost the same value as reference voltage. However at full load operation the

magnitude of the output voltage decreases below the reference voltage as a result of

the voltage decrease in the input DC link voltage. The reduction of the voltage

increases at lower frequencies as shown in table 4.1. If the THD levels are examined

it is seen that the distortion of the waveforms are approximately same. Also it is clear

that the distortion level is increasing with the load. The distortion levels of the output

voltages are given in table 4.1. The results are clearly not acceptable for practical

conditions. Also the efficiency of the system increases with the increased frequency.

96

The closed loop control operation experiments gave much better results in

comparison with the feed forward case as found in the simulations. The output

voltage follows the reference voltage for both no load and full load (1 kVA) cases

without any oscillations and with distortion levels are within acceptable limits.

Magnitude error, THD, and efficiency of the system with closed loop control are

given in table 4.2. As the rectified DC-link voltage is regulated the magnitude error

of the system is reduced to negligible values. The existing small error results from

the voltage drop on the output inverter switches. THD values are increased as the

load is increased and the efficiency of the system is also increased compared to the

open loop case. Efficiency increases with the increasing frequency. The distortion

level is also increased with the increasing frequency. As the frequency of the output

voltage increases, the number of samples taken within a period is decreased and with

decreased number of voltage feed-back samples the controller can not track the

reference as perfect as it does at low frequencies. The reason of the increasing

distortion level can be summarized in that way.

As pointed out in section 4.4.6, the designed actual DC-DC converter filter

inductor couldn’t be used in the experiments as a result of manufacturing problems.

Following this an air core solid conductor inductor had to be used. The losses of that

inductor are also calculated in section 4.4.6 and this is far above the expected loss

calculated in section 3.2.5. Thus the efficiency of the system with actual inductor is

supposed to be higher than measured as given in table 4.4.

Also the system is operated in order to determine the effect of load power

factor variations on the capability of the converter to follow the specified reference

voltage. The output waveforms for different power factors were obtained with low

distortion levels as indicated in table 4.3. The distortion level increases with the

reduced power factor. Because as the power factor decreased the amount of the

reactive current flowing into the rectified DC-link capacitor increases and the

waveform of the rectified DC-link voltage is distorted a little bit compared to

resistive load case (pf=1).

97

CHAPTER 5

CONCLUSION

5.1 General

As discussed in the introduction part of the thesis, conventional ac motor

drivers and power supplies use some modulation techniques in order to keep the

output current sinusoidal regardless of the output voltage. Output voltage of a

conventional driver or power supply is either a square-wave or in the case of a PWM

inverter, composed of high frequency pulses, typically in the 6 kHz – 20 kHz range.

In both cases there are some drawbacks. Square-wave inverters’ output voltages

contain high-amplitude low frequency harmonics. In PWM inverters the harmonics

of the output voltage are carried to higher frequencies eliminating lower order

harmonics but this also introduces some additional problems such as acoustic noise,

additional iron losses, switching losses, insulation problems etc.

An ideal inverter should have a purely sinusoidal voltage and current outputs.

In this study, an idea of an inverter has been proposed which can produce a low

distortion sinusoidal output voltage.

The proposed idea in this thesis is to generate rectified sinusoids and form a

variable frequency and amplitude DC-link. This link is called the “rectified DC-

link”. The output stage of the proposed inverter is an H bridge which inverts these

rectified sinusoids in order to form the sinusoidal output. In this thesis a single phase

implementation of the proposed inverter configuration is targeted in order to identify

possible problems and investigate the performance of the inverter.

98

The investigation of possible circuit topologies for obtaining the “rectified

DC link” and inverting this waveform is found to be utilizing a synchronous buck

converter along with an H-bridge inverter. Software indicated that a closed loop

control was essential to obtain the desired voltage magnitude and shape.

The proposed circuit is implemented by using the DSP software development

kit of Technosoft MCK 2407A. Naturally a microcontroller with far smaller

capabilities could do the necessary task. Other details of the implementation are

described in the related sections. Necessary software for controlling the system have

also been developed and loaded into the DSP board controller.

In chapter four, experimental studies have been conducted on the

implemented system configuration. A series of tests have been performed in the

laboratory to identify the system performance at steady state conditions.

5.2 Experimental Results

First feed forward control operation of the system is studied. The output

voltage waveforms are found to have THD content above the acceptable levels for no

load operation. The distortion further increased for full load operation. The results

are given in table 4.1.

As the feed forward control was insufficient, a feedback loop is added to the

control scheme from the rectified DC-link. Then the performance of the circuit is

measured once again at 10, 50 and 100 Hz. In closed loop operation, the performance

of the circuit is found to be very good. In other words the distortion of the output

voltage is found to be less than 2%.

The magnitude error is very small too. They are in the order of 1.95% at the

worst case. This is mainly because of the voltage drop on the output transistors. The

efficiency of the system is found to be somewhat small due to the filter inductance

99

losses. However it is found that the efficiency reaches very high levels if a proper

inductor with a proper core is used.

The effect of the load power factor on the system operation is also

investigated at 50Hz. It is shown that the output voltage followed the reference under

full load (1 kVA) condition for pf = 0, 0.3, 0.8, and 1, however a slight increase in

the distortion level is obtained with the decreasing power factor.

The minimum voltage capability of the inverter is also investigated. It is

shown that for low voltage values (lower then 10V), the output voltage can no longer

track the reference as a result of the dead-time between switching signals. This

problem can be solved by reducing the switching frequency for lower voltage levels.

Semiconductor switch stresses are also studied. The IGBT’s of the DC-DC

converter are found to have the same ratings as transistors of a conventional inverter.

The size of the filter at the output of the DC-DC converter is also compared with a

power filter that should be used to obtain a sinusoidal voltage waveform at the output

of a PWM inverter.

It is found that the filter inductor size needed in the proposed configuration is

one fourth of the volume of the inductor employed in the conventional inverter case.

The capacitor size of a conventional filter is 2.2 µF as proposed by the filter

manufacturer. This value is one fourth in value but naturally not in size. However

capacitor size is not very large in any case.

In summary, it can be concluded that by using the proposed topology, two

extra transistors need to be used, as compared to conventional PWM inverter. In

return the inverter transistors of the proposed circuit operate at low frequency less

than (400 Hz). Therefore these are likely to cost far less. The filter used in the

proposed circuit is smaller and the overall filter cost is likely to be somewhat less

than the one used in the PWM inverter sinusoidal filter. In other words the overall

100

cost of the topology proposed here may be marginally higher but an important size

advantage is possible.

For very high power applications the proposed topology is very advantageous

cost wise and size wise since the output transistors are of low frequency type and the

filter becomes much smaller.

5.3 Conclusion and Future Work

At the end of this study, variable frequency and amplitude voltage and current

waveforms with low distortion levels are obtained which an ideal inverter should

have at its output. Major contribution of this study is to obtain the sinusoidal

waveforms with a novel approach. The advantages and disadvantages of the system

are as follows

Advantages:

• Low distortion sinusoidal output voltage

• Sinusoidal input current possible

• Small size of filter elements (both inductor and capacitor)

• Low Losses

Disadvantages:

• # of switches increased. (but sinusoidal input current is possible, note that for

conventional inverters additional switches are needed for this purpose)

The future work on this study will consist of

• Higher frequency operation

• Solution of low frequency distortion problem

• Investigation of dynamic load response of the system

101

• A 3-phase inverter implementation

• Development of advanced control algorithms that will increase the control

bandwidth and reliability

• Development of better and more reliable protection circuits

• Implementation of input power factor correction algorithms to the existing

software

102

REFERENCES

[1] H.Bülent ERTAN, M. Yıldırım Üçtuğ, Ron Colyer, Alfio Consoli, “Modern Electrical Drives”, NATO ASI Series, 2000.

[2] Ned MOHAN, Tore M. UNDELAND, William P. ROBBINS, “Power

Electronics Converters, Applications, and Design”, John Wiley & Sons, 1995 [3] Cyril W. LANDER, “Power Electronics”, McGraw-Hill, 1993 [4] B.K. BOSE, “Modern Power Electronics Evolution, Technology, and

Applications”, IEEE Press, 1992. [5] James W. NILSSON, Susan A. RIEDEL, “Introduction to Pspice Manual for

Electric Circuits Using ORCAD Release 9.1”, Prentice Hall, 1996. [6] Odön FERENCZI, “Power Supplies Part B Switched-Mode Power Supplies”,

Elsevier Science Publishers, Amsterdam, 1987. [7] M. Morris MANO, “Digital Design”, Prentice Hall, 1991. [8] “HV Floating MOS-Gate Driver ICs”, Application Note AN978-b, International

Rectifier. [9] Eric R. MOTTO, “Hybrid Circuits Simplify IGBT Module Gate Drive”,

Powerex Inc., Youngwood, Pennsylvania, USA. [10] “New 3rd Generation FUJI IGBT Modules N Series”, Applicatiom Manual, Fuji

Electric. [11] “IGBT-Driving Hybrid ICs”, Application Manual, Fuji Electric. [12] Mike WALTERS, “An Integrated Synchronous Rectifier IC with

Complementary Switching”, Intersil, 1995. [13] “Ferrite Cores, Design and Application”, Magnetics, 2003. [14] “Ferrite Cores, Materials”, Magnetics, 2003. [15] “TMS320F/C24X DSP Controllers CPU and Instruction Set”, Texas

Instruments, 1999.

103

[16] “TMS320F/C24X DSP Controllers System and Peripherals”, Texas Instruments,

1999. [17] “Gate Drive Considerations for IGBT Efficiency Application Note”, Dynex

Semiconductor, 2000. [18] Wenkang HUANG, “A New Control for Multi-Phase Buck Converter with Fast

Transient Response”, IEEE, 2001. [19] Ognjen DJEKIC, Miki BRKOVIC, Apurba ROY, “High Frequency

Synchronous Buck Converter for Low Voltage Applications”, IEEE, 1998. [20] Kazuo TSUKAMOTO, Tatsuo SAKAI, Toshiaki YACHI, “A Highly Efficient

Buck Converter with Double-Anti-Crossover Synchronous Rectification Using a Newly Developed Control IC”, IEEE, 1998.

[21] Daniel W. HART, “Introduction To Power Electronics”, Prentice Hall, 1997. [22] “Online Manuals”, Orcad Family Release 9.2.

104

APPENDIX A

DATA SHEETS OF THE COMPONENTS AND FULL PROGRAM CODES

In order to understand the concept, detailed information about the

components and full program codes of both inductance design software and system

control software are given below.

105

A.1 Flow Charts and Source Code of The Controller Program Written in C

language

Figure A.1 Flow Chart of the main program for open loop control.

106

Figure A.2 Flow Chart of the interrupt service routine for open loop control.

107

Figure A3. Flow Chart of the main program for closed loop control.

108

INTERRUPTROUTINE

START

Store Necessary registers andaccumulator

Set Interrupt flag and disable allinterrupts

Calculate the instantaneous referencesignal from the look-up table

depending on the pre-enteredfrequency value.

Do the necessary scaling for the ADCresult value and calculate the errorbetween reference and the actual

value.

Configure the compare registerCMPR1 with the calculated referencevalue to generate necessary switchingsignals for PWM1 and PWM2 outputs.(DC - DC converter switching signals)

Detect the zero-cross points of thereference signal and generate thenecessary switching signals for the

inverter part

Reset the ADC

Restore the accumulator andnecessary registers

End of InterruptRoutine

Wait the Analog Digital Converterfinishes its conversion.

Store the result to the result register.

Integrate the error value.

Multiply the error and the integral ofthe error with pre-defined P and Icoefficients and calculate the new

reference for the PWM signals

Figure A4. Flow Chart of the interrupt service routine for closed loop control.

109

#include "vect240.h"

#include "f2407_c.h"

#define MON2407 (int(*)(void))0x0300

#define END_APPL asm (" setc INTM");\

asm (" LDP #0E0h");\

asm (" SPLK #004Fh, 07029h");

/*#define SETBIT(REG,BIT) (REG|(1<<BIT));

#define CLRBIT(REG,BIT) (REG&=~(1<<BIT));

#define TOGGLEBIT(REG,BIT) (REG^=(1<<BIT));

#define TESTBIT(REG,BIT) (REG & (1<<BIT));*/

const float sine[] = 0, 0.018, 0.035, 0.052, 0.070, 0.087, 0.105, 0.122, 0.139, 0.156,

0.174, 0.191, 0.208, 0.225, 0.242, 0.259, 0.276, 0.292, 0.309, 0.326,

0.342, 0.358, 0.375, 0.391, 0.407, 0.423, 0.438, 0.454, 0.469, 0.485,

0.500, 0.515, 0.530, 0.545, 0.559, 0.574, 0.588, 0.602, 0.616, 0.629,

0.643, 0.656, 0.669, 0.682, 0.695, 0.707, 0.719, 0.731, 0.743, 0.755,

0.766, 0.777, 0.788, 0.799, 0.810, 0.819, 0.829, 0.839, 0.848, 0.857,

0.866, 0.875, 0.883, 0.891, 0.899, 0.906, 0.914, 0.921, 0.927, 0.934,

0.940, 0.946, 0.951, 0.956, 0.961, 0.966, 0.970, 0.974, 0.978, 0.982,

0.985, 0.988, 0.990, 0.993, 0.995, 0.996, 0.998, 0.999, 0.999, 1 ,

1, 1, 0.999, 0.999, 0.998, 0.996, 0.995, 0.993, 0.990, 0.988,

0.985, 0.982, 0.978, 0.974, 0.970, 0.966, 0.961, 0.956, 0.951, 0.946,

0.940, 0.934, 0.927, 0.921, 0.914, 0.906, 0.899, 0.891, 0.883, 0.875,

0.866, 0.857, 0.848, 0.839, 0.829, 0.819, 0.810, 0.799, 0.788, 0.777,

0.766, 0.755, 0.743, 0.731, 0.719, 0.707, 0.695, 0.682, 0.669, 0.656,

0.643, 0.629, 0.616, 0.602, 0.588, 0.574, 0.559, 0.545, 0.530, 0.515,

0.500, 0.485, 0.469, 0.454, 0.438, 0.423, 0.407, 0.391, 0.375, 0.358,

0.342, 0.326, 0.309, 0.292, 0.276, 0.259, 0.242, 0.225, 0.208, 0.191,

0.174, 0.156, 0.139, 0.122, 0.105, 0.087, 0.070, 0.052, 0.035, 0.018,

0 ;

unsigned int ort;

float er;

float ier;

float lm;

int pb;

int n;

float c;

float f;

float k;

int k1;

float p;

int ret_val_mon;

extern void t2per_ISR_ASM();

int deadtime(int);

int dt;

float err;

void main(void)

ret_val_mon = 1; /* must be initialized */

*SCSR1 = (*SCSR1 | 0x0084); /*ADC and EVA clock enabled on system control and status register*/

110

*WDCR = 0x00E8; /*watchdog reset*/

*GPTCONA = 0x0400 ; /*start ADC on T2 period int general purpose timer control register*/

*T2PR = 0x012C; /*15000 Hz T2 freq*/

*T2CNT = 0x0000; /*reset GPT2 counter*/

*T2CON = 0x1000; /*timer in continuous up mode with prescaler x1*/

*T1PR = 0x07AD; /*15000 Hz T2 freq*/

*T1CNT = 0x0000; /*reset GPT2 counter*/

*DBTCONA = 0x09F0;

*ACTRA = 0x0006;

*T1CON = 0x1000;

*tpint2vec = (unsigned int)&t2per_ISR_ASM; /*load ISR address to Int. vector in on-hip block B2*/

*ADCTRL1 = 0x4000; /*reset ADC*/

asm (" NOP ");

*ADCTRL1 = 0x1010; /*free run, prescaler 1,start-stop mode,cascaded mode, calibration disabled, self-test

disabled.*/

*ADCTRL2 = 0x4100; /*reset SEQ1 and EVM A trigger starts conversion*/

*MAX_CONV = 0x0000;

*CHSELSEQ1 = 0x0000;




/*IO mux control register is configured to its first function as PWM1 "secondary is IOPA6"*/

*MCRA = (*MCRA | 0x00E0);

*PBDATDIR = *PBDATDIR | 0xC0C0; /*configure IOPF3 as output*/

*PBDATDIR = *PBDATDIR & 0xC080;

*PADATDIR = *PADATDIR | 0x0000; /*configure IOPA5 as input*/

*IMR = 0x0014; /* INT3 & INT5 unmasked */

*EVAIMRB = 0x0001; /*T2 period interrupt enabled*/

n = 0; /*initialize all variables*/

c = 0;

k = 0;

k1 = 0;

f = 50*1.6;

p = 0;

ort = 0;

err = 0;

lm = 0;

er = 0;

ier = 0;

*CMPR1 = 0x0000;

*COMCONA = (*COMCONA | 0x8000);

*COMCONA = (*COMCONA | 0x0200);

*T2CON = 0x1040; /*start timer*/

*T1CON = 0x1040; /*start timer*/

asm (" CLRC INTM ");

for ( ; ;)

ret_val_mon = (*MON2407)();/*communication and monitor program*/

111

END_APPL /*restoring accumulator and necessary registers*/

void timer (void)

if ((*PADATDIR & 0x0020) == 0x0000)

while ((*ADCTRL2 & 0x1000) != 0x0000)

asm (" NOP "); /*(waiting the adc finishes the conversion)*/

lm = (*RESULT0*0.7);

k = 0.0258*f*n;

k1 = k;

c = 6976/f;

p = 0xFF00*sine[k1];

p = (p+0xFF00*sine[k1])/2;

p = (p+0xFF00*sine[k1])/2;

if ((p - lm) <= 0)

*CMPR1 = 0x004F ;

ier = ier - ier*0.8;

else

if ((p - lm)*0.032 >= 1572)

*CMPR1 = 0x0624;

ier = ier + (p - lm)*0.032;

else

ier = ier + (p - lm)*0.032;

*CMPR1 = (((p - lm)*0.032)+(ier*0.003)) ;

if (n < c)

if (n == 0)

pb = *PBDATDIR & 0x0080;

if (pb==0)

*PBDATDIR = *PBDATDIR ^ 0x0040;

deadtime(1);


else

112


deadtime(1);


n++;

else

n++;

else

n=0;

*ADCTRL2 = *ADCTRL2 | 0X4000;

*EVAIFRB = (*EVAIFRB | 0x0001); /*clear timer 2 period interrupt flag*/

else

while ((*ADCTRL2 & 0x1000) != 0x0000)

asm (" NOP "); /*(waiting the adc finishes the conversion)*/

*CMPR1 = 0x0000;

*ADCTRL2 = *ADCTRL2 | 0X4000;

*EVAIFRB = (*EVAIFRB | 0x0001); /*clear timer 2 period interrupt flag*/

int deadtime(ar)

int ar;

int n1;

n1=0;

while(n1<ar)

n1++;

.text

.global _t2per_ISR_ASM

.global _timer

_t2per_ISR_ASM:

CALL _timer;

; End interrupt service routine

MAR *, AR1 ; ARP=1, AR1=TOS+5

MAR *- ; AR1--, AR1=TOS+4

LACL *- ; retore ACCL, AR1=TOS+3

113

ADD *-,16 ; retore ACCH, AR1=TOS+2

LST #0, *- ; restore ST0, AR1=TOS+1

LST #1, *- ; restore ST1, AR1=TOS

CLRC INTM

RET

A.2 Source Code of The Inductor Design Software peakV=input('Enter Peak voltage in Volts>'); freq=input('Enter line frequency in Hz>'); R=input('Enter Load Resistance in Ohms>'); clc; close all; clear all; kcu=0.3; Jrms=210; Bp=0.35; f=15000; T=1/f; Vs=530; D=Vo/Vs; i=1; Idc=Vo/R for L=0:0.000025:0.01 Imax(i)=Vo*((1/R+((1-D)*T)/(2*L))); Imin(i)=Vo*((1/R-((1-D)*T)/(2*L))); Ipp(i)=Imax(i)-Imin(i); bb(i)=Imax(i)-D*Imin(i); Bc(i)=Bp; cc=(Ipp(i)^2/3*(1-D^3)-Ipp(i)*bb(i)*(1-D^2)+bb(i)^2*(1-D))/(1-D)^2; ccc=(Ipp(i)^2/3+Ipp(i)*Imin(i)+Imin(i)^2)*D; IRMS(i)=sqrt(cc+ccc); AP(i)= 10000*(L*Imax(i)*IRMS(i))./(kcu*Jrms*Bc(i)); if Imin(i) < 0 t1=-(Imin(i))*D*T/Ipp(i); t3=Imax(i)*(1-D)*T/Ipp(i); t2=D*T-t1; t=t1+t2+t3; t4=T-t; IDC(i)= (((Imax(i).*(t2+t3))./2)+((Imin(i).*(t1+t4))./2)).*15000; Irms(i)=(sqrt((1/T)*((Imax(i)^2/3*(t2+t3))+(Imin(i)^2/3*(t1+t4))))); AP(i)= 10000*(L*Imax(i)*Irms(i))./(kcu*Jrms*Bc(i)); else Irms(i)=(sqrt((((Imax(i)-Imin(i))^2*D)/3)+(((Imax(i)-Imin(i))^2*(1-D))/3))+Imin(i)); AP(i)= 10000*(L*Imax(i)*Irms(i))./(kcu*Jrms*Bc(i)); end L1(i)=L; i=i+1; end plot(L1,Imax); hold on plot(L1,AP,'r'); hold on figure plot(L1,IRMS,'g');

114

A.3 Data Sheets of the Components

115

A.4 Simulation model

L2

950uH

1

2

R437

2

R2

0.5

10megM2

IRF740

-+ +

-R1

25

Z10

IXGK50N60A

0

+-

+

-

Sbreak

S1

R4

0.5

Vgate1

Vcontrol

D2431

D26

HFA25TB60

31

U8A

UA772L

3 2

8 4

1+ -

V+ V-

OU

T

M1

IRF740

0

+-

+

-Sbreak

S2

15

V2

V16

Vcap

V7

530Vdc

M3

IRF740

R254

2

R342424

1k

Vgate1

L1

150mH

1

2

-++ -

E1

E

Vcap

Vcap

00

0

Vcontrol

0

D2131

V5

TD = 10msTF = 1pPW = 10msPER = 20msV1 = -15VTR = 1pV2 = 15V

0

D25

HFA25TB60

31

V17864

15Vdc

V785


R3098706

1k

C1

5pF1

2

R19

25

R3

2

0

U5A

UA772L

3 2

8 4

1+ -

V+ V-

OU

T

200

Z9

IXGK50N60A 0

0-+

+ -

0

10meg

0

C2

180nF1

2

0

0

V6


R40758905

4k

0

D2231

U419428598A

1 2

C3

20uF

0

R8

0.1

D2331

V10


R5

2

M4

IRF740

Figure A-5 Simulation Model

127

A.5 Determination of Suitable Topology for the Output Stage

Seven different circuit topologies have been proposed. These topologies are

variations of well-known H-Bridge inverters.

Also it is important to emphasize that the switches of the output stage are

switched at low frequencies, thus reducing losses and cost. First thyristorized

topologies are examined because of their low costs. Then IGBT and MOSFETs are

examined.

Initially mode by mode analysis is applied to the circuits and it is seen that

five of the topologies can satisfactorily operate for purely resistive load. However

when the load is changed to be inductive, only two of them seemed to be working

properly in all situations. Two of them could not work for both resistive and the

inductive loads.

It must be noted that all of the switches used at the output stage are low speed

switches.

In order to simplify the problem, the issue of obtaining sinusoidal input

currents to the input stage is not considered in this study. During the analysis the

input part, that is the full rectified sinusoid generator, is assumed to be ideal and

conducting current in both directions. The load is first assumed to be purely resistive

and than a combined resistive+inductive load is considered.

A.5.1 Full Controlled H-Bridge Inverters

In this section different full controlled bridge inverters are examined.

Although all of them have four controlled switches, the type of that circuit devices

changes and also some of them has anti-parallel diodes. In order to specify the

differences, individual circuits are named as topology 1, 2 … etc.

128

A.5.1.1 Topology One of the Full Controlled Bridge Inverter

The first topology of full controlled bridge inverter consists of four tyristors

as shown in figure A.6. That is, all of the switches are controllable at this time. This

circuit operates well when the load is purely resistive. T1 and T4 switches are turned

on for one cycle, and T3 and T2 for the next cycle.

For inductive load, this circuit fails. After T1 and T4 switches are turned on,

because of the lagging current, these switches can not be turned off even if the gate

signals are removed. So a sinusoidal signal can not be obtained at the terminals of the

load.

Figure A.6 First topology consists of four tyristors

A.5.1.2 Topology Two of the Full Controlled H-Bridge Inverter

The second topology of full controlled bridge inverter is a modified version

of the four thyristorized circuit. At this time four anti-parallel diodes are added as

shown in figure A.7

Figure A.7 Four anti-parallel diodes are added to topology one

129

This circuit operates well for the purely resistive load. But in spite of the

freewheeling diodes the circuit does not operate when the load is inductive.

At the first sight it is thought that (assume positive current and voltage) the

reactive current can be commutated from T1 and T4 switches to D2 and D3 diodes.

But it is not the case. The same problem with topology one is still exists. The

thyristors can not be turned off while there is a current flowing through them.

A.5.1.3 Topology Three of the Full Controlled H-Bridge Inverter

The third topology of full controlled bridge inverter consists of two tyristors

and two transistors (or GTO’s) as shown in figure A.8.

Figure A.8 Third topology consists of two tyristors and two transistors

For resistive load the circuit works well. Let’s look at what will happen when

an inductive load is connected.

At the first mode, T1 and TR2 are turned on and the voltage and the current

are positive as shown in figure A.9.

Figure A.9 T1 and TR2 are turned on

130

At the second mode, the load voltage must be the reversed of the input

voltage so the cross elements (T2 and TR1 must be turned on). But as the current is

lagging T1 can not be turned off even TR2 can be. At this time the load current

closes its path through D2 as shown in figure A.10. Because TR1 and T2 can not go

into conduction as it can not draw negative current. The load is shorted so load

voltage is zero until the current in T1 reverses its direction. This is not what we want.

This topology also fails.

Figure A.10 load current closes its path through D2

A.5.1.4 Topology Four of the Full Controlled H-Bridge Inverter

The fourth topology of full controlled bridge inverter consists of four

transistors. GTO’s can also be used but they are produced for very high power

applications in the ranges of megawatts so BJT’s, Mosfets, and IGBT s are suitable

for low power application. Note that the cost effective solution is to use BJT s.

The circuit shown in figure A.11 works properly when the load is purely

resistive. In the case of an inductive load, the circuit has some problems. Initially

TR1 and TR4 are in conduction. When the source voltage drops to zero TR1 and

TR4 are turned off and the cross switches TR2 and TR3 are turned on. At this point

that is the switching instant, the current is first forced to drop to zero and than

immediately change direction. Due to the high di/dt, there is a huge voltage spike

occurs on the load.

131

Figure A.11 Fourth topology consists of four transistors

This problem will be solved by providing a path to the reactive current. This

is achieved by connecting anti-parallel diodes to the transistors as shown in figure

A.12. During the mode by mode analysis, I assume that the capacitor voltage is kept

constant.

Figure A.12 Anti-parallel diodes connected to topology shown in figure A.11

Mode 1:

The voltage and the current are positive. TR1 and TR4 are on. The load

voltage is the input voltage minus the voltage drops on the transistors as shown in

figure A.13.

Figure A.13 TR1 and TR4 are on

132

Mode 2:

The voltage is negative but the current is still positive. TR1 and TR4

are turned off. The current continues to flow through D2 and D3 and even if the gate

signals are applied, TR2 and TR3 can not be turned on. The load voltage is the

reverse of the input voltage minus the voltage drops on the diodes. This mode

continues until the load current becomes zero as shown in figure A.14.

Figure A.14 D2 and D3 are on

Mode 3:

Both the voltage and the current are negative. TR2 and TR3 are on as

shown in figure A.15. The load voltage is the reverse of the input voltage minus the

voltage drops on the transistors.

Figure A.15 TR2 and TR3 are on

Mode 4:

The voltage is now positive but the current is still negative. TR2 and

TR3 are turned off. The current continues to flow through D1 and D4 and even the

gate signals are applied, TR1 and TR4 can not be turned on as shown in figure A.16.

The load voltage is the input voltage minus the voltage drops on the diodes. This

mode continues until the load current becomes zero.

133

Figure A.16 D1 and D4 are on

The theoretical voltage and current waveforms indicating the operation

modes for inductive load are shown in Figure A.17

Figure A.17 Theoretical voltage and current waveforms indicating the operation

modes for inductive load

A.5.1.5 Topology Five of the Full Controlled H-Bridge Inverter

The fifth topology of full controlled inverter’s is a mid-point connection

inverter, consists of only two transistors but two capacitors at the input as shown in

figure A.18. During the mode by mode analysis, I assume that the capacitor voltages

are same and kept constant. This circuit works properly for in-phase load voltage and

current.

134

Figure A.18 Fifth topology consists of two transistors, two capacitors at the input

For inductive load;

Mode 1:

The voltage and the current are positive. TR1 is on. The load voltage

is the input voltage minus the voltage drop on the transistor as shown in figure A.19.

Figure A.19 TR1 is on

Mode 2:

The voltage is negative but the current is still positive. TR1 is turned

off. The current continues to flow through D2 and even the gate signals are applied,

TR2 can not be turned on as shown in figure A.20. The load voltage is the reverse of

the input voltage minus the voltage drop on the diode. This mode continues until the

load current becomes zero.

135

Figure A.20 D2 is on

Mode 3:

Both the voltage and the current are negative. TR2 is on as shown in

figure A.21. The load voltage is the reverse of the input voltage minus the voltage

drop on the transistor.

Figure A.21 TR2 is on

Mode 4:

The voltage is now positive but the current is still negative. TR2 is

turned off. The current continues to flow through D1 and even the gate signals are

applied, TR1 can not be turned on as shown in figure A.22. The load voltage is the

input voltage minus the voltage drop on the diode. This mode continues until the load

current becomes zero.

Figure A.22 D1 is on

136

The theoretical voltage and current waveforms indicating the operation modes

for inductive load are as shown in figure A.23. Note that, under the given

assumptions, the waveforms are same with topology six except for the amplitude of

the input voltage levels. It is the half of the bridge inverter topologies as two

capacitors are connected in series. But this topology uses half the number of

semiconductor switches used in other full controlled bridge inverters.

Figure A.23 Theoretical voltage and current waveforms indicating the operation

modes for inductive load

Topology two would also be suitable for our application. But force

commutation circuits must be used to turn off the thyristors which means additional

cost and volume. That’s why this topology is rejected.

Under the given assumptions, the results are satisfactory for circuit topologies

four and five of the full controlled bridge inverters. But when the practical facts are

taken into account (the non ideal capacitor voltages), topology five of the full

controlled H-bridge inverter seems to be difficult to implement practically. So,

topology four of the full controlled bridge inverter is chosen as the inverter stage for

the further analysis.

137

A.6 Sinusoidal Filters Available in the Market

138

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