a new era in etch insert image - applied materials€¦ · a new era in etch july 13, 2015 insert...
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Applied Centris™ Sym3™ Etch
A New Era in Etch
July 13, 2015
Insert Image
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Scaling Challenge: Variation at All Scales
Within Wafer - Macro Within Die - Micro
Source: Applied Materials Source: Intel.com
Feature Scale - Nano
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3
Scaling Challenge: Variation Control at Atomic Scale
22nm FinFET
0
2
4
6
8
10
12
14
522009
452010
382011
322012
272013
242014
212015
192016
172017
152018
132019
Gate
CD
Uniform
ity (Å)
Half Pitch (nm)
Source: Chipworks
Silicon Bond Length
2015
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0
10
20
30
40
50
6X 4X 3X 2X 2Y 1X 1Y 1Z
Aspect R
atio*
Node
DRAM STI
DRAM BWL
Scaling Challenge: Profile Control at High Aspect Ratios
*AR at Etch includes hard mask
SEM Source: TechInsights
200nm
85nm
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Implications of Scaling Challenges
Macroscopic Uniformity
Microscopic/Nanoscopic Uniformity
High Aspect Ratio Etch Capability
Chamber Design
Process Capability
Ion Energy Control
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■ New chamber design
built from the ground up
■ True Symmetry™
for < 0.5nm CD uniformity
■ Etch byproduct control
for atomic-scale pattern engineering
■ Tunable ion energy
for high aspect ratio profile control
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Introducing the Applied Centris™ Sym3™ Etch A New Era in Etch
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Limitations of Current Etch Technology: Symmetry
Gas
Flow
Temperature
RF
Plasma
Design Tradeoffs Lead to Asymmetry and Macro-Scale Non-Uniformity
Metrology, Inspection, and Process Control for
Microlithography XXVIProc. of SPIE Vol. 8324
83241Y (2012)
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True Symmetry™ Technology Eliminates Tradeoff Between Flow, RF, and Temperature
Baseline
Symmetric Chamber
and Pumping
Symmetric RF
and Gas Injection
Thermal
Symmetry
CD
Uniform
ity (
1
)
Sym3
< 0.5nm
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Limitations of Current Technology: Chamber Conductance
Low Conductance Leads to More Redeposition, Producing Feature-Dependent Etch
+ + + + + +
Plasma
+ +
+ Etchant
Ions
Byproduct
Effusion
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Byprod.
Conc. (a.u.)
1
0
Sym3™: Designed to Control Etch Byproducts
Sym3 Chamber High conductance
Designed for efficient byproduct removal
+
+
+
+
+ + + +
Plasma
+
+
+
+
+ + + +
Plasma
Low conductance leads to
accumulation and resulting
etch variation
High conductance produces
uniform etch
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Minimizing Within-Die Variation: Depth Loading Control
Loading Challenge
High Conductance Overcomes Depth Loading
20nm
Sym3 Performance
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Sym3 Performance
Minimizing Within-Die Variation: Pattern Loading Control
Byproduct redeposition widens isolated lines
High Conductance Overcomes Pattern Loading
Loading Challenge
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Enabling Smaller CD: Line Edge Smoothing
High Conductance Improves Byproduct Control, Producing Smoother Line Edges
Source/
Drain
Gate
Resist Roughness
Baseline LER 3.4nm
Byproduct Roughens Resist
Sym3 LER 1.3nm
Byproduct Control Smooths Lines
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High Aspect Ratio Etch Profile Engineering
Ion Energy and Angle Control
~30:1 AR
Sym3 Performance
300
250
200
150
100
50
0
-10 0 10
En
erg
y (
eV
)
Angle (°)
Conventional
300
250
200
150
100
50
0
-10 0 10
En
erg
y (
eV
)
Angle (°)
Sym3
Sym3 Creates Vertical Profiles in Next-Generation 3D Structures
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Applied Centris™ Sym3™ Etch A New Era in Etch
■ Designed with True Symmetry™
for atomic-level precision
■ Byproduct control for within-chip
feature patterning uniformity
■ Tunable ion energy for exceptional
high aspect ratio etch capability
■ Fastest ramp of a new Applied etch product
with >300 chambers shipped in one year
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