A Network Processor based Internet Protocol

Router for a Third Generation Mobile System

Lasse Kantola

Nokia Networks

Supervisor: Professor Patrick̈Osterg̊ard

Instructor: Tero Tiittanen, M.Sc.

1

Contents

• Background

• Problem description

• Methods

• Own contribution

• Results

– Internet Protocol

– 3GPP

– Network Processors

– Implementation of an Example Router

• Conclusion

2

Background (1/2)

• IP in user terminals

• IP in transport networks as a data and signal bearer

IP

NetworkRadio AccessNetwork

SubsystemIP Multimedia

Circuit switchedNetworks (PSTN)

InternetWWW

IP

IP

IPIP

Core

3

Background (2/2)

• Data rates and volumes are growing

• Various quality, capacity and speed requirements

• More intelligent and faster routers are required

• SW based solution: Flexible, Poor performance

• ASIC based solution: Expensive, Inflexible

• Network processor: Programmable, Optimised for packet processing

4

Problem Description

Study the usage and the feasibility of using a network processor based IP

routing device in a Third Generation Partnership Project (3GPP) compliant

network.

Scope

• 3GPP transport network layer in UTRAN and CS- and PS-core network

• IP routing. (No higher level processing)

5

Methods

• Studying standards and requirements:

– Internet Protocol: RFCs from IETF

– 3GPP specifications and reports

• Studying network processor theory and

architectures

• Implementing an example IP router using

a network processor simulator

3GPPNP?

IETF RFCs

Network ProcessorTheory, Architectures

ExampleRouter Specifications

6

Own contribution

• Literature study: IETF, 3GPP, Network processor literature and white

papers. (Biggest part)

• Example router implementation: Specification, Design,

Implementation, Simulation. (Based heavily on existing code from the

reference material)

7

Internet Protocol (1/4)

Link layer

Internet layer IP, ICMP, IGMP, IPv6

Application layer Telnet, FTP, SMTP, ...

TCP, UDP, SCTPTransport layer

address resolution, IP encapsulation

Study focus was on internet and link layers.

8

Internet Protocol (2/4)

Following topics were studied:

• IPv4, ICMP, IPv6, (nomulticast)

• IP over ATM, Ethernet, ARP

• UDP, TCP

• Quality of Service: Diffserv, Intserv

• briefly mentioned SCTP, IPSec, PPP

9

Internet Protocol (3/4)

An important input was the forwarding algorithm from RFC1812:

1. Receive a packet from the link layer.

2. Validate the IP header.

3. Process IP options.

4. Decide the next hop IP addresss based on the destination address.

5. Force forwarding constraints.

6. Decrease TTL.

7. Fragment packet if necessary.

8. Determine link layer address based on next hop IP.

9. Encapsulate and send to link layer.

10

Internet Protocol (4/4)

Packet processing functions that are required from a router are:

• Address lookup

• Forwarding

• Error detection

• Fragmentation and reassembly

• Protocol demultiplexing, classification

• Queueing and scheduling

• Traffic measurement, policing and shaping

11

3GPP (1/3)

circuit switched core

MGW

MSC

MGW

MSC

SGSN GGSN

BSC

BTS

BTS

NodeB

NodeB

RNC

RNC

Radio Access Network (RAN) Core Network (CN)

BSS

RNSpacket switched core

Reviewed IP bearers in RNC, MSC, MGW and GSN.

12

3GPP (2/3)

• IP data and signal bearers:

– Packet switched data: IP/UDP/GTP

– Circuit switched data: IP/UDP/RTP

– Signalling: IP/SCTP/M3UA

– NodeB data transport: IP/UDP

• Studied RTP, GTP and SS7 protocols

• QoS: configurable Diffserv codepoint marking required

• Interworking: ATM – IP, IPv4 – IPv6, signalling gateways

13

3GPP (3/3)

3GPP standards do not introduce any new requirements. Some IETF

requirements are lessened and some others mandated.

Desirable features are support for various link layer techniques: (ATM,

Ethernet, PPP) and Diffserv.

14

Network processors

Network processors are a relatively new technology and there are various

architectures and companies that offer different solutions.

Network Processor Forum (NPF) develops standards and benchmarks.

Evaluation should considerfunctionality, performanceandcost. These

three are often mutually exclusive.

Network processor are usually located in a line card between a switching

fabric and a media interface.

The network processors use parallelism, pipelines, optimised instruction set

and specialiced coprocessors to achieve high speed.

15

InterfaceXScaleCore

MediaandSwitchFabricInterfaceMicroengines

(16 in IXP2850)

SRAMInterface

Hash unitTimersInterfaceHardwareetc.

DRAMInterface

2 Crypto engines(only in IXP2850)

PCI

Example of an parallel architecture: Intel IXP2850 network processor.

16

Scheduler Buffer

Interface

PatternProcessingEngine Traffic Shaper

Reorder Buffer and

OutputInterface

StreamEditor

PacketAssembler

onboardmemory

StateEngine

PCI busInterface

Classifier Buffer

Input

Example of an pipelined architecture: Agere APP550 network processor.

17

APP550 program architecture

+ DID(FPL)Pass2(FPL)

BM−script(C−NP)

TS−script(C−NP)

Scheduler BufferClassifier Buffer

SED−script(C−NP)

Input Interface

Output interface

ASI−script(C−NP)

Packet

Drop

Enqueue

Parameters64B blocks

Delay / StopProcessingQueue

Packets in 64B blocks

Flow ID

Policing result

PatternProcessingEngine

TrafficManager

StreamEditor

StateEngine

+ Input port + TagPass1

• Classifier: two passes, classification language FPL.

• VLIW engines: statistics, buffer management, traffic shaping, packet

modification, C-NP simplified C language.

• Pipelined nature→ execution time limited.

18

Example router – Requirements

• Uses Agere APP550

• 2 ATM interfaces

• 2 Ethernet interfaces

• Diffserv routing. (nomarking)

IP version 4 + DiffServ Network

EthernetGigabit

GigabitEthernetATM

ATM

ExampleRouter

19

Example router – Design

Not all functionality is possible to implement in the network processor.

Slow path processing in the controlling host processor is needed.

1. Requirements are analysed to derive the external packet formats and

functionality in the logical level.

2. Scheduling hierarchy is designed and the interface between the

classifier and traffic manager is decided.

3. Policing, buffer management and traffic shaping uses algorithms from

the reference: dual token bucket, weighted random early detection

(WRED), modified weighted round robin (WRR).

4. Classifier is programmed in two passes.

20

Example router – Testing

Testing is done with the simulator. The simulation runs can be automated,

which helps in repeating tests and performing long test runs.

• Verifying specific functionality with individual packets.

• Testing QoS differentiation and performance with traffic flows.

21

Conclusion

The network processors look like a practical base for an IP router. However,

new technology and an abundance of options require careful evaluation on a

case-by-case basis.

Future work

• Requirements for other parts of 3GPP system (e.g. IMS).

• Host software in the example implementation.

• Processing for higher layers than IP. (This is challenging for the

network processors, because in addition to a fast processing also a

capability to keep packets a long time is needed.)

22

Various NP architectures

23

Memory Access Unit

Packet Transform Engine

InternalMemorynPcores

Pack

et I

/O to

TM

/ Sw

itchi

ng F

abri

c

Pack

et I

/O to

Fram

er

Metering Engine Policy Engine

External SearchEngine Interface

External MemoryInterface

A simplified structure of a AMCC nP7510 network processor. (TM=Traffic

Manager)

24

Connections to physical interfaces

CP−12 CP−13 CP−14 CP−15CP−0 CP−1 CP−2 CP−3

ExecutiveProcessor

QueueManagementUnit

TableLookupUnit

BufferManagementUnit

FabricProcessor

External Host CPUPCI

Queue Storage orExternalTraffic Manager

Table Storage orExternalClassifier

Multiple Internal Buses

Switching FabricFrame storage

A block diagram of a C-Port C-5e architecture.

25

EgressSwitchInterface

Protocol Processors(16 picoengines)

EmbeddedPowerPC

Embedded Processor Complex

IngressDataFlow

EgressDataFlow

TrafficManagerandScheduler

DataStore

MultiplexedIngress MACs

MultiplexedEgress MACs

IngessSwitchInterface

Architecture of a Hifn network processor chip.

26

TOPparse TOPsearch TOPresolve TOPmodify

memorymemory memory memory

Architecture of a EZchip NP-1c network processor.

27

Interfaces to Memory and Coprocessors

HashEngine

MeteringEngine

CounterEngine

TCAMEngine

long pipeline of 200 processors

Channel multiplexer

Architecture of the Xelerated X10q network processor.

28

Cisco PXF network processor with 32 packet engines partitioned to four

pipelines.

29