a multilevel converter-based universal power conditioner

PESC’99, Charleston, South Carolina, June 27 – July 1, pp. 393-399.

A Multilevel Converter-Based Universal Power Conditioner

Leon M. Tolbert, Fang Z. Peng Thomas G. HabetlerOak Ridge National Laboratory Georgia Institute of TechnologyP.O. Box 2009, Bldg. 9102-1 School of Electrical and Computer EngineeringOak Ridge, TN 37831-8038 Atlanta, GA 30332-0250Tel: (865) 576-6206 Tel: (404) 894-9829Fax: (865) 241-6124 Fax: (404) 894-4641E-mail: [email protected] E-mail: [email protected]: [email protected]

Abstract This paper presents the development of a controlscheme for a multilevel diode-clamped converter connected in aseries-parallel fashion to the electrical system such that it cancompensate for deviations in utility voltage and act as aharmonic and/or reactive current source for a load. Simulationresults are given for the real-time control scheme when appliedto a 5-level converter for different combinations of the followingpower conditioning objectives: sag compensation, voltagebalancing, current harmonic compensation, and reactive powercompensation. Level usage in the series inverter and parallelinverter is analyzed for the different compensation objectives,and a method to maximize level usage at low modulation indicesis highlighted.

I. INTRODUCTION

Deregulation of the power industry will undoubtedly have alarge impact on utilities’ competition for customers. Manyindustrial and commercial customers that cannot toleratevariations in their electrical supply will request “premiumpower” with specifications restricting certain tolerances in autility’s voltage magnitude, distortion, and limits on thenumber of outages per year. Utilities, in turn, will putlimitations on the power factor, current harmonic distortion,and peak power that the customer can impose on the utility.To meet the objectives detailed in these new premium poweragreements, the implementation of advanced power electronictechnologies that can simultaneously improve the powerquality for both utilities and their customers will be indemand.

By connecting two active inverter-based filters with acommon dc link, the combined back-to-back converter can beinterfaced with the utility system in both a series and parallelmanner. By having these two inverters connected to theelectrical system, simultaneous control of the current

demanded from the utility and the voltage delivered to theload can be accomplished. This series-parallel active powerfilter has been referred to as a universal power conditioner[1-3] when applied to electrical distribution systems, and as auniversal power flow controller when applied at thetransmission level [4-6].

Multilevel voltage source inverters’ unique structure allowsthem to span high voltages and to reduce individual deviceswitching frequency without the use of transformers. Thediode-clamped inverter can synthesize a desired waveformfrom several levels of dc voltages, and all six phases of aback-to-back converter can share the same common dc link[7]. Consequently, the integration of a multilevel diode-clamped inverter into a universal power conditioner is anenticing prospect.

A multilevel universal power conditioner (MUPC) offersmany options when deciding what type of control should beused in the compensation of source voltages and loadcurrents. The objectives of the compensation (voltage sag,unbalanced voltages, voltage harmonics, current harmonics,or reactive power) also play an important role in the controlof the two back-to-back inverters.

For a multilevel power conditioner that will perform sagcompensation, the majority of its operating mode will likelybe in low modulation index operating regions because sagsare quite infrequent and for a minimal duration. Because ofthis, how to maximize level usage in a diode-clamped inverterfor low modulation indices has been previously explored [11].A procedure has been developed that enables the inverter toswitch at higher frequencies during low modulation indices.This increases the frequency spectrum and hastens thedynamic response of the inverter, yet does not exceed theallowable switching loss of the active devices.

Because of the different compensation objectives of theseries inverter and the parallel inverter, two distinct controltechniques are adapted for their use. Simulation results verifythat the algorithms developed will enable the back-to-backdiode-clamped converter to function as a universal powerconditioner.

______________Prepared by the Oak Ridge National Laboratory, Oak Ridge, Tennessee 37831-8038, managed by Lockheed Martin Energy Research, Corp. for theU.S. Department of Energy under contract DE-AC05-96OR22464. A contractorof the U.S. Government has authored the submitted manuscript. Accordingly,the U.S. Government retains a nonexclusive, royalty-free license to publish orreproduce the published form of this contribution, or allow others to do so, forU.S. Government purposes.


II. SERIES INVERTER CONTROL

Fig. 1 shows a block diagram of the two inverters (seriesand parallel) and the interconnection with the electricalsystem. For the analysis in this paper, the turns ratio for eachof the series transformers was chosen to be 1. The algorithmused to regulate the load voltage is the short time windowsampling technique proposed by Joos and Moran [8]. Theload reference voltage, which must be synchronized with thesource phase voltages, is generated directly from the sampleof two line-line source voltages over a short time frame. Thistechnique requires that the source voltage be close tosinusoidal, which is the case for the majority of electricalinstallations at the interface between a large industrialcustomer and a utility.

To determine the phase angle for a sinusoidalsynchronizing voltage, vsync, one can make use of thefollowing equations:

( )( )

−⋅

⋅=

− 1cos

sinarctan

kk

k

syncssync

ssyncsync vTv

Tv

ωω

θ , (1)

where 3

ScaSabsync

vvv −= , (2)

and where vSab and vSca are source line-line instantaneoussamples and Ts is the sampling period. For a system with1024 samples per cycle, ωTs = 2π/1024 radians. By samplingthese two line-line voltages, a synchronization signal can beobtained even if one of the phase voltages collapses to zero, asin the case of a single phase to ground solid fault.

The three instantaneous load reference voltages can then begiven by the following equations:

( )syncnom

LaV

v θsin3

* ⋅= ,

−⋅=

32sin

3* πθsync

nomLb

Vv , (3)

+⋅=

32

sin3

* πθsyncnom

LcV

v ,

where Vnom is the nominal or desired line-line voltage for theload electrical system. The instantaneous reference signalsfor the series inverter to compensate for deviations in thesource voltage are then equal to the difference between theinstantaneous load reference voltages given in (3) and theactual source phase voltages derived from the line-lineinstantaneous samples:

−−=

3** ScaSabLaSIa

vvvv ,

−−=

3** SabSbcLbSIb

vvvv , (4)

−−=

3** SbcScaLcSIc

vvvv .

These three series inverter reference signals (4) are themodulation waveforms that are compared against a set oftriangular carrier waves to determine the switching of theseries inverter active devices.

A control structure is shown in block diagram form inFig. 2. From the serial inverter reference voltages (4), theamplitude modulation index (ma) is determined. For lowmodulation indices (ma < 0.50 for all three phases), the

vSab , v

Sbc , v

Sca

* * *

+

-

fm

[(m-1)V

dc ] -1

ma

FrequencyMultiplier for

Low ModulationIndices

[11(Table III)

VSIa+j, VSIb+j, VSIc+j* * *

SeriesInverter

Gate DriverSignal

Generator[11 (5)]

ReferenceRotation orSFO-PWM

Voffset[11 (3-4)]

(j, j, j)

RedundantState

Addition

sa,

+

vLa, vLb, vLcLoad Voltage

ReferenceGenerator

(3)

vS

ab , vSca

SynchronizingVoltage

(1-2)v

SIa , v

SIb , v

SIc

* * *

[11(8)]

AmplitudeCalculation

Am

fc [n]mf [n]

VariableFrequencyMultiband

CarrierGeneration

[10 (9)]

+

Vdc

syncθ

vnom

(4)

[11 (1)]

syncθ

[11 (2)]

Fig. 2. Serial inverter control block diagram.

LSILSILSI

Cp

Cp Cp

VLc

VLb

vPIa

vPIb

vPIcvSIc

iPIbiPIc iPIa

Vsb

iLc

iLa

iLb

VLa

seriesmultilevel

diode-clampedinverter

LoadUtility

isa

iSb

iSc

Vsa

Vsc

parallelmultilevel

diode-clampedinverter

commondc link

vSIb

vSIa

LPI

Fig. 1. Series-parallel connection to electrical system of back-to-back multileveldiode clamped inverters for universal power conditioner.


carrier frequency can be increased, and the reference voltagesare rotated among carrier bands as detailed in [11]. For highmodulation indices (ma > 1.00), SFO-PWM is implementedas discussed in [10]. The modified reference signals, whichmay differ from the original reference signals by a triplenaddition (SFO-PWM) or redundant state addition (referencerotation), are then compared against the multiband triangularcarriers to calculate the switching signals that are the controlsignals for the active devices.

Computer simulations were used to evaluate theperformance of the synchronizing and balancing algorithmunder different sag or surge conditions. The amplitudemagnitude of the load reference voltage Vnom was chosen to beequal to a 5-level diode-clamped inverter’s dc link voltage.

In order to reduce the ripple in the load voltage because ofinjection of voltage by the series inverter, the low pass filterformed by LSI and Cp in Fig. 1 is necessary. For a 60 Hzelectrical system, the optimum cutoff frequency of the filterwas found to be 60 Hz. Higher cutoff frequencies of the filterresulted in high ripple content of the load voltage, and lowercutoff frequencies resulted in large phase shifts between the

source voltage and load voltage and a reduction in themagnitude of the load voltage.

Fig. 3 shows series compensation for a single-phase fault onphase a that decreased its voltage to 0.3⋅Vnom. The invertercompensates immediately and almost instantaneously for thisfault such that the load voltage is well regulated andbalanced. Even with this severe fault, the referencewaveforms for the three phases of the inverter have anamplitude modulation index less than 0.5 (for a transformerturns ratio of 1), and hence only three of the five availablelevels in the diode-clamped inverter are needed.

As shown in Fig. 3 (c), (d), and (e), the synchronization andvoltage regulation algorithm makes use of all three inverterphases to compensate for a sag in just one of the three sourcevoltage phases. This illustrates that this algorithm isapplicable to only three-phase, three-wire systems and not tothree-phase, four-wire systems. For the example representedin Fig. 3, rotation of the reference waveform among differentcarrier band sets is possible as discussed in [11]. A single-phase fault that reduces the source voltage to less than

-3-2-10123

volta

ge (p

.u.)

(a) source phase voltages, vSa, vSb, vSc

-4-3-2-101234

volta

ge (p

.u.)

(b) load line-line voltages, vLab, vLbc, vLca

0

1

2

3

4

volta

ge (p

.u.)

(c) series inverter phase voltage, vSIa

0

1

2

3

4

volta

ge (p

.u.)

(d) series inverter phase voltage, vSIb

0

1

2

3

4

volta

ge (p

.u.)

(e) series inverter phase voltage, vSIc

Fig. 3. System voltage waveforms for single-phase sag (vSa) to 0.3⋅Vnom.

-3-2-10123

volta

ge (p

.u.)


-4-3-2-101234

volta

ge (p

.u.)


0

1

2

3

4

volta

ge (p

.u.)


0

1

2

3

4

volta

ge (p

.u.)


0

1

2

3

4

volta

ge (p

.u.)


Fig. 4. System voltage waveforms for two-phase sag (vSa,vSb) to 0.35⋅Vnom.


0.25⋅Vnom is necessary before use of all five levels in onephase of the diode-clamped inverter is required.

For the algorithm defined by (1) and (2), a significantdouble phase fault that involves phase a results in a phaseshift between the load voltage and source voltage at theinitiation and conclusion of compensation by the seriesinverter. Fig. 4 represents the case where phases a and bhave a double-phase fault to ground that causes the sourcevoltage to dip by 65% to 0.35⋅Vnom. The phase shift in theload voltages can be seen at the beginning and end of thefault. For this particular example, the phase shift introducedwas 22.5°. The worst case would be when two phases arecompletely grounded, and the resultant phase shift is 60.8° inthe phase voltage at the beginning and ending of voltagecompensation.

Because phase a is the reference for the other two phases inthe synchronization algorithm, simulations have shown that ifphase a is not involved in the fault, however, no substantialphase shift is introduced in the load voltages. Fig. 5 showsthe case where phases b and c of the source voltage have been

reduced to 0.1⋅Vnom by a severe sag. As shown in Fig. 5, theload voltages are well regulated, even for this extreme case.A double-line to ground fault that reduces the source voltageto less than 0.53⋅Vnom is necessary before all five levels of thediode-clamped inverter are needed. A less severe fault willresult in only three levels being used and reference rotationbeing possible [11].

The drawback of the synchronizing and balancingalgorithm is that it cannot compensate for voltage harmonicsbecause it was derived for sinusoidal source voltages. Thealgorithm does function for small distortions in the sourcevoltage (generally less than 5% total harmonic distortion), butthe load voltage will have about the same harmonic content asthe source voltage. Fig. 6 represents three source voltagesthat have a 5% 5th harmonic sequence and experience a three-phase unbalanced sag for a three-cycle duration. The loadvoltage is balanced and well regulated, but it has about thesame distortion as the source voltage.

Another drawback of the algorithm is that hardwareimplementation is difficult because of the precision needed

-3-2-10123

volta

ge (p

.u.)


-4-3-2-101234

volta

ge (p

.u.)


0

1

2

3

4

volta

ge (p

.u.)


0

1

2

3

4

volta

ge (p

.u.)


0

1

2

3

4

volta

ge (p

.u.)


Fig. 5. System voltage waveforms for two-phase sag (vSb,vSc) to 0.10⋅Vnom.

-3-2-10123

volta

ge (p

.u.)


-4-3-2-101234

volta

ge (p

.u.)


0

1

2

3

4

volta

ge (p

.u.)


0

1

2

3

4

volta

ge (p

.u.)


0

1

2

3

4

volta

ge (p

.u.)


Fig. 6. System voltage waveforms for three-phase unbalanced sag when sourcevoltage has 5% 5th harmonic distortion.


for the calculation of the denominator of (1). The analog todigital conversion for most digital signal processors will nothave the required precision for a sampling rate of 1024samples/cycle. Execution time of the processor is also aconcern when calculating (1) because of the arctan term.

III. PARALLEL INVERTER CONTROL

The parallel inverter is responsible for supplying thereactive and/or harmonic current demanded by the load.Generalized instantaneous power theory, as outlined by Pengin [9], is used for the control of the parallel inverter. Thistheory works well for balanced voltages, which should be thecase for the load voltages because of the series compensationof the source voltage. For the case where unbalanced voltageswere present, the instantaneous power theory where thecurrents are chosen to follow the voltage waveform is moreappropriate [12]. A control structure is shown in blockdiagram form in Fig. 7.

Using instantaneous power theory (generalized pq-theory),the instantaneous reference current for the parallelcompensation control is given by the following vectorequation:

LL

Lc

LL

LcPI vv

vqvvvp

i vvvv

vvvv

⋅×+

⋅=

*** (5)

where pc* and qc* are extracted from the active and reactivepower of the load, pL and qL, which are given as follows:

LcLcLbLbLaLaLLL ivivivivp ⋅+⋅+⋅=⋅=vv ; (6)

LLL ivqvvv ×= , (7)

or LbLcLcLbLa ivivq ⋅−⋅= ,

LcLaLaLcLb ivivq ⋅−⋅= ,

and LaLbLbLaLc ivivq ⋅−⋅= .

For the compensation objective of making the sourcecurrent unity power factor (and sinusoidal for a source voltagewith little distortion), qc* is set equal to qL and pc* is set equalto the load ripple active power pL, where

LLL ppp −=~ , (8)

and where Lp is the dc component of the load active power.A low pass filter is necessary for extraction of the dc

component from the load active power. A digital low passfilter was implemented as follows:

kkk Lcs

sL

cs

cL p

TTTp

TTTp ⋅

++⋅

+=

− 1, (9)

where Tc is the inverse of the filter’s cutoff frequency fc. Fora sampling frequency of 1024 times per cycle and a 60 Hzelectrical system, the optimum cutoff frequency of the lowpass filter was found to be 5 Hz. Simulation results showedthat with a lower cutoff frequency of the low pass filter, moreof the active power ripple is filtered but at the expense of anextended response time to step changes in the load current.Higher cutoff frequencies resulted in better response timesbut at the expense of filtering less of the active power ripple.With the 5 Hz cutoff frequency, the response time to a stepchange was approximately 1.5 cycles and generally betterthan 90% of the active power ripple was filtered.

The parallel inverter of the MUPC injects currents byimpressing a voltage across the parallel inductors, LPI, that isthe difference between the load voltage VL and output voltageVPI. The parallel inverter has to provide a voltage VPI* suchthat the inverter supplies a current that tracks the currentreference computed in (5). This voltage was computed fromthe following vector equation:

( )s

pPIPILPI T

Liivv

ω⋅−+=

vvvv ** . (10)

Again from simulation, an impedance of the parallelinductance of 40⋅ωTs ohms yielded a current that tracked thereference current well. Smaller values resulted incompensation currents with a high ripple content, and forlarger values, the tracking of the reference current was tooslow to eliminate the distortion present in the load current.

Simulation results showed that the amplitude of the desiredload voltage Vnom should not be more than 70% of the overall

VLab , V

Lbc , VLca

+

+

fm[11(1)]

[(m

-1)V

dc]-1

ma

FrequencyMultiplier for

Low ModulationIndices

[11 (Table III)]

VPIa+j, VPIb+j, VPIc+j* * *

ParallelInverter

Gate DriverSignal

Generator[11 (5)]

ReferenceRotation orSFO-PWM

Voffset[11 (3-4)]

(j, j, j)

RedundantState

Addition

sPIa, sPIb, sPIc

+

VP

Ia , VP

Ib , VP

Ic* * *

[11 (8)]

AmplitudeCalculation

Am

[11(2)]

fc [n]mf [n]

VariableFrequencyMultiband

CarrierGeneration

[10 (9)]

+

PI(10)

IPIa , IP

Ib , IPIc

+

-

iLa , iLb , iLc

Extraction Circuit to FindReactive and/or Harmonic

Current Components(5-9)

IPIa, IPIb, IPIc* * *

vLab , v

Lbc , vLca

(10)(10)

Fig. 7. Parallel inverter control block diagram.


dc link voltage for the MUPC to be able to impress enoughvoltage across the parallel inductance to compensate forreactive currents when the load voltage is at its maximum orminimum amplitude. Without this margin, completecompensation of reactive currents may not be possible.

Fig. 8 shows waveforms for an electrical system withcurrent compensation where the load current had a 20% 7th

harmonic component and a 0.7 displacement power factor.The source current immediately becomes sinusoidal and inphase with the source phase voltages once compensation bythe MUPC has begun. The parallel inverter supplies asubstantial reactive current to compensate for the largereactive power drawn by the load.

The filter described by (9) does not completely filter theripple in the load power for severely unbalanced conditions.Fig. 9 shows what the source voltage, load current, and sourcecurrent look like for compensation of the load current underunbalanced current conditions (iLb = -iLa, iLc = 0).

Fig. 10 shows some waveforms from an MUPC system withan ideal low-pass filter with the same load current example asused in Fig. 9. The currents are now almost completelydistortion-free as shown in Fig. 10(b), and the ripple in thereal power transmitted to the load has been eliminated asshown in Fig. 10(f).

IV. CONCLUSIONS

In this paper, a real-time control scheme was developed fora complete multilevel universal power conditioner system.Because of the different compensation objectives of the seriesinverter and parallel inverter, two distinct techniques wereadapted for use by the two converters.

The short time window sampling technique employed foruse with the series inverter enabled regulation of the loadvoltage under unbalanced fault conditions with theassumption that the source voltage is fairly sinusoidal.Simulation results showed that only for a severe fault wouldall of the levels in a MUPC be required for compensation. Forthe majority of the sags experienced on an electrical system,only part of the voltage levels in a MUPC are used. Underthese conditions, the rotation of level usage as described in[11] is an effective means of balancing level usage and insome cases increasing possible switching frequency.

The generalized pq-method was used for load currentcompensation by the parallel inverter. This methodminimized the currents drawn from the utility by eliminatingall of the reactive power and the ripple in the real powertransferred to the load.

Because the parallel inverter of the MUPC injects currentsby impressing a voltage across an inductance with respect tothe load voltage, in most cases all of the voltage levels in theparallel inverter are used. In addition, the desired loadvoltage Vnom should not be more than 70% of the dc link

voltage, so that the MUPC can still impress the propervoltage across the parallel inductance when the load voltageis at its maximum or minimum amplitude.

REFERENCES

[1] H. Fujita, H. Akagi, “The Unified Power Quality Conditioner: TheIntegration of Series- and Shunt-Active Filters,” IEEE Transactions onPower Electronics, vol. 13, no. 2, March 1998, pp. 315-322.

[2] S.-J. Jeon, G.-H. Cho, “A Series-Parallel Compensated UninterruptiblePower Supply with Sinusoidal Input Current and Sinusoidal OutputVoltage,” IEEE Power Electronics Specialists Conference, 1997, pp.297-303.

[3] F. Kamran, T. G. Habetler, “Combined Deadbeat Control of a Series-Parallel Converter Combination Used as a Universal Power Filter,” IEEETransactions on Power Electronics, vol. 13, no. 1, Jan. 1998, pp. 160-168.

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

(a) load currents, iLa, iLb, iLc

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

(b) source currents, iSa, iSb, iSc

-2

-1

0

1

2

(c) source phase voltages, vSa, vSb, vSc

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

(d) parallel inverter current for phase a, iPIa

-1

0

1

2

3

4

5

(e) parallel inverter phase voltage, vPIa

0

0.2

0.4

0.6

0.8

1

(f) load real power, pL

Fig. 8. System waveforms for current compensation with load current that has20% 7th harmonic component and a displacement power factor of 0.7.


[4] B. Mwinyiwiwa, B.-T. Ooi, Z. Wolanski, “Multimodular UPFCOperated by Phase-Shifted Triangle Carrier SPWM Strategy,”Conference Record – IEEE Industry Applications Society AnnualMeeting, 1997, pp. 1641-1646.

[5] Y. Chen, B. Mwinyiwiwa, Z. Wolanski, B.-T. Ooi, “Unified Power FlowController (UPFC) Based on Chopper Stabilized Multilevel Converter,”IEEE Power Electronics Specialists Conference, 1997, pp. 331-337.

[6] L. Gyugi, et. al., “The Unified Power Flow Controller: A New Approachto Power Transmission Control,” IEEE Transactions on Power Delivery,vol. 10, no. 2, April 1995, pp. 1085-1093.

[7] J. S. Lai, F. Z. Peng, “Multilevel Converters – A New Breed of PowerConverters,” IEEE Transactions on Industry Applications, vol. 32, no.3, May 1996, pp. 509-517.

[8] G. Joos, L. Moran, “Principles of Active Power Filters,” IEEE – IAS’98Tutorial Course Notes, St. Louis, Missouri, October 1998.

[9] F. Z. Peng, G. W. Ott, Jr., D. J. Adams, “Harmonic and Reactive PowerCompensation Based on the Generalized Instantaneous Reactive Power

Theory for Three-Phase Four-Wire Systems,” IEEE Transactions onPower Electronics, vol. 13, no. 6, Nov. 1998, pp. 1174-1181.

[10] L. M. Tolbert, T. G. Habetler, “Novel Multilevel Inverter Carried-BasedPWM Methods,” Conference Record - IEEE Industry ApplicationsSociety Annual Meeting, 1998, pp. 1424-1431.

[11] L. M. Tolbert, F. Z. Peng, T. G. Habetler, “Multilevel Carrier-BasedPWM Methods at Low Modulation Indices,” IEEE Applied PowerElectronics Conference, 1999, pp. 1032-1039.

[12] L. Rossetto, P. Tenti, “Evaluation of Instantaneous Power Terms inMulti-Phase Systems: Techniques and Applications to Power-Conditioning Equipment,” ETEP, vol. 4, Nov. 1994, pp. 469-475.

-0.6

-0.4

-0.2

0

0.2

0.4

0.6


-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8


-2

-1

0

1

2


-0.6

-0.4

-0.2

0

0.2

0.4

0.6

(d) parallel inverter current for phase a, iPIa

-1

0

1

2

3

4

5


-0.2

0

0.2

0.4

0.6

0.8

1

1.2


Fig. 9. System waveforms for current compensation under unbalanced currentconditions (iLb = - iLa, iLc = 0) using the filter described by (9).

-0.6

-0.4

-0.2

0

0.2

0.4

0.6


-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8


-2

-1

0

1

2


-0.6

-0.4

-0.2

0

0.2

0.4

0.6

(d) parallel inverter current for phase a, iPia

-1

0

1

2

3

4

5


-0.2

0

0.2

0.4

0.6

0.8

1

1.2


Fig. 10. System waveforms for current compensation for unbalanced currentconditions (iLb = - iLa, iLc = 0) using an ideal low-pass active filter.

a multilevel converter-based universal power conditioner

Documents