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Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

aADSP-2186M

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2000

DSPMicrocomputer

FUNCTIONAL BLOCK DIAGRAM

ARITHMETIC UNITS

SHIFTERMACALU

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

POWER-DOWNCONTROL

MEMORY

PROGRAMMEMORY

8K 24 BIT

DATAMEMORY

8K 16 BIT

EXTERNALADDRESS

BUS

EXTERNALDATABUS

BYTE DMACONTROLLER

FULL MEMORY MODE

SPORT0

SERIAL PORTS

SPORT1

PROGRAMMABLEI/O

ANDFLAGS

TIMER

HOST MODE

OR

EXTERNALDATABUS

INTERNALDMAPORT

DAG1

DATA ADDRESSGENERATORS

DAG2

PROGRAMSEQUENCER

ADSP-2100 BASEARCHITECTURE

ICE-Port is a trademark of Analog Devices, Inc.

FEATURES

Performance

13.3 ns Instruction Cycle Time @ 2.5 V (Internal),

75 MIPS Sustained Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby Power

Dissipation with 200 CLKIN Cycle Recovery from

Power-Down Condition

Low Power Dissipation in Idle Mode

Integration

ADSP-2100 Family Code Compatible (Easy to Use

Algebraic Syntax), with Instruction Set Extensions

40K Bytes of On-Chip RAM, Configured as

8K Words Program Memory RAM

8K Words Data Memory RAM

Dual-Purpose Program Memory for Both Instruction and

Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP and 144-Ball Mini-BGA

System Interface

Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;

All Inputs Tolerate up to 3.6 V Regardless of Mode

16-Bit Internal DMA Port for High-Speed Access to

On-Chip Memory (Mode Selectable)

4 MByte Memory Interface for Storage of Data Tables

and Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program

and Data Memory Transfers (Mode Selectable)

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals (Mode Selectable)

Programmable Memory Strobe and Separate I/O

Memory Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

through Internal DMA Port

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

Signaling

UART Emulation through Software SPORT Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging in

Final Systems

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ADSP-2186MTABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 3DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 7Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 7Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 8Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 9Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 10Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . 11Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Memory Mapped Registers (New to the

ADSP-2186M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . 13Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . 14Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . 14Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Byte Memory DMA (BDMA, Full Memory Mode) . . . . 14Internal Memory DMA Port

(IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . 15Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . 15IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . 16Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . 16

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . . 16Target Board Connector for EZ-ICE Probe . . . . . . . . . . 17Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 17

PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . . 17Target System Interface Signals . . . . . . . . . . . . . . . . . . . 17

RECOMMENDED OPERATING CONDITIONS . . . . . 18ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . 18ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . 19TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 19GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . . 19FREQUENCY DEPENDENCY FOR

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 20ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . 20POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . 20Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . . 23Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . 25Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 29IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . . 30IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . . 31IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . . 32IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . . 33IDMA Read, Short Read Cycle in Short Read

Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . . 35LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . 37Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . 38OUTLINE DIMENSIONS

100-Lead Metric Thin Plastic Quad Flatpack (LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

OUTLINE DIMENSIONS144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . . 40

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

TablesTable I. Interrupt Priority and Interrupt

Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table II. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 11Table III. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 12Table IV. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 13Table V. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table VI. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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ADSP-2186M

–3–

GENERAL DESCRIPTIONThe ADSP-2186M is a single-chip microcomputer optimizedfor digital signal processing (DSP) and other high-speed numericprocessing applications.

The ADSP-2186M combines the ADSP-2100 family base archi-tecture (three computational units, data address generators, anda program sequencer) with two serial ports, a 16-bit internal DMAport, a byte DMA port, a programmable timer, Flag I/O, exten-sive interrupt capabilities, and on-chip program and data memory.

The ADSP-2186M integrates 40K bytes of on-chip memoryconfigured as 8K words (24-bit) of program RAM, and 8Kwords (16-bit) of data RAM. Power-down circuitry is also pro-vided to meet the low power needs of battery-operated portableequipment. The ADSP-2186M is available in a 100-lead LQFPpackage and 144 Ball Mini-BGA.

In addition, the ADSP-2186M supports new instructions, whichinclude bit manipulations—bit set, bit clear, bit toggle, bit test—new ALU constants, new multiplication instruction (× squared),biased rounding, result-free ALU operations, I/O memory trans-fers, and global interrupt masking, for increased flexibility.

Fabricated in a high-speed, low-power, CMOS process, theADSP-2186M operates with a 13.3 ns instruction cycle time.Every instruction can execute in a single processor cycle.

The ADSP-2186M’s flexible architecture and comprehensiveinstruction set allow the processor to perform multiple opera-tions in parallel. In one processor cycle, the ADSP-2186M can:

• Generate the next program address• Fetch the next instruction• Perform one or two data moves• Update one or two data address pointers• Perform a computational operation

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports• Receive and/or transmit data through the internal DMA port• Receive and/or transmit data through the byte DMA port• Decrement timer

DEVELOPMENT SYSTEMThe ADSP-2100 Family Development Software, a complete setof tools for software and hardware system development, supportsthe ADSP-2186M. The System Builder provides a high-levelmethod for defining the architecture of systems under develop-ment. The Assembler has an algebraic syntax that is easy toprogram and debug. The Linker combines object files into anexecutable file. The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface to displaydifferent portions of the hardware environment.

The EZ-KIT Lite is a hardware/software kit offering a completeevaluation environment for the ADSP-218x family: an ADSP-2189M-based evaluation board with PC monitor software plusassembler, linker, simulator, and PROM splitter software. TheADSP-2189M EZ-KIT Lite is a low cost, easy to use hardwareplatform on which you can quickly get started with your DSPsoftware design. The EZ-KIT Lite includes the following features:

• 75 MHz ADSP-2189M• Full 16-Bit Stereo Audio I/O with AD73322 Codec• RS-232 Interface• EZ-ICE Connector for Emulator Control• DSP Demo Programs• Evaluation Suite of VisualDSP

The ADSP-218x EZ-ICE® Emulator aids in the hardwaredebugging of an ADSP-2186M system. The ADSP-2186Mintegrates on-chip emulation support with a 14-pin ICE-Portinterface. This interface provides a simpler target board connec-tion that requires fewer mechanical clearance considerationsthan other ADSP-2100 Family EZ-ICEs. The ADSP-2186Mdevice need not be removed from the target system when usingthe EZ-ICE, nor are any adapters needed. Due to the smallfootprint of the EZ-ICE connector, emulation can be supportedin final board designs.

The EZ-ICE performs a full range of functions, including:

• In-target operation• Up to 20 breakpoints• Single-step or full-speed operation• Registers and memory values can be examined and altered• PC upload and download functions• Instruction-level emulation of program booting and execution• Complete assembly and disassembly of instructions• C source-level debugging

See Designing An EZ-ICE-Compatible Target System in theADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) aswell as the Designing an EZ-ICE-Compatible System section ofthis data sheet for the exact specifications of the EZ-ICE targetboard connector.

Additional InformationThis data sheet provides a general overview of ADSP-2186Mfunctionality. For additional information on the architecture andinstruction set of the processor, refer to the ADSP-2100 FamilyUser’s Manual. For more information about the developmenttools, refer to the ADSP-2100 Family Development Toolsdata sheet.

EZ-ICE is a registered trademark of Analog Devices, Inc.

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ADSP-2186M

ARCHITECTURE OVERVIEWThe ADSP-2186M instruction set provides flexible data movesand multifunction (one or two data moves with a computation)instructions. Every instruction can be executed in a singleprocessor cycle. The ADSP-2186M assembly language uses analgebraic syntax for ease of coding and readability. A compre-hensive set of development tools supports program development.

Figure 1 is an overall block diagram of the ADSP-2186M. Theprocessor contains three independent computational units:the ALU, the multiplier/accumulator (MAC), and the shifter.The computational units process 16-bit data directly and haveprovisions to support multiprecision computations. The ALUperforms a standard set of arithmetic and logic operations;division primitives are also supported. The MAC performssingle-cycle multiply, multiply/add, and multiply/subtract opera-tions with 40 bits of accumulation. The shifter performs logicaland arithmetic shifts, normalization, denormalization, andderive exponent operations.

The shifter can be used to efficiently implement numericformat control, including multiword and block floating-pointrepresentations.

The internal result (R) bus connects the computational units sothat the output of any unit may be the input of any unit on thenext cycle.

A powerful program sequencer and two dedicated data addressgenerators ensure efficient delivery of operands to these computa-tional units. The sequencer supports conditional jumps, subroutinecalls, and returns in a single cycle. With internal loop countersand loop stacks, the ADSP-2186M executes looped code withzero overhead; no explicit jump instructions are required tomaintain loops.

Two data address generators (DAGs) provide addresses forsimultaneous dual operand fetches (from data memory andprogram memory). Each DAG maintains and updates fouraddress pointers. Whenever the pointer is used to access data

(indirect addressing), it is post-modified by the value of one offour possible modify registers. A length value may be associatedwith each pointer to implement automatic modulo addressingfor circular buffers.

Efficient data transfer is achieved with the use of fiveinternal buses:

• Program Memory Address (PMA) Bus• Program Memory Data (PMD) Bus• Data Memory Address (DMA) Bus• Data Memory Data (DMD) Bus• Result (R) Bus

The two address buses (PMA and DMA) share a single externaladdress bus, allowing memory to be expanded off-chip, and thetwo data buses (PMD and DMD) share a single external databus. Byte memory space and I/O memory space also share theexternal buses.

Program memory can store both instructions and data, permit-ting the ADSP-2186M to fetch two operands in a single cycle,one from program memory and one from data memory. TheADSP-2186M can fetch an operand from program memory andthe next instruction in the same cycle.

In lieu of the address and data bus for external memory connec-tion, the ADSP-2186M may be configured for 16-bit InternalDMA port (IDMA port) connection to external systems. TheIDMA port is made up of 16 data/address pins and five controlpins. The IDMA port provides transparent, direct access to theDSPs on-chip program and data RAM.

An interface to low-cost byte-wide memory is provided by theByte DMA port (BDMA port). The BDMA port is bidirectionaland can directly address up to four megabytes of external RAMor ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slowmemories and I/O memory-mapped peripherals with program-mable wait state generation. External devices can gain control of

ARITHMETIC UNITS

SHIFTERMACALU

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

POWER-DOWNCONTROL

MEMORY

PROGRAMMEMORY

8K 24 BIT

DATAMEMORY

8K 16 BIT

EXTERNALADDRESS

BUS

EXTERNALDATABUS

BYTE DMACONTROLLER

FULL MEMORY MODE

SPORT0

SERIAL PORTS

SPORT1

PROGRAMMABLEI/O

ANDFLAGS

TIMER

HOST MODE

OR

EXTERNALDATABUS

INTERNALDMAPORT

DAG1

DATA ADDRESSGENERATORS

DAG2

PROGRAMSEQUENCER

ADSP-2100 BASEARCHITECTURE

Figure 1. Functional Block Diagram

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ADSP-2186M

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external buses with bus request/grant signals (BR, BGH, and BG).One execution mode (Go Mode) allows the ADSP-2186M tocontinue running from on-chip memory. Normal executionmode requires the processor to halt while buses are granted.

The ADSP-2186M can respond to eleven interrupts. There canbe up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interruptsgenerated by the timer, the serial ports (SPORTs), the Byte DMAport, and the power-down circuitry. There is also a masterRESET signal. The two serial ports provide a complete synchro-nous serial interface with optional companding in hardware anda wide variety of framed or frameless data transmit and receivemodes of operation.

Each port can generate an internal programmable serial clock oraccept an external serial clock.

The ADSP-2186M provides up to 13 general-purpose flag pins.The data input and output pins on SPORT1 can be alternativelyconfigured as an input flag and an output flag. In addition, eightflags are programmable as inputs or outputs, and three flags arealways outputs.

A programmable interval timer generates periodic interrupts.A 16-bit count register (TCOUNT) decrements every n pro-cessor cycle, where n is a scaling value stored in an 8-bit register(TSCALE). When the value of the count register reaches zero,an interrupt is generated and the count register is reloaded froma 16-bit period register (TPERIOD).

Serial PortsThe ADSP-2186M incorporates two complete synchronousserial ports (SPORT0 and SPORT1) for serial communicationsand multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2186MSPORTs. For additional information on Serial Ports, refer tothe ADSP-2100 Family User’s Manual.

• SPORTs are bidirectional and have a separate, double-buffered transmit and receive section.

• SPORTs can use an external serial clock or generate theirown serial clock internally.

• SPORTs have independent framing for the receive and trans-mit sections. Sections run in a frameless mode or with framesynchronization signals internally or externally generated.Frame sync signals are active high or inverted, with either oftwo pulsewidths and timings.

• SPORTs support serial data word lengths from 3 to 16 bitsand provide optional A-law and µ-law companding accordingto CCITT recommendation G.711.

• SPORT receive and transmit sections can generate uniqueinterrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer ofdata with only one overhead cycle per data word. An interruptis generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receiveand transmit a 24 or 32 word, time- division multiplexed,serial bitstream.

• SPORT1 can be configured to have two external interrupts(IRQ0 and IRQ1) and the FI and FO signals. The internallygenerated serial clock may still be used in this configuration.

PIN DESCRIPTIONSThe ADSP-2186M is available in a 100-lead LQFP packageand a 144-Ball Mini-BGA package. In order to maintain maxi-mum functionality and reduce package size and pin count, someserial port, programmable flag, interrupt and external bus pinshave dual, multiplexed functionality. The external bus pins areconfigured during RESET only, while serial port pins are soft-ware configurable during program execution. Flag and interruptfunctionality is retained concurrently on multiplexed pins. Incases where pin functionality is reconfigurable, the default state isshown in plain text; alternate functionality is shown in italics.

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ADSP-2186MCommon-Mode Pins

Pin Name # of Pins I/O Function

RESET 1 I Processor Reset InputBR 1 I Bus Request InputBG 1 O Bus Grant OutputBGH 1 O Bus Grant Hung OutputDMS 1 O Data Memory Select OutputPMS 1 O Program Memory Select OutputIOMS 1 O Memory Select OutputBMS 1 O Byte Memory Select OutputCMS 1 O Combined Memory Select OutputRD 1 O Memory Read Enable OutputWR 1 O Memory Write Enable Output

IRQ2 1 I Edge- or Level-Sensitive Interrupt Request1

PF7 I/O Programmable I/O Pin

IRQL1 1 I Level-Sensitive Interrupt Requests1


IRQL0 1 I Level-Sensitive Interrupt Requests1


IRQE 1 I Edge-Sensitive Interrupt Requests1


Mode D 1 I Mode Select Input—Checked Only During RESETPF3 I/O Programmable I/O Pin During Normal Operation

Mode C 1 I Mode Select Input—Checked Only During RESETPF2 I/O Programmable I/O Pin During Normal Operation

Mode B 1 I Mode Select Input—Checked Only During RESETPF1 I/O Programmable I/O Pin During Normal Operation

Mode A 1 I Mode Select Input—Checked Only During RESETPF0 I/O Programmable I/O Pin During Normal Operation

CLKIN, XTAL 2 I Clock or Quartz Crystal InputCLKOUT 1 O Processor Clock OutputSPORT0 5 I/O Serial Port I/O PinsSPORT1 5 I/O Serial Port I/O PinsIRQ1:0, FI, FO Edge- or Level-Sensitive Interrupts, FI, FO2

PWD 1 I Power-Down Control InputPWDACK 1 O Power-Down Control OutputFL0, FL1, FL2 3 O Output FlagsVDDINT 2 I Internal VDD (2.5 V) Power (LQFP)VDDEXT 4 I External VDD (2.5 V or 3.3 V) Power (LQFP)GND 10 I Ground (LQFP)VDDINT 4 I Internal VDD (2.5 V) Power (Mini-BGA)VDDEXT 7 I External VDD (2.5 V or 3.3 V) Power (Mini-BGA)GND 20 I Ground (Mini-BGA)EZ-Port 9 I/O For Emulation UseNOTES1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interruptvector address when the pin is asserted, either by external devices, or set as a programmable flag.

2SPORT configuration determined by the DSP System Control Register. Software configurable.

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ADSP-2186M

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Memory Interface PinsThe ADSP-2186M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full exter-nal overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities.The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running.

The following tables list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory orHost). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set. For theshared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinout tables.

Full Memory Mode Pins (Mode C = 0)


A13:0 14 O Address Output Pins for Program, Data, Byte, and I/O SpacesD23:0 24 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also

used as Byte Memory Addresses.)

Host Mode Pins (Mode C = 1)


IAD15:0 16 I/O IDMA Port Address/Data BusA0 1 O Address Pin for External I/O, Program, Data, or Byte Access1

D23:8 16 I/O Data I/O Pins for Program, Data, Byte, and I/O SpacesIWR 1 I IDMA Write EnableIRD 1 I IDMA Read EnableIAL 1 I IDMA Address Latch PinIS 1 I IDMA SelectIACK 1 O IDMA Port Acknowledge Configurable in Mode D; Open Drain

NOTE1In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.

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ADSP-2186MTerminating Unused PinsThe following table shows the recommendations for terminating unused pins.

Pin Terminations

I/O 3-State Reset Hi-Z*

Pin Name (Z) State Caused By Unused Configuration

XTAL I I FloatCLKOUT O O FloatA13:1 or O (Z) Hi-Z BR, EBR FloatIAD12:0 I/O (Z) Hi-Z IS FloatA0 O (Z) Hi-Z BR, EBR FloatD23:8 I/O (Z) Hi-Z BR, EBR FloatD7 or I/O (Z) Hi-Z BR, EBR FloatIWR I I High (Inactive)D6 or I/O (Z) Hi-Z BR, EBR FloatIRD I I BR, EBR High (Inactive)D5 or I/O (Z) Hi-Z FloatIAL I I Low (Inactive)D4 or I/O (Z) Hi-Z BR, EBR FloatIS I I High (Inactive)D3 or I/O (Z) Hi-Z BR, EBR FloatIACK FloatD2:0 or I/O (Z) Hi-Z BR, EBR FloatIAD15:13 I/O (Z) Hi-Z IS FloatPMS O (Z) O BR, EBR FloatDMS O (Z) O BR, EBR FloatBMS O (Z) O BR, EBR FloatIOMS O (Z) O BR, EBR FloatCMS O (Z) O BR, EBR FloatRD O (Z) O BR, EBR FloatWR O (Z) O BR, EBR FloatBR I I High (Inactive)BG O (Z) O EE FloatBGH O O FloatIRQ2/PF7 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let FloatIRQL1/PF6 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let FloatIRQL0/PF5 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let FloatIRQE/PF4 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let FloatSCLK0 I/O I Input = High or Low, Output = FloatRFS0 I/O I High or LowDR0 I I High or LowTFS0 I/O I High or LowDT0 O O FloatSCLK1 I/O I Input = High or Low, Output = FloatRFS1/IRQ0 I/O I High or LowDR1/FI I I High or LowTFS1/IRQ1 I/O I High or LowDT1/FO O O FloatEE I I FloatEBR I I FloatEBG O O FloatERESET I I FloatEMS O O FloatEINT I I FloatECLK I I FloatELIN I I FloatELOUT O O FloatNOTES*Hi-Z = High Impedance.1. If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.2. If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as inter-

rupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1, prior to enabling interrupts, and let pins float.3. All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.4. CLKIN, RESET, and PF3:0/MODE D:A are not included in the table because these pins must be used.

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InterruptsThe interrupt controller allows the processor to respond to the11 possible interrupts and reset with minimum overhead. TheADSP-2186M provides four dedicated external interrupt inputpins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7:4pins). In addition, SPORT1 may be reconfigured for IRQ0,IRQ1, FI and FO, for a total of six external interrupts. TheADSP-2186M also supports internal interrupts from the timer,the byte DMA port, the two serial ports, software, and the power-down control circuit. The interrupt levels are internally prioritizedand individually maskable (except power- down and reset). TheIRQ2, IRQ0, and IRQ1 input pins can be programmed to beeither level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive. The priorities and vectoraddresses of all interrupts are shown in Table I.

Table I. Interrupt Priority and Interrupt Vector Addresses

Interrupt VectorSource Of Interrupt Address (Hex)

Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)Power-Down (Nonmaskable) 002CIRQ2 0004IRQL1 0008IRQL0 000CSPORT0 Transmit 0010SPORT0 Receive 0014IRQE 0018BDMA Interrupt 001CSPORT1 Transmit or IRQ1 0020SPORT1 Receive or IRQ0 0024Timer 0028 (Lowest Priority)

Interrupt routines can either be nested with higher priority inter-rupts taking precedence or processed sequentially. Interruptscan be masked or unmasked with the IMASK register. Individualinterrupt requests are logically ANDed with the bits in IMASK;the highest priority unmasked interrupt is then selected. Thepower-down interrupt is nonmaskable.

The ADSP-2186M masks all interrupts for one instructioncycle following the execution of an instruction that modifies theIMASK register. This does not affect serial port autobufferingor DMA transfers.

The interrupt control register, ICNTL, controls interrupt nest-ing and defines the IRQ0, IRQ1, and IRQ2 external interruptsto be either edge- or level-sensitive. The IRQE pin is an exter-nal edge sensitive interrupt and can be forced and cleared. TheIRQL0 and IRQL1 pins are external level sensitive interrupts.

The IFC register is a write-only register used to force and clearinterrupts. On-chip stacks preserve the processor status and areautomatically maintained during interrupt handling. The stacksare twelve levels deep to allow interrupt, loop, and subroutinenesting. The following instructions allow global enable or disableservicing of the interrupts (including power down), regardless

of the state of IMASK. Disabling the interrupts does not affectserial port autobuffering or DMA.

ENA INTS;DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATIONThe ADSP-2186M has three low power modes that significantlyreduce the power dissipation when the device operates understandby conditions. These modes are:

• Power-Down• Idle• Slow Idle

The CLKOUT pin may also be disabled to reduce externalpower dissipation.

Power-DownThe ADSP-2186M processor has a low power feature that letsthe processor enter a very low-power dormant state throughhardware or software control. Following is a brief list of power-down features. Refer to the ADSP-2100 Family User’s Manual,“System Interface” chapter, for detailed information about thepower-down feature.

• Quick recovery from power-down. The processor beginsexecuting instructions in as few as 200 CLKIN cycles.

• Support for an externally generated TTL or CMOS processorclock. The external clock can continue running during power-down without affecting the lowest power rating and 200 CLKINcycle recovery.

• Support for crystal operation includes disabling the oscillatorto save power (the processor automatically waits approximately4096 CLKIN cycles for the crystal oscillator to start or stabi-lize), and letting the oscillator run to allow 200 CLKIN cyclestart-up.

• Power-down is initiated by either the power-down pin (PWD)or the software power-down force bit. Interrupt support allowsan unlimited number of instructions to be executed beforeoptionally powering down. The power-down interrupt alsocan be used as a nonmaskable, edge-sensitive interrupt.

• Context clear/save control allows the processor to continuewhere it left off or start with a clean context when leaving thepower-down state.

• The RESET pin also can be used to terminate power-down.

• Power-down acknowledge pin indicates when the processorhas entered power-down.

IdleWhen the ADSP-2186M is in the Idle Mode, the processorwaits indefinitely in a low-power state until an interrupt occurs.When an unmasked interrupt occurs, it is serviced; executionthen continues with the instruction following the IDLE instruc-tion. In Idle mode IDMA, BDMA and autobuffer cycle stealsstill occur.

REV. 0–10–

ADSP-2186MSlow IdleThe IDLE instruction is enhanced on the ADSP-2186M to letthe processor’s internal clock signal be slowed, further reducingpower consumption. The reduced clock frequency, a program-mable fraction of the normal clock rate, is specified by a selectabledivisor given in the IDLE instruction.

The format of the instruction is:

IDLE (n);

where n = 16, 32, 64, or 128. This instruction keeps the proces-sor fully functional, but operating at the slower clock rate. Whileit is in this state, the processor’s other internal clock signals, suchas SCLK, CLKOUT, and timer clock, are reduced by the sameratio. The default form of the instruction, when no clock divisoris given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows downthe processor’s internal clock and thus its response time to incom-ing interrupts. The one-cycle response time of the standard idlestate is increased by n, the clock divisor. When an enabled inter-rupt is received, the ADSP-2186M will remain in the idle statefor up to a maximum of n processor cycles (n = 16, 32, 64, or128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have anexternally generated serial clock (SCLK), the serial clock ratemay be faster than the processor’s reduced internal clock rate.Under these conditions, interrupts must not be generated at afaster than can be serviced, due to the additional time theprocessor takes to come out of the idle state (a maximum of nprocessor cycles).

SYSTEM INTERFACEFigure 2 shows typical basic system configurations with theADSP-2186M, two serial devices, a byte-wide EPROM, andoptional external program and data overlay memories (mode-selectable). Programmable wait state generation allows theprocessor to connect easily to slow peripheral devices. The

ADSP-2186M also provides four external interrupts and twoserial ports or six external interrupts and one serial port. HostMemory Mode allows access to the full external data bus, butlimits addressing to a single address bit (A0). Through the useof external hardware, additional system peripherals can be addedin this mode to generate and latch address signals.

Clock SignalsThe ADSP-2186M can be clocked by either a crystal or aTTL-compatible clock signal.

The CLKIN input cannot be halted, changed during opera-tion, nor operated below the specified frequency during normaloperation. The only exception is while the processor is in thepower-down state. For additional information, refer to Chap-ter 9, ADSP-2100 Family User’s Manual, for detailed informationon this power-down feature.

If an external clock is used, it should be a TTL-compatible signalrunning at half the instruction rate. The signal is connected tothe processor’s CLKIN input. When an external clock is used,the XTAL input must be left unconnected.

The ADSP-2186M uses an input clock with a frequency equal tohalf the instruction rate; a 37.50 MHz input clock yields a 13 nsprocessor cycle (which is equivalent to 75 MHz). Normally,instructions are executed in a single processor cycle. All devicetiming is relative to the internal instruction clock rate, which isindicated by the CLKOUT signal when enabled.

Because the ADSP-2186M includes an on-chip oscillator circuit,an external crystal may be used. The crystal should be connectedacross the CLKIN and XTAL pins, with two capacitors con-nected as shown in Figure 3. Capacitor values are dependent oncrystal type and should be specified by the crystal manufacturer.A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used.

A clock output (CLKOUT) signal is generated by the processorat the processor’s cycle rate. This can be enabled and disabled bythe CLKODIS bit in the SPORT0 Autobuffer Control Register.

1/2x CLOCKOR

CRYSTALFL0–2

CLKIN

XTAL

SERIALDEVICE

SCLK1RFS1 OR IRQ0TFS1 OR IRQ1DT1 OR FODR1 OR FI

SPORT1

SERIALDEVICE

A0–A21

DATA

BYTEMEMORY

I/O SPACE(PERIPHERALS)DATA

ADDR

DATA

ADDR

2048 LOCATIONS

OVERLAYMEMORY

TWO 8KPM SEGMENTS

TWO 8KDM SEGMENTS

D23–0

A13–0

D23–8

A10–0

D15–8

D23–16

A13–014

24

SCLK0RFS0TFS0DT0DR0

SPORT0

ADDR13–0

DATA23–0

ADSP-2186M

CS

CS

1/2x CLOCKOR

CRYSTAL

SERIALDEVICE

SPORT1

16

IDMA PORT

SERIALDEVICE

SPORT0

1

16

ADSP-2186M

HOST MEMORY MODEFULL MEMORY MODE

MODE D/PF3MODE C/PF2

MODE B/PF1MODE A/PF0

SYSTEMINTERFACE

ORCONTROLLER

IRQ2/PF7IRQE/PF4IRQL0/PF5IRQL1/PF6

IOMS

BMS

PMSDMSCMS

BRBG

BGHPWD

PWDACK

WRRD

ADSP-2186MCLKIN

XTAL

FL0–2

SCLK1RFS1 OR IRQ0TFS1 OR IRQ1DT1 OR FODR1 OR FI

IRD/D6IWR/D7IS/D4IAL/D5IACK/D3IAD15–0

SCLK0RFS0TFS0DT0DR0

IRQ2/PF7IRQE/PF4IRQL0/PF5IRQL1/PF6

MODE D/PF3MODE C/PF2

MODE B/PF1MODE A/PF0

A0

DATA23–8

IOMS

BMS

PMSDMSCMS

BRBG

BGHPWD

PWDACK

WRRD

Figure 2. Basic System Interface

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–11–

CLKIN XTAL CLKOUT

DSP

Figure 3. External Crystal Connections

RESETThe RESET signal initiates a master reset of the ADSP-2186M.The RESET signal must be asserted during the power-upsequence to assure proper initialization. RESET during initialpower-up must be held long enough to allow the internal clockto stabilize. If RESET is activated any time after power-up, theclock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for thecrystal oscillator circuit to stabilize after a valid VDD is applied tothe processor, and for the internal phase-locked loop (PLL) to lockonto the specific crystal frequency. A minimum of 2000 CLKINcycles ensures that the PLL has locked but does not include thecrystal oscillator start-up time. During this power-up sequencethe RESET signal should be held low. On any subsequent resets,the RESET signal must meet the minimum pulsewidth specifi-cation, tRSP.

The RESET input contains some hysteresis; however, if anRC circuit is used to generate the RESET signal, the use of anexternal Schmidt trigger is recommended.

The master reset sets all internal stack pointers to the empty stackcondition, masks all interrupts, and clears the MSTAT register.When RESET is released, if there is no pending bus request andthe chip is configured for booting, the boot-loading sequence is

Table II. Modes of Operation

MODE D MODE C MODE B MODE A Booting Method

X 0 0 0 BDMA feature is used to load the first 32 program memory words fromthe byte memory space. Program execution is held off until all 32 wordshave been loaded. Chip is configured in Full Memory Mode.1

X 0 1 0 No automatic boot operations occur. Program execution starts at externalmemory location 0. Chip is configured in Full Memory Mode. BDMA canstill be used, but the processor does not automatically use or wait for theseoperations.

0 1 0 0 BDMA feature is used to load the first 32 program memory words fromthe byte memory space. Program execution is held off until all 32 wordshave been loaded. Chip is configured in Host Mode. IACK has activepull-down. (REQUIRES ADDITIONAL HARDWARE).

0 1 0 1 IDMA feature is used to load any internal memory as desired. Programexecution is held off until internal program memory location 0 is writtento. Chip is configured in Host Mode. IACK has active pull-down.1

1 1 0 0 BDMA feature is used to load the first 32 program memory words fromthe byte memory space. Program execution is held off until all 32 wordshave been loaded. Chip is configured in Host Mode; IACK requires exter-nal pull down. (REQUIRES ADDITIONAL HARDWARE)

1 1 0 1 IDMA feature is used to load any internal memory as desired. Programexecution is held off until internal program memory location 0 is writtento. Chip is configured in Host Mode. IACK requires external pull-down.1

NOTE1Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

performed. The first instruction is fetched from on-chip pro-gram memory location 0x0000 once boot loading completes.

Power SuppliesThe ADSP-2186M has separate power supply connections forthe internal (VDDINT) and external (VDDEXT) power supplies.The internal supply must meet the 2.5 V requirement. Theexternal supply can be connected to either a 2.5 V or 3.3 V supply.All external supply pins must be connected to the same supply.All input and I/O pins can tolerate input voltages up to 3.6 V,regardless of the external supply voltage. This feature providesmaximum flexibility in mixing 2.5 V and 3.3 V components.

MODES OF OPERATIONSetting Memory ModeMemory Mode selection for the ADSP-2186M is made duringchip reset through the use of the Mode C pin. This pin is multi-plexed with the DSP’s PF2 pin, so care must be taken in howthe mode selection is made. The two methods for selecting thevalue of Mode C are active and passive.

Passive ConfigurationPassive Configuration involves the use a pull-up or pull-downresistor connected to the Mode C pin. To minimize power con-sumption, or if the PF2 pin is to be used as an output in the DSPapplication, a weak pull-up or pull-down, on the order of 10 kΩ,can be used. This value should be sufficient to pull the pin to thedesired level and still allow the pin to operate as a programmableflag output without undue strain on the processor’s output driver.For minimum power consumption during power-down, recon-figure PF2 to be an input, as the pull-up or pull-down willhold the pin in a known state, and will not switch.

REV. 0–12–

ADSP-2186MActive ConfigurationActive Configuration involves the use of a three-statable externaldriver connected to the Mode C pin. A driver’s output enableshould be connected to the DSP’s RESET signal such that itonly drives the PF2 pin when RESET is active (low). WhenRESET is deasserted, the driver should three-state, thus allow-ing full use of the PF2 pin as either an input or output. Tominimize power consumption during power-down, configurethe programmable flag as an output when connected to a three-stated buffer. This ensures that the pin will be held at a constantlevel, and will not oscillate should the three-state driver’s levelhover around the logic switching point.

IACK ConfigurationMode D = 0 and in host mode: IACK is an active, driven signaland cannot be “wire OR’d.”

Mode D = 1 and in host mode: IACK is an open drain andrequires an external pull-down, but multiple IACK pins can be“wire OR’d” together.

MEMORY ARCHITECTUREThe ADSP-2186M provides a variety of memory and peripheralinterface options. The key functional groups are Program Memory,Data Memory, Byte Memory, and I/O. Refer to the followingfigures and tables for PM and DM memory allocations in theADSP-2186M.

Program MemoryProgram Memory (Full Memory Mode) is a 24-bit-widespace for storing both instruction opcodes and data. The ADSP-2186M has 8K words of Program Memory RAM on chip, andthe capability of accessing up to two 8K external memory over-lay spaces using the external data bus.

Program Memory (Host Mode) allows access to all internalmemory. External overlay access is limited by a single externaladdress line (A0). External program execution is not available inhost mode due to a restricted data bus that is 16 bits wide only.

ACCESSIBLE WHENPMOVLAY = 0

0x0000 –0x1FFF2

EXTERNALMEMORY

0x0000 –0x1FFF2

RESERVED


0x2000 –0x3FFF2

0x2000 –0x3FFF2

EXTERNALMEMORY


PMOVLAY = 0RESERVED

0x2000 –0x3FFF

PM (MODE B = 0)

ALWAYSACCESSIBLEAT ADDRESS0x0000 – 0x1FFF

PM (MODE B = 1)1

RESERVED

NOTES:1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 02SEE TABLE III FOR PMOVLAY BITS

RESERVED

0x2000 –0x3FFF

0x3FFF

8KINTERNAL

0x0000

8K EXTERNALPMOVLAY = 1, 2

0x1FFF

0x2000

PROGRAM MEMORYMODE B = 0 ADDRESS

0x3FFF

8K EXTERNALPMOVLAY = 0

0x0000

RESERVED

0x1FFF

0x2000

PROGRAM MEMORYMODE B = 1 ADDRESS

Figure 4. Program Memory

Table III. PMOVLAY Bits

PMOVLAY Memory A13 A12:0

0 Reserved Not Applicable Not Applicable1 External Overlay 1 0 13 LSBs of Address Between 0x2000 and 0x3FFF2 External Overlay 2 1 13 LSBs of Address Between 0x2000 and 0x3FFF

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Data MemoryData Memory (Full Memory Mode) is a 16-bit-wide space usedfor the storage of data variables and for memory-mapped controlregisters. The ADSP-2186M has 8K words on Data MemoryRAM on-chip. Part of this space is used by 32 memory-mappedregisters. Support also exists for up to two 8K external memoryoverlay spaces through the external data bus. All internal accesses

ACCESSIBLE WHENDMOVLAY = 2

ACCESSIBLE WHENDMOVLAY = 1

0x0000 – 0x1FFF1

0x0000 – 0x1FFF1

EXTERNALMEMORY

32 MEMORYMAPPED

REGISTERS

0x3FFF

INTERNAL8160 WORDS

0x0000

DATA MEMORY ADDR

0x3FE0

EXTERNAL 8KDMOVLAY = 1, 2

0x1FFF

0x3FDF

0x2000

DM OVLAY = 0RESERVED

0x0000 – 0x1FFF

DATA MEMORY


NOTE:1SEE TABLE IV FOR DMOVLAY BITS

Figure 5. Data Memory Map

complete in one cycle. Accesses to external memory are timedusing the wait states specified by the DWAIT register and thewait state mode bit.

Data Memory (Host Mode) allows access to all internalmemory. External overlay access is limited by a single externaladdress line (A0).

Table IV. DMOVLAY Bits

DMOVLAY Memory A13 A12:0

0 Reserved Not Applicable Not Applicable1 External Overlay 1 0 13 LSBs of Address Between 0x2000 and 0x3FFF2 External Overlay 2 1 13 LSBs of Address Between 0x2000 and 0x3FFF

Memory Mapped Registers (New to the ADSP-2186M)The ADSP-2186M has three memory mapped registers that differfrom other ADSP-21xx Family DSPs. The slight modificationsto these registers (Wait State Control, Programmable Flag andComposite Select Control, and System Control) provide theADSP-2186M’s wait state and BMS control features. Defaultbit values at reset are shown; if no value is shown, the bit is unde-fined at reset. Reserved bits are shown on a grey field. These bitsshould always be written with zeros.

DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0

DM(0x3FFE)

WAITSTATE CONTROL

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WAIT STATE MODE SELECT0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING

FROM 0 TO 7)1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING

FROM 0 TO 15)

Figure 6. Wait State Control Register

BMWAIT CMSSEL0 = DISABLE CMS1 = ENABLE CMS

DM(0x3FE6)

PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL

PFTYPE0 = INPUT1 = OUTPUT

(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)

1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Figure 7. Programmable Flag and Composite ControlRegister

RESERVED, ALWAYSSET TO 0

SPORT0 ENABLE0 = DISABLE1 = ENABLE

DM(0x3FFF)

SYSTEM CONTROL

SPORT1 ENABLE0 = DISABLE1 = ENABLE

SPORT1 CONFIGURE0 = FI, FO, IRQ0, IRQ1, SCLK1 = SPORT1

DISABLE BMS0 = ENABLE BMS1 = DISABLE BMS, EXCEPT WHEN MEMORY STROBES ARE THREE-STATED

PWAITPROGRAM MEMORYWAIT STATES

0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULDALWAYS BE WRITTEN WITH ZEROS.

RESERVEDSET TO 0

Figure 8. System Control Register

I/O Space (Full Memory Mode)The ADSP-2186M supports an additional external memoryspace called I/O space. This space is designed to support simpleconnections to peripherals (such as data converters and externalregisters) or to bus interface ASIC data registers. I/O space sup-ports 2048 locations of 16-bit wide data. The lower eleven bitsof the external address bus are used; the upper three bits areundefined. Two instructions were added to the core ADSP-2100Family instruction set to read from and write to I/O memoryspace. The I/O space also has four dedicated three-bit wait stateregisters, IOWAIT0–3, which in combination with the wait statemode bit, specify up to 15 wait states to be automatically gener-ated for each of four regions. The wait states act on addressranges as shown in Table V.

REV. 0–14–

ADSP-2186MTable V. Wait States

Address Range Wait State Register

0x000–0x1FF IOWAIT0 and Wait State Mode Select Bit0x200–0x3FF IOWAIT1 and Wait State Mode Select Bit0x400–0x5FF IOWAIT2 and Wait State Mode Select Bit0x600–0x7FF IOWAIT3 and Wait State Mode Select Bit

Composite Memory Select (CMS)The ADSP-2186M has a programmable memory select signal thatis useful for generating memory select signals for memoriesmapped to more than one space. The CMS signal is gener-ated to have the same timing as each of the individual memoryselect signals (PMS, DMS, BMS, IOMS) but can combine theirfunctionality.

Each bit in the CMSSEL register, when set, causes the CMSsignal to be asserted when the selected memory select isasserted. For example, to use a 32K word memory to act as bothprogram and data memory, set the PMS and DMS bits in theCMSSEL register and use the CMS pin to drive the chipselect of the memory, and use either DMS or PMS as theadditional address bit.

The CMS pin functions like the other memory select signalswith the same timing and bus request logic. A 1 in the enable bitcauses the assertion of the CMS signal at the same time as theselected memory select signal. All enable bits default to 1 at reset,except the BMS bit.

Byte Memory Select (BMS)The ADSP-2186M’s BMS disable feature combined with theCMS pin allows use of multiple memories in the byte memoryspace. For example, an EPROM could be attached to the BMSselect, and an SRAM could be connected to CMS. Because atreset BMS is enabled, the EPROM would be used for booting.After booting, software could disable BMS and set the CMSsignal to respond to BMS, enabling the SRAM.

Byte MemoryThe byte memory space is a bidirectional, 8-bit-wide, externalmemory space used to store programs and data. Byte memory isaccessed using the BDMA feature. The byte memory space con-sists of 256 pages, each of which is 16K × 8.

The byte memory space on the ADSP-2186M supports read andwrite operations as well as four different data formats. The bytememory uses data bits 15:8 for data. The byte memory uses databits 23:16 and address bits 13:0 to create a 22-bit address. Thisallows up to a 4 meg × 8 (32 megabit) ROM or RAM to be usedwithout glue logic. All byte memory accesses are timed by theBMWAIT register and the wait state mode bit.

Byte Memory DMA (BDMA, Full Memory Mode)The byte memory DMA controller allows loading and storing ofprogram instructions and data using the byte memory space. TheBDMA circuit is able to access the byte memory space while theprocessor is operating normally and steals only one DSP cycleper 8-, 16- or 24-bit word transferred.

BDMA CONTROL

BMPAGE BTYPEBDIR0 = LOAD FROM BM1 = STORE TO BM

BCR0 = RUN DURING BDMA1 = HALT DURING BDMA

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x3FE3)

BDMAOVERLAY

BITS*

THESE BITS SHOULD ALWAYSBE WRITTEN WITH ZEROS.

*

Figure 9. BDMA Control Register

The BDMA circuit supports four different data formats that areselected by the BTYPE register field. The appropriate numberof 8-bit accesses are done from the byte memory space to buildthe word size selected. Table VI shows the data formats sup-ported by the BDMA circuit.

Table VI. Data Formats

BTYPE Internal Memory Space Word Size Alignment

00 Program Memory 24 Full Word01 Data Memory 16 Full Word10 Data Memory 8 MSBs11 Data Memory 8 LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.The BIAD register field is used to specify the starting addressfor the on-chip memory involved with the transfer. The 14-bitBEAD register specifies the starting address for the external bytememory space. The 8-bit BMPAGE register specifies the start-ing page for the external byte memory space. The BDIR registerfield selects the direction of the transfer. Finally, the 14-bitBWCOUNT register specifies the number of DSP words totransfer and initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequentialaddressing. A BDMA interrupt is generated on the completionof the number of transfers specified by the BWCOUNT register.

The BWCOUNT register is updated after each transfer so it canbe used to check the status of the transfers. When it reaches zero,the transfers have finished and a BDMA interrupt is generated.The BMPAGE and BEAD registers must not be accessed by theDSP during BDMA operations.

The source or destination of a BDMA transfer will always beon-chip program or data memory.

When the BWCOUNT register is written with a nonzero valuethe BDMA circuit starts executing byte memory accesses with waitstates set by BMWAIT. These accesses continue until the countreaches zero. When enough accesses have occurred to create adestination word, it is transferred to or from on-chip memory.The transfer takes one DSP cycle. DSP accesses to externalmemory have priority over BDMA byte memory accesses.

The BDMA Context Reset bit (BCR) controls whether theprocessor is held off while the BDMA accesses are occurring.Setting the BCR bit to 0 allows the processor to continue opera-tions. Setting the BCR bit to 1 causes the processor to stopexecution while the BDMA accesses are occurring, to clear thecontext of the processor, and start execution at address 0 whenthe BDMA accesses have completed.

REV. 0

ADSP-2186M

–15–

The BDMA overlay bits specify the OVLAY memory blocks tobe accessed for internal memory. For ADSP-2186M, set to zeroBDMA overlay bits in BDMA control register.

The BMWAIT field, which has four bits on ADSP-2186M,allows selection of up to 15 wait states for BDMA transfers.

Internal Memory DMA Port (IDMA Port; Host MemoryMode)The IDMA Port provides an efficient means of communicationbetween a host system and the ADSP-2186M. The port is usedto access the on-chip program memory and data memory of theDSP with only one DSP cycle per word overhead. The IDMAport cannot, however, be used to write to the DSP’s memory-mapped control registers. A typical IDMA transfer process isdescribed as follows:

1. Host starts IDMA transfer.

2. Host checks IACK control line to see if the DSP is busy.

3. Host uses IS and IAL control lines to latch either the DMAstarting address (IDMAA) or the PM/DM OVLAY selectioninto the DSP’s IDMA control registers. If Bit 15 = 1, thevalue of bits 7:0 represent the IDMA overlay: bits 14:8 mustbe set to 0. If Bit 15 = 0, the value of Bits 13:0 represent thestarting address of internal memory to be accessed andBit 14 reflects PM or DM for access. For ADSP-2186M,IDDMOVLAY and IDPMOVLAY bits in IDMA overlayregister should be set to zero.

4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-nal memory (PM or DM).

5. Host checks IACK line to see if the DSP has completed theprevious IDMA operation.

6. Host ends IDMA transfer.

The IDMA port has a 16-bit multiplexed address and data busand supports 24-bit program memory. The IDMA port is com-pletely asynchronous and can be written while the ADSP-2186Mis operating at full speed.

The DSP memory address is latched and then automatically incre-mented after each IDMA transaction. An external device cantherefore access a block of sequentially addressed memory byspecifying only the starting address of the block. This increasesthroughput as the address does not have to be sent for eachmemory access.

IDMA Port access occurs in two phases. The first is the IDMAAddress Latch cycle. When the acknowledge is asserted, a 14-bitaddress and 1-bit destination type can be driven onto the bus byan external device. The address specifies an on-chip memorylocation, the destination type specifies whether it is a DM orPM access. The falling edge of the IDMA address latch signal(IAL) or the missing edge of the IDMA select signal (IS) latchesthis value into the IDMAA register.

Once the address is stored, data can be read from, or written to,the ADSP-2186M’s on-chip memory. Asserting the select line(IS) and the appropriate read or write line (IRD and IWRrespectively) signals the ADSP-2186M that a particular transac-tion is required. In either case, there is a one-processor-cycledelay for synchronization. The memory access consumes oneadditional processor cycle.

Once an access has occurred, the latched address is automati-cally incremented, and another access can occur.

Through the IDMAA register, the DSP can also specify thestarting address and data format for DMA operation. Assertingthe IDMA port select (IS) and address latch enable (IAL) directsthe ADSP-2186M to write the address onto the IAD0–14 businto the IDMA Control Register. If Bit 15 is set to 0, IDMAlatches the address. If Bit 15 is set to 1, IDMA latches into theOVLAY register. This register, shown below, is memory mappedat address DM (0x3FE0). Note that the latched address (IDMAA)cannot be read back by the host. When Bit 14 in 0x3FE7 is setto 1, timing in Figure 31 applies for short reads. When Bit 14in 0x3FE7 is set to zero, short reads use the timing shown in Fig-ure 32. For ADSP-2186M, IDDMOVLAY and IDPMOVLAYbits in IDMA overlay register should be set to zero.

Refer to the following figures for more information on IDMAand DMA memory maps.

IDMA OVERLAY

DM (0x3FE7)

RESERVED SET TO 01,2 IDDMOVLAY2 IDPMOVLAY2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SHORT READ ONLY0 = ENABLE1 = DISABLE

IDMA CONTROL (U = UNDEFINED AT RESET)

DM (0x3FE0)

IDMAA ADDRESS

U U U U U U U U U U U U U U U

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IDMAD DESTINATION MEMORY TYPE0 = PM1 = DM

NOTES:1RESERVED BITS ARE SHOWN ON A GRAY FIELD.2THESE BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS.

0

RESERVED SET TO 0

0

RESERVED SET TO 0

Figure 10. IDMA Control/OVLAY Registers

RESERVED

0x2000 –0x3FFF

DMA PROGRAM MEMORY


0x0000 –0x1FFF

DMADATA MEMORY


NOTE: IDMA AND BDMA HAVE SEPARATE DMA CONTROL REGISTERS.

RESERVED

Figure 11. Direct Memory Access—PM and DMMemory Maps

Bootstrap Loading (Booting)The ADSP-2186M has two mechanisms to allow automatic load-ing of the internal program memory after reset. The method forbooting is controlled by the Mode A, B, and C configuration bits.

When the MODE pins specify BDMA booting, the ADSP-2186Minitiates a BDMA boot sequence when reset is released.

The BDMA interface is set up during reset to the followingdefaults when BDMA booting is specified: the BDIR, BMPAGE,BIAD, and BEAD registers are set to 0, the BTYPE register isset to 0 to specify program memory 24-bit words, and theBWCOUNT register is set to 32. This causes 32 words ofon-chip program memory to be loaded from byte memory.

REV. 0–16–

ADSP-2186MThese 32 words are used to set up the BDMA to load in theremaining program code. The BCR bit is also set to 1, whichcauses program execution to be held off until all 32 words areloaded into on-chip program memory. Execution then begins ataddress 0.

The ADSP-2100 Family development software (Revision 5.02and later) fully supports the BDMA booting feature and cangenerate byte-memory space-compatible boot code.

The IDLE instruction can also be used to allow the processorto hold off execution while booting continues through theBDMA interface. For BDMA accesses while in Host Mode, theaddresses to boot memory must be constructed externally to theADSP-2186M. The only memory address bit provided by theprocessor is A0.

IDMA Port BootingThe ADSP-2186M can also boot programs through its InternalDMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, theADSP-2186M boots from the IDMA port. IDMA feature canload as much on-chip memory as desired. Program execution isheld off until on-chip program memory location 0 is written to.

Bus Request and Bus GrantThe ADSP-2186M can relinquish control of the data and addressbuses to an external device. When the external device requiresaccess to memory, it asserts the bus request (BR) signal. If theADSP-2186M is not performing an external memory access, itresponds to the active BR input in the following processor cycle by:

• Three-stating the data and address buses and the PMS, DMS,BMS, CMS, IOMS, RD, WR output drivers,

• Asserting the bus grant (BG) signal, and

• Halting program execution.

If Go Mode is enabled, the ADSP-2186M will not halt programexecution until it encounters an instruction that requires anexternal memory access.

If the ADSP-2186M is performing an external memory accesswhen the external device asserts the BR signal, it will not three-state the memory interfaces nor assert the BG signal until theprocessor cycle after the access completes. The instruction doesnot need to be completed when the bus is granted. If a singleinstruction requires two external memory accesses, the bus willbe granted between the two accesses.

When the BR signal is released, the processor releases the BGsignal, re-enables the output drivers, and continues programexecution from the point at which it stopped.

The bus request feature operates at all times, including whenthe processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-2186M requires theexternal bus for a memory or BDMA access, but is stopped.The other device can release the bus by deasserting bus request.Once the bus is released, the ADSP-2186M deasserts BG andBGH and executes the external memory access.

Flag I/O PinsThe ADSP-2186M has eight general purpose programmableinput/output flag pins. They are controlled by two memorymapped registers. The PFTYPE register determines the direc-tion, 1 = output and 0 = input. The PFDATA register is used to

read and write the values on the pins. Data being read from apin configured as an input is synchronized to the ADSP-2186M’sclock. Bits that are programmed as outputs will read the valuebeing output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2186M has fivefixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0–FL2 arededicated output flags. FI and FO are available as an alternateconfiguration of SPORT1.

Note: Pins PF0, PF1, PF2, and PF3 are also used for deviceconfiguration during reset.

Instruction Set DescriptionThe ADSP-2186M assembly language instruction set has analgebraic syntax that was designed for ease of coding and read-ability. The assembly language, which takes full advantage of theprocessor’s unique architecture, offers the following benefits:

• The algebraic syntax eliminates the need to remember crypticassembler mnemonics. For example, a typical arithmetic addinstruction, such as AR = AX0 + AY0, resembles a simpleequation.

• Every instruction assembles into a single, 24-bit word thatcan execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly lan-guage and is completely source and object code compatiblewith other family members. Programs may need to be relocatedto utilize on-chip memory and conform to the ADSP-2186M’sinterrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional jump,call, return, or arithmetic instructions, the condition canbe checked and the operation executed in the same instruc-tion cycle.

• Multifunction instructions allow parallel execution of anarithmetic instruction with up to two fetches or one write toprocessor memory space during a single instruction cycle.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEMThe ADSP-2186M has on-chip emulation support and anICE-Port, a special set of pins that interface to the EZ-ICE.These features allow in-circuit emulation without replacing thetarget system processor by using only a 14-pin connection fromthe target system to the EZ-ICE. Target systems must have a14-pin connector to accept the EZ-ICE’s in-circuit probe, a14-pin plug.

Issuing the chip reset command during emulation causes theDSP to perform a full chip reset, including a reset of its memorymode. Therefore, it is vital that the mode pins are set correctlyPRIOR to issuing a chip reset command from the emulator userinterface. If a passive method of maintaining mode information isbeing used (as discussed in Setting Memory Modes), it does notmatter that the mode information is latched by an emulatorreset. However, if the RESET pin is being used as a method ofsetting the value of the mode pins, the effects of an emulatorreset must be taken into consideration.

One method of ensuring that the values located on the modepins are those desired is to construct a circuit like the one shownin Figure 12. This circuit forces the value located on the ModeA pin to logic high; regardless of whether it is latched via theRESET or ERESET pin.

REV. 0

ADSP-2186M

–17–

PROGRAMMABLE I/O

MODE A/PFO

RESET

ERESET

1k

ADSP-2186M

Figure 12. Mode A Pin/EZ-ICE Circuit

See the ADSP-2100 Family EZ-Tools data sheet for completeinformation on ICE products.

The ICE-Port interface consists of the following ADSP-2186Mpins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS,and ELOUT

These ADSP-2186M pins must be connected only to the EZ-ICEconnector in the target system. These pins have no function exceptduring emulation, and do not require pull-up or pull-downresistors. The traces for these signals between the ADSP-2186Mand the connector must be kept as short as possible, no longerthan 3 inches.

The following pins are also used by the EZ-ICE: BR, BG,RESET, and GND.

The EZ-ICE uses the EE (emulator enable) signal to take con-trol of the ADSP-2186M in the target system. This causes theprocessor to use its ERESET, EBR, and EBG pins instead ofthe RESET, BR, and BG pins. The BG output is three-stated.These signals do not need to be jumper-isolated in your system.

The EZ-ICE connects to your target system via a ribbon cableand a 14-pin female plug. The female plug is plugged onto the14-pin connector (a pin strip header) on the target board.

Target Board Connector for EZ-ICE ProbeThe EZ-ICE connector (a standard pin strip header) is shown inFigure 13. You must add this connector to your target boarddesign if you intend to use the EZ-ICE. Be sure to allow enoughroom in your system to fit the EZ-ICE probe onto the 14-pinconnector.

1 2

3 4

5 6

7 8

9 10

11 12

13 14

GND

KEY (NO PIN)

RESET

BR

BG

TOP VIEW

EBG

EBR

ELOUT

EE

EINT

ELIN

ECLK

EMS

ERESET

Figure 13. Target Board Connector for EZ-ICE

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-tion—Pin 7 must be removed from the header. The pins mustbe 0.025 inch square and at least 0.20 inch in length. Pin spac-ing should be 0.1 × 0.1 inches. The pin strip header must haveat least 0.15 inch clearance on all sides to accept the EZ- ICEprobe plug.

Pin strip headers are available from vendors such as 3M,McKenzie, and Samtec.

Target Memory InterfaceFor your target system to be compatible with the EZ-ICEemulator, it must comply with the memory interface guidelineslisted below.

PM, DM, BM, IOM, AND CMDesign your Program Memory (PM), Data Memory (DM), ByteMemory (BM), I/O Memory (IOM), and Composite Memory(CM) external interfaces to comply with worst case device tim-ing requirements and switching characteristics as specified inthis data sheet. The performance of the EZ- ICE may approachpublished worst-case specification for some memory accesstiming requirements and switching characteristics.

Note: If your target does not meet the worst-case chip specifica-tion for memory access parameters, you may not be able toemulate your circuitry at the desired CLKIN frequency. Depend-ing on the severity of the specification violation, you may havetrouble manufacturing your system as DSP components statisti-cally vary in switching characteristic and timing requirementswithin published limits.

Restriction: All memory strobe signals on the ADSP-2186M(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in yourtarget system must have 10 kΩ pull-up resistors connected whenthe EZ-ICE is being used. The pull-up resistors are necessarybecause there are no internal pull-ups to guarantee their stateduring prolonged three-state conditions resulting from typicalEZ-ICE debugging sessions. These resistors may be removed atyour option when the EZ-ICE is not being used.

Target System Interface SignalsWhen the EZ-ICE board is installed, the performance on somesystem signals change. Design your system to be compatiblewith the following system interface signal changes introduced bythe EZ-ICE board:

• EZ-ICE emulation introduces an 8 ns propagation delaybetween your target circuitry and the DSP on the RESETsignal.

• EZ-ICE emulation introduces an 8 ns propagation delaybetween your target circuitry and the DSP on the BR signal.

• EZ-ICE emulation ignores RESET and BR when single-stepping.

• EZ-ICE emulation ignores RESET and BR when in EmulatorSpace (DSP halted).

• EZ-ICE emulation ignores the state of target BR in certainmodes. As a result, the target system may take control of theDSP’s external memory bus only if bus grant (BG) is assertedby the EZ- ICE board’s DSP.

REV. 0–18–

ADSP-2186M–SPECIFICATIONSRECOMMENDED OPERATING CONDITIONS

K Grade B GradeParameter Min Max Min Max Unit

VDDINT 2.37 2.63 2.25 2.75 VVDDEXT 2.37 3.6 2.25 3.6 VVINPUT

1 VIL = –0.3 VIH = +3.6 VIL = –0.3 VIH = +3.6 VTAMB 0 +70 –40 +85 °CNOTES1The ADSP-2186M is 3.3 V tolerant (always accepts up to 3.6 V max VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT; because VOH (max)≈ VDDEXT (max). This applies to bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7) and input only pins (CLKIN, RESET,BR, DR0, DR1, PWD).

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS K/B Grades

Parameter Test Conditions Min Typ Max Unit

VIH Hi-Level Input Voltage1, 2 @ VDDINT = max 1.5 VVIH Hi-Level CLKIN Voltage @ VDDINT = max 2.0 VVIL Lo-Level Input Voltage1, 3 @ VDDINT = min 0.7 VVOH Hi-Level Output Voltage1, 4, 5 @ VDDEXT = min, IOH = –0.5 mA 2.0 V

@ VDDEXT = 3.0 V, IOH = –0.5 mA 2.4 V@ VDDEXT = min, IOH = –100 µA6 VDDEXT – 0.3 V

VOL Lo-Level Output Voltage1, 4, 5 @ VDDEXT = min, IOL = 2 mA 0.4 VIIH Hi-Level Input Current3 @ VDDINT = max, VIN = 3.6 V 10 µAIIL Lo-Level Input Current3 @ VDDINT = max, VIN = 0 V 10 µAIOZH Three-State Leakage Current7 @ VDDEXT = max, VIN = 3.6 V8 10 µAIOZL Three-State Leakage Current7 @ VDDEXT = max, VIN = 0 V8 10 µAIDD Supply Current (Idle)9 @ VDDINT = 2.5, tCK = 15 ns 9 mAIDD Supply Current (Idle)9 @ VDDINT = 2.5, tCK = 13.3 ns 10 mAIDD Supply Current (Dynamic)10 @ VDDINT = 2.5, tCK = 15 ns11, TAMB = 25°C 35 mAIDD Supply Current (Dynamic)10 @ VDDINT = 2.5, tCK = 13.3 ns11, TAMB = 25°C 38 mAIDD Supply Current (Power-Down)12 @ VDDINT = 2.5, TAMB = 25°C in Lowest 100 µA

Power ModeCI Input Pin Capacitance3, 6 @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C 8 pFCO Output Pin Capacitance6, 7, 12, 13 @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C 8 pF

NOTES1 Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.2 Input only pins: RESET, BR, DR0, DR1, PWD.3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.5 Although specified for TTL outputs, all ADSP-2186M outputs are CMOS-compatible and will drive to VDDEXT and GND, assuming no dc loads.6 Guaranteed but not tested.7 Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.8 0 V on BR.9 Idle refers to ADSP-2186M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.

10IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2and Type 6, and 20% are idle instructions.

11VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.12See Chapter 9 of the ADSP-2100 Family User’s Manual for details.13Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

REV. 0

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–19–

ABSOLUTE MAXIMUM RATINGS1

ValueParameter Min Max

Internal Supply Voltage (VDDINT) –0.3 V +3.0 VExternal Supply Voltage (VDDEXT) –0.3 V +4.0 VInput Voltage2 –0.5 V +4.0 VOutput Voltage Swing3 –0.5 V VDDEXT + 0.5 VOperating Temperature Range –40°C +85°CStorage Temperature Range –65°C +150°CLead Temperature (5 sec) LQFP 280°C

NOTES1Stresses greater than those listed may cause permanent damage to the device.These are stress ratings only; functional operation of the device at these or any otherconditions greater than those indicated in the operational sections of this specifi-cation is not implied. Exposure to absolute maximum rating conditions forextended periods may affect device reliability.

2Applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0,TFS1, A1–A13, PF0–PF7) and Input only pins (CLKIN, RESET, BR, DR0,DR1, PWD).

3Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK,A0, DT0, DT1, CLKOUT, FL2–0, BGH).

TIMING SPECIFICATIONSGENERAL NOTESUse the exact timing information given. Do not attempt toderive parameters from the addition or subtraction of others.While addition or subtraction would yield meaningful results foran individual device, the values given in this data sheet reflectstatistical variations and worst cases. Consequently, you cannotmeaningfully add up parameters to derive longer times.

TIMING NOTESSwitching characteristics specify how the processor changes itssignals. You have no control over this timing—circuitry externalto the processor must be designed for compatibility with thesesignal characteristics. Switching characteristics tell you what theprocessor will do in a given circumstance. You can also useswitching characteristics to ensure that any timing require-ment of a device connected to the processor (such as memory)is satisfied.

Timing requirements apply to signals that are controlled bycircuitry external to the processor, such as the data input for aread operation. Timing requirements guarantee that the proces-sor operates correctly with other devices.

MEMORY TIMING SPECIFICATIONSThe table below shows common memory device specificationsand the corresponding ADSP-2186M timing parameters, foryour convenience.

Memory TimingDevice ParameterSpecification Parameter Definition1

Address Setup to tASW A0–A13, xMS Setup beforeWrite Start WR Low

Address Setup to tAW A0–A13, xMS Setup beforeWrite End WR Deasserted

Address Hold Time tWRA A0–A13, xMS Hold beforeWR Low

Data Setup Time tDW Data Setup before WRHigh

Data Hold Time tDH Data Hold after WR HighOE to Data Valid tRDD RD Low to Data ValidAddress Access Time tAA A0–A13, xMS to Data Valid

NOTE1xMS = PMS, DMS, BMS, CMS or IOMS.

ESD SENSITIVITYESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe ADSP-2186M features proprietary ESD protection circuitry, permanent damage may occur ondevices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0–20–

ADSP-2186M• Each address and data pin has a 10 pF total load at the pin.

• The application operates at VDDEXT = 3.3 V and tCK = 30 ns.

Total Power Dissipation = PINT + (C × VDDEXT2 × f )

PINT = internal power dissipation from Power vs. Frequencygraph (Figure 15).

(C × VDDEXT2 × f ) is calculated for each output:

# of C VDDEXT2 f PD

Parameters Pins pF V MHz mW

Address 7 10 3.32 16.67 12.7Data Output, WR 9 10 3.32 16.67 16.3RD 1 10 3.32 16.67 1.8CLKOUT, DMS 2 10 3.32 33.3 7.2

38.0

Total power dissipation for this example is PINT + 38.0 mW.

Output Drive CurrentsFigure 14 shows typical I-V characteristics for the output driverson the ADSP-2186M. The curves represent the current drivecapability of the output drivers as a function of output voltage.

VOH

VOL

SOURCE VOLTAGE – V

0 0.5 1.0

SO

UR

CE

CU

RR

EN

T –

mA

60

0

–20

–40

–60

40

20

VDDEXT = 3.6V @ –40C

VDDEXT = 3.3V @ +25C




VDDEXT = 3.6V @ –40C

80

–801.5 2.0 2.5 3.0 3.5 4.0

Figure 14. Typical Output Driver Characteristics

FREQUENCY DEPENDENCY FOR TIMINGSPECIFICATIONStCK is defined as 0.5 tCKI. The ADSP-2186M uses an input clockwith a frequency equal to half the instruction rate. For example,a 37.50 MHz input clock (which is equivalent to 26.6 ns) yieldsa 13.3 ns processor cycle (equivalent to 75 MHz). tCK valueswithin the range of 0.5 tCKI period should be substituted for allrelevant timing parameters to obtain the specification value.

Example: tCKH = 0.5 tCK – 2 ns = 0.5 (15 ns) – 2 ns = 5.5 ns

ENVIRONMENTAL CONDITIONS1

RatingDescription Symbol LQFP Mini-BGA

Thermal Resistance θCA 48°C/W 63.3°C/W(Case-to-Ambient)

Thermal Resistance θJA 50°C/W 70.7°C/W(Junction-to-Ambient)

Thermal Resistance θJC 2°C/W 7.4°C/W(Junction-to-Case)

NOTE1Where the Ambient Temperature Rating (TAMB) is:TAMB = TCASE – (PD × θCA)TCASE = Case Temperature in °CPD = Power Dissipation in W

POWER DISSIPATIONTo determine total power dissipation in a specific application,the following equation should be applied for each output:

C × VDD2 × f

C = load capacitance, f = output switching frequency.

Example:

In an application where external data memory is used and no otheroutputs are active, power dissipation is calculated as follows:

Assumptions:

• External data memory is accessed every cycle with 50% of theaddress pins switching.

• External data memory writes occur every other cycle with50% of the data pins switching.

REV. 0

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VALID FOR ALL TEMPERATURE GRADES.1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.2TYPICAL POWER DISSIPATION AT 2.5V VDDINT AND 25C, EXCEPT WHERE SPECIFIED.3IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.4IDLE REFERS TO STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.

NOTES:

12

PO

WE

R (

PID

LEn

) –

mW

20mW

15mW

14.25mW

15.7mW

16.4mW

24mW

IDLE (16)IDLE (128)

IDLE

POWER, IDLE n MODES2

1/tCK – MHz50 75

14

16

18

20

22

24

26

55 60 70 8065

14

PO

WE

R (

PID

LE)

– m

W 24mW

28mW

VDD = 2.65V

20mW

24mW

VDD = 2.5V

16.5mW

20mW

VDD = 2.35V

POWER, IDLE1, 2, 4

1/tCK – MHz50

16

18

20

22

24

26

28

30

55 60 65 70 75 80

1/tCK – MHz50 80

60

82mW

70mW

61mW

95mW

82mW

POWER, INTERNAL1, 2, 3

110mW

PO

WE

R (

PIN

T)

– m

W VDD = 2.65V

VDD = 2.5V

VDD = 2.35V

5555 60 65 70 75

65

70

75

80

8590

95

100

105

110

115

VDD = 2.65V

VDD = 2.5V

VDD = 2.35V

Figure 15. Power vs. Frequency

Capacitive LoadingFigure 16 and Figure 17 show the capacitive loading character-istics of the ADSP-2186M.

CL – pF

RIS

E T

IME

(0.4

V–

2.4V

) – n

s

30

3000 50 100 150 200 250

25

15

10

5

0

20

T = 85CVDD = 0V TO 2.0V

Figure 16. Typical Output Rise Time vs. Load Capacitance(at Maximum Ambient Operating Temperature)

CL – pF

14

0

VA

LID

OU

TPU

T D

ELA

Y O

R H

OLD

– n

s

50 100 150 250200

12

4

2

–2

10

8

NOMINAL

16

18

6

–4

–6

Figure 17. Typical Output Valid Delay or Hold vs. LoadCapacitance, CL (at Maximum Ambient OperatingTemperature)

REV. 0–22–

ADSP-2186MTEST CONDITIONSOutput Disable TimeOutput pins are considered to be disabled when they have stoppeddriving and started a transition from the measured output highor low voltage to a high impedance state. The output disabletime (tDIS) is the difference of tMEASURED and tDECAY, as shownin the Output Enable/Disable diagram. The time is the intervalfrom when a reference signal reaches a high or low voltage levelto when the output voltages have changed by 0.5 V from themeasured output high or low voltage.

The decay time, tDECAY, is dependent on the capacitive load,CL, and the current load, iL, on the output pin. It can beapproximated by the following equation:

t

C

iDECAY

L

L

=× 0 5. V

from which

tDIS = tMEASURED – tDECAY

is calculated. If multiple pins (such as the data bus) are disabled,the measurement value is that of the last pin to stop driving.

1.5V

OUTPUT

INPUT

1.5V2.0V

0.8V

Figure 18. Voltage Reference Levels for AC Measure-ments (Except Output Enable/Disable)

Output Enable TimeOutput pins are considered to be enabled when they have madea transition from a high-impedance state to when they start driving.The output enable time (tENA) is the interval from when a refer-ence signal reaches a high or low voltage level to when the outputhas reached a specified high or low trip point, as shown Figure19. If multiple pins (such as the data bus) are enabled, the mea-surement value is that of the first pin to start driving.

2.0V

1.0V

tENA

REFERENCESIGNAL

OUTPUT

tDECAY

VOH(MEASURED)

OUTPUT STOPSDRIVING

OUTPUTSTARTSDRIVING

tDIS

tMEASURED

VOL(MEASURED)

VOH (MEASURED) – 0.5V

VOL (MEASURED) +0.5V

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSETHIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

VOH(MEASURED)

VOL(MEASURED)

Figure 19. Output Enable/Disable

TOOUTPUT

PIN50pF

1.5V

IOH

IOL

Figure 20. Equivalent Loading for AC Measurements(Including All Fixtures)

REV. 0

ADSP-2186M

–23–

Parameter Min Max Unit

Clock Signals and ResetTiming Requirements:tCKI CLKIN Period 26.6 80 nstCKIL CLKIN Width Low 8 nstCKIH CLKIN Width High 8 ns

Switching Characteristics:tCKL CLKOUT Width Low 0.5tCK – 2 nstCKH CLKOUT Width High 0.5tCK – 2 nstCKOH CLKIN High to CLKOUT High 0 13 ns

Control Signals Timing Requirements:tRSP RESET Width Low 5tCK

1 nstMS Mode Setup before RESET High 2 nstMH Mode Hold after RESET High 5 ns

NOTE1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystaloscillator start-up time).

tCKOH

tCKI

tCKIH

tCKIL

tCKH

tCKL

tMHtMS

CLKIN

CLKOUT

PF(3:0)*

RESET

*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 21. Clock Signals

REV. 0–24–

ADSP-2186MParameter Min Max Unit

Interrupts and FlagsTiming Requirements:tIFS IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 0.25tCK + 10 nstIFH IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 0.25tCK ns

Switching Characteristics:tFOH Flag Output Hold after CLKOUT Low5 0.5tCK – 5 nstFOD Flag Output Delay from CLKOUT Low5 0.5tCK + 4 ns

NOTES1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized onthe following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information oninterrupt servicing.)

2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.3IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.5Flag Outputs = PFx, FL0, FL1, FL2, FO.

tFOD

tFOH

tIFH

tIFS

CLKOUT

FLAGOUTPUTS

IRQxFI

PFx

Figure 22. Interrupts and Flags

REV. 0

ADSP-2186M

–25–


Bus Request–Bus GrantTiming Requirements:tBH BR Hold after CLKOUT High1 0.25tCK + 2 nstBS BR Setup before CLKOUT Low1 0.25tCK + 10 ns

Switching Characteristics:tSD CLKOUT High to xMS, RD, WR Disable 0.25tCK + 8 nstSDB xMS, RD, WR Disable to BG Low 0 nstSE BG High to xMS, RD, WR Enable 0 nstSEC xMS, RD, WR Enable to CLKOUT High 0.25tCK – 3 nstSDBH xMS, RD, WR Disable to BGH Low2 0 nstSEH BGH High to xMS, RD, WR Enable2 0 ns

NOTESxMS = PMS, DMS, CMS, IOMS, BMS.1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized onthe following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

2BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.

CLKOUT

tSD

tSDBtSE

tSEC

tSDBHtSEH

tBS

BR

tBH

CLKOUT

PMS, DMSBMS, RD

WR

BG

BGH

Figure 23. Bus Request–Bus Grant

REV. 0–26–


Memory ReadTiming Requirements:tRDD RD Low to Data Valid 0.5tCK – 5 + w nstAA A0–A13, xMS to Data Valid 0.75tCK – 6 + w nstRDH Data Hold from RD High 0 ns

Switching Characteristics:tRP RD Pulsewidth 0.5tCK – 3 + w nstCRD CLKOUT High to RD Low 0.25tCK – 2 0.25tCK + 4 nstASR A0–A13, xMS Setup before RD Low 0.25tCK – 3 nstRDA A0–A13, xMS Hold after RD Deasserted 0.25tCK – 3 nstRWR RD High to RD or WR Low 0.5tCK – 3 ns

NOTESw = wait states × tCK.xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

D0–D23

tRDA

tRWRtRP

tASR

tCRD

tRDDtAA

tRDH

DMS, PMS,BMS, IOMS,

CMS

RD

WR

Figure 24. Memory Read

REV. 0

ADSP-2186M

–27–


Memory WriteSwitching Characteristics:tDW Data Setup before WR High 0.5t

CK – 4 + w ns

tDH Data Hold after WR High 0.25tCK – 1 nstWP WR Pulsewidth 0.5tCK – 3 + w nstWDE WR Low to Data Enabled 0 nstASW A0–A13, xMS Setup before WR Low 0.25tCK – 3 nstDDR Data Disable before WR or RD Low 0.25tCK – 3 nstCWR CLKOUT High to WR Low 0.25t

CK – 2 0.25 t

CK + 4 ns

tAW A0–A13, xMS, Setup before WR Deasserted 0.75tCK – 5 + w nstWRA A0–A13, xMS Hold after WR Deasserted 0.25tCK – 1 nstWWR WR High to RD or WR Low 0.5tCK – 3 ns

NOTESw = wait states × tCK.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

D0–D23

tWP

tAW

tCWRtDH

tWDE

tDW

tASW tWWR

tWRA

tDDR

DMS, PMS,BMS, CMS,

IOMS

RD

WR

Figure 25. Memory Write

REV. 0–28–

ADSP-2186MSerial Ports


Serial PortsTiming Requirements:tSCK SCLK Period 26.6 nstSCS DR/TFS/RFS Setup before SCLK Low 4 nstSCH DR/TFS/RFS Hold after SCLK Low 7 nstSCP SCLKIN Width 12 ns

Switching Characteristics:tCC CLKOUT High to SCLKOUT 0.25tCK 0.25tCK + 6 nstSCDE SCLK High to DT Enable 0 nstSCDV SCLK High to DT Valid 12 nstRH TFS/RFSOUT Hold after SCLK High 0 nstRD TFS/RFSOUT Delay from SCLK High 12 nstSCDH DT Hold after SCLK High 0 nstTDE TFS (Alt) to DT Enable 0 nstTDV TFS (Alt) to DT Valid 12 nstSCDD SCLK High to DT Disable 12 nstRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 12 ns

CLKOUT

SCLK

TFSOUT

RFSOUT

DT

ALTERNATEFRAME MODE

tCC tCC

tSCS tSCH

tRH

tSCDEtSCDH

tSCDD

tTDE

tRDV

MULTICHANNELMODE,

FRAME DELAY 0(MFD = 0)

DRTFSINRFSIN

RFSOUTTFSOUT

tTDV

tSCDV

tRD

tSCP

tSCK

tSCP

TFSIN

RFSIN

ALTERNATEFRAME MODE

tRDV

MULTICHANNELMODE,

FRAME DELAY 0(MFD = 0)

tTDV

tTDE

Figure 26. Serial Ports

REV. 0

ADSP-2186M

–29–


IDMA Address LatchTiming Requirements:tIALP Duration of Address Latch1, 2 10 nstIASU IAD15–0 Address Setup before Address Latch End2 5 nstIAH IAD15–0 Address Hold after Address Latch End2 3 nstIKA IACK Low before Start of Address Latch2, 3 0 nstIALS Start of Write or Read after Address Latch End2, 3 3 nstIALD Address Latch Start after Address Latch End1, 2 2 ns

NOTES1Start of Address Latch = IS Low and IAL High.2End of Address Latch = IS High or IAL Low.3Start of Write or Read = IS Low and IWR Low or IRD Low.

IACK

IAL

IS

IAD15–0

RD OR WR

tIKA

tIALP

tIALD

tIASUtIAH

tIASU

tIALS

tIAH

tIALP

Figure 27. IDMA Address Latch

REV. 0–30–


IDMA Write, Short Write CycleTiming Requirements:tIKW IACK Low before Start of Write1 0 nstIWP Duration of Write1, 2 10 nstIDSU IAD15–0 Data Setup before End of Write2, 3, 4 3 nstIDH IAD15–0 Data Hold after End of Write2, 3, 4 2 ns

Switching Characteristic:tIKHW Start of Write to IACK High 10 ns

NOTES1Start of Write = IS Low and IWR Low.2End of Write = IS High or IWR High.3If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.4If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.

IAD15–0 DATA

tIKHW

tIKW

tIDSU

IACK

tIWP

tIDH

IS

IWR

Figure 28. IDMA Write, Short Write Cycle

REV. 0

ADSP-2186M

–31–


IDMA Write, Long Write CycleTiming Requirements:tIKW IACK Low before Start of Write1 0 nstIKSU IAD15–0 Data Setup before End of Write2, 3, 4 0.5tCK + 5 nstIKH IAD15–0 Data Hold after End of Write2, 3, 4 0 ns

Switching Characteristics:tIKLW Start of Write to IACK Low4 1.5tCK nstIKHW Start of Write to IACK High 10 ns

NOTES1Start of Write = IS Low and IWR Low.2If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.3If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.4This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.

IAD15–0 DATA

tIKHW

tIKW

IACK

IS

IWR

tIKLW

tIKHtIKSU

Figure 29. IDMA Write, Long Write Cycle

REV. 0–32–


IDMA Read, Long Read CycleTiming Requirements:tIKR IACK Low before Start of Read1 0 nstIRK End of Read after IACK Low2 2 ns

Switching Characteristics:tIKHR IACK High after Start of Read1 10 nstIKDS IAD15–0 Data Setup before IACK Low 0.5t

CK – 2 ns

tIKDH IAD15–0 Data Hold after End of Read2 0 nstIKDD IAD15–0 Data Disabled after End of Read2 10 nstIRDE IAD15–0 Previous Data Enabled after Start of Read 0 nstIRDV IAD15–0 Previous Data Valid after Start of Read 11 nstIRDH1 IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3 2tCK – 5 nstIRDH2 IAD15–0 Previous Data Hold after Start of Read (PM2)4 tCK – 5 ns

NOTES1Start of Read = IS Low and IRD Low.2End of Read = IS High or IRD High.3DM read or first half of PM read.4Second half of PM read.

tIRK

tIKR

PREVIOUSDATA

READDATA

tIKHR

tIKDS

tIRDV

tIRDH

tIKDD

tIRDEtIKDH

IAD15–0

IACK

IS

IRD

Figure 30. IDMA Read, Long Read Cycle

REV. 0

ADSP-2186M

–33–


IDMA Read, Short Read Cycle1, 2

Timing Requirements:tIKR IACK Low before Start of Read3 0 nstIRP1 Duration of Read (DM/PM1)4 10 2tCK – 5 nstIRP2 Duration of Read (PM2)5 10 tCK – 5 ns

Switching Characteristics:tIKHR IACK High after Start of Read3 10 nstIKDH IAD15–0 Data Hold after End of Read6 0 nstIKDD IAD15–0 Data Disabled after End of Read6 10 nstIRDE IAD15–0 Previous Data Enabled after Start of Read 0 nstIRDV IAD15–0 Previous Data Valid after Start of Read 10 ns

NOTES1Short Read Only must be disabled in the IDMA Overlay memory mapped register.2Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.3Start of Read = IS Low and IRD Low.4DM Read or first half of PM Read.5Second half of PM Read.6End of Read = IS High or IRD High.

tIRP

tIKR

PREVIOUSDATA

tIKHR

tIRDVtIKDD

tIRDEtIKDH

IAD15–0

IACK

IS

IRD

Figure 31. IDMA Read, Short Read Cycle

REV. 0–34–


IDMA Read, Short Read Cycle in Short Read Only Mode1

Timing Requirements:tIKR IACK Low before Start of Read2 0 nstIRP Duration of Read3 10 ns

Switching Characteristics:tIKHR IACK High after Start of Read2 10 nstIKDH IAD15–0 Previous Data Hold after End of Read3 0 nstIKDD IAD15–0 Previous Data Disabled after End of Read3 10 nstIRDE IAD15–0 Previous Data Enabled after Start of Read 0 nstIRDV IAD15–0 Previous Data Valid after Start of Read 10 ns

NOTES1Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to theregister or by an external host writing to the register. Disabled by default.

2Start of Read = IS Low and IRD Low. Previous data remains until end of read.3End of Read = IS High or IRD High.

tIRP

tIKR

PREVIOUSDATA

tIKHR

tIRDVtIKDD

tIRDEtIKDH

IAD15–0

IACK

IS

IRD

Figure 32. IDMA Read, Short Read Only Cycle

REV. 0

ADSP-2186M

–35–

100-LEAD LQFP PIN CONFIGURATION

5

4

3

2

7

6

9

8

1

D19

D18

D17

D16

IRQ

E+P

F4

IRQ

L0+P

F5

GN

D

IRQ

L1+P

F6

DT

0

TFS

0

SC

LK0

VD

DE

XT

DT

1/F

OTF

S1/

IRQ

1

DR

1/FI

GN

D

SC

LK1

ER

ES

ET

RE

SE

T

D15

D14

D13

D12

GND

D11

D10

D9VDDEXT

GND

D8D7/ IWR

D6/IRD

D5/IAL

D4/IS

GNDVDDINT

D3/IACK

D2/IAD15

D1/IAD14

D0/IAD13

BG

EBG

BR

EBR

A4/IAD3

A5/IAD4

GND

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

CLKIN

XTALVDDEXT

CLKOUT

GND

VDDINT

WR

RD

BMS

DMS

PMS

IOMS

CMS

71

72

73

74

69

70

67

68

65

66

75

60

61

62

63

58

59

56

57

54

55

64

52

53

51

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

PIN 1IDENTIFIER

TOP VIEW(Not to Scale)

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

11

10

16

15

14

13

18

17

20

19

22

21

12

24

23

25

ADSP-2186M

IRQ

2+P

F7

RF

S0

DR

0

EM

S

EE

EL

OU

T

EC

LK

EL

IN

EIN

T

A3/

IAD

2

A2/

IAD

1

A1/

IAD

0

A0

PW

DA

CK

BG

H

FL

0

FL1

FL

2

D23

D22

D21

D20

GN

D

PF

1 [M

OD

E B

]

GN

D

PW

DV

DD

EX

T

PF0

[MO

DE

A]

PF2

[MO

DE

C]

PF

3 [M

OD

E D

]

RFS

1/IR

Q0

REV. 0–36–

ADSP-2186MThe LQFP package pinout is shown in the table below. Pin names in bold text replace the plain text named functions whenMode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed inbrackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure)of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external inter-rupt and flag pins. This bit is set to 1 by default upon reset.

LQFP Package Pinout

Pin Pin Pin PinNo. Pin Name No. Pin Name No. Pin Name No. Pin Name

1 A4/IAD3 26 IRQE + PF4 51 EBR 76 D162 A5/IAD4 27 IRQL0 + PF5 52 BR 77 D173 GND 28 GND 53 EBG 78 D184 A6/IAD5 29 IRQL1 + PF6 54 BG 79 D195 A7/IAD6 30 IRQ2 + PF7 55 D0/IAD13 80 GND6 A8/IAD7 31 DT0 56 D1/IAD14 81 D207 A9/IAD8 32 TFS0 57 D2/IAD15 82 D218 A10/IAD9 33 RFS0 58 D3/IACK 83 D229 A11/IAD10 34 DR0 59 VDDINT 84 D2310 A12/IAD11 35 SCLK0 60 GND 85 FL211 A13/IAD12 36 VDDEXT 61 D4/IS 86 FL112 GND 37 DT1/FO 62 D5/IAL 87 FL013 CLKIN 38 TFS1/IRQ1 63 D6/IRD 88 PF3 [MODE D]14 XTAL 39 RFS1/IRQ0 64 D7/IWR 89 PF2 [MODE C]15 VDDEXT 40 DR1/FI 65 D8 90 VDDEXT

16 CLKOUT 41 GND 66 GND 91 PWD17 GND 42 SCLK1 67 VDDEXT 92 GND18 VDDINT 43 ERESET 68 D9 93 PF1 [MODE B]19 WR 44 RESET 69 D10 94 PF0 [MODE A]20 RD 45 EMS 70 D11 95 BGH21 BMS 46 EE 71 GND 96 PWDACK22 DMS 47 ECLK 72 D12 97 A023 PMS 48 ELOUT 73 D13 98 A1/IAD024 IOMS 49 ELIN 74 D14 99 A2/IAD125 CMS 50 EINT 75 D15 100 A3/IAD2

REV. 0

ADSP-2186M

–37–

144-Ball Mini-BGA Package Pinout (Bottom View)

IRQL0 + PF5IRQ2 + PF7NCCMSGNDDT1/FODR1/FIGNDNCEMSEEECLK

IRQE + PF4NCIRQL1 + PF6IOMSGNDPMSDR0GNDRESETELINELOUTEINT

NCNCNCBMSDMSRFS0TFS1/ IRQ1SCLK1ERESETEBRBREBG

CLKOUTVDDINTNCVDDEXTVDDEXTSCLK0D0/IAD13RFS1/ IRQ0BGD1/IAD14VDDINTVDDINT

CLKINGNDGNDGNDVDDINTDT0TFS0D2/IAD15D3/IACKGNDNCGND

XTALNCGNDA10/IAD9NCNCNCD6/IRDD5/IALNCNCD4/IS

A13/IAD12NCA12/IAD11A11/IAD10FL1NCNCD7/IWRD11D8NCD9

VDDEXTVDDEXTA8/IAD7FL0PF0[MODE A]

FL2PF3[MODE D]

GNDGNDVDDEXTGNDD10

NCWRNCBGHA9/IAD8PF1[MODE B]

PF2[MODE C]

NCD13D12NCGND

PWDACKA6/IAD5RDA5/IAD4A7/IAD6PWDVDDEXTD21D19D15NCD14

A4/IAD3A3/IAD2GNDNCNCGNDVDDEXTD23D20D18D17D16

A2/IAD1A1/IAD0GNDA0NCGNDNCNCNCD22GNDGND

123456789101112

M

L

K

J

H

G

F

E

D

C

B

A

REV. 0–38–

ADSP-2186MThe Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named functions whenMode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed inbrackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) ofthe System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interruptand flag pins. This bit is set to 1 by default upon reset.

Mini-BGA Package Pinout

Ball # Pin Name Ball # Pin Name Ball # Pin Name Ball # Pin Name

A01 A2/IAD1 D01 NC G01 XTAL K01 NCA02 A1/IAD0 D02 WR G02 NC K02 NCA03 GND D03 NC G03 GND K03 NCA04 A0 D04 BGH G04 A10/IAD9 K04 BMSA05 NC D05 A9/IAD8 G05 NC K05 DMSA06 GND D06 PF1 [MODE B] G06 NC K06 RFS0A07 NC D07 PF2 [MODE C] G07 NC K07 TFS1/IRQ1A08 NC D08 NC G08 D6/IRD K08 SCLK1A09 NC D09 D13 G09 D5/IAL K09 ERESETA10 D22 D10 D12 G10 NC K10 EBRA11 GND D11 NC G11 NC K11 BRA12 GND D12 GND G12 D4/IS K12 EBG

B01 A4/IAD3 E01 VDDEXT H01 CLKIN L01 IRQE + PF4B02 A3/IAD2 E02 VDDEXT H02 GND L02 NCB03 GND E03 A8/IAD7 H03 GND L03 IRQL1 + PF6B04 NC E04 FL0 H04 GND L04 IOMSB05 NC E05 PF0 [MODE A] H05 VDDINT L05 GNDB06 GND E06 FL2 H06 DT0 L06 PMSB07 VDDEXT E07 PF3 [MODE D] H07 TFS0 L07 DR0B08 D23 E08 GND H08 D2/IAD15 L08 GNDB09 D20 E09 GND H09 D3/IACK L09 RESETB10 D18 E10 VDDEXT H10 GND L10 ELINB11 D17 E11 GND H11 NC L11 ELOUTB12 D16 E12 D10 H12 GND L12 EINT

C01 PWDACK F01 A13/IAD12 J01 CLKOUT M01 IRQL0 + PF5C02 A6/IAD5 F02 NC J02 VDDINT M02 IRQL2 + PF7C03 RD F03 A12/IAD11 J03 NC M03 NCC04 A5/IAD4 F04 A11/IAD10 J04 VDDEXT M04 CMSC05 A7/IAD6 F05 FL1 J05 VDDEXT M05 GNDC06 PWD F06 NC J06 SCLK0 M06 DT1/FOC07 VDDEXT F07 NC J07 D0/IAD13 M07 DR1/FIC08 D21 F08 D7/IWR J08 RFS1/IRQ0 M08 GNDC09 D19 F09 D11 J09 BG M09 NCC10 D15 F10 D8 J10 D1/IAD14 M10 EMSC11 NC F11 NC J11 VDDINT M11 EEC12 D14 F12 D9 J12 VDDINT M12 ECLK

REV. 0

ADSP-2186M

–39–

OUTLINE DIMENSIONSDimensions shown in millimeters.

100-Lead Metric Thin Plastic Quad Flatpack (LQFP) (ST-100)

SEATINGPLANE

0.750.60 TYP0.50

1.60 MAX

12TYP

0.150.05

6 ± 4

0 – 7

0.08MAX LEAD

COPLANARITY

TOP VIEW(PINS DOWN)

1

2526

5150

75100 76

0.270.22 TYP0.17

16.2016.00 TYP SQ15.80

0.50BSC

LEAD PITCH

14.0514.00 TYP SQ13.95

12.00 BSC

LEAD WIDTH

NOTE:THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEALPOSITION WHEN MEASURED IN THE LATERAL DIRECTION.

REV. 0–40–

C02

048–

3.5–

10/0

0 (r

ev. 0

)P

RIN

TE

D IN

U.S

.A.

ADSP-2186MOUTLINE DIMENSIONS

Dimensions shown in millimeters.

144-Ball Mini-BGA(CA-144)

SEATINGPLANE

1.00

DETAIL A

0.550.500.45

BALL DIAMETER

0.12MAX

1.40 MAX

DETAIL A

0.80BSC

8.80BSC

0.80 BSC8.80 BSC

ABCDEFGHJKLM

12 11 10 9 8 7 6 5 4 3 2 1

TOP VIEW

10.10 10.00 SQ 9.90

10.1010.00 SQ 9.90

NOTES: 0.850.40

0.25

THE ACTUAL POSITION OF THE BALL POPULATIONIS WITHIN 0.150 OF ITS IDEAL POSITION RELATIVETO THE PACKAGE EDGES.

1.

THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08OF ITS IDEAL POSITION RELATIVE TO THE BALLPOPULATION.

2.

ORDERING GUIDE

Ambient Temperature Instruction Package PackagePart Number Range Rate Description* Option

ADSP-2186MKST-300 0°C to 70°C 75 100-Lead LQFP ST-100ADSP-2186MBST-266 –40°C to +85°C 66 100-Lead LQFP ST-100ADSP-2186MKCA-300 0°C to 70°C 75 144-Ball Mini-BGA CA-144ADSP-2186MBCA-266 –40°C to +85°C 66 144-Ball Mini-BGA CA-144

*In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labeled TQFP packages (1.6 mmthick) are now designated as LQFP.

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