a low noise cmos voltage...
TRANSCRIPT
A Low Noise CMOS Voltage Reference
A Thesis
Presented to
The Academic Faculty
by
William Timothy Holman
In Partial Fulfillment
of the Requirements for the Degree
Doctor of Philosophy in Electrical Engineering
Georgia Institute of Technology
October 7, 1994
Copyright c 1994 by William Timothy Holman
ii
A Low Noise CMOS Voltage Reference
Approved:
____________________________________J. Alvin Connelly, Chairman
____________________________________Phillip E. Allen
____________________________________W. Marshall Leach, Jr.
____________________________________Thomas D. Morley
____________________________________John P. Uyemura
Date Approved ______________________
iii
ACKNOWLEDGMENTS
An engineering dissertation is never the work of a single individual, but instead a
product of the labor of many contributors. While this thesis is the result of much effort
by myself and Dr. J. Alvin Connelly, to a lesser extent it is also the result of the efforts of
those who laid the groundwork of my career and profession. Every teacher, every co-
worker, every member of my family, every friend I have known, and all the engineers
and scientists who developed the technologies discussed in this document are no less an
author of this dissertation than I am. Their influences, both great and small, gave me the
means and desire to perform this research and earn my doctorate.
I would like to give special thanks to the faculty of the School of Electrical and
Computer Engineering at the Georgia Institute of Technology for their instruction and
assistance throughout my graduate school experience. I would especially like to thank
Dr. Al Connelly for his understanding, support, and suggestions throughout this research.
Any student would be hard pressed to find an advisor who could do as fine a job as he
has for me. Most of all, I want to thank my family for their love and support, especially
my parents, Bill and Sue Holman. They gave me the support and opportunities I needed
to earn my degrees and become a part of the engineering profession.
Remember that a thesis is not just a collection of drawings, equations, and
measurements. An engineering dissertation is part of a miracle, a miracle that
encompasses the efforts of many people - past, present, and future - in the fields of
science and engineering. Every day I am awed by the technologies and the ideas that
have altered the world in my lifetime alone. It amazes me that such miracles could exist,
and I am proud to be a participant in their creation.
iv
TABLE OF CONTENTS
Page
SUMMARY.... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
INTRODUCTION ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
CHAPTER I - QUANTIFYING CMOS VOLTAGE REFERENCEPERFORMANCE... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Voltage Reference Accuracy .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Relative Accuracy in a Voltage Reference.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CHAPTER II - AN ANALYSIS OF STANDARD CMOS BANDGAPREFERENCES ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
A Theoretical Analysis of Bandgap Reference Temperature Coefficient . . . . . . . . . . . . . . . . . 16
Higher-Order Temperature Compensation.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Intrinsic Noise in CMOS Bandgap References.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Intrinsic Noise Sources in CMOS Components.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
A Small-Signal Analysis of Simple Bandgap Voltage References .. . . . . . . . . . . . . . . . . . . . . . . . 28
The Operational Amplifier Bandgap Reference Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
The PTAT Current Source Bandgap Reference Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Other Design Considerations for CMOS Bandgap Voltage References .. . . . . . . . . . . . . . . . . . 39
CHAPTER III - A PRACTICAL LOW NOISE CMOS BANDGAPREFERENCE TOPOLOGY .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Noise Multiplication versus Noise Addition.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
The ∆VBE Summing Bandgap Reference Topology ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
The Operation of the ∆VBE Summing Bandgap Reference .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Temperature Dependence of the ∆VBE Summing Bandgap Reference.. . . . . . . . . . . . . . . . . . . 50
A Noise Analysis of the ∆VBE Summing Bandgap Reference.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
CHAPTER IV - NONIDEAL COMPONENTS IN THE LOW NOISE CMOSBANDGAP REFERENCE... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
The Lateral PNP Bipolar Transistor .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Lateral PNP Transistor Layout and Characteristics.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
v
The Lateral PNP Transistor as a Floating Diode.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
The Darlington "Pseudo-BiCMOS" Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Nonideal Characteristics of the DBiLNA Buffer Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Input Offset Voltage Variation in the Buffer Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
CHAPTER V - THE ∆VBE SUMMING BANDGAP REFERENCE... . . . . . . . . . . . . . . . . . . .102
Layout and Fabrication .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Simulation of the ∆VBE Summing Bandgap Reference.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Reference Output Voltage and Quiescent Current.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Temperature Coefficient. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Output Noise .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Minimum Operating Voltage and Power Supply Rejection .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
CHAPTER VI - FUTURE DIRECTIONS FOR THE LOW NOISE CMOSBANDGAP REFERENCE... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
An Improved ∆VBE Summing Subcircuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
A New Method of High-Order Temperature Compensation .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
An Improved ∆VBE Summing Bandgap Reference .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
A Low Noise Fractional Bandgap Reference.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
CONCLUSIONS AND RECOMMENDATIONS... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Conclusions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Recommendations for Future Research .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
BIBLIOGRAPHY.... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
APPENDIX A - PSPICE LISTING FOR THE ∆VBE SUMMING BANDGAPREFERENCE SIMULATION... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
APPENDIX B - PSPICE LISTING FOR THE IMPROVED ∆VBE SUMMINGBANDGAP REFERENCE SIMULATION ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
VITA... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
vi
LIST OF TABLES
Table Page
Table 1-1. Overall Performance Comparison of CMOS Bandgap Circuits. . . . . . . . . . . . . . . 9
Table 1-2. A Comparison of Relative Error in Previous CMOS Bandgap References.. 10
Table 4-1. A Summary of Typical LPNP Transistor Parameters .. . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 4-2. A Summary of Typical DBiLNA Parameters.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 5-1. A Summary of Measured Parameters for the ∆VBE Summing Bandgap Reference with 784 Ω Bias Resistor and VDD = 5 V ... . . . . . . . . . . . . . . . . . . . . . . . .129
vii
LIST OF ILLUSTRATIONS
Figure Page
Fig. 1-1. The Effect of Voltage Reference Relative Error on a D/A Converter's Resolution .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Fig. 1-2. A Typical VBE Multiplier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Fig. 2-1. The Bandgap Voltage Reference Principle.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Fig. 2-2. Bandgap Reference Output with PTAT Bias Current (Tr = 300 ˚K).. . . . . . . . . . 22
Fig. 2-3. Bandgap Reference Output with PTAT2 Compensation (Tr = 300 ˚K) .. . . . . . 25
Fig. 2-4. The Operational Amplifier Bandgap Voltage Reference.. . . . . . . . . . . . . . . . . . . . . . . . 29
Fig. 2-5. AC Equivalent Circuit of the Op Amp Bandgap Reference .. . . . . . . . . . . . . . . . . . . . 30
Fig. 2-6. The PTAT Current Source Bandgap Reference .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Fig. 2-7. AC Equivalent Circuit of the PTAT Current Source Bandgap Reference .. . . . 35
Fig. 2-8. A Low Noise Bandgap Reference Topology ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Fig. 3-1. Multiplication vs. Addition of DC and Noise Voltage Sources .. . . . . . . . . . . . . . . . 46
Fig. 3-2. The ∆VBE Summing Bandgap Reference Topology ... . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Fig. 3-3. The ∆VBE Summing Subcircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Fig. 3-4. ∆VBE Summing Bandgap Reference Output with K = 3, m = 1, p(j) = 1.. . . . . 59
Fig. 3-5. Simplified Small-Signal Equivalent Circuit for the VBE1 Generator.. . . . . . . . . . 61
Fig. 3-6. The VBE1 Generator with a PTAT Current Source .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Fig. 3-7. Simplified Small-Signal Equivalent Circuit of the ∆VBE Summing Subcircuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Fig. 4-1. Current Flow in the Lateral PNP Transistor .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Fig. 4-2. A Minimum Size Lateral PNP Transistor Layout and Schematic.. . . . . . . . . . . . . . 77
Fig. 4-3. The 40 Emitter Dot Lateral PNP Transistor.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
viii
Fig. 4-4. Lateral ß vs. Lateral IC for the 40 Emitter Dot LPNP Transistor .. . . . . . . . . . . . . . 79
Fig. 4-5. Lateral Efficiency vs. IE for the 40 Emitter Dot LPNP Transistor.. . . . . . . . . . . . . 79
Fig. 4-6. Lateral ß vs. Lateral IC for the 1 Emitter Dot LPNP Transistor.. . . . . . . . . . . . . . . . 80
Fig. 4-7. Lateral Efficiency vs. IE for the 1 Emitter Dot LPNP Transistor .. . . . . . . . . . . . . . 80
Fig. 4-8. En vs. Frequency for the 40 Emitter Dot LPNP Transistor .. . . . . . . . . . . . . . . . . . . . . 82
Fig. 4-9. In vs. Frequency for the 40 Emitter Dot LPNP Transistor .. . . . . . . . . . . . . . . . . . . . . . 82
Fig. 4-10. Lateral PNP Transistors Used as Floating Diodes.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Fig. 4-11. Small-Signal Diagram of the Diode-Connected LPNP Transistor .. . . . . . . . . . . 88
Fig. 4-12. DC Effects of Intrinsic Resistances in the Diode-Connected LPNP Transistor .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Fig. 4-13. The DBiLNA Buffer Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Fig. 4-14. Equivalent Input Noise Voltage (En) for a Typical DBiLNA... . . . . . . . . . . . . . . . 93
Fig. 4-15. Equivalent Input Noise Current (In) for a Typical DBiLNA... . . . . . . . . . . . . . . . . 93
Fig. 4-16. Nonideal Effects in the DBiLNA Buffer Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Fig. 5-1. The ∆VBE Summing Bandgap Reference.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Fig. 5-2. The ∆VBE Summing Subcircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Fig. 5-3. Chip Pin-Out for the ∆VBE Summing Bandgap Reference.. . . . . . . . . . . . . . . . . . . . .106
Fig. 5-4. Parasitic Ground Resistances in the Bandgap Reference Layout .. . . . . . . . . . . . . .109
Fig. 5-5. Parasitic Resistances in the ∆VBE Summing Subcircuit . . . . . . . . . . . . . . . . . . . . . . . . .110
Fig. 5-6. Photograph of the Fabricated ∆VBE Summing Bandgap Reference.. . . . . . . . . . .112
Fig. 5-7. PSpice Macromodel for the Lateral PNP Transistor.. . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Fig. 5-8. Simulation of Quiescent Current versus Temperature for the Bandgap Reference .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Fig. 5-9. Reference Output Voltage versus Temperature with Different Bias Resistors .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Fig. 5-10. Simulation of Reference Output Voltage versus Temperature with a 784 Ω Bias Resistor .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
ix
Fig. 5-11. Simulation of Reference Output Voltage versus Temperature with 768 Ω, 784 Ω, and 806 Ω Bias Resistors .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Fig. 5-12. Reference Output Voltage versus Temperature for Four Test Circuits . . . . . . .122
Fig. 5-13. Output Noise of the ∆VBE Summing Bandgap Reference .. . . . . . . . . . . . . . . . . . . .124
Fig. 5-14. Simulation of Output Noise Spectral Density versus Frequency ... . . . . . . . . . . .125
Fig. 5-15. Simulation of Total RMS Output Noise versus Frequency... . . . . . . . . . . . . . . . . . .125
Fig. 5-16. Reference Voltage versus Power Supply Voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Fig. 5-17. Simulation of Reference Voltage versus Power Supply Voltage .. . . . . . . . . . . . .127
Fig. 5-18. Simulation of Power Supply Rejection versus Frequency... . . . . . . . . . . . . . . . . . . .128
Fig. 6-1. An Improved ∆VBE Summing Subcircuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Fig. 6-2. Small-Signal Diagram of the Improved ∆VBE Summing Subcircuit. . . . . . . . . . .134
Fig. 6-3. Temperature Coefficient Errors in the ∆VBE Summing Bandgap Reference .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Fig. 6-4. A Simple IPTAT Current Source.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Fig. 6-5. A Current Source with Adjustable Temperature Coefficient . . . . . . . . . . . . . . . . . . . .138
Fig. 6-6. Block Diagram of the Improved ∆VBE Summing Bandgap Reference .. . . . . . .140
Fig. 6-7. VREF versus Temperature for the Improved ∆VBE Summing Bandgap Reference .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Fig. 6-8. Output Noise versus Frequency for the Improved ∆VBE Summing Bandgap Reference.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Fig. 6-9. Total Output Noise for the Improved ∆VBE Summing Bandgap Reference .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Fig. 6-10. Power Supply Rejection versus Frequency for the Improved ∆VBE Summing Bandgap Reference.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
Fig. 6-11. Supply Current versus Temperature for the Improved ∆VBE Summing Bandgap Reference .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
Fig. 6-12. The Low Noise Fractional Bandgap Reference Topology... . . . . . . . . . . . . . . . . . . .144
Fig. 6-13. Output Voltage versus Temperature (˚C) for the Fractional Bandgap Reference .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
x
Fig. 6-14. Output Noise versus Frequency for the Fractional Bandgap Reference .. . . . .145
Fig. 6-15. A Fractional Bandgap Reference with a Voltage Multiplier Stage.. . . . . . . . . . .146
1
SUMMARY
Recent research in CMOS integrated noise generators has resulted in the
development of components that make possible the design of a high performance linear
CMOS bandgap reference with low output noise. The effects of output noise on the
performance of previously reported CMOS bandgap references are calculated and
compared, and a low noise linear CMOS bandgap reference is proposed, simulated,
fabricated, and tested. This circuit uses lateral bipolar transistors as floating p-n diodes
and differential input devices to create a low noise bandgap reference with a temperature
coefficient comparable to previous CMOS bangap circuits and output noise nearly an
order of magnitude lower. The operation and performance of these lateral bipolar
transistors and the low noise amplifiers built from them are discussed. A new method of
higher-order temperature coefficient compensation for bandgap references is also derived
and simulated.
2
INTRODUCTION
Although low noise design principles have been used in analog integrated circuits
for many years, relatively little effort has been made to apply these principles to
monolithic CMOS voltage references. Previous analysis has shown that reference noise
is the dominant source of noise in high performance circuits such as A/D and D/A
converters [1]. Methods to reduce error from integrated circuit reference noise may
involve external components such as capacitors or filter networks, or complex circuits to
average the value of the reference voltage over time. These approaches can be greatly
simplified or avoided completely if the voltage reference initially has very low intrinsic
noise. Ideally, the voltage reference circuit should be placed on the same substrate as the
desired CMOS VLSI application. Consequently, there is a need for a high performance
CMOS voltage reference that has much lower output noise that previous circuit
approaches.
This research details the design and performance of a low noise monolithic
CMOS voltage reference using a new topology to minimize intrinsic noise gain in the
circuit while maintaining low temperature coefficients through the application of the
bandgap voltage reference principle [2]. The topology is novel and quite simple, yet the
resulting circuit generates far less output noise than a standard CMOS bandgap reference
while exhibiting a comparably low temperature coefficient. This low noise CMOS
voltage reference is easily trimmed, is relatively insensitive to process variations, and can
operate at supply voltages of 5 V or less. A prototype circuit has been successfully
implemented in a single poly, double metal 1.2 µm n-well process and could also be
constructed in smaller gate length n-well technologies, p-well processes, or BiCMOS
processes.
3
Before discussing the design and performance of a low noise CMOS voltage
reference, the terms “reference” and “regulator” should be explicitly defined. By
definition, a voltage reference is a circuit that provides a stable output voltage
independent of the supply voltage and temperature [3]. Usually, a voltage reference
lacks the ability to sink or source any appreciable amount of current and may have a high
output impedance. A voltage regulator, on the other hand, can be considered a voltage
reference coupled with an low impedance output stage that allows the circuit to sink
and/or source appreciable current to a load. Since low noise CMOS buffer amplifiers can
be designed using techniques described in this dissertation, no attempt has been made to
extend the results of this voltage reference research to a high output current voltage
regulator, since a low noise voltage regulator is quite easily constructed once a low noise
voltage reference is available.
4
CHAPTER I
QUANTIFYING CMOS VOLTAGE REFERENCE PERFORMANCE
Voltage Reference Accuracy
When discussing the design of a low noise CMOS voltage reference, it is
necessary to explore the general performance limitations of voltage references to better
understand the advantages of building such a circuit. The obvious purpose of any voltage
reference is to provide a stable value of voltage over a given range of operating
conditions. An actual circuit's performance will be constrained by its absolute error (how
close the output voltage can be set to a desired value at nominal operating conditions) and
its relative error (how much the voltage varies from the nominal value over the full range
of operating conditions). Since high performance voltage references generally have some
means of trimming their nominal output value [4], [5], the absolute error can effectively
be set to zero by adjusting the circuit. In these cases, relative error will determine the
limit of the voltage reference's usefulness.
For example, consider an n-bit digital-to-analog converter which uses a voltage
reference to generate a precision analog output voltage for a given digital input word.
Assuming the D/A converter is ideal in every other respect, and assuming that no
oversampling or averaging of the reference voltage occurs, the relative accuracy of the
voltage reference will determine how many bits can effectively be converted. First, let
Verror be defined as the maximum excursion from the nominal reference voltage
Vnominal. If VREF = Vnominal ± Verror, let the relative error (|Verror/Vnominal|) of the
voltage reference be less than 0.5 LSB, or 2 -(n+1). Given this constraint, a graph of the
relative error versus the maximum number of bits can be generated (Fig. 1-1). For
5
example, assume the D/A converter's voltage reference has a nominal value of 1.2 V with
an error voltage of ± 1.2 mV. The relative error will be
Relative Error = Verror
Vnominal =
1.2 mV
1.2 V = 0.001 ≤ 2 -(n+1) . (1-1)
The maximum value of n that satisfies the above equation is n = 8, and the D/A converter
will therefore be constrained to a maximum of 8 bits of resolution given this amount of
relative error.
In conclusion, the relative error of a voltage reference ultimately determines how
useful the circuit will be for precision applications such as digital-to-analog and analog-
to-digital conversion. Minimizing relative error will increase the maximum number of
bits of resolution possible in data conversion applications. The next step in this analysis
is to determine what factors affect the relative error and how they can be reduced.
6
100
10-1
10-2
10-3
10-4
10-5
0
2
4
6
8
10
12
14
Relative Error of Voltage Reference vs. Maximum Number of Bits
Relative Error
Num
ber
of B
its Low Noise (?) Diff
SC
Low Zout, Diff, High PSRR
SC
IDAC
Fig. 1-1. The Effect of Voltage Reference Relative Error on a D/A Converter'sResolution
Relative Accuracy in a Voltage Reference
Assume that the output voltage of a given reference circuit can be set to a
particular nominal value through laser trimming, resistor adjustment, etc. Ignoring
effects such as component aging and thermal cycling, the reference voltage will therefore
be a function of the relative stability of the circuit over the range of operating conditions
in which it is used. Furthermore, the relative stability of the voltage reference will be
7
determined by four factors; (1) the temperature coefficient of the reference over the
operating temperature range, (2) the power supply noise rejection (or PSR) over the
operating voltage range, (3) the load regulation over the range of output load impedances,
and (4) the peak-to-peak output noise generated by the intrinsic noise sources of the
circuit. An obvious conclusion can be made with respect to these conditions: the relative
accuracy (and therefore the usefulness) of a voltage reference is constrained by the
parameter(s) with the greatest effect on the output voltage.
For example, consider a simple 1.4 V reference constructed using a VBE
multiplier circuit [3], [6] as shown in Fig. 1-2. Because the reference voltage is
approximately twice the value of a base-emitter voltage drop, the temperature coefficient
of this reference will be about twice that of a base-emitter junction, or - 4 mV / ˚C (- 2900
ppm / ˚C). If the reference operates over a ± 10 ˚C temperature range, the output voltage
may vary by as much as ± 40 mV from the nominal value. Even if the reference has very
good supply regulation due to the current source, low output noise due to the use of a low
noise transistor, and excellent load regulation from a low impedance output buffer, the
relative error of the reference will be determined by the temperature coefficient because
its effect is so much greater than the effect of any other parameter on the reference's
output voltage. A good low noise transistor or a high PSRR current source would be
wasted on this circuit, since their benefits would be insignificant when compared to the
variation in the output voltage as the temperature changed.
8
10 KΩ
10 KΩ
V DD
VREF =2 * VBE
Fig. 1-2. A Typical VBE Multiplier Circuit
By the same logic, the relative error of a CMOS bandgap reference with high
intrinsic noise, excellent supply regulation, and a very low temperature coefficient will be
constrained by the maximum peak value of the output noise. An analysis using the
parameters of previously presented CMOS bandgap references [7] will illustrate this
point. Assume that each CMOS bandgap reference in Table 1-2 has a constant output
load and is operating over a ± 10 ˚C temperature range and a ± 50 mV variation in supply
voltage. Using the conservative assumption that Vnoise(peak-to-peak) is equal to six times
Vnoise(RMS) for ±3 standard deviations from the RMS noise value [8], the maximum
∆VREF due to intrinsic noise will be three times Vnoise(RMS). Table 1-2 shows the
maximum variation in output voltage due to the effects of both noise and power supply
rejection ratio.
9
Table 1-1. Overall Performance Comparison of CMOS Bandgap Circuits
Circuit VREF
(V)
Total
Output
Noise1
(RMS)
White
Noise
(nV/ Hz )
PSRR+
at DC
(dB)
Temp.
Coeff
(ppm/˚C)
Supply
Current
(µA)
Chip
Area
(mm2)
Low Zout
Bandgap
[9]
1.2285 162 µV
(250 KHz
BW)
316 -60 23.3 79 0.42
Diff.
Bandgap
[10]
2.48 320 µV
(500 KHz
BW)
~400 -67 20.9 1200 1.16
Differ.
SC
Bandgap
[11]
6.2 310 µV
(250 KHz
BW)
453 -90 15 480 0.47
High
PSRR
Bandgap
[9]
1.2281 280 µV
(250 KHz
BW)
500 -77 23.3 20 0.18
SC
Bandgap
[5]
1.192 400 µV
(250 KHz
BW)
566 -50 13.1 1200 2.26
IDAC
Bandgap
[12]
1.28 905 µV
(250 KHz
BW)
1800 -60.4 ~80 3.05 Not
Avail-
able
1. The total output noise includes both 1/f noise and white noise over the specified bandwidth.
10
Table 1-2. A Comparison of Relative Error in Previous CMOS Bandgap References
Circuit VREF
(V)
Total
Output
Noise
(RMS)
∆ VREF
due to
Noise(± 3σ)
PSRR+
at DC
(dB)
∆ VREF
due to∆ VDD
Temp.
Coeff
(ppm/˚C)
∆ VREF
due to
∆ Temp
Low Zout
Bandgap
[9]
1.2285 162 µV
(250 KHz
BW)
486 µV -60 50 µV 23.3 286 µV
Diff.
Bandgap
[10]
2.48 320 µV
(500 KHz
BW)
960 µV -67 22.3 µV 20.9 518 µV
Differ.
SC
Bandgap
[11]
6.2 310 µV
(250 KHz
BW)
930 µV -90 1.6 µV 15 930 µV
High
PSRR
Bandgap
[9]
1.2281 280 µV
(250 KHz
BW)
840 µV -77 7.1 µV 23.3 286 µV
SC
Bandgap
[5]
1.192 400 µV
(250 KHz
BW)
1.2 mV -50 158 µV 13.1 156 µV
IDAC
Bandgap
[12]
1.28 905 µV
(250 KHz
BW)
2.72 mV -60.4 47.7 µV ~80 1.02 mV
11
Some obvious conclusions can be made from the results shown in Table 1-2.
First, intrinsic output noise and the temperature coefficient are the dominant sources of
error for VREF. In turn, the range of operating temperatures will determine which of
these two factors dominates the relative error of a given bandgap reference. Over the
moderate temperature excursion of the previous example (± 10 ˚C), peak-to-peak output
noise causes as great or greater relative error in VREF than the change due to the
temperature coefficient. Over very large temperature excursions (± 60 ˚C), changes in
VREF due to the temperature coefficient will dominate the output noise error in five of the
six circuits. Therefore, as long as the circuit is not being used over extreme
environmental conditions, reducing the output noise in a CMOS bandgap reference will
result in a significant reduction in relative error. Load regulation should be not a factor in
the relative accuracy of these circuits, assuming that a good low-impedance output buffer
is available. Furthermore, given a reasonably good PSRR (60 dB or greater), small
power supply changes have a negligible effect on the reference voltage when compared
to the errors caused by the temperature coefficient and the intrinsic noise.
Ignoring the effects of PSRR and load regulation, the relative errors of these
references are plotted on Fig. 1-1 using the noise and temperature coefficient error
voltages calculated in Table 1-2. Given these temperature changes and output noise
values, the maximum resolution of these references ranges from 7 to 10 bits. Note that
those CMOS bandgap references with lower temperature coefficients do not necessarily
have the higher maximum resolutions, since the output noise tends to be the dominant
error under these conditions. The low noise voltage reference presented in this
dissertation can attain up to 11 bits of resolution over the same operating conditions
because of its much lower output noise.
As a final note, the best means of comparing the output noise of different bandgap
reference circuits is to divide output noise by the nominal reference voltage to obtain a
12
noise voltage per regulated volt. Using this method with the circuits in Table 1-2, the
differential bandgap reference [10] has the lowest output noise among linear circuits with
a noise voltage of 129 µV RMS / Hz over a 500 KHz bandwidth. Consequently, in
Chapter V this circuit is used as a benchmark for comparing the output noise of the low
noise bandgap reference.
13
CHAPTER II
AN ANALYSIS OF STANDARD CMOS BANDGAP REFERENCES
The very best commercial IC voltage references use a buried Zener diode formed
by ion implantation to obtain very low 1/f noise and very low temperature coefficients
[13], [14]. These components achieve their low temperature coefficients by canceling the
negative temperature coefficient of the Zener effect with the positive temperature
coefficient of the avalanche effect. Interestingly, the manufacturers of these precision
Zener references do not specify that these components will have a particular value of
output voltage (i.e. minimum absolute error), but instead specify that the output voltage
variation in ppm / ˚C over time under normal operating conditions will be extremely
small (i.e. minimum relative error). Unfortunately, ion-implanted Zener references are
designed as discrete devices which require additional external components and high-
frequency filtering for proper operation, since they generate high levels of white noise. A
good low voltage Zener diode is not generally available in a typical CMOS process [3],
and surface defects in a standard diffused diode would generate excessive 1/f noise even
if the device were successfully fabricated.
If a high quality voltage reference is required which can be integrated into a bulk
CMOS process without the use of external components, the best circuit choice is the
bandgap reference, as demonstrated by the examples presented in the previous chapter.
Bandgap references are easily implemented in CMOS, BiCMOS, or bipolar technologies
and can readily achieve temperature coefficients of 20 ppm / ˚C or less. As shown in
Table 1-1 and Table 1-2, nearly all of the previously presented CMOS bandgap circuits
14
have high power supply rejection ratios and/or low output impedances [7], although they
also tend to suffer from high intrinsic output noise.
The integrated circuit bandgap voltage reference works by combining two easily
generated voltages having equal and opposite temperature coefficients. One of these
voltages is a forward-biased diode voltage drop (or a base-emitter voltage drop if a
bipolar transistor is used) with a temperature coefficient of approximately -2 mV / ˚C.
The second voltage is based on the thermal voltage VT from the p-n junction voltage-
current equation, or
VT =kT
q(2-1)
where k is Boltzmann's constant, q is electron charge, and T is absolute temperature in ˚K
[6]. The thermal voltage's temperature coefficient is therefore proportional with respect
to absolute temperature (or PTAT), and is multiplied by a gain constant K until the
temperature coefficient has reached approximately +2 mV / ˚C. The two voltages are
then summed to produce a reference voltage VREF with an ideal temperature coefficient
of 0 mV / ˚C (Fig. 2-1). The circuit gets the name "bandgap reference" because the value
of VREF at the minimum temperature coefficient is ideally equal to Vg0, the bandgap
voltage of silicon extrapolated to 0 ˚K (or 1.205 V) [15], [16]. Unfortunately, the
temperature coefficient of VBE is only inversely proportional to absolute temperature
(IPTAT) to the first order. Higher order nonlinearities cause the temperature coefficient
of VREF to become non-zero above or below the nominal operating temperature. These
temperature coefficient nonlinearities will be derived in detail in the next section.
15
∑+
+
Gain= K
TC ≈ - 2 mV / ˚C
TC ≈ + 2 mV / ˚C
TC ≈ 0 mV / ˚C
VBE
V T =kT / q
V REF =VBE + KVT
≈ 1.2 V
Fig. 2-1. The Bandgap Voltage Reference Principle
In a bandgap voltage reference, the thermal voltage VT can be generated by the
difference between two base-emitter voltage drops. The relationship between the voltage
VBE and the collector current IC in a transistor is
VBE = VT lnIC
IS
(2-2)
where IS is the reverse saturation current of the base-emitter junction [6]. Given two
forward biased base-emitter voltage drops, VBE1 and VBE2, assume that the base-emitter
junction area of the second transistor is larger and/or the collector current of the first
transistor is smaller. The voltage difference between the two junctions can be expressed
as
VBE1 − VBE2 = VT lnIC1
IS1
− VT ln
IC2
IS2
= VT ln
K1IC2
IS1
− ln
IC2
K2IS1
(2-3)
16
where K1 and K2 are constants such that K1K2 > 1. Simplifying equation (2-3) gives
VBE1 − VBE2 = VT lnK1IC2K2IS1
IS1IC2
= VT ln K1K2( ) = ∆VBE (2-4)
with the result that ∆VBE will be equal to VT times a positive constant. In some bandgap
reference circuits, bipolar transistors are connected base to collector and can be replaced
by simple p-n diodes. In these cases, the voltage drop between the two diodes could be
represented by ∆VD instead of ∆VBE. However, the circuits presented in this dissertation
use bipolar transistors to generate the voltage difference, and the terms "VBE" and
"∆VBE" will be used even when diodes are shown to simplify the schematic.
In addition to bipolar junctions, a VT-dependent voltage can also be produced by
the difference of the gate-source voltages between two MOSFETs operating in the
subthreshold region, since these transistors exhibit an exponential relationship between
gate-source voltage and drain current in this operating region [3]. A CMOS bandgap
reference with very low quiescent current has been constructed using this subthreshold
biasing method [17], but the circuit's high intrinsic device noise (due to low operating
current) and standard bandgap circuit topology do not make it a viable candidate for a
low noise CMOS voltage reference.
A Theoretical Analysis of Bandgap Reference Temperature Coefficient
As mentioned in the previous section, standard bandgap voltage references do not
exhibit a non-zero temperature coefficient over their entire operating temperature range
because the voltage across a forward biased base-emitter junction is not strictly IPTAT.
17
The relationship between temperature, collector current, and base-emitter voltage in a
bipolar transistor is given by
IC (T ) = C Tη e
q (VBE (T )−Vg0 )
kT (2-5)
where C is a constant and η is a positive variable somewhat influenced by the fabrication
process [4], [16]. Rearranging terms and taking the natural logarithm of both sides of
equation (2-5) gives
ln IC (T )[ ] − ln(C) − η ln(T ) =q
kTVBE (T ) − Vg0( ) . (2-6)
Since this analysis is concerned with the variation in VBE as operating temperature varies
around a nominal temperature Tr, the values of VBE and IC at temperature Tr must also
be included. Replacing T with Tr in equation (2-6) results in
ln( IC (Tr)) − ln(C) − η ln(Tr) =q
kTrVBE (Tr ) − Vg0( ) . (2-7)
Equation (2-7) can then be subtracted from equation (2-6) to obtain
lnIC (T )
IC (Tr)
− η lnT
Tr
=
q
kTVBE (T ) − Vg0( ) −
q
kTrVBE (Tr) − Vg0( ) . (2-8)
Multiplying both sides of equation (2-8) by kT/q and rearranging terms finally gives
18
VBE (T ) = Vg0 1−T
Tr
+
T
TrVBE (Tr) +
kT
qln
IC (T )
IC(Tr)
− η ln
T
Tr
. (2-9)
As mentioned in the previous section, a bandgap reference voltage can be
generated by summing VBE(T) from equation (2-9) with a gain constant K times the
difference between two base-emitter voltages, or
VREF = VBE (T ) + K ∆VBE (T ). (2-10)
To simplify the analysis, let VBE(T) = VBE1(T) and ∆VBE(T) = VBE1(T) - VBE2(T). The
bandgap reference voltage VREF now becomes a linear combination of two base-emitter
voltages VBE1 and VBE2 such that
VREF = VBE1(T ) + K VBE1(T ) − VBE2 (T )( ) = (K +1)VBE1(T ) − KVBE2(T ). (2-11)
Substituting equation (2-9) for the terms VBE1(T) and VBE2(T) in equation (2-11) and
rearranging terms gives the result
VREF = Vg0 1− T
Tr
+ (K +1)
T
TrV BE1(Tr ) − K
T
TrVBE2(Tr )
+ (K +1)VT lnIC1(T )
IC1(Tr )
− KVT lnIC2 (T )
IC2(Tr)
− ηVT lnT
Tr
.
(2-12)
Equation (2-12) is the most general form of the bandgap voltage reference
equation for two base-emitter junctions, but this equation can be greatly simplified given
some basic restrictions for collector currents IC1 and IC2. One very common design
19
assumption is for both currents to be directly temperature dependent such that IC1(T) =
HTm and IC2(T) = JTm, where H and J are constants and m is the coefficient of the
absolute temperature T. Substituting these values into equation (2-12) gives
VREF = Vg0 1−T
Tr
+ (K +1)
T
TrV BE1(Tr ) − K
T
TrVBE2(Tr )
+ (K +1)VT m lnT
Tr
− K VT m ln
T
Tr
− η VT ln
T
Tr
(2-13)
which can be simplified to
VREF = Vg0 1−T
Tr
+ (K +1)
T
TrV BE1(Tr ) − K
T
TrVBE2(Tr )
− (η − m)VTlnT
Tr
.
(2-14)
In order to first-order compensate a bandgap reference circuit under these conditions, the
gain factor K for VREF must be chosen so that the temperature coefficient is equal to zero
for T = Tr. First, the derivative of VREF with respect to temperature is taken to obtain
∂VREF
∂T=−
Vg0Tr
+K +1Tr
VBE1(Tr) −K
TrVBE2(Tr) − (η − m)
k
q1+ ln
T
Tr
. (2-15)
Next, the derivative is set equal to zero at T = Tr with the result
20
∂VREF
∂T
T =Tr
=−Vg0Tr
+K +1Tr
VBE1(Tr) −K
TrVBE2(Tr) − (η − m)
k
q=0 . (2-16)
Solving for the gain constant K gives the first-order compensation requirement of
K =Vg0 − VBE1(Tr ) + (η − m)
k
qV BE1(Tr ) − VBE2(Tr )
. (2-17)
If K is set to this value, equation (2-14) reduces to
VREF = Vg0 + (η − m) kT
q 1− ln
T
Tr
(2-18)
where
VREF T=Tr= Vg0 + (η − m)
kTr
q (2-19)
is the nominal (and maximum) value of the reference voltage. At temperatures above or
below Tr, the value of VREF will fall below the nominal value. The temperature
dependent portion of the VREF expression is the voltage VREFTD, where
VREFTD = (η − m) kT
q 1− ln
T
Tr
. (2-20)
21
Note that if the VREFTD term can be precisely canceled, the value of VREF ideally
reduces to Vg0, the extrapolated silicon bandgap voltage at 0 ˚K. However, the value of
Vg0 is semi-empirical in equation (2-5), and the bandgap voltage Vg is slightly non-linear
with respect to temperature itself [4], [16]. As such, the "ideal" bandgap reference
voltage VREF = Vg0 may vary slightly from one process to another.
Higher-Order Temperature Compensation
The value of VREFTD as given in equation (2-20) must be reduced or canceled to
minimize the temperature coefficient of the bandgap reference voltage VREF in equation
(2-18) . This process can be accomplished by one of two separate methods (or a
combination of the two). The first method is to minimize the value of (η - m), where η is
a temperature coefficient somewhat dependent on process and m is the temperature
coefficient of the current source supplying the two diodes in the bandgap reference
circuit. Typically η ≈ 4 for most processes, while m ≈ -1 for an IPTAT current source or
+1 for a PTAT current source [6], [16]. Clearly, using a PTAT bias current will nearly
halve the temperature coefficient of VREF as compared to an IPTAT current, and setting
η = m will cancel VREFTD completely. Unfortunately, building a PTAT4 current source
is a difficult task, and in fact only PTAT2 sources have been used in previous bandgap
circuits. Nevertheless, even the use of a PTAT bias current will significantly reduce the
temperature dependence of VREF as shown in Fig. 2-2. The voltage VREF obtains an
average temperature coefficient of less than 20 ppm / ˚C without resorting to more
complex circuit methods.
22
Ref
eren
ce O
utpu
t (V
olts
)
Temperature (˚K)
1.2814
1.2816
1.2818
1.2820
1.2822
1.2824
1.2826
240 260 280 300 320 340 360
TC [250 ˚K - 300 ˚K] ≈ +18 ppm /˚C
TC [300 ˚K - 350 ˚K] ≈ -16 ppm /˚C
Fig. 2-2. Bandgap Reference Output with PTAT Bias Current (Tr = 300 ˚K)
Since building a PTAT4 current source is impractical, the (η - m) term in equation
(2-20) can also be minimized by adding and then subtracting additional bandgap voltages
from VREF. Assume that three bandgap reference voltages with m ≈ 0 (constant current
bias) are summed together and subtracted from four bandgap voltages with m ≈ 1 (PTAT
bias). If η ≈ 4, the resulting reference voltage will be
VREF ≈4 Vg0 + 4∗3 kT
q 1− ln
T
Tr
−3Vg0 −3∗4 kT
q 1− ln
T
Tr
(2-21)
which reduces to
23
VREF ≈ Vg0 . (2-22)
A bipolar bandgap reference using stacked diodes to implement this type of
compensation has been constructed [4], and trimmed temperature coefficients as low as
0.5 ppm / ˚C over the -25 to +85 ˚C temperature range have been reported.
Unfortunately, good stackable p-n diodes are not possible in a bulk CMOS process, and
the minimum operating voltage of the bipolar version is 5.5 V, which makes the
technique impractical for low voltage applications.
Besides altering the value of m, the effect of VREFTD on VREF in equation (2-20)
can also be reduced by adding a linearizing voltage which will directly cancel the
temperature dependent terms. One variation of this method requires an adjustment of the
gain K and the addition of a PTAT2 term to a CMOS bandgap reference voltage [5]. To
understand how this cancellation works, consider the Taylor series expansion of the
voltage VREFTD around T = Tr. VREFTD can be expressed as
VREFTD = VREFTD(Tr) + ′ V REFTD(Tr ) T − Tr[ ]
+′ ′ V REFTD(Tr) T − Tr[ ] 2
2!+
′ ′ ′ V REFTD(Tr) T − Tr[ ] 3
3!+...
(2-23)
which is evaluated to obtain the result
VREFTD = (η − m)kTr
q+ 0 − (η − m)
k
qTr
T − Tr[ ] 2
2
+ (η − m) k
qTr2
T − Tr[ ] 3
6+... .
(2-24)
24
Next, VREFTD is approximated using the first three terms of the Taylor series expansion
such that all polynomial terms of order n = 3 or higher are ignored, or
VREFTD ≈ (η − m)kTr
q− (η − m)
k
qTr
T − Tr[ ] 2
2. (2-25)
Therefore, VREFTD is approximately equal to
VREFTD ≈ (η − m) k
q
Tr
2+ T −
T2
2Tr
. (2-26)
The temperature dependent terms in VREFTD are then canceled by adding the
linearization voltage VCOMP such that
VCOMP = (η − m) k
q −T +
T2
2Tr
. (2-27)
The T dependent term of VCOMP is generated by slightly adjusting the gain K in equation
(2-14), while the T2 term is summed with VREF using a PTAT2 current source. Fig. 2-3
shows that the PTAT-biased bandgap voltage reference's average temperature coefficient
is approximately 1 ppm / ˚C once the PTAT2 term is added. Note that the value of m can
be arbitrary in equation (2-27), although increasing m will reduce the magnitude of the
reference voltage deviations at the extreme ends of the operating temperature range.
25
1.24370
1.24372
1.24374
1.24376
1.24378
1.24380
1.24382
1.24384
240 260 280 300 320 340 360
Ref
eren
ce O
utpu
t (V
olts
)
Temperature (˚K)
TC [250 ˚K - 300 ˚K] ≈ +1.1 ppm /˚C
TC [300 ˚K - 350 ˚K] ≈ +0.9 ppm /˚C
Fig. 2-3. Bandgap Reference Output with PTAT2 Compensation (Tr = 300 ˚K)
In conclusion, this temperature compensation analysis is only valid in the case
where the currents through both base-emitter junctions of the bandgap reference are
strictly equal to some constant times Tm, and thus are always proportional to one another
by a constant factor. If this proportionality between IC1 and IC2 is affected by other
operating conditions such as the magnitude of the output voltage, the error term in
equation (2-12) will be far more complex, and the temperature dependent term VREFTD
may be quite different from equation (2-20).
26
Intrinsic Noise in CMOS Bandgap References
Overall, previous CMOS bandgap designs have proven to be good performers in
every respect except for high output noise [7]. The design of a high performance, low
noise CMOS bandgap reference requires an understanding of what types of noise are
generated by CMOS components and how the topology of the circuit amplifies this noise
at the output of the circuit.
Intrinsic Noise Sources in CMOS Components
A typical analog CMOS circuit may contain PFETs, NFETs, polysilicon resistors,
capacitors, p-n diodes, and vertical bipolar transistors [3]. Of these components, by far
the largest low frequency noise contributions come from the flicker noise sources of the
MOSFET transistors, especially the NFETs (which generally have much higher flicker
noise than PFETs of similar size and operating current) [8], [18], [19]. Over a 1 Hz noise
bandwidth, the equivalent input noise voltage of an MOS transistor can be expressed as
En2 = Ethermal
2 + E1/ f2 =
8kT(1+ gmbs / gm )
3gm+
KF
2CoxWL ′ K f(2-28)
where f is the frequency, k is Boltzmann's constant, T is absolute temperature, KF is the
flicker coefficient of the 1/f noise component, K´ is the transconductance parameter, Cox
is the oxide capacitance, gm is the gate-channel transconductance, gmbs is the bulk-
channel transconductance, and W and L are the width and length of the MOSFET. As
this equation shows, flicker noise is inversely proportional to the square root of the gate
area of the MOSFET [3], [8]. Therefore, to reduce a given MOSFET's 1/f noise by a
factor of ten would require that the gate area be made 100 times larger. However, the 1/f
noise of a particular CMOS circuit may also be reduced by changing the topology and
27
using PFETs instead of NFETs for those devices that contribute the greatest amount to
the output noise.
Besides 1/f noise, CMOS circuits can also generate a considerable amount of
white noise, usually in the form of MOSFET channel noise and resistor thermal noise.
For a given voltage drop, these noise sources are inversely proportional to the square root
of the current flowing through the components [3], [8], provided the width-to-length ratio
of a MOSFET is increased linearly with respect to the drain current. In other words,
MOSFETs with larger drain currents will have less channel noise, and smaller resistors
will have higher currents and smaller thermal noises. Furthermore, switched-capacitor
circuits have no particular advantage over linear designs in terms of thermal or channel
noise, since the kT/C noise generated by the switches will be equal to the thermal noise
generated by their equivalent resistances [20], [21].
Vertical bipolar transistors and p-n diodes usually do not contribute in any
significant way to the output noise of a typical CMOS circuit. In the first place, the shot
and thermal noise sources of a bipolar transistor are normally smaller than the channel
noise of a MOSFET with the same current drain [18], [22]. Second, the 1/f noise corner
frequencies of these devices are very small when compared to those of a PFET or NFET
of similar size. A typical bipolar transistor may have En and In 1/f noise corner
frequencies of 100 Hz or less, while a MOS transistor may have an En 1/f noise corner in
the tens of KHz [3], [8], [18], [19]. Unfortunately, the collector of a vertical transistor
will be constrained to VDD or VSS, limiting the application of this device. Either the
anode or the cathode of a p-n diode will be constrained to VDD or VSS as well.
Since the six bandgap references presented in the previous chapter have small to
moderate areas (0.18 mm2 to 2.26 mm2) and small to moderate supply currents (3.05 µA
to 1.2 mA), high 1/f and white noise levels are to be expected. None of these circuits was
designed with low output noise as a principal requirement. Reducing the output noise of
28
a CMOS bandgap circuit will require the use of larger MOSFETs, higher currents, and/or
the use of bipolar devices in place of MOSFETs at critical places in the circuit.
Fortunately, research over the past ten years has shown that a good lateral bipolar
transistor is available in any standard CMOS process [18]. These transistors have an
unconstrained lateral collector, although they also have a vertical parasitic collector
which siphons off a portion of the emitter current. With proper attention to their
limitations, lateral bipolar transistors can provide better device matching and significantly
reduced flicker and white noise when used as replacements for MOSFET transistors in
critical places in a CMOS circuit.
A Small-Signal Analysis of Simple Bandgap Voltage References
The Operational Amplifier Bandgap Reference Circuit
Besides the intrinsic noise generated by its components, a standard CMOS
bandgap reference suffers from noise multiplication due to the topology of the circuit. To
get a better understanding of the relative contributions of each noise source at the output
of a typical bandgap reference, consider the circuit in Fig. 2-4 [6], a well-known standard
bandgap reference circuit using an operational amplifier. This circuit has the advantages
of a very low impedance output and a very high power supper rejection ratio limited by
the PSRR of the op amp.
Assuming a noisy operational amplifier with infinite gain, infinite input
resistance, and zero output resistance, the reference voltage will be
VREF = VBE1 +R2R3
∆V BE( ) (2-29)
29
where ∆VBE is the difference between the base-emitter voltage drops of Q1 and Q2 2.
The base-emitter junction area of Q2 must be larger than that of Q1 and/or IC2 must be
less than IC1 to ensure that VBE1 is less than VBE2. Since the operational amplifier has
zero voltage drop across its inputs, the current through R3 will be proportional to ∆VBE,
and this current will create a voltage drop across R2 to generate the full bandgap
reference voltage at the output.
-
+VBE2
VBE1
VBE1
R1R2
R3
∆VBE
R3
Q1Q2
VREF = VBE1
+ R2R3
∆VBE
Fig. 2-4. The Operational Amplifier Bandgap Voltage Reference
2. For bandgap circuits which use PNP bipolar transistors, the "VBE" and "∆VBE" voltages are actually
"VEB" and "∆VEB" voltages, since the voltage drops are emitter-base voltages rather than base-emitter
voltages. However, the standard convention in the literature for bandgap references is to call these voltages
"VBE" and "∆VBE" when they are generated by a forward-biased p-n junction, regardless of the polarity of
the bipolar transistor. This convention will be used in this dissertation as well.
30
-
+
* *
*
**
*
*
**
R1R2
R3
ER1ER2
ER3
Eout
In1
In2
En1
En2
Id2 Id1rd1rd2
Fig. 2-5. AC Equivalent Circuit of the Op Amp Bandgap Reference
The ratio of R2 divided by R3 must be sufficiently large to amplify the ∆VBE
voltage in order for the bandgap reference to achieve minimum temperature coefficient.
Unfortunately, this gain also amplifies the intrinsic noise sources of the circuit. Using the
small-signal diagram of Fig. 2-5, the output noise voltage can be expressed as
Eout2 = Kn1
2 En12 + En2
2( ) + Rn1In1( )2 + Rn22 In2 + Id1( )2
+ KR1ER1( )2 + KR2ER2( )2 + KR3ER3( )2 + RD2Id2( )2(2-30)
31
where
Kn1 =1
rd2 + R3rd2 + R2 + R3
− rd1rd1 + R1
(2-31)
Rn1 =1
1rd2 + R3
+ 1R2
rd1
rd1 + R1
− 1
R2
(2-32)
Rn2 =1
1rd1
+ 1R1
rd2 + R3
rd2 + R2 + R3
− 1
R1
(2-33)
KR1 =1
1− rd1 + R1rd1
rd2 + R3
rd2 + R2 + R3
(2-34)
KR2 =1
1− rd1rd1 + R1
rd2 + R2 + R3
rd2 + R3
(2-35)
KR3 =1
1+ rd2 + R3R2
rd1
rd1 + R1
− rd2 + R3
R2
(2-36)
RD2 =rd2
rd2 + R3R2
− 1+ rd2 + R3R2
rd1
rd1 + R1
. (2-37)
32
Because of the relatively low dynamic resistance of a diode at a given DC current,
one can safely assume that R1 and R2 will be much greater than rd1 and rd2 if the bandgap
output voltage is about 1.2 V. Given these assumptions, equations (2-30) through (2-37)
can be reduced to
Eout2 = 1+
R2rd2 + R3
2En1
2 + En22 + rd1In2( )2 + rd1Id1( )2 +
rd1R1
ER1
2
+ R2rd2 + R3
2ER3
2 + rd2Id2( )2( ) + R2In1( )2 + ER22 .
(2-38)
As equation (2-38) shows, the feedback network formed by R2 and (rd2+R3) acts
as a multiplier for most of the intrinsic noise sources of the bandgap circuit. This noise
multiplication is especially undesirable with respect to the equivalent input noise of the
amplifier, which can have a very high 1/f corner frequency in a CMOS technology. The
gain ratio can be reduced if the ∆VBE voltage across R3 is increased by making the base-
emitter junction area of Q2 much larger than the area of Q1 and/or setting the current
through Q2 much smaller than the current through Q1. However, in practice it is difficult
to make ∆VBE much larger than 150 mV due to the exponential current-voltage behavior
of a p-n junction, so R2 will always be considerably larger than (rd2+R3). A second
possibility is to bypass R2 with a capacitor to reduce the AC gain of the bandgap
reference while preserving the DC characteristics. The noise gain will be attenuated
above the frequency set by the pole of R2 and the capacitor, although area considerations
for a practical integrated circuit would limit the size of an integrated capacitor. An
external discrete capacitor is a better solution in this case, but the use of any external
component is extremely undesirable for an integrated low noise voltage reference.
33
The PTAT Current Source Bandgap Reference Circuit
Another common CMOS bandgap reference circuit consists of a PTAT current
source which supplies current to a base-emitter junction in series with a resistor as shown
in Fig. 2-6 [6]. Although the power supply rejection is generally not as good as that of
the op amp bandgap reference, it can be improved considerably through the use of
cascode current mirrors and long channel MOSFETs. The circuit does not have a low
impedance output, but a unity-gain output buffer amplifier can be added if needed.
In this circuit, MOSFETs M1 through M4 form a feedback loop which forces the
voltages at the sources of M4 and M5 to be equal. In turn, the current through resistor R1
is dependent on the difference between VBE1 and VBE2. This PTAT current is multiplied
by the current mirror ratio of M3 to M2 and appears across resistor R2 at the output. The
resulting reference voltage is
VREF = VBE3 +R2
R1 W3
L3
L2
W2
∆VBE (2-39)
where W3, L3, W2, and L2 are the widths and lengths of transistors M3 and M2,
respectively.
34
. . .
VBE3
R1
VBE1 VBE1
VDD VDD V DD
V BE2
Q1 Q2 Q3
R2
M1 M2 M3
M4 M5
ID4 ID5
V REF = VBE3 +
R2R1
W3
L3
L2W2
∗ ∆VBE
W3L3
L2W2
∗ ID5
Fig. 2-6. The PTAT Current Source Bandgap Reference
35
*G
*G
*G
*G
*G
D
D
SS
S
D
D
S
* *
* * *
D
S
R1 R2
Eout
rd1 rd2 rd3Id1 Id2 Id3
ER1 ER2
Eg1 Eg2 Eg3
Eg4 Eg5
gm1∗Vgs1
gm2∗Vgs2
gm3∗Vgs3
gm4∗Vgs4
gm5∗Vgs5
Fig. 2-7. AC Equivalent Circuit of the PTAT Current Source Bandgap Reference
The noise gain mechanisms in this circuit can be examined using the small signal
diagram in Fig. 2-7. Since the drain-source resistances of the MOSFETs are much larger
than the other equivalent resistances in the circuit, all rds terms can be ignored. The
output noise of the PTAT current source bandgap circuit is therefore equal to
36
Eout2 = K1
2 Id1rd1( )2 + Eg1gm1( )2rd1 + 1
gm4
2+ Eg4
2
+ K12 Eg2gm2( )2
R1 + rd2 +1
gm5
2+ Eg5
2
+ K22 ER1
2 + Id2rd2( )2 + Eg32[ ] + ER2
2 + Id3rd3( )2
(2-40)
where the gain constants K1 and K2 are defined as
K1 =gm3 R2 + rd3( )
gm2 R1 + rd2( ) − gm1rd1(2-41)
K2 =gm3 R2 + rd3( )gm2 R1 + rd2( ) . (2-42)
Once again, the same mechanism that amplifies the ∆VBE voltage also amplifies
most of the intrinsic noise sources in the circuit. However, the presence of the
transconductance and dynamic resistance terms in the K1 and K2 gain equations indicates
these gains should be influenced by device currents. To determine this current
dependence, assume M1 through M3 have the same gate length and that their device
widths are related by the equation
W1 = P2W2 = P3W3 (2-43)
where P2 and P3 are constants. Since all three devices are connected as current mirrors,
their drain currents will also be related by the same constants such that
37
ID1 = P2ID2 = P3ID3 . (2-44)
Ignoring lambda effects, a PFET in saturation has a transconductance value of
gm = 2 ′ K pW
L ID (2-45)
where K´p is the transconductance parameter and ID is the drain current [3]. Substituting
equations (2-43) and (2-44) into equation (2-45) gives the result
gm1 = P2gm2 = P3gm3 . (2-46)
Likewise, given the equation for the dynamic resistance of a p-n diode [6]
rd =VT
IC(2-47)
then the small-signal resistances of diode connected transistors Q1, Q2, and Q3 will be
related by
rd1 =rd2P2
=rd3P3
. (2-48)
Since R1 = ∆VBE / ID5, equation (2-2) can be substituted for ∆VBE to obtain
38
R1 =VT ln
IS2 IC1IS1IC2
ID5(2-49)
where ID5 is the drain current of M5 and IS1 and IS2 are the respective reverse saturation
currents of Q1 and Q2. The R2 term can also be replaced by
R2 =VREF - VBE3
IC3=
VREF - VT lnIC 3IS3
IC3. (2-50)
Knowing that IC3 = -ID5, IC2 = ID5 = -ID2, and IC1 = ID4 = -ID1, equations (2-43) through
(2-50) can be substituted into the equations for gains K1 and K2 to obtain
K1 =VREF − VT ln
IC3IS3
+ VT
VT lnIS2IC1IS1IC2
(2-51)
K2 =V REF − VT ln
IC3IS3
+ VT
VT lnIS2IC1IS1IC2
+ VT
. (2-52)
Interestingly, equations (2-51) and (2-52) indicate that gains K1 and K2 are only weakly
dependent on currents IC1, IC2, and IC3 because of the natural logarithm terms. These
gains can be decreased by increasing IC3 (although this will have little effect due to the
39
larger VREF term), increasing the ratio of IC1 to IC2, or increasing the base-emitter
junction area ratio of Q2 to Q1. Also, the equivalent shot and channel noise voltages of
equation (2-40) are inversely proportional to the square root of device current, so higher
currents will reduce the intrinsic white noise if not necessarily the gains K1 and K2.
Unfortunately, the PTAT current source bandgap reference topology cannot be
used to construct a practical low noise bandgap reference. At higher operating currents
and lower output noise levels, resistor R2 rapidly becomes too small to trim effectively,
as illustrated in the next section.
Other Design Considerations for CMOS Bandgap Voltage References
Up to this point, only the issues of temperature compensation and gain
mechanisms of intrinsic noise in bandgap references have been examined. However, a
low noise CMOS bandgap reference design must address additional constraints to be
practical in an integrated circuit application. Among these are
(1) Circuit size,
(2) Power dissipation,
(3) Minimum operating voltage,
(4) Device mismatch,
(5) Ease of output trimming.
Circuit size and power dissipation are related design constraints because of their
effects on bandgap reference output noise. As mentioned in the section on CMOS device
noise, intrinsic thermal noise is (at best) inversely dependent on the square root of
quiescent current or component size, while 1/f noise will be inversely proportional to the
square root of the gate areas of the MOSFETs used in the circuit. For example, consider
the differential bandgap reference [10] discussed in Chapter I. With an area of 1.16 mm2
40
and a quiescent current of 1.2 mA, this circuit generates approximately 320 µV RMS of
output noise over a 500 KHz bandwidth. If one were willing to apply brute force
techniques to reduce white noise and 1/f noise by an order of magnitude, the circuit
would require a quiescent current of 120 mA and an area of 116 mm2. Clearly, these area
and current requirements would be unacceptably large for an integrated circuit. A
workable low noise bandgap circuit requires a topology that bypasses the inverse square
root limitation. Maximum limits of 2 mm2 of circuit area and 10 mA of quiescent current
were established as desirable design goals early in this research.
The minimum operating voltage is the next consideration in choosing a topology
for a low noise bandgap reference design. As nominal supply voltages for integrated
circuits fall to 3.3 V and below, a minimum operating voltage of 3.0 V or less becomes
very desirable. The standard bandgap circuits presented in the previous section are good
performers in this respect and can operate down to the supply voltage limits of the op
amp and PTAT bias circuit. On the other hand, design strategies which rely on stacked
diodes or stacked base-emitter junctions [8], [4] to generate the bandgap voltage quickly
become impractical, since each forward-biased p-n junction increases the minimum
operating voltage by approximately 0.65 V.
Finally, device mismatch and circuit trimming must be considered in the bandgap
design. A good bandgap reference design should be relatively insensitive to device
mismatches and changes in the values of the components used to trim the operating point
of the circuit. Device matching in integrated circuit technologies in general and bandgap
reference designs in particular has been previously investigated in depth [5], [9], and this
dissertation will not focus on this issue to any great extent. The more important question
in the design of a low noise bandgap reference is how the topology of the circuit affects
the circuit's sensitivity to component mismatches, especially when trimming the output
voltage to a nominal value. Ideally, the circuit should have a broad trimming range such
41
that very small changes in (for example) a trimming resistor do not drastically alter the
output voltage and temperature coefficient of the circuit. Consider the sensitivity
parameter
x
y
S=
∂y
y∂xx
=∂y
∂x
x
y(2-53)
which is defined as the sensitivity of the parameter y with respect to a change in
parameter x [3]. Using equations (2-2) and (2-4), the bandgap reference voltage between
two base-emitter junctions can be defined as
VREF = VBE1 + K∆VBE = VT lnIC1IS1
+ KVT ln
IS2IS1
IC1IC 2
. (2-54)
Note that the terms IC1, IS1, IC2, and IS2 are all inside a natural logarithm operator, and as
such VREF is relatively insensitive to changes in them. For example, assuming VBE1 =
0.65 V, ∆VBE = 0.55 V, K = 4, and VREF = 1.2 V, the sensitivity of VREF with respect to
IC1 is calculated to be
IC1
VREF
S =∂VREF
∂IC1
IC1VREF
=K +1( )VT
V REF= 0.108 (2-55)
which indicates that a 1% increase in IC1 will lead to a 0.108% increase in VREF. On the
other hand, the sensitivity of VREF with respect to the gain K is
42
K
VREF
S =∂VREF
∂K
K
VREF=
K ∆VBE
VREF= 0.458 (2-56)
which is more than four times larger. The gain K generally depends on resistor and/or
current mirror ratios and is usually the parameter that is adjusted in standard bandgap
reference designs to obtain the nominal operating voltage. This situation is worsened if
the resistor values themselves are uniformly reduced for higher currents and lower
intrinsic noise. A bandgap reference design that must be trimmed with 1 Ω adjustments
to a 100 Ω resistor is simply not practical in a CMOS process.
Fig. 2-8 shows a low noise bandgap reference topology [8] that avoids the
problem of gain K sensitivity by summing the ∆VBE voltage drops with stacked diodes
rather than multiplying a single ∆VBE voltage. Unfortunately, this circuit cannot be
implemented in a bulk CMOS process due to the lack of a stackable floating p-n diode.
Furthermore, a minimum of three diodes must be stacked to generate the ∆VBE voltage,
and this in turn raises the minimum supply voltage of the circuit.
43
VDD
IPTAT
R1
VREF
D1
D2
D3
D4
D5
D6
D7
Diodes D1 through
D4 are identical.
Diodes D5 through
D7 are identical
devices of greater
area.
Fig. 2-8. A Low Noise Bandgap Reference Topology
44
CHAPTER III
A PRACTICAL LOW NOISE CMOS BANDGAP REFERENCE TOPOLOGY
As illustrated in the previous two chapters, standard bandgap reference circuits
are not well suited for low output noise applications in CMOS processes. On the other
hand, there is no reason why a low noise CMOS bandgap reference cannot be
constructed. Unlike a standard amplifier, the desired output signal of a voltage reference
is a DC voltage, while the undesired intrinsic noise is generated at AC frequencies. Since
the DC gain mechanism need not be intrinsically linked with the AC noise gain, it is
theoretically possible to create a variation of the bandgap voltage reference which
preserves the desired DC output voltage while minimizing high frequency gain without
using bypass capacitors. A practical low noise CMOS bandgap reference requires a new
topology which achieves low output noise while maintaining acceptable chip area, power
consumption, minimum supply voltage, temperature coefficient, and component
sensitivity. This chapter introduces a new low noise bandgap topology which meets all
these requirements and can be implemented in a bulk single poly, double metal CMOS
process.
Noise Multiplication versus Noise Addition
Unfortunately, a standard bandgap reference's intrinsic noise is increased by the
approximate multiplication factor used to amplify the ∆VBE voltage. Unless one is
willing to use large bypass capacitors, the DC and AC gain mechanisms cannot be
separated. However, there is an alternative approach that can reduce the circuit's output
noise while preserving the desired DC characteristics of the bandgap reference. This
approach involves adding several ∆VBE voltages together instead of multiplying a single
45
∆VBE voltage by a gain factor. Assuming that the intrinsic noise sources associated with
the ∆VBE voltages are uncorrelated, those sources will be RMS summed [8] as ∆VBE
voltages are stacked, while the correlated DC voltages will be added linearly. Fig. 3-1
shows a simple example of this principle. Assume that a voltage source has a desired DC
voltage of 1 volt combined with an undesired noise voltage of 1 nV / Hz . If a DC
reference voltage of N volts is desired, the use of an amplifier with gain N will result in
equal amplification of the noise voltage and the DC voltage, with a resulting output noise
voltage of N nV / Hz . Furthermore, the amplifier stage will also contribute to the output
noise in an actual reference circuit. On the other hand, adding N voltage sources together
provides a DC voltage of N volts with an output noise voltage of only N nV / Hz , since
the uncorrelated intrinsic noise sources are RMS summed.
46
Gain=N
*
1 VDC
Singlevoltagesource
*
1 VDC
*
1 VDC
N voltagesourcesstacked
1 nV
Hz
1 nV
Hz
1 nV
Hz
+_
+_
+_
V DC = (N) V
Vnoise =(N) nV
Hz
VDC =(N) V
Vnoise =
N( ) nV
Hz
Fig. 3-1. Multiplication vs. Addition of DC and Noise Voltage Sources
The ∆V BE Summing Bandgap Reference Topology
To meet the dual requirements of low output noise and low temperature
coefficient, a new low noise bandgap reference topology has been implemented in a
standard single poly, double metal 1.2 µm n-well CMOS process. As demonstrated in the
previous section, the assumption behind this topology is that the output noise of a
bandgap circuit can be significantly reduced by generating the full ∆VBE voltage through
47
summation rather than multiplication. Although circuits such as the stacked diode
bandgap reference of Fig. 2-8 also use this concept, their application is limited by higher
supply voltage requirements and the need for a stackable floating p-n diode which cannot
be implemented in a bulk CMOS process. Fig. 3-2 shows an original topology which
circumvents these problems by isolating each ∆VBE summing section with a buffer
amplifier (Fig. 3-3). In order to avoid the design problems associated with switched
capacitor circuits (e.g, clock feedthrough, output only available for a portion of the clock
cycle) [23], a linear circuit has been implemented. Besides this new topology, the
reference also achieves lower noise through higher supply currents, low intrinsic AC
gain, and the use of lateral bipolar transistors [18].
∑+
+
∑+
+
∑+
+K Summing Sections
VDD
VBE1
IBIAS1
∆VBE ∆VBE ∆VBE
D1
VREF =VBE1 +K * ∆VBE
Fig. 3-2. The ∆VBE Summing Bandgap Reference Topology
The Operation of the ∆V BE Summing Bandgap Reference
Consider the ∆VBE summing subcircuit of Fig. 3-3. The current from the source
IBIAS2 has two possible paths; (1) through diode D2 into the output of the voltage
follower A1 and (2) through diode D3 and resistor R1. By making the junction area of
diode D3 larger than diode D2 (and thereby increasing the reverse saturation current) and
48
by making resistor R1 sufficiently large to reduce the current though D3, the voltage drop
across D3 will always be smaller than the voltage drop across D2 for a given range of
IBIAS2 values. The voltage VIN will appear at the output of the voltage follower A1, rise
by the value of VBE2, and fall by the value of VBE3 at the output node. The voltage VIN
is thereby increased by the difference between two base-emitter voltages, or a ∆VBE
voltage. At the same time, the output voltage is isolated from power supply variations by
the power supply rejection of IBIAS2. By cascading two or more of these subcircuits
together, the positive temperature coefficient of the output voltage can be increased with
each additional stage. As shown in Fig. 3-2, diode D1 is placed at the input of these
cascaded ∆VBE summers to provide an input voltage with a negative temperature
coefficient and thereby set the temperature coefficient of the voltage VREF as close to
zero as possible. The resulting reference voltage will be
VREF = VBE1 + ∆VBE, j j=1
K
∑ (3-1)
where K is the number of ∆VBE summing subcircuits. If all of the summed ∆VBE
voltages are equal, equation (3-1) can be reduced to
VREF = VBE1 + K ∆VBE . (3-2)
49
-
+
VIN
VIN
VDD
IBIAS2
R1
V IN + VBE2
A1 VOUT = VIN + VBE2 − VBE3 = VIN + ∆VBE
IC2 IC3D2 D3
Fig. 3-3. The ∆VBE Summing Subcircuit
The ∆VBE summing bandgap reference has some important advantages when
compared to the CMOS bandgap circuits discussed in Chapter I. First, the parameter K is
not determined by resistor ratios or current mirror ratios. The generated reference voltage
is therefore completely insensitive to the gain K in equation (3-2). Similarly, the circuit
is relatively insensitive to component mismatches, since the effects of these mismatches
will be attenuated by the natural logarithmic relationship between collector current and
base emitter voltage in equation (2-2). This same insensitivity will give the circuit a
broad trimming range and make the output voltage easier to adjust. Also, the circuit does
not require the higher power supply voltage of the stacked diode bandgap reference in
Chapter II. The minimum power supply voltage will be
VDD(min) = V REF(max) + VBE3,K (max) + VIBIAS2 ,K (max) (3-3)
50
where VBE3,K and VIBIAS2,K are the respective voltages across diode D3 and current
source IBIAS2 in the Kth (or last) ∆VBE summing subcircuit. Assuming VBE3,K(max) =
0.6 V and VIBIAS2,K(max) = 1 V, the minimum supply voltage will be about 2.8 V.
While this minimum VDD is not as low as that of the standard op amp or PTAT current
source bandgap circuits in Chapter II, it is still good enough to make the ∆VBE summing
bandgap reference practical in a 3.0 V CMOS VLSI design.
In terms of low output noise, another useful characteristic of the ∆VBE summing
bandgap topology is the low AC gain it exhibits. Because p-n diodes have very low
dynamic resistance for relatively large amount of device currents, they act as a low
impedance load for a transistor used as a current source. For example, a 1 mA current
requires a 700 Ω resistor to generate a 0.7 V voltage drop, while a diode will only have a
dynamic resistance of 26 Ω. Consequently, noise from the bias circuit is significantly
attenuated due to D1 in the VBE1 generator and D2 in the ∆VBE summing subcircuit. A
complete noise analysis of the ∆VBE summing bandgap reference is included later in this
chapter.
The most essential components in the ∆VBE summing bandgap reference are the
floating diodes D1 and D2 in the summing subcircuit. Diodes D1, D2, and D3 are
implemented using lateral bipolar transistors, which can be fabricated in a bulk CMOS
process [18]. These devices and their applications will be discussed in more detail in the
next chapter.
Temperature Dependence of the ∆V BE Summing Bandgap Reference
While the ∆VBE summing bandgap reference topology has low intrinsic noise
gain, the temperature dependence of the circuit is equally important when minimizing
relative error. The ∆VBE voltage generated by the ∆VBE summing subcircuit (Fig. 3-3)
differs from that of the two simple bandgap circuits discussed in Chapter II because the
51
currents through diodes D2 and D3 are not uniformly proportional to one another with
respect to temperature. Instead, the current through D3 is proportional to the output
voltage divided by the value of R1. Assuming that IBIAS2,j = G(j)Tp(j), the resulting
temperature-dependent current equations for each ∆VBE summing subcircuit are
IC3, j (T ) =VOUT,j (T )
R1, j (T )(3-4)
IC2, j (T ) = IBIAS2, j − IC3, j (T ) = G( j)T p( j ) −VOUT,j (T )
R1, j (T )(3-5)
where G(j) and p(j) are the magnitude and temperature coefficient of the current source
for the jth ∆VBE subcircuit. Ignoring higher order nonlinearities, R1,j(T) and VOUT,j(T)
can be expressed as
R1, j (T ) = R1, j (Tr) 1+ α R,j T − Tr( )( ) (3-6)
VOUT,j (T ) = VOUT,j (Tr) 1− αT, j T − Tr( )( ) (3-7)
where αR,j and αT,j are first-order temperature coefficients and R1,j(Tr) and VOUT,j(Tr)
are the nominal values at T = Tr.
The derivation of the output voltage of the ∆VBE summing bandgap reference
requires an examination of the bandgap reference equations of Chapter II without the
underlying assumption that IC2 is equal to a constant times IC3, and the independent
temperature behavior of voltage VBE1 in Fig. 3-2 must be considered as well. To begin
the analysis, the reference voltage can be expressed as
52
VREF = VBE1(T ) + j=1
K
∑ VBE2, j (T ) −V BE3, j (T )[ ] (3-8)
where K is the number of ∆VBE summing subsections. Substituting equation (2-9) for
each of the base-emitter voltages gives the result
VREF = Vg0 1−T
Tr
+
T
TrVBE1(Tr) +
kT
q ln
IC1(T)
IC1(Tr)
− η kT
q ln
T
Tr
+
T
Tr
j=1
K
∑ VBE2, j (Tr) − VBE3, j (Tr)[ ]
+ kTq
j=1
K
∑ lnIC2, j (T)
IC 2, j (Tr )
− ln
IC3, j (T)
IC 3, j (Tr )
.
(3-9)
Note that equation (3-9) is simply a more general equation for a standard bandgap
reference's temperature behavior than equation (2-12). Now, taking the derivative of
equation (3-9) with respect to temperature gives
∂VREF
∂T=−
Vg0Tr
+ VBE1(Tr)
Tr+ k
q ln
IC1(T )
IC1(Tr)
+ kT
q
′ I C1(T)
IC1(T)
− h kq
lnTTr
− h
kq
+ 1Tr
j=1
K
∑ VBE2, j (Tr) − VBE3, j (Tr )[ ]
− kT
q
j=1
K
∑ ′ I C2, j (Tr)
IC2, j (Tr)−
′ I C3, j (Tr)
IC3, j (Tr)
+ kq
j=1
K
∑ lnIC2, j (T )
IC 2, j (Tr )
− ln
IC3, j (T )
IC3, j (Tr)
.
(3-10)
53
For minimum temperature coefficient at the nominal operating temperature, the
derivative of equation (3-10) must be set to zero at T = Tr to obtain
∂VREF∂T
T =Tr
=−Vg0Tr
+ VBE1(Tr)Tr
+ kTr q
′ I C1(Tr )
IC1(Tr )− η
kq
+ 1Tr
j=1
K
∑ V BE2 , j (Tr ) − VBE3, j (Tr )[ ]
− kTr
q
j=1
K
∑′ I C2 , j (Tr )
IC2 , j (Tr )−
′ I C3, j (Tr )
IC3, j (Tr )
= 0.
(3-11)
Multiplying both sides of equation (3-11) by T and rearranging terms gives the following
result
− T
TrVg0 + T
TrVBE1(Tr) +
T
Tr
j=1
K
∑ VBE2, j (Tr ) − VBE3, j (Tr )[ ]
= −kTrT
q
′ I C1(Tr )
IC1(Tr )−
kTrT
q
j=1
K
∑′ I C2, j (Tr)
IC2, j (Tr)−
′ I C3, j (Tr)
IC3, j (Tr)
− η
kT
q.
(3-12)
Equation (3-12) is then substituted into equation (3-9) to obtain
54
VREF = Vg0 + kT
q ln
IC1(T )
IC1(Tr)
+ η kT
q 1− ln
T
Tr
−kTrT
q
′ I C1(Tr )
IC1(Tr )−
kTrT
q
j=1
K
∑′ I C2, j (Tr )
IC2, j (Tr )−
′ I C 3, j (Tr)
IC 3, j (Tr)
+ kTq
j=1
K
∑ lnIC2, j (T)
IC 2, j (Tr )
− ln
IC 3, j (T )
IC3, j (Tr)
.
(3-13)
Up to this point, no assumption has been made about the current through diode D1. Now
let IC1(T) = HTm, where the exponent m is independent of the exponent p of the current
sources feeding diodes D2,j and D3,j in the ∆VBE summing subcircuits. Applying this
condition reduces equation (3-13) to
VREF = Vg0 + (η − m) kT
q 1− ln
T
Tr
−kT
q Tr
j=1
K
∑′ I C2, j (Tr)
IC2, j (Tr)−
′ I C3, j (Tr)
IC3, j (Tr)
+ kTq
j=1
K
∑ lnIC2, j (T)
IC 2, j (Tr )
− ln
IC 3, j (T )
IC3, j (Tr)
(3-14)
where the nominal reference voltage at T = Tr is
VREF T =Tr= Vg0 + (η − m)
kTr
q 1− Tr
j=1
K
∑′ I C 2, j (Tr )
IC 2, j (Tr )−
′ I C3, j (Tr )
IC3, j (Tr )
. (3-15)
55
Although equation (3-14) is somewhat complex, some interesting conclusions can
easily be made. First, the expression for VREF is identical to equation (2-18) except for
the addition of the summation terms containing IC2,j and IC3,j. In fact, if IC2,j(T) equals a
constant times IC3,j(T) (as is typical for a standard bandgap reference) then equation (3-
14) reduces to equation (2-18). However, equations (3-4) and (3-5) show that this
condition does not hold in the ∆VBE summing bandgap reference. Secondly, consider the
functions
f A(T) = T (3-16)
f B,j (T ) =IC2, j (T )
IC3, j (T )(3-17)
and their derivatives
∂ ln f A(T )[ ]∂T
T =Tr
= ′ f A(T )
f A(T ) T =Tr
=′ f A(Tr )
f A(Tr )=
1Tr
(3-18)
∂ ln f B,j (T )[ ]∂T
T =Tr
= ′ f B,j (T)
f B,j (T) T =Tr
=′ f B,j (Tr)
f B,j (Tr)
=′ I C2, j (Tr )
IC2, j (Tr )−
′ I C 3, j (Tr)
IC 3, j (Tr).
(3-19)
Substituting these functions into equation (3-14) gives
56
VREF = Vg0 + (η − m) kTq
Tr ′ f A(Tr)
f A(Tr)− ln
f A(T )f A(Tr)
− kT q
Tr ′ f B,j (Tr)
f B,j (Tr)− ln
f B,j (T )
f B,j (Tr )
j=1
K
∑(3-20)
which in turn can be reduced to
VREF = Vg0 +kT
q (η − m) yA (T,Tr ) − yB, j (T,Tr )
j=1
K
∑
(3-21)
where the function yx(T,Tr) is equal to
yx (T,Tr ) = Tr ′ f x (Tr )
f x (Tr )− ln
f x (T )
f x (Tr )
. (3-22)
As equations (3-21) and (3-22) show, the error terms in equation (3-14) have the
same general form given by yx(T,Tr), yet have opposite amplitudes, depending on the
values of fA(T) and fB,j(T) for temperatures above and below Tr. Specifically, if both
error terms satisfy the condition
T∗ yx (T,Tr)[ ] < Tr2
′ f x (Tr )
f x (Tr ) for all T ≠ Tr (3-23)
then cancellation will occur between the two error terms, and either one or the other will
dominate. Accordingly, the shape of the higher-order temperature dependence of VREF
57
will either be convex (as in Fig. 2-2) or concave, depending on the component values,
device currents, and the values of K, m, and p(j). This temperature coefficient
cancellation can be better illustrated by assuming that IC2,j(T) >> IC3,j(T), in which case
equation (3-5) can be approximated by
IC2, j (T ) ≈ G( j) T p( j) . (3-24)
Assuming that p(j) = p for all j, equations (3-4) and (3-24) can be substituted into
equation (3-14) to obtain
VREF ≈ Vg0 + (η − m) kT
q 1− ln
T
Tr
−kT
q Tr
j=1
K
∑ p
Tr+ αT, j + α R,j
+ kTq
j=1
K
∑ p lnTTr
− ln
1− αT,j (T − T j )
1+ αR,j (T − T j )
(3-25)
which in turn can be simplified to
VREF ≈ Vg0 + (η − m − pK) kT
q 1− ln
T
Tr
−kT
q Tr
j=1
K
∑ αT,j + α R,j[ ]
+ kTq
j=1
K
∑ ln1+ α R,j (T − T j )
1− α T,j (T − T j )
.
(3-26)
58
Note that the values of R1,j and G(j) have no effect on the temperature dependence of
VREF in equation (3-26). Assuming three ∆VBE summing subcircuits are used (K = 3)
and that η = 4, m = 1, and p = 1, equation (3-26) can be further reduced to
VREF ≈ Vg0 −kT
q Trα T,j + Trα R,j − ln
1+ α R,j (T − T j )
1− α T,j (T − T j )
j=1
3∑ . (3-27)
If R1,j is a polysilicon resistor then the temperature coefficient αR,j will be a positive
value, typically equal to 0.001. Since the output voltage VOUT,j(T) of each ∆VBE
subsection will either have a negative temperature coefficient or a zero temperature
coefficient (at the reference output), the temperature coefficient aT,j will always be non-
negative, decreasing from an approximate value of 0.0019 to zero as j increases. Fig. 3-4
shows a plot of equation (3-27) versus temperature given these estimates. Note the
concave shape of the error term, as opposed to the convex shape in Fig. 2-2. The average
temperature coefficient is slightly greater than that of a PTAT-biased bandgap reference,
and the nominal reference voltage is less than Vg0.
59
1.1595
1.1600
1.1605
1.1610
240 260 280 300 320 340 360
Ref
eren
ce O
utpu
t (V
olts
)
Temperature (˚K)
TC [250 ˚K - 300 ˚K] ≈ -22 ppm /˚C
TC [300 ˚K - 350 ˚K] ≈ +22 ppm /˚C
Fig. 3-4. ∆VBE Summing Bandgap Reference Output with K = 3, m = 1, p(j) = 1
Although this particular example of the ∆VBE summing bandgap reference has a
temperature coefficient comparable to that of a standard PTAT-biased bandgap reference,
equation (3-26) shows that the ∆VBE summing bandgap circuit's temperature coefficient
can be much more flexible. Since m, K, and p(j) are each separately adjustable, the
potential exists to balance the convex and concave curvatures of the error terms to
achieve an extremely low average temperature coefficient. Methods of implementing
more precise curvature cancellation will be discussed in greater detail in Chapter VI.
Equation (3-26) also indicates that there is no particular relationship between the
number of ∆VBE summing subcircuit stages and the temperature coefficient of the
complete bandgap reference. While changing K does affect the magnitude of the concave
60
curvature error term, the same effect can be achieved by changing the value of p(j) for
one or more summing subcircuits, or by altering the value of m. Given this conclusion,
the number of ∆VBE summing subcircuit stages should be determined by considerations
such as power consumption, chip area, and output noise rather than higher-order
temperature compensation.
A Noise Analysis of the ∆V BE Summing Bandgap Reference
The ∆VBE summing bandgap reference achieves low noise through three
mechanisms. First, the circuit relies heavily on the use of lateral bipolar PNP transistors,
which have inherently lower 1/f and white noise than MOSFETs under similar operating
conditions [18], [19]. Secondly, the circuit operates at higher supply currents to reduce
the intrinsic noise sources of its components. Third, the topology of the circuit maintains
the required DC bandgap characteristics while minimizing AC (and noise) gain to the
reference output. Consider the simplified small-signal diagram of Fig. 3-5, which shows
the intrinsic noise sources for the PTAT current source and diode D1 from Fig. 3-2 (the
output resistance of the PFET is large enough to neglect). From this diagram, the output
noise of the VBE voltage generator can be expressed as
Eout1 = rd1 gm2 Ebias1
2 + Enp2( ) + Id1
2 (3-28)
where Ebias1 is the equivalent noise voltage generated by the bias circuit, Enp is the
equivalent input noise of the PFET, and Id1 is the shot noise current of diode D1.
Because the dynamic impedance of D1 (rd1) is relatively small for a given DC current,
the gains of noise sources Ebias1 and Enp through the PFET are quite low. Furthermore,
unless the current through D1 is very small, the shot noise of the diode will be negligible
compared to these sources. As the current through D1 is increased, the output noise of
61
the circuit will decrease as long as the width to length ratio of the PFET does not change.
Since rd1 is inversely proportional to current and the transconductance gm is only
proportional to the square root of the current [3], [6], the noise gain of the circuit will be
inversely proportional to the square root of the bias current. The shot noise of the diode
and the equivalent input noise voltage of the PFET will also decrease with the square root
of the increase of bias current.
*
** *
Id1rd1
Eout1
Ebias EnpEg gm∗Eg
Fig. 3-5. Simplified Small-Signal Equivalent Circuit for the VBE1 Generator
If the IBIAS1 current source is a variation of the PTAT current source used in the
bandgap reference of Fig. (2-6), equations (2-40) through (2-42) can be modified to
obtain a more complete expression for Eout1 by simply setting R1 (and ER1) to zero. The
resulting PTAT-biased VBE1 generator circuit is shown in Fig. 3-6. The new equation for
Eout1 is
62
Eout12 = K1
2 Id1Brd1B( )2 + Eg1gm1( )2rd1B + 1
gm4
2+ Eg4
2
+ K12 Eg2gm2( )2
R1 + rd2B +1
gm5
2+ Eg5
2
+ K22 ER1
2 + Id2Brd2B( )2 + Eg32[ ] + Id1rd1( )2
(3-29)
where the gain constants K1 and K2 are defined as
K1 =gm3rd1
gm2 R1B + rd2B( ) − gm1rd1B(3-30)
K2 =gm3rd1
gm2 R1B + rd2B( ) . (3-31)
Using the same device width assumptions from the noise analysis of the PTAT-biased
bandgap reference in Chapter II, gains K1 and K2 can be reduced to
K1 =1
lnIs2BIC1BIs1BIC2B
(3-32)
K2 =1
lnIs2BIC1BIs1BIC 2B
+1
. (3-33)
63
These results indicate that gains K1 and K2 are inversely dependent on the natural
logarithm of the ratio of IC1B to IC2B, or the ratio of the base-emitter junction areas of
Q2B to Q1B. Because of the lack of a true resistor load in the drain of PFET M3, gains K1
and K2 will both be less than unity provided the value of the natural logarithm term in
equation (3-32) is greater than one, a condition easily achieved in an actual circuit.
. . .
VBE1
VDD V DD V DD
Q1
M1 M2 M3
M4 M5
ID4 ID5
Q1B Q2B
V BE1B VBE1B
VBE2B
W3L3
L2W2
∗ ID5
R1B
Fig. 3-6. The VBE1 Generator with a PTAT Current Source
In general, the intrinsic thermal and shot noise sources in the PTAT bias circuit
will be inversely dependent on the square root of the device currents. Given the
attenuation of most of these sources by gains K1 or K2, white noise output can be
64
expected to decrease as currents IC1B, IC2B, and IC1 are increased (while maintaining the
ratio of IC1B to IC2B). As this happens, MOSFET 1/f noise sources will begin to
dominate the output noise since they are a function of device geometry rather than
transconductance [3]. For a CMOS circuit, an NFET will generally have a much higher
1/f flicker coefficient due to increased surface defects as compared to a PFET [18].
Therefore, the 1/f noise output can be approximated by
Eout1 (1/ f )2 ≈ K1
2 Eg4 (1/ f )2 + Eg5 (1/ f )
2[ ] . (3-34)
The flicker noise component of Eout1 can be reduced by increasing the gate areas of M4
and M5 in Fig. (3-6), or by increasing the ratio of IC1B to IC2B. Subsequent circuit
simulations will show that NFET flicker noise from the bias circuit is the primary source
of 1/f noise in the ∆VBE summing bandgap reference.
The same relationship between output noise and bias current also holds true for
the ∆VBE summing subcircuit. Ignoring the output resistance of the current source PFET
and assuming that rd2 is much smaller than (rd3+R1), the simplified output noise voltage
expression for this circuit (Fig. 3-7) is
Eout22 = K3
2 Esource2 + En
2 + In Rsource( )2 + rd2Id2( )2 + rd3Id3( )2[ ] + K4
2ER12 + K5
2 gmrd2( )2Ebias2
2 + Enp2( ).
(3-35)
65
*
**
**
*
**
*
*
gm∗Eg
Eg
Enp
En
In
E in
Ein
rd3rd2 Id2 Id3
Esource
Rsource
R1
ER1
Eout2
Ebias2
Fig. 3-7. Simplified Small-Signal Equivalent Circuit of the ∆VBE Summing Subcircuit
The attenuation factors K3, K4, and K5 can be expressed as
K3 =R1
rd2 + rd3 + R1(3-36)
K4 =rd2 + rd3
rd2 + rd3 + R1(3-37)
66
K5 =R1
rd3 + R1(3-38)
where Rsource is the equivalent output resistance of the input voltage source to the circuit,
Esource is the equivalent noise voltage of the input source, En and In are the equivalent
input noise sources of the voltage follower, ER1 is the thermal noise voltage of resistor
R1, and Id2 and Id3 are the shot noise currents of diodes D2 and D3. In turn, the
expressions for the attenuation factors can be simplified by assuming that rd3 >> rd2 and
then substituting equations (2-47) and (3-4) to obtain
K3 ≈
VOUT
IC3VT
IC 3+ VOUT
IC3
≈VOUT
VT + VOUT(3-39)
K4 ≈rd3
rd3 + R1≈
VT
VT + VOUT(3-40)
K5 ≈ K3 ≈VOUT
VT + VOUT. (3-41)
Equations (3-39) through (3-41) indicate that attenuation factors K3, K4, and K5 are
independent of IC2 and IC3 to the first order. Furthermore, gains K3 and K5 are
approximately equal to one, since VOUT will always be greater than VBE1 (or ≈ 0.7 V) in
the ∆VBE summing bandgap reference, and therefore VOUT will be much greater than
VT.
67
As with the VBE1 generator, the Ebias2 and Enp terms may be replaced by the
PTAT current source terms from Fig 3-6. In this case, noise generated by the bias circuit
will be influenced by the PTAT bias currents in the same way the output noise of the
VBE1 generator is affected. The intrinsic noises of D2, D3 and R1 will all be reduced as
the DC bias current is increased, but in general the output noise of the ∆VBE summing
subcircuit will be dominated by noise from the IBIAS2 current source, noise from the
input voltage source, and the equivalent input noise voltage and current of the unity gain
buffer.
In conclusion, an inverse relationship between the operating current of the ∆VBE
summing subcircuit and output noise exists for the ∆VBE summing bandgap reference,
but the noise contribution of any particular device only decreases with the square root of
the current at best. For a ∆VBE summing bandgap reference composed of a VBE1
generator cascaded with one or more ∆VBE summing subcircuits, assume that the noise at
the output of the VBE1 generator (Eout1) is approximately equal to the noise generated by
the current source IBIAS2 in each ∆VBE summing subcircuit. Furthermore, assume the
average DC output voltages of all the ∆VBE subcircuits (VOUT) are roughly equal. Given
these assumptions, the total output noise of the reference can be approximated as
EREF2 ≈ K En
2 + InRsource( )2 + rd2Id2( )2 + rd3Id3( )2[ ] + K
VTVT + VOUT
2ER1
2 + K +1( ) Eout12
(3-42)
where K is the number of ∆VBE summing subcircuits, provided all the summing
subcircuits are identical with matched device currents. As such, equation (3-42) indicates
that the number of summing subcircuit stages should be made as small as possible to
68
minimize the output noise of the ∆VBE summing bandgap reference. In addition to
lowering total output noise, reducing the value of K will also reduce circuit size and total
operating current.
As previously shown in equation (3-26), the temperature performance of the
∆VBE summing bandgap reference is relatively independent of the number of ∆VBE
summing subcircuit stages. To determine the minimum practical value of K, assume the
nominal reference voltage of the ∆VBE summing bandgap reference is 1.16 V and the
forward-biased voltage of diode D1 is 0.7 V. From equations (2-4) and (3-3), the
required ∆VBE voltage drop of each ∆VBE summing subcircuit stage can be
approximated as
∆VBE = VT ln K1K2( ) ≈460 mV
K(3-43)
where K1 is the DC operating current ratio of D2 to D3, and K2 is the ratio of D3 junction
area to D2 junction area. For K = 2, 3, and 4, ∆VBE will be equal to 230 mV, 153 mV,
and 115 mV, respectively. Assuming K2 is equal to 10 (i.e. D3 is ten times larger than
D2), the respective values of K1 will be 731, 37.3, and 8.55. For K = 2, a D2 to D3
current ratio of 731 is impractical, but ratios of 37.3 and 8.55 for K = 3 and K = 4 can be
readily achieved. Adding more ∆VBE stages to increase the value of K would reduce K1
even further, but the tradeoff would be increased circuit size and total operating current
with no corresponding improvement in noise or temperature performance. Accordingly,
the optimum number of ∆VBE summing subcircuit stages should be three or four,
depending on the resistor values and operating currents in the bandgap reference.
69
CHAPTER IV
NONIDEAL COMPONENTS IN THE LOW NOISE CMOS BANDGAP REFERENCE
The analysis of the ∆VBE summing bandgap reference topology in Chapter III
was performed using two critical assumptions: (1) a floating p-n diode is available in a
bulk CMOS technology, and (2) a low noise buffer amplifier with very high gain can be
constructed in the same process. In the analysis, these components were essentially
treated as ideal devices. Unfortunately, a true floating p-n diode is not available in a
standard n-well CMOS process, and compact low noise buffer amplifiers are not easily
constructed due to the high 1/f noise of MOSFET devices [3], [8]. Implementing the
∆VBE summing bandgap reference requires the use of a non-standard component formed
by enhancing a parasitic bipolar structure inherent in the CMOS process - namely, the
lateral PNP bipolar transistor. Despite some significant drawbacks, these bipolar devices
can be used as floating p-n diodes as well as low noise input transistors for the buffer
amplifier. The characteristics and nonideal behavior of lateral bipolar transistors in these
applications will be examined in this chapter. The use of the buffer amplifier in the
∆VBE summing subcircuit also requires an examination of other nonideal amplifier
characteristics. Errors introduced by amplifier offset voltage, bias current, output
resistance, and gain error must be considered in the design.
The Lateral PNP Bipolar Transistor
The analysis of Chapter III showed that the ∆VBE summing subcircuit requires a
low noise CMOS operational amplifier, since the AC gain between the input and output
nodes is nearly unity. However, CMOS operational amplifiers typically suffer from high
70
levels of noise, especially at low frequencies. Previous publications on standard CMOS
amplifier circuits have reported midband equivalent input noise voltages (En) ranging
from 9.8 nV / Hz to 70 nV / Hz , with 1/f noise corner frequencies between 7 KHz and
159 KHz, and En @ 1 KHz results of 95 nV / Hz to 1.7 µV / Hz [24] - [32]. These high
noise levels can seriously degrade overall performance in low noise CMOS analog
applications, and much effort in recent years has focused on reducing En, particularly the
1/f component.
In a typical two-stage CMOS operational amplifier, the equivalent input noise
voltage is dominated by the En of the transistors in the differential input stage, especially
by the input transistors when their transconductances are much greater than those of the
current load transistors [33]. By reducing the equivalent input noise in these input
transistors, the En for the entire amplifier is reduced. In a 1 Hz noise bandwidth, the
equivalent input noise voltage of a saturated MOS transistor can be expressed as
En2 = Ethermal
2 + E1/ f2 =
8kT(1+ gmbs / gm)
3gm+
KF
2CoxWLK' f(4-1)
where f is the frequency, k is Boltzmann's constant, T is absolute temperature, KF is the
flicker coefficient of the 1/f noise component, K´ is the transconductance parameter, Cox
is the oxide capacitance, gm is the gate-channel transconductance, gmbs is the bulk-
channel transconductance, and W and L are the width and length of the MOSFET [3].
Equation (4-1) shows that the thermal noise component is independent of frequency and
inversely proportional to the square root of gm provided gmbs << gm. The 1/f noise
component is inversely proportional to both frequency and the square root of the gate
area of the transistor. Reducing the thermal noise means increasing gm, where
71
gm ≈ 2 ′ K WL ID (4-2)
and ID is the drain current. By increasing the width-to-length ratio and drain current,
thermal noise En levels of 10 nV / Hz or less are readily achieved for a typical MOSFET.
In fact, midband En values as low as 2 nV / Hz have been obtained for CMOS amplifiers
using input transistors with large width-to-length ratios (> 600) and high drain currents (>
1 mA) [34], [35]. The more difficult challenge is to reduce the 1/f noise component,
which is usually quite large in a MOSFET due to current flow near the surface (and the
surface defects) of the device [36], [38]. One common means of lowering 1/f noise in a
CMOS amplifier is to use some type of switched-capacitor input offset cancellation
technique, which has the added benefit of canceling much of the low frequency noise.
Some drawbacks to this method are increased circuit complexity, clock feedthrough, and
availability of the output signal only during a portion of the clock cycle [23].
For continuous time applications, 1/f noise in a CMOS amplifier can be reduced
by increasing the gate areas of the transistors in the input stage. Several low noise
CMOS operational amplifiers have been constructed using this technique, but the
inevitable penalties are the greatly increased area requirements and large input
capacitances [37], [35], [38]. The input transistors by themselves can be as large as 0.09
mm2 to 0.15 mm2 each, making the amplifier impractically large for applications where
size is critical.
An alternative to large geometry MOS transistors is a BiCMOS process where
bipolar transistors are used in the input stage of the amplifier. Ignoring 1/f noise and fT
limitations, the midband equivalent input noise voltage in a bipolar transistor can be
approximated as
72
En (bipolar)2 ≈ 4kTrx +2q
VT2
IC(4-3)
where rx is the intrinsic base resistance, q is electron charge, VT is thermal voltage, and
IC is collector current [35]. Given typical MOS and bipolar operating parameters, a
bipolar transistor will have smaller midband En values when compared to a saturated
MOS transistor at device currents of approximately 1 µA and greater. More importantly,
the bipolar transistor will have much less 1/f noise for a given component area, with 1/f
noise corner frequencies typically 100 Hz and lower [35], [38]. However, bipolar input
transistors also have a disadvantage in low noise design because of the equivalent input
noise current (In) generated by the base current. The midband In of a bipolar transistor is
approximated by
In2 ≈2 qIB (4-4)
where IB is the base current [35]. Given a input source resistance of RS, an amplifier's
total equivalent input noise (Eni) in a 1 Hz bandwidth can be expressed as
Eni2 =4 kTRS + En
2 + In2RS
2 (4-5)
with the InRS term dominating the En term if RS > En/In. Since In for a MOSFET is
usually negligibly small, amplifiers with MOS input transistors may have lower total
equivalent input noise when high source resistances are required. The optimum input
source resistance for a BiCMOS amplifier with bipolar input transistors will be much
lower than for a comparable CMOS amplifier [35].
73
Noise considerations aside, a major problem with implementing a BiCMOS
technology is the extra processing required to fabricate high quality bipolar transistors on
the same substrate with MOSFETs. The integration of low noise analog circuits with
digital circuits in a standard CMOS process is more desirable. One solution to this
dilemma is the use of lateral bipolar transistors in a bulk CMOS process as demonstrated
by E.A. Vittoz [9] and other researchers [36], [39], [35] - [40]. Lateral bipolar NPN
transistors have been successfully fabricated in 6 µm, 4 µm, 3 µm, and 2 µm p-well
CMOS processes. These transistors exhibit low wideband En noise and much lower 1/f
noise as compared to typical NFET transistors, although their applications are limited by
low Early voltages and parasitic collector currents caused by the vertical substrate NPN
transistor formed in these devices. Amplifiers fabricated using these lateral NPN devices
as input transistors have obtained low midband En values coupled with fc values as small
as 10 Hz to 300 Hz [38], [36], [40].
Only lateral PNP transistors can be constructed in an n-well CMOS process.
Vittoz and other researchers have used lateral NPN transistors in p-well processes. In a
standard n-well CMOS process, a lateral PNP bipolar transistor is created by biasing the
n-well of a PMOS transistor to enhance the diffusion current mechanism between the
source and drain. In a normal PFET, drift current flows between the source and drain
through the inversion region formed by a gate voltage that is negative with respect to the
source of the transistor [41]. Holes are attracted to the top of the n-well by the negative
gate voltage, and a conduction channel is formed between the p-type source and drain.
The n-well is generally connected to the highest available voltage on the chip (usually
VDD), ensuring that the n-well is reverse-biased with respect to the source, drain, and
substrate.
In a lateral PNP transistor, the gate is biased slightly positive with respect to the
source to form an accumulation region at the surface of the transistor [18], [41].
74
Electrons are attracted to the surface of the n-well, and holes are forced away from the
gate and further below the surface. The n-well voltage is then reduced until the p-n
junction formed by the source and well becomes forward-biased, and the holes in the n-
well act as minority carriers for the flow of diffusion current between the source and
drain. As shown in Fig. 4-1, the PFET drain and source become the emitter and collector
of the lateral PNP transistor, while the n-well becomes the base terminal.
An unavoidable consequence of lateral parasitic current flow is the formation of a
vertical PNP transistor between the emitter, base, and substrate of the structure. Because
of the lack of a buried layer in a bulk CMOS process, part of the emitter current is lost to
this parasitic collector, thereby limiting the application of such devices in CMOS design.
Despite this drawback, lateral PNP transistors have been used with great success as input
devices for low noise amplifiers designed in the MOSIS 1.2 µm n-well CMOS process.
75
GateBase
Emitter LateralCollector
p-diff p-diff p-diff
n-well
p-substrate(Vertical Collector)
- - - - - -
diffusion current
VGate > VEmitter > VBase ≥ VCollector (Lateral)
Note: Dimensionsare not to scale.
Fig. 4-1. Current Flow in the Lateral PNP Transistor
Lateral PNP Transistor Layout and Characteristics
Since integrated PNP transistors generally have lower ß and fT as compared to
NPN transistors, an initial question was whether lateral PNP transistors would have
sufficiently good (and repeatable) ß, gain-bandwidth, and noise characteristics to be
useful in a low noise, high performance op amp design. Accordingly, lateral PNP
transistors of varying sizes were constructed and characterized in two different MOSIS
fabrication runs. Transistor structures with 1 emitter dot and 20 emitter dots were
fabricated in the MOSIS N24U run, and 40 emitter dot lateral PNP transistors were
fabricated in the MOSIS N36Y run.
The lateral PNP bipolar transistor is formed by creating a rectangular PFET
structure where a p-diffusion emitter is surrounded by a p-diffusion lateral collector. The
76
n-well serves as the base, and the minimum polysilicon gate length sets the base width
(Fig. 4-2). To reduce vertical collector current, these transistors were laid out as multi-
emitter devices, where each emitter dot is a minimum area p-diffusion contact surrounded
by a polysilicon gate (Fig. 4-3). This technique maximizes the ratio of lateral collector
current to vertical parasitic collector current and improves the lateral collector current
efficiency and noise characteristics of the transistor [36]. As an added precaution against
latch-up problems due to the unavoidable substrate currents, each device is surrounded by
a p+ substrate guard ring. With layout programs such as MAGIC, this guard ring also
prevents the inadvertent merging of the n-well base with bases of adjacent lateral PNP
transistors and VDD-connected n-wells of nearby PFETs.
For bipolar operation, the polysilicon gate of the lateral PNP transistor must be
properly biased. At the very least, the gate must be zero-biased with respect to the
emitter to prevent the PFET transistor between the collector (drain) and emitter (source)
from turning on. A small positive bias is preferable, with a gate-emitter voltage of 250
mV or more giving good results. Little additional change in the DC characteristics
occurs as VGE increases past 0.5 V. This positive biasing of the gate also drives diffusing
minority carriers (holes) in the base deeper into the n-well and away from surface defects,
thereby reducing low frequency 1/f noise [38], [36]. For the measurements in this
dissertation, VGE was set to 1 V (equal to the minimum VGE magnitude anticipated in the
buffer amplifier application).
77
nwell psubstratediffusion
nwellcontact
Base
LateralCollector
EmitterGate(poly)
31.2 µm
33.0 µm
pdiffcontact
Emitter
Gate
Base
LateralCollector
VerticalCollector
VSS( )
VSS
Fig. 4-2. A Minimum Size Lateral PNP Transistor Layout and Schematic
Base
Vss
71.4 µm
84.0 µm
Emitter
Gate
LateralCollector
Fig. 4-3. The 40 Emitter Dot Lateral PNP Transistor
78
In order for a lateral PNP transistor to function in the input stage of a low noise
CMOS amplifier, the device must have good lateral ß and adequate lateral collector
current efficiency at the desired operating point. Figs. 4-4 through 4-6 show the lateral ß
(ICL/IB) and lateral efficiencies for typical 40 emitter dot and 1 emitter dot transistors,
respectively. At low current densities (< 100 nA per emitter dot) and high values of VCE
(-4.0 V), lateral ß ranged as high as 240 in the 40 emitter dot devices and 125 in the 1
emitter dot transistors. (Because the 40 emitter dot transistors were fabricated on a
different run from the 1 emitter dot transistors, their higher maximum lateral ß values are
apparently due to process variation between these runs.) Assuming that a minimum
operating ß of 50 is desired, ß rolloff from high-level injection [41] limits the maximum
current density of these transistors to about 5 µA per emitter dot.
Despite the effects of high level injection, the 40 emitter dot transistor operates
over more than four decades of collector current with a minimum lateral ß of 50 (Fig. 4-
4). Within this operating range, the lateral efficiency of the transistor ranges from 0.60 to
0.85 (Fig. 4-5), with lateral efficiency defined as
Lateral efficiency = ICL + IB
IE=
IE - ICV
IE(4-6)
where ICL and ICV are the lateral and vertical collector currents. These efficiency values
represent a significant improvement over those reported for lateral NPN transistors with
longer base widths, which exhibit typical lateral efficiencies of 0.25 to 0.50. Since
reducing emitter dot size increases the ratio of sidewall area to bottom area, higher
efficiencies were anticipated. As with their NPN predecessors, lateral PNP transistors
suffer from low Early voltages (typically 14 V to 18 V), so a cascode topology should be
used to increase output resistance in subcircuits such as current mirrors.
79
250
200
150
100
50
0 100 nA 1 µA 10 µA 100 µA 1 mA 10 mA
Lateral Collector Current (40 Emitter Dot LPNP)
Lateral ß
V CE =−0.4 V
V CE =−1.6 V
V CE =−2.8 V
V CE =−4.0 V
Fig. 4-4. Lateral ß vs. Lateral IC for the 40 Emitter Dot LPNP Transistor
Emitter Current (40 Emitter Dot LPNP)
1.0
0.8
0.6
0.4
0.2
0
LateralEfficiency
100 nA 1 µA 10 µA 100 µA 1 mA 10 mA
V CE = −0.4 V
V CE = −4.0 V
Fig. 4-5. Lateral Efficiency vs. IE for the 40 Emitter Dot LPNP Transistor
80
125
100
75
50
25
0
Lateral ß
100 nA 1 µA 10 µA 100 µA 10 nALateral Collector Current (1 Emitter Dot LPNP)
V CE = −4.0 V
V CE = −0.4 V
Fig. 4-6. Lateral ß vs. Lateral IC for the 1 Emitter Dot LPNP Transistor
1.0
0.8
0.6
0.4
0.2
0
LateralEfficiency
Emitter Current (1 Emitter Dot LPNP)
100 nA 1 µA 10 µA 100 µA 10 nA
V CE =−4.0 V
V CE =−0.4 V
Fig. 4-7. Lateral Efficiency vs. IE for the 1 Emitter Dot LPNP Transistor
81
The gain-bandwidth of these transistors was also a concern for the low noise
amplifier design. Assuming a nominal base width of 1.2 µm and using process values
provided by MOSIS, a first-order approximation of fT ≈ 200 MHz was calculated from
the base transit time [34], [41]. Actual measurements of a test structure at a current
density of approximately 5 µA per emitter dot gave fT = 85 MHz, which is reasonable
given that the transistor is operating in high-level injection.
The main advantage of the lateral PNP transistor is the improved noise
performance, especially at lower frequencies. Figs. 4-8 and 4-9 show the typical En and
In versus frequency for a 40 emitter dot transistor. Because part of the emitter current is
lost to the parasitic vertical collector, ICL is less than IC(ideal) and the En of a lateral PNP
transistor is slightly higher as compared to an ideal PNP transistor. The measured
midband En was 1.92 nV / Hz , while fc was only 3.2 Hz. Using equation (4-3), the
intrinsic base resistance for the 40 dot emitter transistor was estimated to be
approximately 150 Ω, or 6 KΩ per emitter dot. For the same transistor, typical
parameters of In = 0.61 pA / Hz and fc = 154 Hz were measured. This midband In
corresponds almost exactly with the value predicted by equation (4-4). Interestingly, the
low frequency 1/f In noise showed a considerably greater variation (± 4.5 dB at 5 Hz) for
the six transistors tested as opposed to the 1/f En noise which was almost identical for the
same devices.
82
105
104
103
102
101
100
1.50
1.75
2.00
2.25
2.50
2.75
3.00
Typical Equivalent Input Noise Voltagefor the 40 Emitter Dot LPNP Transistor
Frequency (Hz)
Emitter current = 225 µALateral collector current = 170 µACollector-emitter voltage = -1.78 V
nV
Hz
Fig. 4-8. En vs. Frequency for the 40 Emitter Dot LPNP Transistor
105
104
103
102
101
100
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Typical Equivalent Input Noise Currentfor the 40 Emitter Dot LPNP Transistor
Frequency (Hz)
Emitter current = 210 µALateral collector current = 159 µABase current = 1.18 µACollector-emitter voltage = -1.98 V
pA
Hz
Fig. 4-9. In vs. Frequency for the 40 Emitter Dot LPNP Transistor
83
Table 4-1 summarizes the parameters of the 40 emitter dot lateral PNP transistor
at operating currents and voltages comparable to those anticipated for the intended low
noise amplifier's input transistors. Despite the effect of high-level injection, parameters
such as ß, gain-bandwidth, lateral efficiency, and equivalent input noise were all within
acceptable levels. The 40 emitter dot LPNP was subsequently used as the input transistor
for the low noise buffer amplifier design. With an area of only 0.006 mm2, this device
exhibits far less 1/f noise than a PFET transistor of identical size in the MOSIS 1.2 µm
CMOS process. However, for the sake of a conservative design, the minimum ß and
lateral current efficiency values from the 1 emitter dot LPNP were used in the circuit
simulations.
Table 4-1. A Summary of Typical LPNP Transistor Parameters
Transistor Area (40 Emitter Dots) 0.006 mm2
Lateral ß 100
Lateral Efficiency 0.76
Base Resistance (RB) 150 Ω
En @ 5 Hz 2.46 nV / Hz
En (midband) 1.92 nV / Hz
fc (En) 3.2 Hz
In @ 5 Hz 3.53 pA / Hz
In (midband) 0.61 pA / Hz
fc (In) 162 Hz
fT 85 MHz (200 MHz maximum)
Early Voltage (VA) 16 V
84
The Lateral PNP Transistor as a Floating Diode
The lateral PNP transistor has adequate ß and excellent noise characteristics,
making it a very good input device for the low noise CMOS amplifier used in the ∆VBE
summing bandgap reference. However, this transistor must also function as a floating
diode in the ∆VBE summing subcircuit. A low Early voltage is not a factor for a diode
connected lateral PNP transistor, since VBC = 0 in this case [6]. The most important
issue to analyze is the effect of the loss of a portion of the emitter current to the parasitic
vertical collector. Specifically, how does this parasitic vertical collector current affect the
DC and AC characteristics of the lateral PNP transistor as opposed to an ideal diode?
For an standard bipolar transistor operating in the active region, the relationship
between emitter current, collector current, and base-emitter voltage is
IE ≈ IC = IS e
VBE
VT
(4-7)
assuming ß is much greater than unity [6]. For a lateral PNP transistor, equation (4-7)
can be modified to
IE ≈ ICL + ICV = ISL e
VBE
VT
+ ISV e
VBE
VT
(4-8)
where ICL and ICV are the lateral and vertical collector currents, respectively. Note that
VBE is identical for both collector currents, since the lateral and vertical devices share the
same base and emitter. Accordingly, equation (4-8) can be reduced to
85
IE ≈ ISL + ISV( ) e
VBE
VT
= IS e
VBE
VT
(4-9)
where the equivalent saturation current IS is equal to the sum of the lateral and vertical
saturation currents. The forward-biased base-emitter voltage is therefore more properly a
function of the emitter current in a lateral PNP transistor rather than either collector
current.
Consider the floating diodes D2 and D3 in the ∆VBE summing subcircuit shown in
Fig. 4-10. The node voltage (VIN + VBE2) is not influenced by the value of the lateral
collector current ICL2, but only by the emitter current IE2 and the base-emitter voltage
VBE2. On the other hand, the output voltage VOUT will be equal to ICL3 multiplied by
R1, so the value of VBE3 must be slightly larger than the ideal case to compensate for the
vertical collector current lost by diode D3. Obviously, the DC non-ideal effects of the
dual collectors in these floating transistors can either be ignored or compensated for in
the actual circuit. However, it is desirable that these diodes be well-matched to the
corresponding diodes in other ∆VBE summing subcircuits on the chip.
86
-
+
10X
VDD
R1VIN
VIN + VBE 2
IBIAS2
VOUT = VIN + VBE2 − VBE3 = VIN + ∆VBE
D2 D3
A1
VIN
ICL2 ICL3
r2
ro(CL)
+VBE2 −
+V BE3 −
Fig. 4-10. Lateral PNP Transistors Used as Floating Diodes
The small-signal impedance of the floating lateral PNP diode is another important
consideration in the design of the ∆VBE summing bandgap reference. As discussed in
Chapter III, the noise amplifier formed by the bias circuit and the IBIAS2 current source
has a load impedance approximately equal to r2, the impedance at the emitter (or anode)
of diode D2 (Fig. 4-10). Assuming that D2 is a diode-connected ideal bipolar transistor,
amplifier A1 has a closed loop output impedance of ro(CL), and emitter current IE2 is
equal to 1 mA, this impedance will be equal to
r2(ideal) =1
gm2+ ro(CL) =
VT
IC2+ ro(CL) ≈
VT
IE2+ ro(CL) ≈ 26 Ω + ro(CL) (4-10)
87
which will simply equal the inverse transconductance of D2 if the amplifier has a
negligibly small output impedance [6]. Now consider the case for the LPNP transistor,
where the 1 mA of emitter current is split between the vertical and lateral collectors, such
that ICL plus ICV equals 1 mA. The equivalent AC resistance is now
r2 =1
gml2 + gmv 2+
ro(CL) ICL2IE2
≈26 Ω +ro(CL) ICL2
1 mA(4-11)
which is always less than r2(ideal) in equation (4-10). The tradeoff is higher impedance
looking back into the lateral collector of a diode-connected LPNP transistor, but this is
only a concern at the output node of the ∆VBE summing subcircuit because of the
increased impedance through the D3 diode. The result is a slightly higher thermal noise
contribution from the R1 resistor, but this thermal noise increase is negligible in the
actual circuit.
The intrinsic emitter, collector, and base resistances of the diode-connected lateral
PNP transistor can also affect the performance of the ∆VBE summing subcircuit. Fig. 4-
11 shows the simplified small-signal diagram for diode-connected LPNP transistor D2,
where rCV is the intrinsic vertical collector resistance, rCL is the intrinsic lateral collector
resistance, and rE is the intrinsic emitter resistance (the impedance of the intrinsic base
resistance is negligible, assuming ß is sufficiently large). The equivalent resistance r2 of
this circuit is
r2 =1
gml + gmv+
ro(CL) ICL
IE+ rE (4-12)
88
where ICL and IE are DC collector and emitter currents. Note that collector resistances
rCL and rCV have no effect on the impedance of the diode because of the influence of the
dependent current sources. On the other hand, the emitter resistor rE and the output
resistance ro(CL) of the buffer amplifier will limit the ultimate minimum value of r2.
r2
ro(CL)
rE
rCLrCV
vc
ve
gml∗ vc − ve( ) gmv∗ vc − ve( )
Fig. 4-11. Small-Signal Diagram of the Diode-Connected LPNP Transistor
The intrinsic resistances will have a much greater influence on the DC
performance than the small-signal performance of the diode-connected LPNP transistor.
Consider Fig. 4-12, where intrinsic resistors RE, RB, and RCL separate the "ideal"
intrinsic base, emitter, and collector terminals from the external contacts. Resistor RCL
can be ignored as long as its voltage drop does not force the transistor into saturation.
However, the voltage drop across this non-ideal device will be equal to
89
V ′ B ′ E = VBE + IE RE + IBRB (4-13)
where VBE is the ideal base-emitter voltage drop.
EB
C
RCLRB
IB
RE
E'
B', C'
IE
Fig. 4-12. DC Effects of Intrinsic Resistances in the Diode-Connected LPNP Transistor
For the 40 emitter dot LPNP transistor, the measured value of RB is
approximately 150 Ω. Typical values of RCL and RE for standard integrated lateral PNP
transistors are normally a few hundred ohms and less than ten ohms, respectively [6],
although these values have not been measured for the devices in the MOSIS 1.2 µm
CMOS process. Assuming an emitter current of 1 mA and a lateral collector current of
600 µA, RCL can be as high as 750 Ω without saturating the transistor. Then, given a
worst case lateral ß of 50 and a worst case RE value of 10 Ω, the V B'E' error voltage will
be
V ′ B ′ E − VBE = IE RE + IBRB ≈10 mV + 1.8 mV = 11.8 mV . (4-14)
90
The voltage drop across RE will have the same temperature coefficient as the emitter
current IE, thereby increasing the output voltage of the ∆VBE summing subcircuit if IE is
PTAT. The voltage drop across RB will be proportional to the base current IB, which in
turn is dependent on the temperature coefficients of IE and ß. Typically, ß will have a
positive temperature coefficient (7000 ppm / ˚C for a typical bipolar transistor), although
the value of this temperature coefficient may vary due to the non-standard doping of the
LPNP transistor [6]. Ultimately, the temperature coefficients of the VB'E' errors due to
RE and RB can be compensated by adjusting the temperature coefficient of the complete
∆VBE summing bandgap reference. Although the absolute error of the reference voltage
may be affected by these errors, the relative error can be minimized by canceling the
cumulative temperature coefficients. Note that these errors will only be significant for
the D2 diode in the ∆VBE summing subcircuit, since the ratio of emitter current to base-
emitter junction area is approximately 100 times higher than for the D3 diode.
In conclusion, the lateral PNP transistor can be used as a reasonably good floating
diode, but a not a good stackable floating diode. For example, if LPNP transistors were
used in the stacked low noise bandgap topology of Chapter II (Fig. 2-8), the emitter
current of each successive transistor would only be equal to the lateral collector current of
the device above. Assuming an average lateral efficiency of 66%, only 29% of the
emitter current of diode-connected transistor D1 would reach the emitter of transistor D4,
and each diode would have a successively higher impedance and lower base-emitter
voltage drop. As this analysis has shown, the ∆VBE summing bandgap reference
topology avoids these problems by separating the devices with buffer amplifiers instead
of stacking them vertically with respect to the power supply.
91
The Darlington "Pseudo-BiCMOS" Low Noise Amplifier
Fig. 4-13 is the schematic of the Darlington "Pseudo-BiCMOS" Low Amplifier,
or DBiLNA. This amplifier was originally designed as a low noise, high gain-bandwidth
amplifier for research in CMOS wideband noise generation (i.e. the CMOS Integrated
Noise Source project). The input stage uses LPNP transistors connected in a Darlington
input configuration [6] to obtain low En while simultaneously reducing input bias current
and In. Because of the requirement for very low input capacitance in the original
Integrated Noise Source application, each input device is composed of a 4 emitter dot
structure cascaded with a 40 emitter dot structure, with the current per emitter dot
constant in both transistors. The bias current is also reduced tenfold, with a 10 reduction
in In [8]. The penalties are reduced common mode input range and increased amplifier
En due to the added shot noise and larger base resistances of transistors Q2 and Q3. The
amplifier circuit requires an area of 0.216 mm2 in the MOSIS 1.2 µm CMOS process,
exclusive of an external compensation capacitor.
Thanks to the high transconductance and low 1/f noise of the lateral PNP
transistor as compared to a typical PFET, the DBiLNA exhibits excellent noise
characteristics. Figs. 4-14 and 4-15 show the En and In frequency curves for a typical
DBiLNA amplifier. The En midband noise voltage level is about 7.3 nV / Hz , with a 1/f
noise level of 32.9 nV / Hz at 1 Hz. These values give a 1/f noise corner frequency (fc)
for En of approximately 19.3 Hz. The En midband level is increased by the Darlington
input configuration, but the advantage is an input bias current of only 150 nA.
Consequently, the typical In midband noise level is only 203 fA / Hz , with a 1/f noise
level of 983 fA / Hz at 1 Hz, resulting in fc (In) = 22.6 Hz.
92
46.8
/3.
6
58.2
/7.
2
0.6
pF
300
Ω
1296
/3.
681
.6/
3.6
43.8
/6.
645
.6/
3.6
34 K
Ω
480/
1848
0/18
511.
2/3.
6
129.
6/3.
6
270/
1.2
384/
1.2
46.8
/3.
6 58.2
/7.
2
V+
40 e
mit-
ter
dots
40 e
mit-
ter
dots
V-
291.
6/16
.2
4 em
it-te
r do
ts4
emit-
ter
dots
291.
6/1
6.2
VD
D
VSS
D1
Vou
t
Not
e: A
ll M
OSF
ET
dim
ensi
ons
are
in µ
m.
R13
Q1
Q2
Q3
Q4
M14
M15
M16
M13
M3
M3A
M3B
M2
M5
CC
CB
RZ
M6
M7
M8
M9
M10
M11
M12
Fig. 4-13. The DBiLNA Buffer Amplifier
93
105
104
103
102
101
100
5
10
15
20
25
30
35
Frequency (Hz)
nV
Hz
DBiLNA Equivalent Input Noise Voltage versus Frequency
Fig. 4-14. Equivalent Input Noise Voltage (En) for a Typical DBiLNA
105
104
103
102
101
100
100
200
300
400
500
600
700
800
900
1000
Frequency (Hz)
DBiLNA Equivalent Input Noise Current versus Frequency
pA
Hz
Fig. 4-15. Equivalent Input Noise Current (In) for a Typical DBiLNA
94
Because of time constraints during the layout of the prototype ∆VBE summing
bandgap reference and a desire to use a buffer amplifier known to be functional, the
DBiLNA was incorporated into the ∆VBE summing subcircuit without modification.
However, the DBiLNA in its present form is not an optimum design for this particular
application, despite the low En and In values. While the amplifier uses a standard CMOS
split pole topology [38], the output stage is deliberately biased at a current of
approximately 1.5 mA to reduce output resistance and frequency response peaking,
resulting in a total quiescent current of 2.1 mA. Furthermore, the output stage uses a
standard inverter topology to permit rail-to-rail output swings and enable the amplifier to
sink and source significant amounts of current. Table 4-2 summarizes the typical
parameters of the DBiLNA amplifier. In many ways the circuit is overdesigned for the
∆VBE summing bandgap reference application, especially in terms of frequency response
and power dissipation. Anticipated changes to the DBiLNA amplifier design will be
discussed in the next section.
95
Table 4-2. A Summary of Typical DBiLNA Parameters
Circuit Area 0.216 mm2
Quiescent Current 2.1 mA @ VDD, SS = ± 2.5 V
Open Loop Gain 84.3 dB (estimated)
-3 dB Frequency (@ ACL=1) 21.7 MHz
En @ 1 Hz 32.9 nV / Hz
En (midband) 7.3 nV / Hz
fc (En) 19.3 Hz
In @ 1 Hz 983 fA / Hz
In (midband) 203 fA / Hz
fc (In) 22.6 Hz
Input bias current 0.15 µA
Input offset voltage -1.1 mV
CMRR (DC) 99.6 dB (estimated)
PSRR+ (DC) 67.6 dB (estimated)
PSRR- (DC) 73.9 dB (estimated)
Slew Rate + (@ CL = 60 pF, RL = 10 KΩ) 39.0 V / µs (estimated)
Slew Rate - (@ CL = 60 pF, RL = 10 KΩ) 42.5 V / µs (estimated)
Nonideal Characteristics of the DBiLNA Buffer Amplifier
Despite the very low equivalent input noise of the DBiLNA amplifier, the circuit's
performance is far from ideal in many respects. The effects of errors introduced by gain
error, amplifier offset voltage, bias current, and output resistance must be considered in
the design of the ∆VBE summing bandgap reference [42].
96
First, it is desirable that the DC open loop gain of the DBiLNA be as high as
possible to minimize gain error. The typical value of AO for this circuit is 84.3 dB, or AO
= 16,470. The gain of the buffer amplifier can therefore be expressed as
VOUT =AO
1+ AOVIN =0 .9999392872 ∗ VIN (4-15)
where VOUT and VIN are the DC voltages across the circuit. This value of closed loop
gain will result in an error voltage of only 60.7 µV for a 1 V input signal, a negligible
value when compared to the input offset voltage of the DBiLNA. On the other hand, the
amplifier's gain-bandwidth product is much too high, with the circuit requiring
approximately 20 pF of external compensation capacitance for unity gain stability.
Ideally, the gain-bandwidth product should be reduced without reducing the value of AO,
but achieving this condition may dictate some type of cascode topology in the input stage
[3] (with the penalty of higher operating voltage).
Output resistance is also a function of open loop gain. The unity gain closed loop
output resistance of the DBiLNA is
ro(CL) =ro
1+ A(s)(4-16)
where ro is the open loop output resistance and A(s) is the open loop frequency response.
Since the DBiLNA uses an inverter output stage, the value of ro will be a function of the
effective lambda and drain currents of the output MOSFETs [3] and may be as high as
100 KΩ. However, division by A(s) will lower ro to a few ohms at frequencies below the
97
dominant pole of the amplifier, and the impedance of diode D2 in the ∆VBE summing
subcircuit (Fig. 4-10) will dominate the load impedance of the IBIAS2 current source.
The output resistance could be reduced further if a common source or common emitter
output stage were used in the buffer amplifier, since the output impedance would become
a function of the transconductance of the output transistor. In any case, the buffer
amplifier only needs to sink current, so the output source transistor (M11 in Fig. 4-13)
will be excluded in future designs to reduce quiescent current requirements.
R1 -
+
D3
**+_
En
In
IBVOS ro(CL)
rout
A(s)
Fig. 4-16. Nonideal Effects in the DBiLNA Buffer Amplifier
Additional errors are introduced by the effects of bias current and offset voltage
(Fig. 4-16). Assuming R1 = 13 KΩ, the offset voltage at the output of the DBiLNA will
be
VOFFSET = VOS + IB R1 = −1.1 mV +1.95 mV = 850 µV. (4-17)
This value of offset voltage is quite significant, especially when several amplifiers are
cascaded together. Of course, the effect of IB could be largely removed by placing a
resistor equal to R1 in the feedback loop [42] at the cost of increased thermal noise, but
VOS due to device mismatch cannot be canceled so easily. Larger input transistors and
98
improved input stage layout techniques will be used in future DBiLNA submissions to
minimize VOS, but a certain amount of process variation is unavoidable. The input offset
voltage is also temperature dependent, such that the change in VOS with respect to
absolute temperature is equal to VOS divided by absolute temperature [6], or
∂VOS
∂T=
VOS
T. (4-18)
Equation (4-18) gives a temperature drift of 3.6 µV / ˚C for VOS = -1.1 mV. As with the
other error voltages in the ∆VBE summing subcircuit, this temperature drift can be
compensated by adjusting the temperature coefficient of the final reference output
voltage.
One additional fact worth noting about the DBiLNA buffer amplifier is the
relative effect of En and In on the output noise. Because In flows through a low AC
impedance (via diodes D3 and D2 to the output of the buffer amplifier of the previous
stage), the noise voltage due to In will be much less than 1 nV / Hz , which is negligible
when compared to the magnitude of En.
Input Offset Voltage Variation in the Buffer Amplifier
Component mismatch due to process variation is an unavoidable consequence of
integrated circuit fabrication. Given a buffer amplifier circuit with a nominal zero input
offset voltage (i.e. VOS = 0), measurement of VOS for a large number of amplifiers will
result in a distribution of offset voltages with a statistical mean of zero and a non-zero
standard deviation. Assuming a Gaussian (or normal) distribution with a mean of zero,
the probability F(VOS) that |VOS| for any particular amplifier will be less than or equal to
some value VM can be expressed as [43]
99
F VOS( ) = ΦVM
σ
− Φ −
VM
σ
(4-19)
where σ is the standard deviation of VOS and the distribution function Φ(z) is equal to
Φ z( ) =12π
−∞z
∫ e−u2 /2 du . (4-20)
For example, let the standard deviation of VOS equal 0.5 mV. The probability
that the amplitude of VOS will be less than or equal to VM = 1 mV is
F VOS( ) = Φ 2( ) − Φ −2( ) ≈0 .97725−0.02275= 0.9545 (4-21)
or 95.45%. If the offset voltage of a single amplifier is multiplied by a factor n in a
standard bandgap reference topology, the standard deviation will be multiplied by the
same factor. If n = 3, the value of F(VOS) for this example becomes
F VOS( ) = Φ23
− Φ −
23
≈ 0.74857 −0.25143 = 0.49714 (4-22)
or 49.71% . In other words, multiplying the input offset voltage of a single amplifier by a
factor of three decreases the probability that the output offset voltage will be less than or
equal to 1 mV from 95.45% to 49.71%.
100
Now consider the buffer amplifiers in the summing subcircuits of the ∆VBE
summing bandgap reference. The offset voltage at the reference output due to the input
offset voltages of the buffer amplifiers will be
VOFFSET = VOS1 + VOS2 + . . . + VOSn (4-23)
where n is the number of ∆VBE summing subcircuit stages. Assuming each input offset
voltage is an independent random variable [43], the probability function for the output
offset voltage of equation (4-19) becomes
F VOFFSET( ) = ΦVM
n σ
− Φ −
VM
n σ
. (4-24)
Unlike the multiplication of a single input offset voltage, summing n input offset voltages
results in a multiplication of the standard deviation by a factor of n . In other words,
summing versus multiplication gives the same n advantage for output voltage variations
due to device mismatch as it does for output noise. Returning to the previous example,
the probability that the total offset voltage of three ∆VBE summing subcircuit stages will
be less than or equal to 1 mV will be
F VOFFSET( ) = Φ23
− Φ −
23
≈0 .87493−0.12507 = 0.74986 (4-25)
or 74.99%, far better than the 49.71% probability if a single ∆VBE summing subcircuit
stage were multiplied by a factor of three. This argument can be extended for any
101
randomly distributed component parameter that is duplicated between the ∆VBE
summing subcircuits.
102
CHAPTER V
THE ∆VBE SUMMING BANDGAP REFERENCE
Given the measurement results for the lateral PNP transistors and DBiLNA
operational amplifiers fabricated in the MOSIS 1.2 µm CMOS process, creation of a
∆VBE summing bandgap reference circuit appeared feasible. Initially, a single ∆VBE
subcircuit was fabricated as a test structure. After confirming the functionality of this
subcircuit, a complete bandgap reference was fabricated and tested. This chapter
summarizes the experimental results of the circuit and compares them to circuit
simulations made with PSpice [44].
Layout and Fabrication
Figs. 5-1 and 5-2 are the schematics for the low noise bandgap reference and
∆VBE summing subcircuit, respectively. This circuit is essentially identical to the
proposed circuit in Chapter III, with the major exception that the PFET current mirrors in
the bias circuit and summing subcircuits have been cascoded. Equation (3-26) in Chapter
III shows that the output voltage of the ∆VBE summing bandgap reference is independent
of the bias current to the first order. Because PMOS transistors in the MOSIS 1.2 µm
CMOS process have a large lambda and low output resistance, these devices were
cascoded not because of concerns of drain current variation, but instead to increase the
internal loop gain and power supply rejection of the PTAT bias circuit [6]. The penalty
for stacking these PMOS transistors is a higher minimum supply voltage for the bias
circuit. The diode-connected LPNP transistor D1 was biased at 10% of the quiescent
current of the ∆VBE summing subcircuits (exclusive of additional current required to
103
operate the buffer amplifiers). Given the results of preliminary simulations, a value of 13
KΩ was chosen for the R1 resistor in the summing subcircuit, and four ∆VBE summing
subcircuits were placed on the chip. To minimize process variations and thermal gradient
effects, the four subcircuits were placed in a mirrored four-quadrant configuration.
A simple means of trimming the output voltage was also required for this circuit.
The reference voltage is easily adjusted by changing the value of resistor R1B in the
PTAT bias circuit, which in turn alters the magnitudes of currents through diode D1 and
the ∆VBE summing subcircuits. As shown in the circuit pin-out of Fig. 5-3, four different
R1B resistors in the range of 300 Ω to 550 Ω were placed on-chip in the hope that one of
them would be fairly close to the desired value for minimum reference temperature
coefficient. Unfortunately, all of these values ultimately proved to be too small, and
external resistors were used for the R1B resistor.
Subsequent testing and examination of the packaged circuit received from MOSIS
revealed an unanticipated problem with the circuit layout. Because of the need to
connect nodes in the circuit to external pads, long runs of metal1 and metal2 were used
throughout the circuit. At the time the chip was submitted for fabrication, little
consideration was given for the parasitic resistance of these metal traces, but these
resistances ultimately proved to be quite significant given the large quiescent currents and
high desired resolution of the reference voltage. According to the parametric
measurements for the MOSIS 1.2 µm CMOS process, metal1 and metal2 have typical
resistances of 0.05 Ω and 0.04 Ω per square, respectively. Some metal traces only a few
µm in width run as far as 1.2 mm across the surface of the chip, with resulting parasitic
resistances as high as 40.63 Ω.
104
. . .
10X
150
µm/
3.6
µm
150
µm/
3.6
µm
150
µm/
3.6
µm
150
µm/
3.6
µm
500
µm/
3.6
µm50
0 µm
/3.
6 µm
200
µm/
3.6
µm
200
µm/
3.6
µm XD
1
BIA
S
VIN
VO
UT
BIA
S
VIN
VO
UT
BIA
S
VIN
VO
UT
VR
EF
VD
D
∆V
BE
Sub
ckt
∆VB
E S
ubck
t
∆VB
E S
ubck
t
VD
DV
DD
VD
D
M3
M3
A
VD
D
M1
M1 A
M2
M2
A
R1B
Q2B
Q1B
M4
M5
1
5
6
2 4 78
9
10
3
11
12
13
Not
e: C
ircl
ed n
umbe
rs d
enot
e PS
pice
nod
es.
Fig. 5-1. The ∆VBE Summing Bandgap Reference
105
-
+
106
98
98
105
104
100
99
99 99
98
2000 µm / 3.6 µm
13 KΩ
10X
OUT
IN
98
99
Note: Circled numbers denote PSpice nodes.
101
103
2000 µm / 3.6 µm
M P1
MP2
VDD
VDD
VDD
V DD
VSSVSS
VSSVSS
102
R1
XA1
XD2 XD3
Fig. 5-2. The ∆VBE Summing Subcircuit
106
D1
D2
M13
0
M16
0
M14
0M
160
10X
150/
3.6
150/
3.6
500/
3.6
500/
3.6
M0
200/
3.6
Pin
24 P
in 1
5 pF
Pin
25
Pin
28
Pin
27
XD
10P
in 1
Pin
34
M14
0AM
160A
150/
3.6
150/
3.6
M0A
200/
3.6
Pin
33
Pin
26
Pin
29
Pin
30
Pin
31
Pin
32
300
Ω35
0 Ω
475
Ω55
0 Ω
Pin
34
Fig. 5-3. Chip Pin-Out for the ∆VBE Summing Bandgap Reference
107
-+ DB
iLN
A #
1V
DD
VSS
Pin
19
Pin
20
Pin
1
Pin
23
Pin
18
Pin
35 C
omp
M2A
2000
/3.6
XD
3AX
D4A
10X
Pin
26
Pin
20
P
in 2
0
Pin
1
Pin
21
Pin
1
M1A
2000
/3.6
Pin
25
Pin
20
Pin
22
13 K
Pin
1
-+ DB
iLN
A #
2V
DD
VSS
Pin
16
Pin
15
Pin
1
Pin
12
Pin
17
Pin
11C
omp
M2B
2000
/3.6
XD
3BX
D4B
10X
Pin
26
Pin
15
P
in 1
5
Pin
1
Pin
14
Pin
1
M1B
2000
/3.6
Pin
25
Pin
15
13 K
Pin
1Pin
13
Fig. 5-3 (cont). Chip Pin-Out for the ∆VBE Summing Bandgap Reference
108
-+ DB
iLN
A #
4V
DD
VSS
Pin
2P
in 4
0
Pin
1
Pin
37
Pin
3
Pin
36 C
omp
M2D
2000
/3.6
XD
3DX
D4D
10X
Pin
26
Pin
40
P
in 4
0
Pin
1
Pin
39
Pin
1
M1D
2000
/3.6
Pin
25
Pin
40
Pin
38
13 K
Pin
1
-+ DB
iLN
A #
3
VD
D
VSS
Pin
5P
in 6
Pin
1
Pin
7
Pin
4
Pin
8
Com
p
M2C
2000
/3.6
XD
3CX
D4C
10X
Pin
26
Pin
6
Pin
6
Pin
1
Pin
9
Pin
1
M1C
2000
/3.6
Pin
25
Pin
6
Pin
10
13 K
Pin
1
Fig. 5-3 (cont). Chip Pin-Out for the ∆VBE Summing Bandgap Reference
109
As shown in Figs. 5-4 and 5-5, the most critical metal pathways occurred either in
the circuit ground node or between the D2 diode-connected LPNP transistor and the
buffer amplifier output in the ∆VBE summing subcircuits. The effects are dramatic:
given the nominal 10 mA supply current of the circuit, simulations at 27 ˚C indicate a 67
mV increase in reference voltage due to parasitic ground resistances, and a 27 mV
increase in the total PTAT voltage generated by the ∆VBE summing subcircuits. These
error voltages are simply too large to ignore in a practical bandgap reference design. On
the other hand, the parasitic resistances could be dramatically reduced in a layout with no
external nodes, reduced quiescent current, and widened metal traces. Future submissions
of the ∆VBE summing bandgap reference will address these issues. Despite the error
voltages, it was still possible to obtain good temperature coefficient and output noise
results from the circuit. Every parasitic voltage drop in the circuit is either PTAT or
IPTAT, and as such can be canceled by adjusting the PTAT or IPTAT voltages used to
generate the bandgap reference voltage.
1.581 Ω
9.473 Ω
5.301 Ω
1.446 Ω 3.600 ΩTo PTATBias CircuitGround
To SummingSubcircuit #3Ground
To SummingSubcircuit #1, #2 Grounds
To VBE1 Generator Circuit Ground
Fig. 5-4. Parasitic Ground Resistances in the Bandgap Reference Layout
110
-
+VIN
D2
A1
V IN
11.97 Ω, 9.58 Ω, 4.25 Ω
40.63 Ω,22.74 Ω,25.98 Ω
Fig. 5-5. Parasitic Resistances in the ∆VBE Summing Subcircuit
Fig. 5-6 is a photograph of the fabricated ∆VBE summing bandgap reference as
received from the MOSIS service. The entire circuit requires about 1.70 mm2 of chip
area, although the bias circuit on the bottom half of the chip would certainly be arranged
more compactly in a production layout. Most of the compromises in layout efficiency
were a direct result of the need to bring out individual circuit nodes to external pads.
Note the symmetrical four-quadrant layout configuration for the ∆VBE summing
subcircuits. These subcircuits are dominated by the DBiLNA buffer amplifier structures,
which take up a total area of 0.864 mm2, more than half the reference circuit size.
However, as mentioned in the previous chapter, the DBiLNA amplifier is extremely
inefficient in terms of area and power consumption for this particular application. In the
first place, each amplifier has an individual bias circuit. A single bias circuit for all four
buffer amplifiers would be sufficient. The gain-bandwidth is too high, leading to
instability in unity-gain configuration unless a 20 pF external compensation capacitor is
used in addition to the 3 pF internal compensation capacitor. Most importantly, the
111
output stage of the DBiLNA maintains a quiescent current of more than 1 mA through
the push-pull output stage. Because the buffer amplifier in the summing subcircuit only
needs to sink current and never source it, the PMOS output device could be removed
without a performance penalty. Overall, the DBiLNA area and quiescent current
requirements could be dramatically reduced in future submissions by redesigning the
output stage and using a common bias circuit. Some type of cascode amplifier topology
with lateral PNP input transistors may prove to be the best solution for this particular
application.
112
Fig. 5-6. Photograph of the Fabricated ∆VBE Summing Bandgap Reference
113
Simulation of the ∆V BE Summing Bandgap Reference
Simulating the reference circuit proved more challenging than originally
anticipated. The simulations in this chapter were made after the fabricated bandgap
reference was tested in order to provide a correlation between the PSpice models and
actual working hardware. Critical layout resistances in high current pathways were
added to the subcircuits in the simulation. The average temperature coefficients of the
internal polysilicon resistors and external metal film resistors were measured and found
to be 834 ppm / ˚C and -16 ppm / ˚C, respectively. However, the most difficult
component to simulate proved to be the lateral PNP transistor. Ideally, the lateral PNP
should be simulated as a dual collector device, or at the very least as a vertical transistor
and lateral transistor with common base and emitter contacts. Unfortunately, PSpice
contains no dual collector transistor models, and there is no simple way to separate the
individual base currents of the vertical and lateral devices in a two transistor model.
Characterization of the vertical PNP transistor without the lateral collector connected was
not sufficient, since the performance of the vertical device proved to be correlated to the
lateral device. The simplest solution was a standard PNP transistor model with a
dependent current source connected to the collector terminal (Fig. 5-7). The current
source sinks a fraction of the total emitter current to simulate the vertical collector, and
the remaining current becomes the lateral collector current. The main drawback is that
the model is valid only for a particular bias point, and therefore multiple models must be
used in the simulation.
Even with the lateral PNP macromodels, parasitic resistances, and component
temperature coefficients taken into account, the final model-to-hardware correlation
proved only partially satisfactory. Precise matching of DC bias voltages and currents
along with simultaneous matching of noise and temperature performance proved
114
impossible, but a reasonable compromise that matched DC voltages within 20 mV was
finally achieved. Given the sensitivity of the ∆VBE summing bandgap reference to small
changes in layout and contact resistances, this difficulty in correlating the results to the
simulation was not surprising. Other effects such as circuit self-heating from the
relatively high power dissipation of 50 mW were also ignored in the simulation.
Appendix A contains the PSpice listing of the ∆VBE summing bandgap reference
simulation. Because of the three high-gain buffer amplifiers, the simulation initially
suffered from very slow DC convergence. This problem was eventually resolved by
increasing the RELTOL tolerance parameter and obtaining .NODESET voltages that
permitted faster convergence with a normal RELTOL value. The PSpice .MODEL Level
3 MOSFET parameters were supplied by MOSIS for this particular 1.2 µm CMOS
fabrication run. The .MODEL parameters for the lateral PNP transistors were generated
from Figs. 4-4 through 4-7 using the PARTS program supplied with PSpice [44].
Parameters such as PNP transistor base resistance and MOSFET flicker coefficient were
obtained from measurements of test structures from previous runs of the MOSIS 1.2 µm
CMOS process. In the following sections the simulation results will be compared to
actual circuit measurements and the differences discussed.
ICL ICV = K IE
IE
Fig. 5-7. PSpice Macromodel for the Lateral PNP Transistor
115
Experimental Results
Because of high quiescent currents, resistive ground paths, and the numerous
external pads of this integrated circuit, the low noise bandgap reference was extremely
sensitive to very small changes in resistance for connections between circuit nodes
through which large currents flowed. Given the necessity of measuring voltages at
resolutions as low as 10 µV, even a change of a few milliohms in the resistance of a
critical metal-to-metal contact has a significant effect on the reference voltage value.
Preliminary attempts to use protoboards and IC sockets gave mixed results; while
repeatable output voltages could be obtained at room temperature if great care was taken,
thermal expansion and contraction of circuit contacts during measurements in the
temperature chamber made reference voltage values impossible to repeat from one run to
the next. Mechanical vibration also affected the output voltage, especially at times when
several people would be walking around or near the lab. Intermittent voltage fluctuations
as high as 500 µV in amplitude were not unusual.
To solve this dilemma, test fixtures were created on universal printed circuit
boards and every component, including the MOSIS bandgap reference chips, were
soldered directly into the test circuit. Every contact in the temperature chamber was
soldered, and critical contacts outside the chamber used Molex pins and sockets. A
soldered 5 V regulator circuit was added to isolate the reference from supply voltage
variation. The final result was a bandgap reference with voltages that could be reliably
repeated to within ± 20 µV over the -40 ˚C to 85 ˚C temperature range, provided the
measurements took place in the late evening when external vibration was at a minimum.
116
Reference Output Voltage and Quiescent Current
The nominal reference voltage of the bandgap reference was determined through
the trial and error method of selecting a particular value of bias resistor, measuring the
temperature coefficient of the output voltage over the -40 ˚C to 85 ˚C range, and then
adjusting the R1B bias resistor until minimum temperature coefficient was obtained at 25
˚C. Preliminary simulations indicated that four ∆VBE summing subcircuit sections would
be required to generate the bandgap reference voltage. However, the fabricated circuit
required only three sections due to the additional PTAT voltage drops across the parasitic
layout resistances in the ∆VBE summing subcircuits. The on-chip R1B bias resistors were
too small to be used for trimming because of the resulting change in the DC bias values,
and external 1% tolerance metal film resistors were used instead.
A 784 Ω resistor was chosen for R1B after a series of temperature runs with a
randomly selected circuit. Given this bias resistor value, a nominal voltage reference
value of 1.13769 V with a standard deviation of 3.98 mV was obtained after measuring
sixteen chips. The standard deviation of the reference voltage is undoubtedly worsened
by process and packaging fluctuations in metal trace and contact resistances, and could be
reduced with lower quiescent currents and better layout techniques. (The quiescent
current of the circuit at room temperature was measured at 10.0 mA, which corresponds
very well with the simulated reference current value of 10.2 mA in Fig. 5-8.) In any case,
this circuit would almost certainly require individual trimming of the bias resistor value
to obtain the optimum reference voltage.
117
Fig. 5-8. Simulation of Quiescent Current versus Temperature for the BandgapReference
Temperature Coefficient
The optimum output voltage for minimum temperature coefficient in a bandgap
reference depends on the operating temperature range of interest. Average temperature
coefficients of bandgap references are generally specified over the commercial
temperature range (0 ˚C to 70 ˚C) at the minimum, and may be specified over the
extended ranges of 0 ˚C to 100 ˚C or -40 ˚C to 85 ˚C as well. Assuming the output
voltage versus temperature curve is symmetrical above and below the nominal reference
value, the middle of the operating temperature range is the obvious place to bias the
output voltage for minimum temperature coefficient (e.g., 35 ˚C for the commercial
temperature range or 22.5 ˚C for the -40 ˚C to 85 ˚C range). Fig. 5-9 is the measured
temperature coefficient for a ∆VBE summing bandgap reference with three values of bias
resistor. Each operating temperature point was maintained for a minimum of one hour in
118
the temperature chamber prior to taking the voltage measurement. At R1B = 784 Ω, the
circuit has a nominal reference voltage of 1.14097 V with an average temperature
coefficient of 34.0 ppm / ˚C over the -40 ˚C to 85 ˚C operating range. At R1B = 784 Ω
the nominal output voltage is 1.13642 V and the average temperature coefficient over the
commercial temperature range is 15.8 ppm / ˚C. With careful trimming, temperature
coefficients of approximately 15 ppm / ˚C over a 70 ˚C span can be obtained with this
circuit. However, trimming resolution is limited by the minimum practical increment of
available bias resistance, which in the case of the MOSIS 1.2 µm CMOS process would
be approximately 25 Ω (a single square of polysilicon), excluding some form of laser
trimming.
119
85756555453525155-5-15-25-35-45
1.136
1.138
1.140
1.142
1.144
1.146
1.148
784 Ω Bias
806 Ω Bias
768 Ω Bias
Low Noise Bandgap Reference Temperature Performance
Ref
eren
ce O
utpu
t Vol
tage
Temperature (˚C)
Fig. 5-9. Reference Output Voltage versus Temperature with Different Bias Resistors
Figs. 5-10 and 5-11 are simulations of temperature coefficient versus output
voltage for the bandgap reference. These simulations show the same concave voltage
curvature as predicted in Chapter III and verified experimentally. However, the
temperature coefficients in these simulations are approximately twice the value of the
corresponding measured temperature coefficients. For example, with R1B = 784 Ω, the
simulation gives VREF = 1.1575 V with an average temperature coefficient of 62.5 ppm /
˚C over the -40 ˚C to 85 ˚C temperature range. At R1B = 806 Ω, the simulation has VREF
= 1.1525 V with an average temperature coefficient of 37.2 ppm / ˚C over the 0 ˚C to 70
˚C temperature range. Attempts to reduce the simulation temperature coefficients while
maintaining proper DC bias levels were unsuccessful. However, the simulation does not
120
account for effects such as circuit self-heating, and the circuit lacks access to most
internal nodes for better characterization. On the other hand, it can be argued that the
poor model-to-hardware temperature correlation is relatively unimportant, since the
actual temperature coefficients are considerably better than the simulation results, and the
overall temperature coefficient in future versions of the bandgap reference can be
adjusted as desired using techniques described in the next chapter.
Fig. 5-10. Simulation of Reference Output Voltage versus Temperature with a 784 ΩBias Resistor
121
Fig. 5-11. Simulation of Reference Output Voltage versus Temperature with 768 Ω, 784Ω, and 806 Ω Bias Resistors
Fig. 5-12 is a plot of temperature versus reference voltage over the -40 ˚C to 85
˚C temperature range for four randomly picked bandgap reference circuits using identical
bias resistors of 784 Ω. Circuit #1 achieves a 28.7 ppm / ˚C temperature coefficient over
the full temperature range, and circuit #3 has a temperature coefficient of 11.4 ppm / ˚C
over the 15 ˚ C to 85 ˚C temperature range. Circuits #2 and #4 apparently are not biased
at a high enough quiescent current, and require a small reduction in their respective bias
resistances to achieve optimum temperature coefficient. These results demonstrate the
need for individual trimming of the circuits, and also tend to indicate that the nominal
reference voltage is approximately 1.14 V once this trimming has been achieved.
122
9080706050403020100-10-20-30-40
1.130
1.132
1.134
1.136
1.138
1.140
1.142
1.144
1.146
1.148
1.150
Circuit #1
Circuit #2
Circuit #3
Circuit #4
Reference Output Voltagewith 784 Ω Bias Resistor
Out
put V
olta
ge
Temperature (˚C)
Fig. 5-12. Reference Output Voltage versus Temperature for Four Test Circuits
Output Noise
Fig. 5-13 is a plot of measured output noise versus frequency for the ∆VBE
summing bandgap reference, averaged over four chips. The output noise spectrum has a
1/f noise corner of approximately 3 KHz, and the overall noise level is much lower than
that of the differential bandgap reference [10]. At 1 Hz, the 1/f noise dominates, but the
output level is only 1.26 µV / Hz . At 100 KHz, the white noise level is only 27.0 nV /
Hz , while the level at 1 MHz drops to 18.9 nV / Hz . In Fig. 5-14, the output noise
simulation for the low noise bandgap reference gives a level of 1.08 µV / Hz at 1 Hz
decreasing to 23.9 nV / Hz . The measured white noise levels are approximately 1 dB
123
higher than the simulated levels, but these differences are within the experimental error
normally encountered in noise measurements. The higher measured noise levels could
also be a result of substrate heating from the circuit's quiescent power dissipation.
Overall, the model-to-hardware correlation for output noise is excellent.
The total simulated output noise at 27 ˚C over a 500 KHz bandwidth is 19.0 µV
RMS (Fig. 5-15), or 16.7 µV RMS per regulated volt. In contrast, the output noise of the
differential bandgap reference is 129 µV RMS per regulated volt over the same
bandwidth, or 17.8 dB greater. The ∆VBE summing bandgap reference has nearly an
order of magnitude less output noise than the differential bandgap reference at a cost of
far less quiescent current than the 71.6 mA predicted by standard current / noise scaling
estimates.
By examining the PSpice output listing for the output noise simulation, the major
contributors of output noise in the ∆VBE summing bandgap reference were identified. At
a frequency of 1 Hz, the dominant 1/f noise contributors are NFETs M4 and M5 in the
PTAT bias circuit (Fig. 5-1), which generate a total noise voltage of 1.00 µV / Hz .
PMOS transistors M1 and M2 generate 300.4 nV / Hz for the next highest 1/f noise
contribution, and all other component 1 /f noise sources are essentially negligible. These
values indicate that the reference circuit's 1/f noise could be reduced by approximately 11
dB if the NMOS transistors M4 and M5 could be replaced or removed using a different
PTAT bias circuit topology.
At a frequency of 100 KHz, the reference output noise is dominated by several
white noise sources in the circuit. Once again, components in the PTAT bias circuit
generate the majority of the noise. Resistor R1B generates a noise voltage of 11.7 nV /
Hz at the output, PFETs M1 and M2 generate 12.4 nV / Hz , and NFETs M4 and M5
generate 10.5 nV / Hz . The bulk of the remaining noise is generated by the Q2 and Q3
LPNP input transistors of the buffer amplifers, which contribute a total of 15 nV / Hz at
124
the output. In turn, the majority of the LPNP input transistor noise is intrinsic base
resistance thermal noise, and this noise can be reduced by using larger geometry input
transistors in the buffer amplifiers.
106
105
104
103
102
101
100
10
100
1000
10000
Reference Output Noise versus Frequency
Frequency (Hz)
nV
Hz
Fig. 5-13. Output Noise of the ∆VBE Summing Bandgap Reference
125
Fig. 5-14. Simulation of Output Noise Spectral Density versus Frequency
Fig. 5-15. Simulation of Total RMS Output Noise versus Frequency
126
Minimum Operating Voltage and Power Supply Rejection
The ∆VBE summing bandgap reference was designed to function with a 5 V
power supply, but CMOS circuit designs are inevitably moving towards smaller power
supply voltages. At the very least, a minimum power supply voltage of 3.0 V or less
would be desirable for a production version of this bandgap reference. Unfortunately, the
cascoded PMOS devices used in an effort to increase power supply rejection also
increase the minimum supply voltage. Fig. 5-16 is a measurement of output voltage
versus power supply voltage over the range VDD = 5.2 V to 3.0 V. As the power supply
voltage is reduced from 5.2 V, the reference provides an average PSR of 42.5 dB until
VDD = 3.6 V. Below this voltage, the PSR dramatically worsens to 8.6 dB, rendering the
low noise bandgap reference useless. This behavior is the direct result of the failure of
the PTAT bias circuit to operate properly at lower supply voltages. The bias circuit fails
long before the ∆VBE summing subcircuit does. However, the PSR needs to be increased
to 60 dB or better regardless of the minimum supply voltage.
One obvious technique for improving power supply rejection in the PTAT bias
circuit while reducing the supply voltage requirement is to remove the cascoded PMOS
transistors in favor of very long channel length transistors for both the PFETs and
NFETs. If this method proves impractical, a different low voltage bias circuit topology
with high PSR and low minimum supply voltage can be used with the circuit.
Figs. 5-17 and 5-18 show simulations of the DC and AC power supply rejection
of the bandgap reference, respectively. The DC PSR results correlate quite well to give a
minimum supply voltage of approximately 3.6 V. The AC power supply rejection has a
simulated -3 dB frequency of 100 KHz, although this parameter was not measured in the
laboratory.
127
5.45.04.64.23.83.43.0
0.85
0.90
0.95
1.00
1.05
1.10
1.15
Supply Voltage
Ref
eren
ce V
olta
ge
Fig. 5-16. Reference Voltage versus Power Supply Voltage
Fig. 5-17. Simulation of Reference Voltage versus Power Supply Voltage
128
Fig. 5-18. Simulation of Power Supply Rejection versus Frequency
Table 5-1 summarizes the measurement results for the ∆VBE summing bandgap
reference. Despite the DC voltage errors introduced by the parasitic layout resistances,
the ∆VBE summing bandgap topology successfully demonstrates that a low noise
bandgap reference with low temperature coefficient is possible and practical in the
MOSIS 1.2 µm n-well CMOS process. Although the circuit area and quiescent current
are greater than desired for a practical circuit, both can be reduced by such methods as
removing duplicated bias circuits, redesigning the buffer amplifier, and trading slightly
higher output noise for reduced current in the ∆VBE summing subcircuits.
129
Table 5-1. A Summary of Measured Parameters for the ∆VBE Summing BandgapReference with 784 Ω Bias Resistor and VDD = 5 V
Circuit Area 1.70 mm2
Quiescent Current 10.0 mA
Average Reference Voltage (@ 27 ˚C, VDD = 5 V) 1.13769 V (σ = 3.98 mV)
Temperature Coefficient (0 ˚C to 70 ˚C) 15.8 ppm / ˚C
Temperature Coefficient (-40 ˚C to 85 ˚C) 34.0 ppm / ˚C
Output Noise (@ 1 Hz) 1.26 µV / Hz
Output Noise (@ 100 KHz) 27.0 nV / Hz
Output Noise per Regulated Volt (500 KHz BW) 16.7 µV RMS
DC Power Supply Rejection Ratio - 42.5 dB
Minimum Power Supply Voltage @ 27 ˚C 3.6 V
130
CHAPTER VI
FUTURE DIRECTIONS FOR THE LOW NOISE CMOS BANDGAP REFERENCE
An Improved ∆V BE Summing Subcircuit
The experimental results of the ∆VBE summing bandgap reference demonstrate
the practicality of a bandgap voltage reference with low output noise in a standard n-well
digital CMOS process. Unfortunately, the disadvantage of relatively high quiescent
current in the ∆VBE summing subcircuit would severely limit the application of the low
noise topology, especially in low power CMOS designs. In this section, the benefits of
replacing the original ∆VBE summing subcircuit with an improved subcircuit will be
examined. If current source IBIAS2 in Fig. 4-10 is changed to a current sink and placed
between the cathode of diode D2 and circuit ground, the DC characteristics of this
improved ∆VBE summing subcircuit will be almost identical to that of the original circuit
analyzed in Chapter III. In Fig. 6-1, the input voltage VIN is mirrored to the cathode of
diode D2, rises by the voltage VBE2, and falls by the voltage VBE3 at the output. In fact,
since amplifier A1 supplies the current IC3 that flows through D3 and R1, IC2 will be
exactly equal to IBIAS2. The reference voltage approximation of equation (3-26)
becomes
131
VREF = Vg0 + (η − m − pK) kT
q 1− ln
T
Tr
−kT
q Tr
j=1
K
∑ αT,j + α R,j[ ]
+ kTq
j=1
K
∑ ln1+ α R,j (T − T j )
1− α T,j (T − T j )
.
(6-1)
This is a more exact expression for the ideal output voltage of the ∆VBE summing
bandgap reference.
-
+
VIN
VIN
IBIAS2
R1
VIN + VBE 2
A1
VOUT = VIN + VBE2 − VBE3 = V IN + ∆VBE
IC2
IC3D2 D3
Fig. 6-1. An Improved ∆VBE Summing Subcircuit
The improved ∆VBE summing subcircuit has some advantages over the previous
design in terms of noise gain and minimum operating voltage. For the original ∆VBE
summing subcircuit, the exact expression for the impedance seen by the IBIAS1 current
source (Fig. 3-3) is
132
rload = rd2 +ro
1+ A(s)
|| rd3 + R1( ) ≈ rd2 (6-2)
if A(s) is very large and R1 is much greater than rd2. As frequency increases and the
magnitude of A(s) decreases, the value of rload will increase until A(s) = 0 and rload
reduces to
rload A(s)=0 = rd2 + ro( ) || rd3 + R1( ) . (6-3)
Now consider the simplified small-signal diagram of the improved ∆VBE
summing subcircuit in Fig. 6-2. The noninverting input of the buffer amplifier is set
equal to AC ground via superposition and the IBIAS2 current sink is replaced by a
transconductance multiplied by an equivalent input noise voltage Ebias2. Given a buffer
amplifier with an output resistance ro and a finite gain A(s), the noise gain from the
IBIAS2 current sink to the output of the buffer amplifier is
Eout
Ebias2=
A(s)rd2 − ro[ ] gm(bias2 )
A(s) +1+ rord3 + R1
(6-4)
for an equivalent bias circuit AC load impedance of
rload = A(s)rd2 − ro
A(s) +1+ rord3 + R1
. (6-5)
133
Assuming A(s) is very large, rload can be approximated as
rload ≈ rd2 . (6-6)
However, in contrast to the original ∆VBE summing subcircuit, the magnitude of rload in
equation (6-5) will be reduced as frequency increases and A(s) decreases, since the ro
term is subtracted from the numerator value. At the frequency where A(s) times rd2 is
equal to ro, the load resistance (and noise gain from the bias circuit) will become zero. At
higher frequencies, rload will rise until A(s) falls to zero and
rload A(s)=0 = ro | | rd3 + R1( ) (6-7)
which is a slightly smaller value than equation (6-3). Therefore, at any given frequency
the noise amplifier formed by the bias circuit and the IBIAS2 current sink will have an
equal or lower gain than the original summing subcircuit configuration, assuming all
component values are identical. Depending on the output resistance of the buffer
amplifier, the 1/f noise of the IBIAS2 NFET current sink, and the parameters of the MOS
transistors in the circuit, the improved ∆VBE summing subcircuit may generate less total
noise than the original subcircuit even when diode D2 is biased at currents below 1 mA.
134
+_
ro rd2
gm(bias2 )
∗Ebias2
V(-)
-A(s) V(-)
Eout2
rd3 + R1
Fig. 6-2. Small-Signal Diagram of the Improved ∆VBE Summing Subcircuit
If IC2 is reduced by a factor of ten and diode D2 is replaced with a 4 emitter dot
device rather than a 40 emitter dot device, the same ∆VBE drop through the summing
subcircuit can be obtained with much lower DC current. Similarly, the magnitude of IC2
could be reduced, the junction area of diode D2 kept the same, and the magnitude of IC3
decreased tenfold by increasing the value of R1. This strategy would minimize the
undesirable effects of emitter and layout resistances for diode-connected LPNP transistor
D2.
The other advantage of this new ∆VBE summing subcircuit topology is the
reduced minimum operating voltage of the circuit. Since IBIAS2 is now connected
between D2 and ground, the minimum output voltage VDD(min) is equal to
VDD(min) = VREF +V BE3 + VAO(min) (6-8)
where VAO(min) is the minimum difference between the supply voltage of the buffer
amplifier and the output voltage (VREF + VBE3). Given a properly designed operational
amplifier circuit, VAO(min) can be less than 200 mV. In this case, a minimum operating
135
voltage of 2.0 V is possible with this circuit, provided a low voltage bias circuit is
implemented as well. Since VIN will always be equal to 0.6 V or greater for each ∆VBE
summing subcircuit stage, the IBIAS2 NFET current sink should have ample voltage drop
for operation in the saturation region [3].
A New Method of High-Order Temperature Compensation
As previously described in Chapter II, several different methods of high-order
temperature compensation have been used in the past to reduce the average temperature
coefficient of bandgap voltage references. Most of these methods have drawbacks, either
in terms of increased circuit complexity or higher minimum operating voltages.
Although the ∆VBE summing bandgap reference has temperature performance
comparable to other CMOS bandgap references presented in recent years, an average
temperature coefficient of 15.8 ppm / ˚C over the commercial temperature range can still
be improved. The ∆VBE summing bandgap reference topology has the potential to
achieve much lower average temperature coefficients without complex circuitry simply
by varying the temperature coefficients of the bias currents for the individual subcircuits.
For example, consider the temperature coefficient curvature errors in each of the
subcircuits in Fig. 6-3, assuming all the bias currents are PTAT (as in the present circuit).
The VBE1 generator has a convex nonlinearity in its voltage versus temperature curve, as
is typical for any p-n junction. The ∆VBE summing subcircuits exhibit concave
temperature coefficient nonlinearities rather than purely PTAT behavior because the ratio
of currents between diodes D2 and D3 is not constant with respect to temperature (Fig. 6-
1). Instead, the current through D3 is set by the output voltage of the subcircuit and the
value of resistor R1, independent of IBIAS2. The cumulative error at the output of the
∆VBE summing bandgap reference is also concave because the summed concave
nonlinearities are greater than the convex nonlinearity of VBE1.
136
∑+
+
∑+
+K Summing Sections
VDD
VBE1
IBIAS1
∆VBE ∆VBE
D1
V REF =VBE1 +K * ∆VBE
Temp
VBE1
Temp
∆VBE
Temp
∆VBE
Fig. 6-3. Temperature Coefficient Errors in the ∆VBE Summing Bandgap Reference
As previously derived in Chapter III, both the concave and convex nonlinearities
have the same general form of
yx (T,Tr ) = Tr ′ f x (Tr )
f x (Tr )− ln
f x (T )
f x (Tr )
(6-9)
but with opposite amplitudes. This result implies that a precise cancellation of the
negative and positive error terms could result in very low average temperature
coefficients for the ∆VBE summing bandgap reference. However, such cancellation will
require some method of separately manipulating the individual nonlinearities in each part
of the circuit.
137
Equation (6-1) gives an approximation for the output voltage VREF with the
assumption that all the bias currents of the ∆VBE summing subcircuits have the same
temperature coefficient p. If the bias currents have different temperature coefficients, the
equation can be expanded to
VREF = Vg0 + (η − m) kTq
1− lnTTr
−kT
q pj 1− ln
T
Tr
j=1
K
∑
− kT q
Tr j=1
K
∑ αT,j + α R,j[ ]
+ kT
q
j=1
K
∑ ln1+ α R,j (T − T j )
1− α T,j (T − T j )
(6-10)
where m is the temperature coefficient for the IBIAS1 current source in the VBE1
generator subcircuit and pj is the IBIAS2 temperature coefficient for the jth summing
subcircuit. There are now (K+1) separate temperature coefficients in equation (6-10),
and each coefficient can be manipulated individually with a separate bias circuit. For
example, the temperature coefficient of VREF will be reduced if the curvature of VREF is
made less concave. If the VBE1 generator is biased with an IPTAT current source (Fig.
6-4) to obtain m ≈ -1 while the ∆VBE summing subcircuits are biased with a PTAT
current source for pj ≈ -1, the convex error term in equation (6-10) can be increased in
magnitude, resulting in greater cancellation of the concave error term. An IPTAT bias
current can also be applied to one or more of the ∆VBE summing subcircuits, changing
the respective temperature coefficient p j from 1 to -1 and decreasing the concave error
term further.
138
VDD VDD VDD
M1 M2 M3
M4 M5
ID4
Q1B
VBE1B VBE1B
R1B
W3L3
L2W2
∗ VBE1B
R1B
ID5 =VBE1B
R1B
Fig. 6-4. A Simple IPTAT Current Source
If necessary, the temperature coefficient nonlinearities of the ∆VBE summing
bandgap reference can be more precisely canceled by combining PTAT and IPTAT
current sources as shown in Fig. 6-5. By varying the ratio between the two currents, the
effective temperature coefficient m can be set over a range of approximately +1 to -1.
VDD
IPTAT PTAT
+1 ≥ m ≥ -1
Fig. 6-5. A Current Source with Adjustable Temperature Coefficient
139
An Improved ∆V BE Summing Bandgap Reference
Fig. 6-6 shows the block diagram for an improved ∆VBE summing bandgap
reference using the new ∆VBE summing subcircuit and the temperature coefficient
cancellation technique described in this chapter. The VBE1 generator uses an IPTAT
current source while the three ∆VBE summing subcircuits are biased with a PTAT current
source. The output voltage is trimmed by adjusting the bias resistors of the two current
sources to obtain a minimum temperature coefficient. Because high quiescent current
may limit the application of the low noise bandgap reference topology, the goal for this
new circuit was minimum output noise with a nominal supply current less than 2 mA. To
minimize the number of ∆VBE summing subcircuit stages, a D3 / D2 junction area ratio of
100 is used (i.e. ten 40 dot LPNP transistors with one 4 dot LPNP transistor). If this large
ratio creates problems due to device mismatch, an additional ∆VBE stage could be added
at the cost of higher output noise, quiescent current, and circuit area.
A detailed PSpice listing is shown in Appendix B. Figs. 6-7 through 6-11 are the
results of the simulation. Fig. 6-7 is the output voltage versus temperature over the -40
˚C to +85 ˚C temperature range. Due to the cancellation of the error terms, the average
temperature coefficient is less than 2 ppm / ˚C. The 1/f noise at 1 Hz is less than 1 µV /
Hz , which is comparable to the original circuit results, while midband white noise is 30
nV / Hz (Fig. 6-8) . The total output noise at 500 KHz is only 20 µV RMS per regulated
VDC (Fig. 6-9), which is less than 16% of the output noise produced by the differential
bandgap reference over the same bandwidth. The circuit's power supply rejection is
approximately 78 dB at DC with a -3 dB rolloff at 8 KHz (Fig. 6-10). This overall
excellent performance is achieved with less than 1.5 mA of total current at 27 ˚C (Fig. 6-
11), and the estimated area is only 1 mm2.
140
∑+
+
∑+
+
∑+
+
VDD
VBE1
∆VBE ∆VBE ∆VBE
D1
IPTAT
IIPTAT
Bias BiasBias
VREF =V BE1 +3 ∗ ∆VBE
Fig. 6-6. Block Diagram of the Improved ∆VBE Summing Bandgap Reference
Fig. 6-7. VREF versus Temperature for the Improved ∆VBE Summing BandgapReference
141
Fig. 6-8. Output Noise versus Frequency for the Improved ∆VBE Summing BandgapReference
Fig. 6-9. Total Output Noise for the Improved ∆VBE Summing Bandgap Reference
142
Fig. 6-10. Power Supply Rejection versus Frequency for the Improved ∆VBE SummingBandgap Reference
Fig. 6-11. Supply Current versus Temperature for the Improved ∆VBE SummingBandgap Reference
143
A Low Noise Fractional Bandgap Reference
As battery powered computing and telecommunications equipment becomes more
common, the demand for analog and digital CMOS circuits that operate at lower supply
voltages increases. The design of high performance CMOS circuits that operate at supply
voltages at 1 V or less is an area of considerable research at this time. With such small
power supply voltages, intrinsic circuit noise reduction becomes even more desirable for
applications such as data acquisition and analog-to-digital conversion.
A standard bandgap reference circuit with VREF = 1.2 V cannot be implemented
with a 1 V power supply. On the other hand, a "fractional" bandgap reference with an
output voltage of
VREF(FR) =VREF
K=
VBE
K+∆ VBE (6-11)
is certainly possible, and a circuit of this type has recently been implemented in a bipolar
process [45]. As equation (6-11) shows, a fractional bandgap reference achieves
minimum temperature coefficient by dividing the base-emitter voltage VBE by the factor
K instead of multiplying ∆VBE by K. The result is a nominal output reference voltage
less than 0.4 V.
Fig. 6-12 shows the proposed topology of a low noise fractional bandgap
reference using a single ∆VBE summing subcircuit stage. Resistors R2 and R3 act as a
simple voltage divider for voltage VBE1, which in turn is summed with a single ∆VBE
voltage. The drawback to this topology is the requirement for a buffer amplifier and
VBE1 voltage generator which can operate at VDD = 1.0 V. Low noise, low voltage
amplifier designs using LPNP bipolar transistors have already been tested in the MOSIS
144
1.2 µm CMOS process, and MOSFET transistors can be operated in the subthreshold
region [3], although circuit simulation at very low supply voltages is hampered by the
lack of good subthreshold region modeling in PSpice [44].
VDD
VBE1
IBIAS1
D1 -
+
VIN
IBIAS2
R1
A1D2 D3
~ 175 mV
~ 875 mV
~ 175 mV
VIN
VOUT ≈300 mV
R2
R3
Fig. 6-12. The Low Noise Fractional Bandgap Reference Topology
Figs. 6-13 and 6-14 show the PSpice simulation results for a simplified model of
the fractional bandgap reference. Since PSpice does a poor job of simulating
subthreshold behavior in MOSFETs, ideal circuit elements were used for the current
sources and buffer amplifier. As such, the simulated average temperature coefficient of
19 ppm / ˚C at the given bias current level is probably inaccurate, but the temperature
coefficient of the actual circuit could be easily adjusted using the techniques described in
this chapter. Similarly, the output noise level is artificially low (especially in the 1/f
region) because of the use of noiseless ideal elements in the simulation.
145
Fig. 6-13. Output Voltage versus Temperature (˚C) for the Fractional Bandgap Reference
Fig. 6-14. Output Noise versus Frequency for the Fractional Bandgap Reference
146
Despite the limitations of this simple simulation, the results indicate that a
fractional bandgap reference is almost certainly practical in the MOSIS 1.2 µm CMOS
process. In fact, given a working fractional bandgap circuit, one obvious application
would be to operate the circuit at higher power supply voltages and add a voltage
multiplier stage to obtain the reference voltage
VREF = VFB 1+RF1RF2
. (6-12)
Resistors RF1 and RF2 could be adjusted to generate any voltage greater than or equal to
VFB, the fractional reference voltage. Since the output noise of VFB and the offset
voltage of the output buffer would be multiplied by the the same resistor ratio, the end
result would be a circuit with reduced circuit size and current requirements at the expense
of higher output noise and component error sensitivity as compared to the standard ∆VBE
summing bandgap reference topology.
-
+FractionalBandgapVoltageReference
VREFVFB
RF1RF2
Fig. 6-15. A Fractional Bandgap Reference with a Voltage Multiplier Stage
147
CONCLUSIONS AND RECOMMENDATIONS
Conclusions
This dissertation demonstrates an original method of noise reduction for a
bandgap voltage reference constructed in a standard 1.2 µm n-well CMOS process.
Output noise is a significant source of error in CMOS bandgap references, and practical
noise reduction without the use of external filtering requires a reference circuit topology
that separates the desired DC performance from the undesired small-signal noise gain.
The original ∆VBE summing bandgap reference attacks this problem from two directions.
First, voltage summation gives lower output noise than direct voltage multiplication.
Second, bipolar diodes produce large DC voltage drops with lower small-signal dynamic
resistance than fixed load resistors.
Another significant contribution of this research is the development of a lateral
PNP bipolar transistor that can be fabricated in the MOSIS 1.2 µm n-well CMOS
process. The ∆VBE summing bandgap topology requires low noise buffer amplifiers and
floating bipolar diodes to function, and this parasitic LPNP transistor structure was the
key component for successful operation. Characterization of lateral PNP transistors over
six fabrication runs has shown them to be repeatable, reliable devices with low intrinsic
1/f noise and good ß and gain-bandwidth.
A low noise bandgap circuit was designed, tested, and fabricated in the MOSIS
1.2 um CMOS process. Although parasitic resistances in the original layout adversely
affected the circuit's performance, the reference generated output noise nearly an order of
magnitude less than previously reported CMOS bandgap references, while maintaining a
comparable temperature coefficient over the commercial temperature range. The major
148
drawback of the circuit was the excessively high quiescent current, but this current could
be significantly reduced using simple design changes in future versions of the reference.
Besides the successful construction and peformance of the reference circuit, a new
methodology of high-order temperature compensation for bandgap voltage references
was developed and simulated in this dissertation. By generating the circuit's ∆VBE
voltage using two diodes with a current ratio that is not constant with respect to
temperature, the temperature coefficient nonlinearity of a standard bipolar diode can be
canceled without the need for complicated circuit methods used in previous CMOS
bandgap reference designs.
In conclusion, this research makes three major new contributions in CMOS
analog design: (1) the design and characterization of a lateral PNP bipolar transistor in a
standard 1.2 µm digital CMOS technology, (2) the analysis, fabrication, and testing of a
functional low noise bandgap reference using a new circuit topology that reduces intrinsic
component noise by nearly an order of magnitude, and (3) the derivation and simulation
of a simple method for cancelling the second- and higher-order nonlinearities in the
temperature coefficients of standard bandgap voltage references.
Recommendations for Future Research
While the experimental results of the low noise bandgap reference have verified
the basic advantages of the new topology, enormous potential remains for extending the
concepts introduced by this dissertation in future designs. The improved ∆VBE summing
subcircuit of Chapter VI coupled with a new bias circuit will permit the fabrication of a
∆VBE summing bandgap reference with low output noise and reduced minimum supply
voltage while simultaneously reducing quiescent current and layout size to levels
competitive with standard CMOS bandgap references. A low noise fractional bandgap
reference that can operate with a 1 V power supply is also possible, although a low
149
voltage bias circuit and buffer amplifier must be designed to make the circuit practical.
An improved version of the ∆VBE summing bandgap reference and a fractional bandgap
reference are planned for fabrication through MOSIS in the coming year.
Another important area yet to be explored is the extension of the ∆VBE summing
bandgap topology to different integrated circuit processes. The MOSIS service offers a
standard CMOS 0.8 µm n-well process and a BiCMOS 2.0 µm n-well process. The 0.8
µm technology should enable a much smaller reference circuit to be fabricated, but lateral
PNP structures constructed in this process have only begun to be examined. On the other
hand, the 2.0 µm process offers a proven high-performance NPN bipolar transistor that
can be used to construct a true floating bipolar diode or replace a noisy NMOS transistor
in a low noise buffer amplifier or bias circuit. A ∆VBE summing bandgap reference
fabricated in a BiCMOS process would have even lower 1/f output noise than already
demonstrated by the CMOS version of the circuit. The bandgap reference could also be
fabricated in a true bipolar IC technology, although the output noise improvement in such
a process might be too small to be worth the effort, given the circuit overhead required by
the topology.
As a final recommendation, the application of the higher-order temperature
compensation method should be examined in greater detail. This compensation
technique can be used with any bandgap topology and is independent of output noise
performance. For example, a noisy but low-power bandgap reference design requiring
external filtering could still use this method to reduce the temperature coefficient.
150
BIBLIOGRAPHY
[1] K.C. Taylor and J.A. Connelly, "An Analysis Methodology to Identify DominantNoise Sources in D/A and A/D Converters," IEEE Transactions on Circuits and Systems,vol. 38, no. 10, pp. 1133-44.
[2] R.J. Widlar, "New Developments in IC Voltage Regulators," IEEE J. Solid-StateCircuits, vol. SC-6, pp. 2-7, February 1971.
[3] P.E. Allen and D.R. Holberg, CMOS Analog Circuit Design. New York: Holt,Rinehart and Winston, 1987.
[4] G.C.M. Meijer, P.C. Schmale, and K.V. Zalinge, "A New Curvature-CorrectedBandgap Reference," IEEE J. Solid-State Circuits , vol. SC-17, pp. 1139-1143, December1982.
[5] B. Song and P.R. Gray, "A Precision Curvature-Compensated CMOS BandgapReference," IEEE J. Solid-State Circuits, vol. SC-18, pp. 634-643, December 1983.
[6] P.R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits.New York: John Wiley & Sons, 1984.
[7] W.T. Holman, "Noise Performance of CMOS and CMOS-Compatible IC VoltageReferences and Regulators," Qualifying Examination, Georgia Institute of Technology,1991.
[8] C.D. Motchenbacher and J.A. Connelly, Low-Noise Electronic System Design. NewYork: John Wiley & Sons, 1993.
[9] M.G. Degrauwe, O.N. Leuthold, E.A. Vittoz, H.J. Oguey, and A. Descombes,"CMOS Voltage References Using Lateral Bipolar Transistors," IEEE J. Solid-StateCircuits, vol. SC-20, pp. 1151-1157, December 1985.
[10] M. Ferro, F. Salerno, and R. Castello, "A Floating CMOS Bandgap VoltageReference for Differential Applications," IEEE J. Solid-State Circuits, vol. 24, pp. 690-697, June 1989.
[11] G. Nicollini and D. Senderowicz, "A CMOS Bandgap Reference for DifferentialSignal Processing," IEEE J. Solid-State Circuits, vol. 26, pp. 41-50, January 1991.
[12] M.G. Degrauwe, O. Nys, E. Dijkstra, J. Rijmenants, S. Bitz, B.L.A.G. Goffart, E.A.Vittoz, S. Cserveny, C. Meixenberger, G. Van Der Stappen, and H.J. Oguey, "IDAC: AnInteractive Design Tool for Analog CMOS Circuits," IEEE J. Solid-State Circuits , vol.SC-22, pp. 1106-1115, December 1987.
151
[13] R. Knapp, "Selection Criteria Assist in Choice of Optimum Reference," EDN, pp.183-192, February 18, 1988.
[14] F. Goodenough, "IC Voltage References: Better Than Ever," Electronic Design, pp.83-89, September 22, 1988.
[15] S.L. Lin and C.A.T. Salama, "A VBE(T) Model with Application to BandgapReference Design," IEEE J. Solid-State Circuits, vol. SC-20, pp. 1283-1285, December1985.
[16] Y.P. Tsividis, "Accurate Analysis of Temperature Effects in IC-VBE Characteristicswith Application to Bandgap Reference Sources," IEEE J. Solid-State Circuits, vol. SC-15, pp. 1076-1084, December 1980.
[17] G. Tzanateas, C.A.T. Salama, and Y.P. Tsividis, "A CMOS Bandgap VoltageReference," IEEE J. Solid-State Circuits, vol. SC-14, pp. 655-657, June 1979.
[18] E.A. Vittoz, "MOS Transistors Operated in the Lateral Bipolar Mode and TheirApplication in CMOS Technology," IEEE J. Solid-State Circuits, vol. SC-18, pp. 273-279, June 1983.
[19] J. Bertails, "Low-Frequency Noise Considerations in MOS Amplifiers Design,"IEEE J. Solid-State Circuits, vol. SC-14, pp. 773-776, August 1979.
[20] K. Hsieh, P.R. Gray, D. Senderowicz, and D.G. Messerschmitt, "A Low-NoiseChopper-Stabilized Switched-Capacitor Filtering Technique," IEEE J. Solid-StateCircuits, vol. SC-16, pp. 708-715, December 1981.
[21] R.C. Yen and P.R. Gray, "A MOS Switched-Capacitor Instrumentation Amplifier,"IEEE J. Solid-State Circuits, vol. SC-17, pp. 1008-1013, December 1982.
[22] M.S.J. Steyaert, W.M.C. Sansen, and C. Zhongyuan, "A Micropower Low-NoiseMonolithic Instrumentation Amplifier for Medical Purposes," IEEE J. Solid-StateCircuits, vol. SC-22, pp. 1163-1168, December 1987.
[23] R. Gregorian and G.C. Temes, Analog MOS Integrated Circuits for SignalProcessing. New York: John Wiley & Sons, 1986.
[24] K.E. Brehmer and J.B. Wieser, "Large Swing CMOS Power Amplifier," IEEE J.Solid-State Circuits, vol. SC-18, pp. 624-629, December 1983.
[25] S.L. Wong and C.A.T. Salama, "An Efficient CMOS Buffer for Driving LargeCapacitive Loads," IEEE J. Solid-State Circuits, vol. SC-21, pp. 464-469, June 1986.
[26] D.M. Monticelli, "A Quad CMOS Single-Supply Op Amp with Rail-to-Rail OutputSwing," IEEE J. Solid-State Circuits, vol. SC-21, pp. 1026-1034, December 1986.
[27] J.A. Fisher and R. Koch, "A Highly Linear CMOS Buffer Amplifier," IEEE J.Solid-State Circuits, vol. SC-22, pp. 330-334, June 1987.
152
[28] J.N. Babanezhad, "A Rail-to-Rail CMOS Op Amp," IEEE J. Solid-State Circuits,vol. SC-23, pp. 1414-1417, December 1988.
[29] C.A. Laber and P.R. Gray, "A Positive-Feedback Transconductance Amplifier withApplications to High-Frequency, High-Q CMOS Switched-Capacitor Filters," IEEE J.Solid-State Circuits, vol. SC-23, pp. 1370-1378, December 1988.
[30] D.M. Maeding, "A CMOS Operational Amplifier with Low Impedance DriveCapability," IEEE J. Solid-State Circuits, vol. SC-18, pp. 227-229, April 1983.
[31] D.B. Ribner and M.A. Copeland, "Design Techniques for Cascoded CMOS OpAmps with Improved PSRR and Common-Mode Input Range," IEEE J. Solid-StateCircuits, vol. SC-19, pp. 919-925, December 1984.
[32] M. Milkovic, "Current Gain High-Frequency CMOS Operational Amplifiers," IEEEJ. Solid-State Circuits, vol. SC-20, pp. 845-851, August 1985.
[33] P.R. Gray and R.G. Meyer, "MOS Operational Amplifier Design - A TutorialOverview," IEEE J. Solid-State Circuits, vol. SC-17, pp. 969-982, December 1982.
[34] T-W. Pan and A.A. Abidi, "A Wide-Band CMOS Read Amplifier for MagneticData Storage Systems," IEEE J. Solid-State Circuits, vol. SC-27, pp. 863-873, August1992.
[35] B. Stefanelli, J.-P. Bardyn, A. Kaiser, and D. Billet, "A Very Low-Noise CMOSPreamplifier for Capacitive Sensors," IEEE J. Solid-State Circuits, vol. SC-28, pp. 971-978, September 1993.
[36] T-W. Pan and A.A. Abidi, "A 50-dB Variable Gain Amplifier Using ParasiticBipolar Transistors in CMOS," IEEE J. Solid-State Circuits, vol. SC-24, pp. 951-961,August 1989.
[37] Texas Instruments, Linear Circuits Data Book, vol. 1, sec. 2, pp. 785-811, 1992.
[38] W.T. Holman, J.A. Connelly, J.O. Perez, and C.D. Motchenbacher, "A Low NoiseOperational Amplifier in a 1.2 µm Digital Technology," Proceedings of the 35th MidwestSymposium on Circuits and Systems, pp. 1120-1123, August 1992.
[39] M.G. Degrauwe, O.N. Leuthold, E.A. Vittoz, H.J. Oguey, and A. Descombes,"CMOS Voltage References Using Lateral Bipolar Transistors," IEEE J. Solid-StateCircuits, vol. SC-20, pp. 1151-1157, December 1985.
[40] J. Hauptmann, F. Dielacher, R. Steiner, C.C. Enz, and F. Krummenacher, "A Low-Noise Amplifier with Automatic Gain Control and Anticlipping Control in CMOSTechnology," IEEE J. Solid-State Circuits, vol. SC-27, pp. 974-981, July 1992.
[41] E.S. Yang, Microelectronics Devices. New York: McGraw-Hill, 1988.
[42] E.J. Kennedy, Operational Amplifier Circuits: Theory and Applications. NewYork: Holt, Rinehart and Winston, 1988.
153
[43] W.M. Hines and D.C. Montgomery, Probability and Statistics in Engineering andManagement Science. New York: The Ronald Press Company, 1972.
[44] PSpice, Microsim Corporation, 1992.
[45] M. Gunawan, G.C.M. Meijer, J. Fonderie, and J.H. Huijsing, "A Curvature-Corrected Low-Voltage Bandgap Reference," IEEE J. Solid-State Circuits, vol. SC-28,pp. 667-670, June 1993.
[46] P. Horowitz and W. Hill, The Art of Electronics. Cambridge: CambridgeUniversity Press, 1989.
[47] E. Vittoz and J. Fellrath, "CMOS Analog Integrated Circuits Based on WeakInversion Operation," IEEE J. Solid-State Circuits, vol. SC-12, pp. 224-231, June 1977.
[48] Y.P. Tsividis and R.W. Ulmer, "A CMOS Voltage Reference," IEEE J. Solid-StateCircuits, vol. SC-13, pp. 774-778, December 1978.
[49] E. Vittoz and O. Neyroud, "A Low-Voltage CMOS Bandgap Reference," IEEE J.Solid-State Circuits, vol. SC-14, pp. 573-577, June 1979.
[50] J. Michejda and S.K. Kim, "A Precision CMOS Bandgap Reference," IEEE J.Solid-State Circuits, vol. SC-19, pp. 1014-1021, December 1984.
[51] D.C. Stone, J.E. Schroeder, R.H. Kaplan, and A.R. Smith, "Analog CMOS BuildingBlocks for Custom and Semicustom Applications," IEEE J. Solid-State Circuits , vol. SC-19, pp. 55-61, February 1984.
[52] E.A. Vittoz, "The Design of High-Performance Analog Circuits on Digital CMOSChips," IEEE J. Solid-State Circuits, vol. SC-20, pp. 657-665, June 1985.
[53] G. Nicolline, D. Pancini, and Sergio Pernici, "Simulation-Oriented Noise Model forMOS Devices," IEEE J. Solid-State Circuits, vol. SC-22, pp. 1209-1212, December1987.
[54] G.J. Scott and T.M. Chen, "Addition of Excess Noise in SPICE CircuitSimulations," Proc. IEEE Southeastcon Conf., vol. 1, pp. 186-190, 1987.
[55] R. Rohrer, L. Nagel, R. Meyer, and L. Weber, "Computationally EfficientElectronic-Circuit Noise Calculations," IEEE J. Solid-State Circuits , vol. SC-6, pp. 204-213, August 1971.
[56] R.G. Meyer, L. Nagel, and S.K. Lui, "Computer Simulation of 1/f NoisePerformance of Electronic Circuits," IEEE J. Solid-State Circuits, vol. SC-8, pp. 237-240, June 1973.
[57] K.E. Kujik, "A Precision Reference Voltage Source," IEEE J. Solid-State Circuits,vol. SC-8, pp. 222-226, June 1973.
[58] Texas Instruments, Linear Circuits Data Book, vol. 3, 1989.
154
[59] G.C.M. Meijer and J.B. Verhoeff, "An Integrated Bandgap Reference," IEEE J.Solid-State Circuits, vol. SC-11, pp. 403-406, June 1976.
[60] R. Knapp, "Back-to-Basics Approach Yields Stable References," EDN, pp. 193-198,June 9, 1988.
[61] J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design.New York: Van Nostrand Reinhold, 1983.
[62] D.J. Allstot and W.C. Black, Jr., "Technological Design Considerations forMonolithic MOS Switched-Capacitor Filtering Systems," Proc. IEEE, vol. 71, no. 8, pp.967-986, August 1983.
[63] Harris Semiconductor, Linear ICs for Commercial Applications, 1990.
[64] Maxim Integrated Products, Analog Design Guide #4, 1991.
[65] Burr-Brown Corporation, Integrated Circuits Data Book, vol. 33, 1989.
[66] R. Gomez and A.A. Abidi, "A 50-MHz CMOS Variable Gain Amplifier forMagnetic Data Storage Systems," IEEE J. Solid-State Circuits, vol. SC-27, pp. 935-939,June 1992.
[67] H.W. Singor and C.A.T. Salama, "A Low-Power High-Speed 10-Bit CMOS-Compatible D/A Converter," IEEE Trans. Circuits and Systems, vol. 38, pp. 322-325,March 1991.
155
APPENDIX A
PSPICE LISTING FOR THE ∆VBE SUMMING BANDGAP REFERENCESIMULATION
* Delta-VBE Summing Bandgap Reference
VDD 1 0 DC 5V AC 1V
M1 2 5 1 1 CMOSP W=50.4U L=3.6U M=3M2 5 5 1 1 CMOSP W=50.4U L=3.6U M=3M1A 4 6 2 1 CMOSP W=50.4U L=3.6U M=3M2A 6 6 5 1 CMOSP W=50.4U L=3.6U M=3M5 6 4 8 0 CMOSN W=50.4U L=3.6U M=10M4 4 4 7 0 CMOSN W=50.4U L=3.6U M=10R1B 8 9 RTCEXT 784D1B 7 9993 DMOD1D2B 9 9993 DMOD2
M3 3 5 1 1 CMOSP W=50.4U L=3.6U M=4M3A 10 6 3 1 CMOSP W=50.4U L=3.6U M=4XD1 9994 9994 10 PNPLAT1
RG1 9990 0 RTCM 1.581RG2 9991 9990 RTCM 9.473RG3 9991 9992 RTCM 5.301RG4 9993 9992 RTCM 1.446RG5 9994 9992 RTCM 3.6
XDVBE1 10 11 5 6 1 9991 DELTAVBE1XDVBE2 11 12 5 6 1 9991 DELTAVBE2XDVBE3 12 13 5 6 1 9990 DELTAVBE3
.MODEL RTCP RES (TC1=.000834)
.MODEL RTCM RES (TC1=.0001)
.MODEL RTCEXT RES (TC1=-.000016)
.SUBCKT DELTAVBE1 104 106 100 101 99 98* 104 = input, 106 = output, 100, 101 = pfetbias, 99 = Vdd, 98 = VssMP1 102 100 99 99 CMOSP W=50.4u L=3.6u M=40MP2 103 101 102 99 CMOSP W=50.4u L=3.6u M=40XA1 104 105 1051 99 98 DBILFARP1 105 1050 RTCM 11.97RP2 105 1051 RTCM 40.63XD2 1050 1050 103 PNPLAT2XD3 106 106 103 PNPLAT3XR1 106 98 POLYRES PARAMS: RES=13K.ENDS
.SUBCKT DELTAVBE2 104 106 100 101 99 98
156
* 104 = input, 106 = output, 100, 101 = pfetbias, 99 = Vdd, 98 = VssMP1 102 100 99 99 CMOSP W=50.4u L=3.6u M=40MP2 103 101 102 99 CMOSP W=50.4u L=3.6u M=40XA1 104 105 1051 99 98 DBILFARP1 105 1050 RTCM 9.58RP2 105 1051 RTCM 22.74XD2 1050 1050 103 PNPLAT2XD3 106 106 103 PNPLAT3XR1 106 98 POLYRES PARAMS: RES=13K.ENDS
.SUBCKT DELTAVBE3 104 106 100 101 99 98* 104 = input, 106 = output, 100, 101 = pfetbias, 99 = Vdd, 98 = VssMP1 102 100 99 99 CMOSP W=50.4u L=3.6u M=40MP2 103 101 102 99 CMOSP W=50.4u L=3.6u M=40XA1 104 105 1051 99 98 DBILFARP1 105 1050 RTCM 4.25RP2 105 1051 RTCM 25.98XD2 1050 1050 103 PNPLAT2XD3 106 106 103 PNPLAT3XR1 106 98 POLYRES PARAMS: RES=13K.ENDS
.SUBCKT POLYRES 1000 1005 PARAMS: WIDTH=1.2 RES=1K RESVAR=1.24C0 1000 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150)R1 1000 1001 RTCP RESVAR*RES/5C1 1001 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150)R2 1001 1002 RTCP RESVAR*RES/5C2 1002 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150)R3 1002 1003 RTCP RESVAR*RES/5C3 1003 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150)R4 1003 1004 RTCP RESVAR*RES/5C4 1004 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150)R5 1004 1005 RTCP RESVAR*RES/5C5 1005 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150).ENDS
.SUBCKT DBILFA 2 1 77 99 98*BiCMOS Low-Frequency Amplifier*2 = +input, 1 = -input, 77= output, 99=PS+, 98=PS-
*Differential Amplifer
X1 3 1001 5 PNPLAT1X2 98 1 1001 PNPLAT0
X4 4 2001 5 PNPLAT1X3 98 2 2001 PNPLAT0
M3A 1001 6 99 99 CMOSP W=48.6U L=16.2U M=6 AS=128.3p AD=140p PS=75.2u Pd=82.1uM3B 2001 6 99 99 CMOSP W=48.6U L=16.2U M=6 AS=128.3p AD=140p PS=75.2u Pd=82.1u
M3 5 6 99 99 CMOSP W=64.8U L=3.6U M=20 AS=128.3p AD=140p PS=75.2u Pd=82.1uM5 4 3 98 98 CMOSN W=72U L=18U M=8 AS=77.8p AD=51.9p PS=48.6u Pd=32.4uM2 3 3 98 98 CMOSN W=72U L=18U M=8 AS=77.8p AD=51.9p PS=48.6u Pd=32.4u
157
*Output StageM6 7 6 99 99 CMOSP W=42.6U L=3.6U M=12 AS=115p AD=76.7p PS=69.3u PD=46.2uM7 7 4 98 98 CMOSN W=43.2U L=3.6U M=3 AS=103.7p AD=103.7p PS=62.4u PD=62.4uM8 7 7 98 98 CMOSN W=43.8U L=6.6U AS=82.1p AD=157.7p PS=49.2u PD=94.8uM9 8 7 98 98 CMOSN W=45.6U L=3.6U AS=82.1p AD=164.2p PS=49.2u PD=98.4uM10 8 8 99 99 CMOSP W=40.8U L=3.6U M=2 AS=146.9p AD=73.5p PS=88.8u PD=44.4uM11 77 8 99 99 CMOSP W=45U L=1.2U M=6 AS=108p AD=64.8p PS=81u PD=48.6uM12 77 4 98 98 CMOSN W=38.4U L=1.2U M=10 AS=103.7p AD=69.1p PS=61.9u PD=41.3u
Cc 77 44 22pXRz 44 4 POLYRES PARAMS: RES=576 WIDTH=2.4*Rtemp 4 98 1E6
*Bias CircuitM13 6 12 11 98 CMOSN W=29.4U L=3.6U AS=83.2p AD=166.3p PS=49.8u PD=99.6uM16 12 12 13 98 CMOSN W=29.4U L=3.6U AS=83.2p AD=166.3p PS=49.8u PD=99.6uM14 6 6 99 99 CMOSP W=46.8U L=3.6U AS=168.5p AD=84.2p PS=108u PD=54uM15 12 6 99 99 CMOSP W=46.8U L=3.6U AS=168.5p AD=84.2p PS=108u PD=54u
XR13 11 98 POLYRES PARAMS: RES=34KD1 13 98 DMOD3Cb 6 99 0.6pF.ENDS
.SUBCKT PNPLAT0 1 2 3* 1 = Lateral Collector 2 = Base 3 = EmitterVSENSE 3 4 0Q1 1 2 4 0 QLAT 4FVERT 1 0 VSENSE 0.33.ENDS
.SUBCKT PNPLAT1 1 2 3* 1 = Lateral Collector 2 = Base 3 = EmitterVSENSE 3 4 0Q1 1 2 4 0 QLAT 40FVERT 1 0 VSENSE 0.33.ENDS
.SUBCKT PNPLAT2 1 2 3* 1 = Lateral Collector 2 = Base 3 = EmitterVSENSE 3 4 0Q1 1 2 4 0 QLAT 40FVERT 1 0 VSENSE 0.45.ENDS
.SUBCKT PNPLAT3 1 2 3* 1 = Lateral Collector 2 = Base 3 = EmitterVSENSE 3 4 0Q1 1 2 4 0 QLAT 400FVERT 1 0 VSENSE 0.33.ENDS
.model QLAT LPNP(Is=6e-17 Xti=4 Eg=1.11 Vaf=16 Bf=150 Ise=0+ Ne=1.5 Ikf=14.68u Xtb=1.5 Br=1 Isc=0 Nc=2 Ikr=0 Rc=4000
158
+ Cjc=1f Mjc=.3333 Vjc=.75 Fc=.5 Cje=1f Mje=.3333 Vje=.75+ Tr=1n Tf=1.807n Itf=1 Xtf=0 Vtf=10 Rb=6000 Re=40)
.model QLAT2 LPNP(Is=6e-17 Xti=4 Eg=1.11 Vaf=18 Bf=200 Ise=0+ Ne=1.5 Ikf=14.68u Xtb=1.5 Br=1 Isc=0 Nc=2 Ikr=0 Rc=0+ Cjc=1f Mjc=.3333 Vjc=.75 Fc=.5 Cje=1f Mje=.3333 Vje=.75 Tr=1n+ Tf=1.807n Itf=1 Xtf=0 Vtf=10 Rb=6000)
.subckt diode40 1 2D1 1 2 mindiode 40.ends
.subckt diode400 1 2D1 1 2 mindiode 400.ends
.MODEL DMOD1 D(IS=1E-17 N=1)
.MODEL DMOD2 D(IS=1e-16 N=1)
.MODEL DMOD3 D(IS=30.56E-15 N=1)
.MODEL DMOD4 D(IS=1E-15 N=1.0)
.MODEL CMOSN NMOS LEVEL=3 TOX=2.28E-8 XJ=0.2U TPG=1+ VTO=0.7834 DELTA=0.93 LD=2.069e-7 KP=9.3977e-5+ UO=620.5 THETA=6.563e-2 RSH=5.455E1 GAMMA=0.5781 NSUB=2.309E16+ NFS=1.98e12 VMAX=1.758E5 ETA=3.489E-2 KAPPA=6.558E-2+ CGDO=4.7004E-10 CGSO=4.7004E-10 CGBO=3.8734E-10+ CJ=3.1958e-4 MJ=1.0425 CJSW=1.394E-10 MJSW=0.125195 PB=0.8 KF=30E-30
.MODEL CMOSP PMOS LEVEL=3 TOX=2.28E-8 XJ=0.2U TPG=-1+ VTO=-0.8792 DELTA=2.14 LD=6.049e-8 KP=28.428U+ UO=187.7 THETA=1.132E-1 RSH=8.909E1 GAMMA=0.3634 NSUB=9.124E15+ NFS=3.46E12 VMAX=3.217E5 ETA=1.294E-1 KAPPA=9.419+ CGDO=1.3742E-10 CGSO=1.3742E-10 CGBO=3.5957E-10+ CJ=4.6804E-4 MJ=0.5013 CJSW=1.5136E-10 MJSW=0.191565 PB=0.85 KF=6E-31
.OPTIONS itl1=1000 itl2=1000 itl4=1000 itl5=0
.NODESET V(1)= 5.0000 V(2)= 3.7648 V(3)= 3.7627 V(4)= 2.0941+V(5)= 3.7652 V(6)= 2.3596 V(7)= .9414 V(8)= .9415+V(9)= .8951 V(10)= .8396 V(11)= .9503 V(12)= 1.0571+V(13)= 1.1577 V(9990)= .0173 V(9991)= .0864 V(9992)= .0874+V(9993)= .0875 V(9994)= .0875 V(XD1.4)= .8396 V(XDVBE1.102)= 3.7641+V(XDVBE1.103)= 1.6550 V(XDVBE1.105)= .8395+V(XDVBE2.102)= 3.7642 V(XDVBE2.103)= 1.7642+V(XDVBE2.105)= .9502 V(XDVBE3.102)= 3.7644+V(XDVBE3.103)= 1.8681 V(XDVBE3.105)= 1.0570+V(XDVBE1.1050)= .8441 V(XDVBE1.1051)= .8237+V(XDVBE2.1050)= .9539 V(XDVBE2.1051)= .9415+V(XDVBE3.1050)= 1.0586 V(XDVBE3.1051)= 1.0474+V(XDVBE1.XA1.3)= 1.2522 V(XDVBE1.XA1.4)= 1.2007+V(XDVBE1.XA1.5)= 2.3997 V(XDVBE1.XA1.6)= 3.7681+V(XDVBE1.XA1.7)= 1.2882 V(XDVBE1.XA1.8)= 3.5560+V(XDVBE1.XD2.4)= 1.6550 V(XDVBE1.XD3.4)= 1.6550+V(XDVBE2.XA1.3)= 1.2520 V(XDVBE2.XA1.4)= 1.1983
159
+V(XDVBE2.XA1.5)= 2.5100 V(XDVBE2.XA1.6)= 3.7681+V(XDVBE2.XA1.7)= 1.2987 V(XDVBE2.XA1.8)= 3.5418+V(XDVBE2.XD2.4)= 1.7642 V(XDVBE2.XD3.4)= 1.7642+V(XDVBE3.XA1.3)= 1.1827 V(XDVBE3.XA1.4)= 1.1261+V(XDVBE3.XA1.5)= 2.6163 V(XDVBE3.XA1.6)= 3.7681+V(XDVBE3.XA1.7)= 1.2428 V(XDVBE3.XA1.8)= 3.5239+V(XDVBE3.XD2.4)= 1.8681 V(XDVBE3.XD3.4)= 1.8681+V(XDVBE1.XA1.11)= .7988 V(XDVBE1.XA1.12)= 2.0086+V(XDVBE1.XA1.13)= .7961 V(XDVBE1.XA1.44)= 1.2007+V(XDVBE2.XA1.11)= .7988 V(XDVBE2.XA1.12)= 2.0086+V(XDVBE2.XA1.13)= .7961 V(XDVBE2.XA1.44)= 1.1983+V(XDVBE3.XA1.11)= .7298 V(XDVBE3.XA1.12)= 1.9396+V(XDVBE3.XA1.13)= .7270 V(XDVBE3.XA1.44)= 1.1261+V(XDVBE1.XA1.1001)= 1.6199 V(XDVBE1.XA1.2001)= 1.6200+V(XDVBE1.XA1.X1.4)= 2.3997 V(XDVBE1.XA1.X2.4)= 1.6199+V(XDVBE1.XA1.X3.4)= 1.6200 V(XDVBE1.XA1.X4.4)= 2.3997+V(XDVBE1.XR1.1001)= .7775 V(XDVBE1.XR1.1002)= .6048+V(XDVBE1.XR1.1003)= .4320 V(XDVBE1.XR1.1004)= .2592+V(XDVBE2.XA1.1001)= 1.7304 V(XDVBE2.XA1.2001)= 1.7305+V(XDVBE2.XA1.X1.4)= 2.5100 V(XDVBE2.XA1.X2.4)= 1.7304+V(XDVBE2.XA1.X3.4)= 1.7305 V(XDVBE2.XA1.X4.4)= 2.5100+V(XDVBE2.XR1.1001)= .8630 V(XDVBE2.XR1.1002)= .6689+V(XDVBE2.XR1.1003)= .4747 V(XDVBE2.XR1.1004)= .2806+V(XDVBE3.XA1.1001)= 1.8370 V(XDVBE3.XA1.2001)= 1.8371+V(XDVBE3.XA1.X1.4)= 2.6163 V(XDVBE3.XA1.X2.4)= 1.8370+V(XDVBE3.XA1.X3.4)= 1.8371 V(XDVBE3.XA1.X4.4)= 2.6163+V(XDVBE3.XR1.1001)= .9296 V(XDVBE3.XR1.1002)= .7015+V(XDVBE3.XR1.1003)= .4735 V(XDVBE3.XR1.1004)= .2454+V(XDVBE1.XA1.XRz.1001)= 1.2007 V(XDVBE1.XA1.XRz.1002)= 1.2007+V(XDVBE1.XA1.XRz.1003)= 1.2007 V(XDVBE1.XA1.XRz.1004)= 1.2007+V(XDVBE2.XA1.XRz.1001)= 1.1983 V(XDVBE2.XA1.XRz.1002)= 1.1983+V(XDVBE2.XA1.XRz.1003)= 1.1983 V(XDVBE2.XA1.XRz.1004)= 1.1983+V(XDVBE3.XA1.XRz.1001)= 1.1261 V(XDVBE3.XA1.XRz.1002)= 1.1261+V(XDVBE3.XA1.XRz.1003)= 1.1261 V(XDVBE3.XA1.XRz.1004)= 1.1261+V(XDVBE1.XA1.XR13.1001)= .6563 V(XDVBE1.XA1.XR13.1002)= .5138+V(XDVBE1.XA1.XR13.1003)= .3714 V(XDVBE1.XA1.XR13.1004)= .2289+V(XDVBE2.XA1.XR13.1001)= .6563 V(XDVBE2.XA1.XR13.1002)= .5138+V(XDVBE2.XA1.XR13.1003)= .3714 V(XDVBE2.XA1.XR13.1004)= .2289+V(XDVBE3.XA1.XR13.1001)= .5873 V(XDVBE3.XA1.XR13.1002)= .4448+V(XDVBE3.XA1.XR13.1003)= .3023 V(XDVBE3.XA1.XR13.1004)= .1598
.DC TEMP LIST -40 -35 -25 -15 -5 0 5 15 25 35 45 55 65 70 75 85
.AC DEC 10 1 100MEG
.NOISE V(13) VDD 10
.PRINT NOISE ONOISE INOISE
.PROBE
160
APPENDIX B
PSPICE LISTING FOR THE IMPROVED ∆VBE SUMMING BANDGAPREFERENCE SIMULATION
* Improved Delta-VBE Summing Bandgap Reference
VDD 1 0 DC 5V AC 1V
M3X 303 705 1 1 CMOSP W=50.4U L=3.6U M=3M3AX 10 706 303 1 CMOSP W=50.4U L=3.6U M=3XD1 0 0 10 PNPLAT1
XBIAS3 708 705 706 1 0 BIASCKTXR1BY 708 0 POLYRES PARAMS: RES=8KM6X 401 705 1 1 CMOSP W=50.4U L=3.6U M=4M6AX 402 706 401 1 CMOSP W=50.4U L=3.6U M=4M7X 402 402 0 0 CMOSN W=50.4U L=7.2U M=8
XBIAS4 508 505 506 1 0 BIASCKTXR3B 508 509 POLYRES PARAMS: RES=700D2BX 509 0 DMOD2M6 201 505 1 1 CMOSP W=50.4U L=3.6U M=4M6A 202 506 201 1 CMOSP W=50.4U L=3.6U M=4M7 202 202 0 0 CMOSN W=50.4U L=7.2U M=8
XOABIAS 906 1 0 OABIAS
XDVBE1 10 11 402 101 906 1 0 DELTAVBEXDVBE2 11 12 202 102 906 1 0 DELTAVBEXDVBE3 12 13 202 103 906 1 0 DELTAVBEXDVBE4 13 14 202 104 906 1 0 DELTAVBE*XDVBE5 14 15 202 105 906 1 0 DELTAVBE
.SUBCKT BIASCKT 8 5 6 99 98* 8=Bias Set, 5=Top PFET out, 6=Bottom PFET out, 99=Vdd, 98=VssM1 2 5 99 99 CMOSP W=50.4U L=3.6U M=3M2 5 5 99 99 CMOSP W=50.4U L=3.6U M=3M1A 4 6 2 99 CMOSP W=50.4U L=3.6U M=3M2A 6 6 5 99 CMOSP W=50.4U L=3.6U M=3M5 6 4 8 98 CMOSN W=50.4U L=7.2U M=8M4 4 4 7 98 CMOSN W=50.4U L=7.2U M=8D1B 7 0 DMOD1.ENDS
.MODEL RTCP RES (TC1=.000834)
.MODEL RTCM RES (TC1=.0001)
.MODEL RTCEXT RES (TC1=-.000016)
.SUBCKT DELTAVBE 104 106 100 101 6 99 98
161
* 104 = input, 106 = output, 100=nfetbias, 101=buffer out,* 6=Op Amp Bias 99=Vdd, 98=VssMN1 102 100 98 98 CMOSN W=50.4U L=7.2U M=8XA1 104 102 101 6 99 98 DBILNAXD2 102 102 101 PNPLAT0XD3 106 106 101 PNPLAT1XR1 106 98 POLYRES PARAMS: RES=33K.ENDS
.SUBCKT POLYRES 1000 1005 PARAMS: WIDTH=1.2 RES=1K RESVAR=1.24C0 1000 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150)R1 1000 1001 RTCP RESVAR*RES/5C1 1001 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150)R2 1001 1002 RTCP RESVAR*RES/5C2 1002 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150)R3 1002 1003 RTCP RESVAR*RES/5C3 1003 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150)R4 1003 1004 RTCP RESVAR*RES/5C4 1004 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150)R5 1004 1005 RTCP RESVAR*RES/5C5 1005 0 (WIDTH*0.11E-15*RES/150)+(WIDTH*WIDTH*0.065E-15*RES/150).ENDS
.SUBCKT DBILNA 2 1 77 6 99 98*BiCMOS Low-Frequency Amplifier*2 = +input, 1 = -input, 77= output, 6=bias, 99=PS+, 98=PS-*Differential Amplifer
X1 3 1001 5 PNPLAT1X2 98 1 1001 PNPLAT1
X4 4 2001 5 PNPLAT1X3 98 2 2001 PNPLAT1
M3A 1001 6 99 99 CMOSP W=48.6U L=16.2U M=6 AS=128.3p AD=140p+ PS=75.2u Pd=82.1uM3B 2001 6 99 99 CMOSP W=48.6U L=16.2U M=6 AS=128.3p AD=140p+ PS=75.2u Pd=82.1u
*M3A 1001 6 99 99 CMOSP W=32.4U L=5.4U M=3 AS=128.3p AD=140p*+ PS=75.2u Pd=82.1u*M3B 2001 6 99 99 CMOSP W=32.4U L=5.4U M=3 AS=128.3p AD=140p*+ PS=75.2u Pd=82.1u
M3 5 6 99 99 CMOSP W=64.8U L=3.6U M=20 AS=128.3p AD=140p+ PS=75.2u Pd=82.1uM5 4 3 98 98 CMOSN W=72U L=18U M=8 AS=77.8p AD=51.9p+ PS=48.6u Pd=32.4uM2 3 3 98 98 CMOSN W=72U L=18U M=8 AS=77.8p AD=51.9p+ PS=48.6u Pd=32.4u
*Output StageM6 7 6 99 99 CMOSP W=42.6U L=3.6U M=12 AS=115p AD=76.7p+ PS=69.3u PD=46.2uM7 7 4 98 98 CMOSN W=43.2U L=3.6U M=3 AS=103.7p AD=103.7p
162
+ PS=62.4u PD=62.4uM12 99 7 77 98 CMOSN W=38.4U L=1.2U M=20 AS=103.7p AD=69.1p+ PS=61.9u PD=41.3u
*M8 7 7 98 98 CMOSN W=43.8U L=6.6U AS=82.1p AD=157.7p*+ PS=49.2u PD=94.8u*M9 8 7 98 98 CMOSN W=45.6U L=3.6U AS=82.1p AD=164.2p*+ PS=49.2u PD=98.4u*M10 8 8 99 99 CMOSP W=40.8U L=3.6U M=2 AS=146.9p AD=73.5p*+ PS=88.8u PD=44.4u*M11 77 8 99 99 CMOSP W=45U L=1.2U M=6 AS=108p AD=64.8p*+ PS=81u PD=48.6u*M12 77 4 98 98 CMOSN W=38.4U L=1.2U M=10 AS=103.7p AD=69.1p*+ PS=61.9u PD=41.3u
Cc 77 44 22pXRz 44 4 POLYRES PARAMS: RES=576 WIDTH=2.4*Rtemp 4 98 1E6
.ENDS
.SUBCKT OABIAS 6 99 98*Op Amp Bias Circuit* 6 = Output, 99 = Vdd, 98 = VssM13 6 12 11 98 CMOSN W=29.4U L=3.6U AS=83.2p AD=166.3p PS=49.8u+ PD=99.6uM16 12 12 13 98 CMOSN W=29.4U L=3.6U AS=83.2p AD=166.3p PS=49.8u+ PD=99.6uM14 6 6 99 99 CMOSP W=46.8U L=3.6U M=2 AS=168.5p AD=84.2p PS=108u+ PD=54uM15 12 6 99 99 CMOSP W=46.8U L=3.6U M=2 AS=168.5p AD=84.2p PS=108u+ PD=54uXR13 11 98 POLYRES PARAMS: RES=34KD1 13 98 DMOD3Cb 6 99 0.6pF.ENDS
.SUBCKT PNPLAT0 1 2 3* 1 = Lateral Collector 2 = Base 3 = EmitterVSENSE 3 4 0Q1 1 2 4 0 QLAT 4FVERT 1 0 VSENSE 0.33.ENDS
.SUBCKT PNPLAT1 1 2 3* 1 = Lateral Collector 2 = Base 3 = EmitterVSENSE 3 4 0Q1 1 2 4 0 QLAT 40FVERT 1 0 VSENSE 0.33.ENDS
.SUBCKT PNPLAT2 1 2 3* 1 = Lateral Collector 2 = Base 3 = Emitter
163
VSENSE 3 4 0Q1 1 2 4 0 QLAT 40FVERT 1 0 VSENSE 0.45.ENDS
.SUBCKT PNPLAT3 1 2 3* 1 = Lateral Collector 2 = Base 3 = EmitterVSENSE 3 4 0Q1 1 2 4 0 QLAT 400FVERT 1 0 VSENSE 0.33.ENDS
.SUBCKT PNPLAT1X 1 2 3* 1 = Lateral Collector 2 = Base 3 = EmitterVSENSE 3 4 0Q1 1 2 4 0 QLAT2 120FVERT 4 0 VSENSE 0.33.ENDS
.model QLAT LPNP(Is=6e-17 Xti=4 Eg=1.11 Vaf=16 Bf=150 Ise=0+ Ne=1.5 Ikf=14.68u Xtb=1.5 Br=1 Isc=0 Nc=2 Ikr=0 Rc=4000+ Cjc=1f Mjc=.3333 Vjc=.75 Fc=.5 Cje=1f Mje=.3333 Vje=.75+ Tr=1n Tf=1.807n Itf=1 Xtf=0 Vtf=10 Rb=6000 Re=40)
.model QLAT2 LPNP(Is=6e-17 Xti=4 Eg=1.11 Vaf=18 Bf=200 Ise=0+ Ne=1.5 Ikf=14.68u Xtb=1.5 Br=1 Isc=0 Nc=2 Ikr=0 Rc=0+ Cjc=1f Mjc=.3333 Vjc=.75 Fc=.5 Cje=1f Mje=.3333 Vje=.75 Tr=1n+ Tf=1.807n Itf=1 Xtf=0 Vtf=10 Rb=6000)
.model QVERT PNP(Is=4.5E-15 Vaf=18 Bf=100 Ikf=1u Rb=0)
.subckt diode40 1 2D1 1 2 mindiode 40.ends
.subckt diode400 1 2D1 1 2 mindiode 400.ends
.MODEL DMOD1 D(IS=1E-17 N=1)
.MODEL DMOD2 D(IS=1e-16 N=1)
.MODEL DMOD3 D(IS=30.56E-15 N=1)
.MODEL DMOD4 D(IS=1E-15 N=1.0)
.MODEL CMOSN NMOS LEVEL=3 TOX=2.28E-8 XJ=0.2U TPG=1+ VTO=0.7834 DELTA=0.93 LD=2.069e-7 KP=9.3977e-5+ UO=620.5 THETA=6.563e-2 RSH=5.455E1 GAMMA=0.5781 NSUB=2.309E16+ NFS=1.98e12 VMAX=1.758E5 ETA=3.489E-2 KAPPA=6.558E-2+ CGDO=4.7004E-10 CGSO=4.7004E-10 CGBO=3.8734E-10+ CJ=3.1958e-4 MJ=1.0425 CJSW=1.394E-10 MJSW=0.125195 PB=0.8+ KF=30E-30
.MODEL CMOSP PMOS LEVEL=3 TOX=2.28E-8 XJ=0.2U TPG=-1+ VTO=-0.8792 DELTA=2.14 LD=6.049e-8 KP=28.428U
164
+ UO=187.7 THETA=1.132E-1 RSH=8.909E1 GAMMA=0.3634 NSUB=9.124E15+ NFS=3.46E12 VMAX=3.217E5 ETA=1.294E-1 KAPPA=9.419+ CGDO=1.3742E-10 CGSO=1.3742E-10 CGBO=3.5957E-10+ CJ=4.6804E-4 MJ=0.5013 CJSW=1.5136E-10 MJSW=0.191565 PB=0.85+ KF=6E-31
.NODESET V(1)=5.0000 V(10)=.7521 V(11)=.8747 V(12)=.9629+V(13)=1.0492 V(14)=1.1337 V(101)=1.6033 V(102)=1.6936+V(103)=1.7818 V(104)=1.8681 V(201)=3.7694 V(202)=.9925+V(303)=3.6887 V(401)=3.6892 V(402)=1.0517 V(505)=3.7716+V(506)=2.3726 V(508)=.8239 V(509)=.7766 V(705)=3.6912+V(706)=2.2042 V(708)=.8341 V(906)=3.7818 V(XD1.4)=.7521+V(XBIAS3.2)=3.6909 V(XBIAS3.4)=2.0221+V(XBIAS3.7)=.8341 V(XBIAS4.2)=3.7710+V(XBIAS4.4)=1.9829 V(XBIAS4.7)=.8239+V(XR3B.1001)=.8145 V(XR3B.1002)=.8050+V(XR3B.1003)=.7955 V(XR3B.1004)=.7861+V(XDVBE1.102)=.7520 V(XDVBE2.102)=.8747+V(XDVBE3.102)=.9629 V(XDVBE4.102)=1.0492+V(XOABIAS.11)=.6596 V(XOABIAS.12)=1.8479+V(XOABIAS.13)=.6567 V(XR1BY.1001)=.6673+V(XR1BY.1002)=.5005 V(XR1BY.1003)=.3337+V(XR1BY.1004)=.1668 V(XDVBE1.XA1.3)=1.1527+V(XDVBE1.XA1.4)=1.1347 V(XDVBE1.XA1.5)=2.2457+V(XDVBE1.XA1.7)=2.5977 V(XDVBE1.XD2.4)=1.6033+V(XDVBE1.XD3.4)=1.6033 V(XDVBE2.XA1.3)=1.1525+V(XDVBE2.XA1.4)=1.1344 V(XDVBE2.XA1.5)=2.3679+V(XDVBE2.XA1.7)=2.6804 V(XDVBE2.XD2.4)=1.6936+V(XDVBE2.XD3.4)=1.6936 V(XDVBE3.XA1.3)=1.1523+V(XDVBE3.XA1.4)=1.1342 V(XDVBE3.XA1.5)=2.4558+V(XDVBE3.XA1.7)=2.7829 V(XDVBE3.XD2.4)=1.7818+V(XDVBE3.XD3.4)=1.7818 V(XDVBE4.XA1.3)=1.1522+V(XDVBE4.XA1.4)=1.1339 V(XDVBE4.XA1.5)=2.5418+V(XDVBE4.XA1.7)=2.8831 V(XDVBE4.XD2.4)=1.8681+V(XDVBE4.XD3.4)=1.8681 V(XDVBE1.XA1.44)=1.1347+V(XDVBE2.XA1.44)=1.1344 V(XDVBE3.XA1.44)=1.1342+V(XDVBE4.XA1.44)=1.1339 V(XDVBE1.XA1.1001)=1.4714+V(XDVBE1.XA1.2001)=1.4714 V(XDVBE1.XA1.X1.4)=2.2457+V(XDVBE1.XA1.X2.4)=1.4714 V(XDVBE1.XA1.X3.4)=1.4714+V(XDVBE1.XA1.X4.4)=2.2457 V(XDVBE1.XR1.1001)=.6998+V(XDVBE1.XR1.1002)=.5248 V(XDVBE1.XR1.1003)=.3499+V(XDVBE1.XR1.1004)=.1749 V(XDVBE2.XA1.1001)=1.5939+V(XDVBE2.XA1.2001)=1.5939 V(XDVBE2.XA1.X1.4)=2.3679+V(XDVBE2.XA1.X2.4)=1.5939 V(XDVBE2.XA1.X3.4)=1.5939+V(XDVBE2.XA1.X4.4)=2.3679 V(XDVBE2.XR1.1001)=.7703+V(XDVBE2.XR1.1002)=.5778 V(XDVBE2.XR1.1003)=.3852+V(XDVBE2.XR1.1004)=.1926 V(XDVBE3.XA1.1001)=1.6819+V(XDVBE3.XA1.2001)=1.6819 V(XDVBE3.XA1.X1.4)=2.4558+V(XDVBE3.XA1.X2.4)=1.6819 V(XDVBE3.XA1.X3.4)=1.6819+V(XDVBE3.XA1.X4.4)=2.4558 V(XDVBE3.XR1.1001)=.8394+V(XDVBE3.XR1.1002)=.6295 V(XDVBE3.XR1.1003)=.4197+V(XDVBE3.XR1.1004)=.2098 V(XDVBE4.XA1.1001)=1.7681+V(XDVBE4.XA1.2001)=1.7681 V(XDVBE4.XA1.X1.4)=2.5418+V(XDVBE4.XA1.X2.4)=1.7681 V(XDVBE4.XA1.X3.4)=1.7681+V(XDVBE4.XA1.X4.4)=2.5418 V(XDVBE4.XR1.1001)=.9069
165
+V(XDVBE4.XR1.1002)=.6802 V(XDVBE4.XR1.1003)=.4535+V(XDVBE4.XR1.1004)=.2267 V(XOABIAS.XR13.1001)=.5277+V(XOABIAS.XR13.1002)=.3957 V(XOABIAS.XR13.1003)=.2638+V(XOABIAS.XR13.1004)=.1319 V(XDVBE1.XA1.XRz.1001)=1.1347+V(XDVBE1.XA1.XRz.1002)=1.1347 V(XDVBE1.XA1.XRz.1003)=1.1347+V(XDVBE1.XA1.XRz.1004)=1.1347 V(XDVBE2.XA1.XRz.1001)=1.1344+V(XDVBE2.XA1.XRz.1002)=1.1344 V(XDVBE2.XA1.XRz.1003)=1.1344+V(XDVBE2.XA1.XRz.1004)=1.1344 V(XDVBE3.XA1.XRz.1001)=1.1342+V(XDVBE3.XA1.XRz.1002)=1.1342 V(XDVBE3.XA1.XRz.1003)=1.1342+V(XDVBE3.XA1.XRz.1004)=1.1342 V(XDVBE4.XA1.XRz.1001)=1.1339+V(XDVBE4.XA1.XRz.1002)=1.1339 V(XDVBE4.XA1.XRz.1003)=1.1339+V(XDVBE4.XA1.XRz.1004)=1.1339
.OPTIONS itl1=1000 itl2=1000 itl4=1000 itl5=0
.DC TEMP LIST -40 -35 -25 -15 -5 0 5 15 25 35 45 55 65 70 75 85
.AC DEC 10 1 100MEG
.NOISE V(14) VDD 10
.PRINT NOISE ONOISE INOISE
.PROBE
166
VITA
William Timothy Holman was born in Nashville, Tennessee, on September 4,
1958. In 1976 he began his studies in the field of Electrical Engineering at the Georgia
Institute of Technology in Atlanta, Georgia. He left school before receiving his
bachelor's degree and worked for several years, after which he transferred to the
University of Tennessee at Knoxville where he was awarded his B.S.E.E. with highest
honors in 1986 and was first exposed to the field of analog microelectronics. In 1987
Tim was admitted to the Electrical Engineering graduate program at the Georgia Institute
of Technology, where he received his M.S.E.E. in 1988. In 1989 he joined the IBM
Corporation in Essex Junction, Vermont as an associate engineer, but returned to Georgia
Tech in 1990 to pursue research in low noise CMOS analog circuit design. He received
the degree of Doctor of Philosophy in Electrical Engineering from the Georgia Tech
School of Electrical and Computer Engineering in 1994.