a low-dropout regulator with psrr enhancement through feed

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Article

A Low-Dropout Regulator with PSRR Enhancementthrough Feed-Forward Ripple Cancellation Techniquein 65 nm CMOS Process

Young-Joe Choe 1, Hyohyun Nam 1 and Jung-Dong Park 2,*1 Division of Electronics and Electrical Engineering, Dongguk University, Seoul 04620, Korea;

[email protected] (Y.-J.C.); [email protected] (H.N.)2 Jung-Dong Park, Division of Electrical and Electronics Engineering, Dongguk University, Seoul 04620, Korea* Correspondence: [email protected]; Tel.: +82-2-2260-3346

Received: 31 December 2019; Accepted: 10 January 2020; Published: 12 January 2020

Abstract: In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejectionratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOStechnology. This technique significantly improves the PSRR over a wide range of frequencies,compared to a conventional LDO regulator. The LDO regulator provides 35–76.8 dB of PSRR in therange of 1 MHz–1 GHz, which shows up to 30 dB of PSRR improvement, compared with that of theconventional LDO regulator. The implemented LDO regulator has a dropout voltage of 0.22 V and amaximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1–1.3V of the input voltage. The load regulation is 2.3 mV/mA while the line regulation is 0.05 V/V. Thecircuit consumes 385 µA with an input voltage of 1.2 V. The total area without pads is 0.092 mm2.

Keywords: CMOS; LDO; low dropout; power supply rejection ratio; regulation

1. Introduction

In the power management system, the demand for integrating the whole power managementintegrated circuit (PMIC) into a single chip has significantly increased [1]. By integrating the powermanagement system into a chip, the system cost is reduced significantly, since the external powermanagement blocks can be dramatically simplified. The main reason for using a low-dropout (LDO)regulator is to reject the ripples from the voltage source, which means power supply rejection (PSR) isvital. For a conventional LDO regulator, it is necessary to have a high DC gain and bandwidth of theerror amplifier [2]. For the voltage regulators, the bandwidth of the circuit should be improved andmust provide a higher power supply rejection (PSR) according to the surrounding blocks. ConventionalLDO regulators provide poor PSR at relatively high frequencies even around 300 kHz.

Various techniques have been introduced to improve PSR. Using an RC filter at the output of theLDO regulator or using two regulators helps to improve the PSR [3]. This technique can improve thePSR, but it also increases the dropout voltage because of the series resistor or the second regulator.Another technique is using a charge pump and an NMOS pass transistor [4]. This method utilizes anNMOS pass transistor which requires that the bias of the NMOS should be higher than the supplyvoltage. [4] implemented a charge pump in order to provide a higher bias which is an independentbias for the regulator. However, this technique dissipates more DC power and increases the complexityof the circuit.

In this paper, we introduce an LDO regulator which achieves a significantly improved PSR byutilizing the feed-forward ripple cancellation technique. The purpose of this technique is to duplicatethe input ripples to the gate of the pass transistor so that it will cancel out the input ripples to increase

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the power supply rejection significantly. The proposed LDO regulator consists of a three-stage erroramplifier (EA), a summing amplifier (SA), and a feed-forward amplifier (FFA), which helps to increasethe PSR and provide a robust output voltage. To precisely control the gain of the summing amplifier,we employ a variable resistor consisting of MOS switches and a binary resistive bank which can changethe total resistance linearly with the control bits. This paper is structured as follows. Section 2 describesthe operation of a conventional LDO regulator and describes various techniques used to improve thePSR of an LDO regulator. Section 3 explains the circuit design of the proposed LDO regulator, and themeasurements for the proposed LDO regulator are presented in Section 4, followed by the conclusionin Section 5.

2. Techniques Used in Low-Dropout Regulator for the Enhanced Power Supply RejectionRatio (PSRR)

A conventional LDO regulator, shown in Figure 1, includes a pass transistor Mpass and an erroramplifier for comparing the voltage of the feedback circuit and Vref. The conventional LDO regulatorhas three paths by which the noise can couple with the output of the LDO regulator. The first pathis through the pass transistor, the second path is from the error amplifier which is connected withthe supply voltage, VDD, and the third path is from the Vref. The first path is mainly dependent onthe feedback network produced by R1 and R2 at low frequencies. As the frequency starts to increase,the load capacitance, CL, takes the role of getting rid of the input ripples. However, the equivalentself-inductance and resistance of the capacitor CL will reduce the effect [1]. The PSR of the second pathis limited by the DC gain and bandwidth of the error amplifier. Therefore, the challenge of the erroramplifier is that both DC gain and bandwidth have to be large. At high frequencies, the effect of thesecond path is weak due to the capacitance seen at the gate of the pass transistor. The PSR of the thirdpath is limited by the bandgap reference or the bias voltage source.

Electronics 2020, 9, x FOR PEER REVIEW 2 of 11

In this paper, we introduce an LDO regulator which achieves a significantly improved PSR by

utilizing the feed-forward ripple cancellation technique. The purpose of this technique is to duplicate

the input ripples to the gate of the pass transistor so that it will cancel out the input ripples to increase

the power supply rejection significantly. The proposed LDO regulator consists of a three-stage error

amplifier (EA), a summing amplifier (SA), and a feed-forward amplifier (FFA), which helps to

increase the PSR and provide a robust output voltage. To precisely control the gain of the summing

amplifier, we employ a variable resistor consisting of MOS switches and a binary resistive bank

which can change the total resistance linearly with the control bits. This paper is structured as follows.

Section 2 describes the operation of a conventional LDO regulator and describes various techniques

used to improve the PSR of an LDO regulator. Section 3 explains the circuit design of the proposed

LDO regulator, and the measurements for the proposed LDO regulator are presented in Section 4,

followed by the conclusion in Section 5.

2. Techniques Used in Low-Dropout Regulator for the Enhanced Power Supply Rejection Ratio

(PSRR)

A conventional LDO regulator, shown in Figure 1, includes a pass transistor Mpass and an error

amplifier for comparing the voltage of the feedback circuit and Vref. The conventional LDO regulator

has three paths by which the noise can couple with the output of the LDO regulator. The first path is

through the pass transistor, the second path is from the error amplifier which is connected with the

supply voltage, VDD, and the third path is from the Vref. The first path is mainly dependent on the

feedback network produced by R1 and R2 at low frequencies. As the frequency starts to increase, the

load capacitance, CL, takes the role of getting rid of the input ripples. However, the equivalent self-

inductance and resistance of the capacitor CL will reduce the effect [1]. The PSR of the second path is

limited by the DC gain and bandwidth of the error amplifier. Therefore, the challenge of the error

amplifier is that both DC gain and bandwidth have to be large. At high frequencies, the effect of the

second path is weak due to the capacitance seen at the gate of the pass transistor. The PSR of the third

path is limited by the bandgap reference or the bias voltage source.

Figure 1. The schematic diagram of the conventional low-dropout regulator.

3. Proposed LDO Regulator Circuit Design

The schematic diagram of the proposed low-dropout regulator is shown in Figure 2. To have a

clean output voltage, a zero-transfer gain from the input to the output is required. To achieve the

zero-transfer gain in an ideal case, a feed-forward ripple cancellation technique is used in the

Mpass

Vref

CL

R1

OUT

IN

R2

Figure 1. The schematic diagram of the conventional low-dropout regulator.

3. Proposed LDO Regulator Circuit Design

The schematic diagram of the proposed low-dropout regulator is shown in Figure 2. To have aclean output voltage, a zero-transfer gain from the input to the output is required. To achieve thezero-transfer gain in an ideal case, a feed-forward ripple cancellation technique is used in the proposedLDO regulator. A feed-forward path carries the same input ripples through the feed-forward amplifierand the summing amplifier to the gate of the Mpass. Then, the ripples at the gate cancel out the ripplesat the source of the Mpass. However, in the practical case, some of the ripples at the source leak through


the drain-source resistance (rds,pass) of the Mpass. Thus, to cancel out the additional ripples fromrds,pass, the produced ripples at the gate of the Mpass should be higher in ripple amplitude [1]. Thepass transistor (Mpass) is implemented using a PMOS transistor considering that the DC voltage levelrequired at the gate is lower than the supply voltage VDD, while the NMOS pass transistor needs ahigher DC voltage level at the gate. The length of the pass transistor is 0.1 um and the width is 1.5 mm.


proposed LDO regulator. A feed-forward path carries the same input ripples through the feed-

forward amplifier and the summing amplifier to the gate of the Mpass. Then, the ripples at the gate

cancel out the ripples at the source of the Mpass. However, in the practical case, some of the ripples at

the source leak through the drain-source resistance (rds,pass) of the Mpass. Thus, to cancel out the

additional ripples from rds,pass, the produced ripples at the gate of the Mpass should be higher in ripple

amplitude [1]. The pass transistor (Mpass) is implemented using a PMOS transistor considering that

the DC voltage level required at the gate is lower than the supply voltage VDD, while the NMOS

pass transistor needs a higher DC voltage level at the gate. The length of the pass transistor is 0.1 um

and the width is 1.5 mm.

Figure 2. The schematic diagram of the proposed low-dropout regulator.

The error amplifier is implemented to have a feedback circuit and controls the output voltage

with RF1 and RF2. The summing amplifier’s objective is to combine the signal from the feed-forward

path with the feedback regulating loop. The summing feedback resistances (R3, R4, Rbank) push the

output pole higher so that it is higher than the gain bandwidth (GBW) of the LDO regulator [1].

Figure 3 shows the transistor-level schematic diagram of the feed-forward, summing, and error

amplifier implemented in the proposed LDO regulator. Specific size and parameters are given in

Table 1. The operational transconductance amplifier (OTA) consists of a differential amplifier with

active load, common source amplifier, compensating capacitor, and a series resistor next to the

compensating capacitor. The differential amplifier with active load performs differential to single-

ended conversion while maintaining the gain [5]. The capacitor CC for compensation achieves pole-

splitting in the circuit, which will affect the stability. The series resistor, Rgd, provides a left half-plane

zero to compensate for the right half-plane zero that was produced by CC.

Mpass

C1

Rbank

OUT

Bandgap

Reference

IN

Vbias

CLR1

R2

R3R4

RF1

RF2

IL

Feed-Forward

Amplifier

Summing

Amplifier

Error

Amplifier

Figure 2. The schematic diagram of the proposed low-dropout regulator.

The error amplifier is implemented to have a feedback circuit and controls the output voltagewith RF1 and RF2. The summing amplifier’s objective is to combine the signal from the feed-forwardpath with the feedback regulating loop. The summing feedback resistances (R3, R4, Rbank) push theoutput pole higher so that it is higher than the gain bandwidth (GBW) of the LDO regulator [1].

Figure 3 shows the transistor-level schematic diagram of the feed-forward, summing, and erroramplifier implemented in the proposed LDO regulator. Specific size and parameters are given in Table 1.The operational transconductance amplifier (OTA) consists of a differential amplifier with active load,common source amplifier, compensating capacitor, and a series resistor next to the compensatingcapacitor. The differential amplifier with active load performs differential to single-ended conversionwhile maintaining the gain [5]. The capacitor CC for compensation achieves pole-splitting in the circuit,which will affect the stability. The series resistor, Rgd, provides a left half-plane zero to compensate forthe right half-plane zero that was produced by CC.

Table 1. Parameters of the feed-forward, summing amplifier, and error amplifier.

Feed-Forward Amp. Summing Amp. Error Amp.

M1 [µm/µm] 10/1 10/1 5/1M2 [µm/µm] 10/1 10/1 5/1M3 [µm/µm] 25/1 25/1 15/1M4 [µm/µm] 25/1 25/1 15/1M5 [µm/µm] 27/1 50/1 95/1M6 [µm/µm] 12/1 8/1 6/1M7 [µm/µm] 12/1 - 6/1M8 [µm/µm] 12/1 12/1 26/1M9 [µm/µm] 12/1 12/1 26/1

CC [pF] 4 4 1Rgd [kΩ] 4 5 -

Electronics 2020, 9, 146 4 of 10Electronics 2020, 9, x FOR PEER REVIEW 4 of 11

Figure 3. Schematic of the feed-forward, the summing amplifier, and the error amplifier.

Table 1. Parameters of the feed-forward, summing amplifier, and error amplifier.

Feed-Forward Amp. Summing Amp. Error Amp.

M1 [μm/μm] 10/1 10/1 5/1

M2 [μm/μm] 10/1 10/1 5/1

M3 [μm/μm] 25/1 25/1 15/1

M4 [μm/μm] 25/1 25/1 15/1

M5 [μm/μm] 27/1 50/1 95/1

M6 [μm/μm] 12/1 8/1 6/1

M7 [μm/μm] 12/1 - 6/1

M8 [μm/μm] 12/1 12/1 26/1

M9 [μm/μm] 12/1 12/1 26/1

CC [pF] 4 4 1

Rgd [kΩ] 4 5 -

For the resistive bank (Rbank) presented in Figure 2, it is implemented to cover the range of

resistance from 750 Ω to 1125 Ω in the typical process condition. Considering the process variation

of the polyresistor and the active device, the designed resistive bank was designed to provide the

correct summing gain over the possible process variation. Figure 4 presents the schematic diagram

of the proposed resistive bank. The aimed resistance of the resistor bank is 950 Ω. The parallel switch

and the series switches use the bits 0, 1, 2, and 3. The 15 resistors, RB, are added to provide a 25 Ω step

from 750 Ω to 1125 Ω. The parallel switches make the entire resistance fixed so that only the number

of RB determines the total resistance. The equation for the resistor bank is given by

0 1 2 3

0 1 2 3

[ ] 600 2 4 8 [ ]( )

MOSFET Pbank B B B B

P MOSFET

R RR R b R b R b R b

R b b b b R

(1)

where RP is the parallel switch and bnumber is the bit number. The resistance bit table is shown in Table

2.

M4

M1 M2

M6

M7

M3

M5

M8

M9

INM

OUT

INP

VCAS

VS

CC

Rgd

VDD

Figure 3. Schematic of the feed-forward, the summing amplifier, and the error amplifier.

For the resistive bank (Rbank) presented in Figure 2, it is implemented to cover the range ofresistance from 750 Ω to 1125 Ω in the typical process condition. Considering the process variation ofthe polyresistor and the active device, the designed resistive bank was designed to provide the correctsumming gain over the possible process variation. Figure 4 presents the schematic diagram of theproposed resistive bank. The aimed resistance of the resistor bank is 950 Ω. The parallel switch andthe series switches use the bits 0, 1, 2, and 3. The 15 resistors, RB, are added to provide a 25 Ω stepfrom 750 Ω to 1125 Ω. The parallel switches make the entire resistance fixed so that only the number ofRB determines the total resistance. The equation for the resistor bank is given by

Rbank[Ω] = 600 +RMOSFETRP

RP + (b0 + b1 + b2 + b3)RMOSFET+ RBb0 + 2RBb1 + 4RBb2 + 8RBb3 [Ω] (1)

where RP is the parallel switch and bnumber is the bit number. The resistance bit table is shown in Table 2.Electronics 2020, 9, x FOR PEER REVIEW 5 of 11

Figure 4. Schematic diagram of the proposed resistive bank.

Table 2. Bit table of the resistive bank.

Bit 3 Bit 2 Bit 1 Bit 0 Resistance [Ω]

0 0 0 0 744

0 0 0 1 772

0 0 1 0 796

0 0 1 1 827

0 1 0 0 845

0 1 0 1 876

0 1 1 0 900

0 1 1 1 935

1 0 0 0 951

1 0 0 1 981

1 0 1 0 1006

1 0 1 1 1041

1 1 0 0 1056

1 1 0 1 1091

1 1 1 0 1115

1 1 1 1 1157

To supply a fixed reference voltage to the error amplifier in any conditions like temperature

changes or power supply variations, the circuit needs a bandgap voltage reference shown in Figure

5. An OTA is implemented to provide feedback for MB1 and MB2. The feedback on the MB1 side is

implemented as positive feedback and the other side as negative feedback. To stabilize the output

voltage of the bandgap reference is to have more negative feedback than the positive one. Three

resistors, RB1, RB2, and RB3, make the loop gain of the negative feedback stronger than that of the

positive feedback.

Figure 4. Schematic diagram of the proposed resistive bank.

To supply a fixed reference voltage to the error amplifier in any conditions like temperaturechanges or power supply variations, the circuit needs a bandgap voltage reference shown in Figure 5.An OTA is implemented to provide feedback for MB1 and MB2. The feedback on the MB1 side isimplemented as positive feedback and the other side as negative feedback. To stabilize the output


voltage of the bandgap reference is to have more negative feedback than the positive one. Threeresistors, RB1, RB2, and RB3, make the loop gain of the negative feedback stronger than that of thepositive feedback.

Table 2. Bit table of the resistive bank.

Bit 3 Bit 2 Bit 1 Bit 0 Resistance [Ω]

0 0 0 0 7440 0 0 1 7720 0 1 0 7960 0 1 1 8270 1 0 0 8450 1 0 1 8760 1 1 0 9000 1 1 1 9351 0 0 0 9511 0 0 1 9811 0 1 0 10061 0 1 1 10411 1 0 0 10561 1 0 1 10911 1 1 0 11151 1 1 1 1157


Figure 5. Schematic diagram of the bandgap voltage reference.

The OTA in the bandgap voltage reference is presented in Figure 6. The reference voltage (VREF)

of 880 mV was selected to have 1 V as the output voltage. The resistors RF1 and RF2 determine the

output voltage, 1 V, based on the ratio of those resistors and the reference voltage from the bandgap

reference. The equation for the output voltage (Voutput) can be expressed as

1 2

2

[ ] [ ]F FOUTPUT REF

F

R RV V V V

R

. (2)

MB2

(18/6)

MB1

(18/6)

CBL

2pF

RB1

40kΩ

VDD

RB2

40kΩ

RB1

15kΩ

DB2DB1

VOUT

M4

(25/1)

M1

(10/1)

M2

(10/1)

M6

(8/1)

M7

(8/1)

M3

(25/1)

M5

(30/1)

M8

(8/1)

M9

(8/1)

INM

OUTINP

VCAS

VS

VDD


The OTA in the bandgap voltage reference is presented in Figure 6. The reference voltage (VREF)of 880 mV was selected to have 1 V as the output voltage. The resistors RF1 and RF2 determine theoutput voltage, 1 V, based on the ratio of those resistors and the reference voltage from the bandgapreference. The equation for the output voltage (Voutput) can be expressed as

VOUTPUT[V] = VREF ×RF1 + RF2

RF2[V]. (2)




The OTA in the bandgap voltage reference is presented in Figure 6. The reference voltage (VREF)

of 880 mV was selected to have 1 V as the output voltage. The resistors RF1 and RF2 determine the

output voltage, 1 V, based on the ratio of those resistors and the reference voltage from the bandgap

reference. The equation for the output voltage (Voutput) can be expressed as

1 2

2

[ ] [ ]F FOUTPUT REF

F

R RV V V V

R

. (2)

MB2

(18/6)

MB1

(18/6)

CBL

2pF

RB1

40kΩ

VDD

RB2

40kΩ

RB1

15kΩ

DB2DB1

VOUT

M4

(25/1)

M1

(10/1)

M2

(10/1)

M6

(8/1)

M7

(8/1)

M3

(25/1)

M5

(30/1)

M8

(8/1)

M9

(8/1)

INM

OUTINP

VCAS

VS

VDD

Figure 6. Schematic diagram of the operational transconductance amplifier (OTA) used in the bandgapvoltage reference.

4. Measurement Results

Figure 7 shows a microphotograph of the implemented LDO regulator with a chip size of0.092 mm2 without pads, while Figure 8 is the power supply rejection ratio (PSRR) and regulationmeasurement setup. Rpar is the parasitic resistance in the measurement setup. An SPI (Serial PeripheralInterface) module is used to control the resistor bank and the biasing points of each OTA. The quiescentcurrent consumption of the circuit is 0.385 mA under a 1.2 V supply voltage.


Figure 6. Schematic diagram of the operational transconductance amplifier (OTA) used in the

bandgap voltage reference.


Figure 7 shows a microphotograph of the implemented LDO regulator with a chip size of 0.092

mm2 without pads, while Figure 8 is the power supply rejection ratio (PSRR) and regulation

measurement setup. Rpar is the parasitic resistance in the measurement setup. An SPI (Serial

Peripheral Interface) module is used to control the resistor bank and the biasing points of each OTA.

The quiescent current consumption of the circuit is 0.385 mA under a 1.2 V supply voltage.

Figure 7. A microphotograph of the proposed low-dropout (LDO) regulator.

(a)

DC Power Supply

Keysight E36313A

Signal Generator

Agilent 83623B

Bias Tee

Picotest

5550B

LDO

Regulator

SPI Module

Precision Source/Measure Unit

Keysight B2902A

Spectrum Analyzer

Keysight E4405B

Power

Divider

OUT

RLCL

4.7μF

Spectrum Analyzer

Keysight E4405B

Rpar




Figure 6. Schematic diagram of the operational transconductance amplifier (OTA) used in the

bandgap voltage reference.


Figure 7 shows a microphotograph of the implemented LDO regulator with a chip size of 0.092

mm2 without pads, while Figure 8 is the power supply rejection ratio (PSRR) and regulation

measurement setup. Rpar is the parasitic resistance in the measurement setup. An SPI (Serial

Peripheral Interface) module is used to control the resistor bank and the biasing points of each OTA.

The quiescent current consumption of the circuit is 0.385 mA under a 1.2 V supply voltage.


(a)

DC Power Supply

Keysight E36313A

Signal Generator

Agilent 83623B

Bias Tee

Picotest

5550B

LDO

Regulator

SPI Module

Precision Source/Measure Unit

Keysight B2902A

Spectrum Analyzer

Keysight E4405B

Power

Divider

OUT

RLCL

4.7μF

Spectrum Analyzer

Keysight E4405B

Rpar


(b)

Figure 8. (a) Power supply rejection ratio (PSRR) and (b) regulation measurement setup of the

proposed LDO regulator.

In Figure 9, the PSRR comparison graph between the simulation and measurement of the

proposed LDO regulator and a conventional LDO regulator is shown. Measurements and simulation

correspond well when we include the parasitic series resistance Rpar in the VDD input port as

presented in Figure 8. Compared with a conventional LDO regulator, 30–40 dB of extra PSRR were

observed from 10 kHz–10 MHz. Figure 10 shows the output voltage when the load changes. Load

regulation can be calculated by Equation (3).

Load Regulation [ / ]OUT

L

VmV mA

I

. (3)

ΔVOUT is 45 mV when ΔIL is 19.38 mA in this work. Thus, the load regulation is calculated to be

2.3 (mV/mA).

Figure 11 shows the change in VOUT when changing the VIN with a 100 Ω load. With Figure 11,

the line regulation can be calculated by Equation (4).

Line Regulation [ / ]OUT

IN

VV V

V

(4)

ΔVOUT is 5 mV when ΔVIN is 300 mV in this work. Thus, the line regulation is calculated to be 0.08

(V/V).

LDO

Regulator

DC Power Supply

Keysight E36313A

OUT

RL

0.98V

Multimeter

Fluke 115

SPI Module

CL

4.7μFPrecision Source/Measure Unit

Keysight B2902A

Rpar

Figure 8. (a) Power supply rejection ratio (PSRR) and (b) regulation measurement setup of the proposedLDO regulator.

In Figure 9, the PSRR comparison graph between the simulation and measurement of the proposedLDO regulator and a conventional LDO regulator is shown. Measurements and simulation correspondwell when we include the parasitic series resistance Rpar in the VDD input port as presented in Figure 8.Compared with a conventional LDO regulator, 30–40 dB of extra PSRR were observed from 10 kHz–10MHz. Figure 10 shows the output voltage when the load changes. Load regulation can be calculatedby Equation (3).

Load Regulation =∆VOUT

∆IL[mV/mA]. (3)


Figure 9. PSRR comparison graph between the simulation and measurement.

Figure 10. Load regulation comparison graph between the simulation and measurement.

103

104

105

106

107

108

109

0

20

40

60

80

100

120

39.02dB@100MHz

PS

RR

[d

B]

Frequency [Hz]

FFRC Sim.

FFRC Meas.

Conv. LDO Sim.

51.87dB @10kHz

36.89dB @1MHz 39dB @100MHz

76.8dB @1MHz

92.65dB @10kHz 92.3dB @100kHz

76.08dB @1MHz

53.06dB@10MHz

58.3dB @10MHz

50.74dB @100kHz

9.7dB @10MHz

0 5 10 15 20 25

0.7

0.8

0.9

1.0

1.1

1.2

Ou

tpu

t V

olt

ag

e [

V]

Load Current [mA]

FFRC Sim.

FFRC Meas.





103

104

105

106

107

108

109

0

20

40

60

80

100

120

39.02dB@100MHz

PS

RR

[d

B]

Frequency [Hz]

FFRC Sim.

FFRC Meas.

Conv. LDO Sim.

51.87dB @10kHz

36.89dB @1MHz 39dB @100MHz

76.8dB @1MHz

92.65dB @10kHz 92.3dB @100kHz

76.08dB @1MHz

53.06dB@10MHz

58.3dB @10MHz

50.74dB @100kHz

9.7dB @10MHz

0 5 10 15 20 25

0.7

0.8

0.9

1.0

1.1

1.2

Ou

tpu

t V

olt

ag

e [

V]

Load Current [mA]

FFRC Sim.

FFRC Meas.


∆VOUT is 45 mV when ∆IL is 19.38 mA in this work. Thus, the load regulation is calculated to be2.3 (mV/mA).

Figure 11 shows the change in VOUT when changing the VIN with a 100 Ω load. With Figure 11,the line regulation can be calculated by Equation (4).

Line Regulation =∆VOUT∆VIN

[V/V] (4)

∆VOUT is 5 mV when ∆VIN is 300 mV in this work. Thus, the line regulation is calculated to be0.08 (V/V).

The performances of the proposed LDO regulator are summarized and compared with the recentlyreported LDO regulators in Table 3.


Figure 11. Line regulation comparison graph between the simulation and measurement with a 100 Ω load.

The performances of the proposed LDO regulator are summarized and compared with the

recently reported LDO regulators in Table 3.

Table 3. Summary of the proposed LDO regulator compared with recently reported LDO

regulators.

LDO Regulator This Work [1] [2] [6] [7]

Technology [nm] 65 130 130 180 65

VIN [V] 1.2 1.15 1.2 1.8 1.2

VOUT [V] 0.98 1 1 1.6 1

Dropout Voltage [V] 0.22 0.15 0.2 0.2 0.2

Maximum Load [mA] 20 25 50 50 25

Quiescent Current [μA] 385 50 65 55 8–297.5

PSRR [dB] 76.8@1 MHz

58.3@10 MHz

67@1 MHz

56@10 MHz

49@2 MHz

38@10 MHz

70@1 MHz

37@10 MHz

52@1 MHz

36@10 MHz

Load Regulation [mV/mA] 2.3 0.048 0.13 0.14 0.042

Line Regulation [mV/mV] 0.08 0.026 4.25 0.075 0.0038

Area [mm2] 0.092 0.049 0.4 0.14 0.087

5. Conclusions

A power supply rejection ratio (PSRR)-enhanced LDO regulator is proposed by utilizing the

feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. In the summing

amplifier, we introduced a resistive bank which is linearly controlled by binary signals to achieve an

optimal ripple cancellation. The regulator provides 35–76.8 dB of PSRR at 1 MHz–1 GHz. The LDO

regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide

an output voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3

(mV/mA), while the line regulation is 0.05 (V/V). The circuit consumes 385 μA with an input voltage

of 1.2 V. The area without the pads is 0.092 mm2.

Author Contributions: Data curation, Y.-J.C.; Methodology, J.-D.P.; Supervision, J.D.P.; Validation, H.N.;

Writing—original draft, Y.-J.C.; Writing—review & editing, J.-D.P.

Funding: This work was supported by the National Research Foundation of Korea(NRF) grant funded by the

Korea government(MSIP) (2019M3F6A1106118); the Korea Institute of Energy Technology Evaluation and

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

0.6

0.7

0.8

0.9

1.0

1.1

1.2 Simulation

Measurement

Ou

tpu

t V

olt

ag

e [

V]

Input Voltage [V]

Figure 11. Line regulation comparison graph between the simulation and measurement with a 100Ω load.

Table 3. Summary of the proposed LDO regulator compared with recently reported LDO regulators.

LDO Regulator This Work [1] [2] [6] [7]

Technology [nm] 65 130 130 180 65VIN [V] 1.2 1.15 1.2 1.8 1.2

VOUT [V] 0.98 1 1 1.6 1Dropout Voltage [V] 0.22 0.15 0.2 0.2 0.2

Maximum Load [mA] 20 25 50 50 25Quiescent Current [µA] 385 50 65 55 8–297.5

PSRR [dB] 76.8@1 MHz58.3@10 MHz

67@1 MHz56@10 MHz

49@2 MHz38@10 MHz

70@1 MHz37@10 MHz

52@1 MHz36@10 MHz

Load Regulation [mV/mA] 2.3 0.048 0.13 0.14 0.042Line Regulation [mV/mV] 0.08 0.026 4.25 0.075 0.0038

Area [mm2] 0.092 0.049 0.4 0.14 0.087

5. Conclusions

A power supply rejection ratio (PSRR)-enhanced LDO regulator is proposed by utilizing thefeed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. In the summingamplifier, we introduced a resistive bank which is linearly controlled by binary signals to achieve anoptimal ripple cancellation. The regulator provides 35–76.8 dB of PSRR at 1 MHz–1 GHz. The LDOregulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide anoutput voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3 (mV/mA),while the line regulation is 0.05 (V/V). The circuit consumes 385 µA with an input voltage of 1.2 V. Thearea without the pads is 0.092 mm2.

Author Contributions: Data curation, Y.-J.C.; Methodology, J.-D.P.; Supervision, J.D.P.; Validation, H.N.;Writing—original draft, Y.-J.C.; Writing—review & editing, J.-D.P. All authors have read and agreed to thepublished version of the manuscript.

Funding: This work was supported by the National Research Foundation of Korea(NRF) grant funded by theKorea government(MSIP) (2019M3F6A1106118); the Korea Institute of Energy Technology Evaluation and Planning(KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No. 20194030202320).

Electronics 2020, 9, 146 10 of 10

Acknowledgments: This work was supported by the National Research Foundation of Korea (NRF) grant fundedby the Korea government (MSIP) (2019M3F6A1106118); the Korea Institute of Energy Technology Evaluationand Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No.20194030202320).

Conflicts of Interest: The funders had no role in the design of the study; in the collection, analyses or interpretationof data; in the writing of the manuscript, or in the decision to publish the results.

References

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4. Gupta, V.; Rincón-Mora, G.A. A 5 mA 0.6 um CMOS Millercompensated LDO regulator with -27 dBworst-case power-supply rejection using 60 pF of on-chip capacitance. In Proceedings of the IEEE InternationalSolid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 11–15 February2007; pp. 520–521.

5. Razavi, B. Fundamentals of Microelectronics; Wiley: Hoboken, NJ, USA, 2006.6. Park, C.; Onabajo, M.; Silva-Martinez, J. External Capacitor-Less Low Drop-Out Regulator with 25 dB

Superior Power Supply Rejection in the 0.4–4 MHz Range. IEEE J. Solid-State Circuits 2014, 49, 486–501.[CrossRef]

7. Lim, Y.; Lee, J.; Park, S.; Jo, Y.; Choi, J. An External Capacitorless Low-Dropout Regulator with High PSR atAll Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique. IEEE J.Solid-State Circuits 2018, 53, 2675–2685. [CrossRef]

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http://dx.doi.org/10.1109/JSSC.2009.2039685

http://dx.doi.org/10.5573/JSTS.2012.12.3.313



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a low-dropout regulator with psrr enhancement through feed

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