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Full Terms & Conditions of access and use can be found at http://www.tandfonline.com/action/journalInformation?journalCode=tetl20 International Journal of Electronics Letters ISSN: 2168-1724 (Print) 2168-1732 (Online) Journal homepage: http://www.tandfonline.com/loi/tetl20 A high step-up DC–DC soft-switched converter using coupled inductor and switched capacitor Navid Salehi, Sayyed Mohammad Mehdi Mirtalaei & Sayyed Hosein Mirenayat To cite this article: Navid Salehi, Sayyed Mohammad Mehdi Mirtalaei & Sayyed Hosein Mirenayat (2018) A high step-up DC–DC soft-switched converter using coupled inductor and switched capacitor, International Journal of Electronics Letters, 6:3, 260-271, DOI: 10.1080/21681724.2017.1357195 To link to this article: https://doi.org/10.1080/21681724.2017.1357195 Accepted author version posted online: 24 Jul 2017. Published online: 04 Aug 2017. Submit your article to this journal Article views: 21 View Crossmark data Citing articles: 1 View citing articles

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Page 1: A high step-up DC–DC soft-switched converter using coupled … · 2018. 7. 17. · comparisonwithnon-isolatedconverters(Franceschini,Lorenzani,Cavatorta,&Bellini,2008; Lin, Huang,

Full Terms & Conditions of access and use can be found athttp://www.tandfonline.com/action/journalInformation?journalCode=tetl20

International Journal of Electronics Letters

ISSN: 2168-1724 (Print) 2168-1732 (Online) Journal homepage: http://www.tandfonline.com/loi/tetl20

A high step-up DC–DC soft-switched converterusing coupled inductor and switched capacitor

Navid Salehi, Sayyed Mohammad Mehdi Mirtalaei & Sayyed HoseinMirenayat

To cite this article: Navid Salehi, Sayyed Mohammad Mehdi Mirtalaei & Sayyed HoseinMirenayat (2018) A high step-up DC–DC soft-switched converter using coupled inductorand switched capacitor, International Journal of Electronics Letters, 6:3, 260-271, DOI:10.1080/21681724.2017.1357195

To link to this article: https://doi.org/10.1080/21681724.2017.1357195

Accepted author version posted online: 24Jul 2017.Published online: 04 Aug 2017.

Submit your article to this journal

Article views: 21

View Crossmark data

Citing articles: 1 View citing articles

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ARTICLE

A high step-up DC–DC soft-switched converter usingcoupled inductor and switched capacitorNavid Salehia,b, Sayyed Mohammad Mehdi Mirtalaeia,b and Sayyed Hosein Mirenayata,b

aDepartment of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran; bSmartMicrogrid Research Center, Najafabad Branch, Islamic Azad University, Najafabad, Iran

ABSTRACTIn this paper, a zero-voltage-switching (ZVS) high step-up threelevel coupled inductor-based boost converter is proposed. Three-level structure of the proposed converter causes significant reduc-tion of the switches and diodes voltage stress. The leakage induc-tance that is caused by coupled inductor leads to voltage ringing,the use of the active-clamp circuit in this structure not onlyeliminates the voltage ringing but also makes all switches turnon and off under ZVS condition that results in improving theefficiency. All the switches in the proposed converter will operatewith an appropriate duty cycle for high step-up applications. Theproposed converter features, operating principles and analysis arediscussed in the paper and to verify the validity of theoreticalanalysis, the experimental results of a 200-W laboratory prototypewith a 4-V input and 400-V output are presented.

ARTICLE HISTORYReceived 12 April 2017Accepted 26 June 2017

KEYWORDSHigh step-up converter;three-level converter;zero-voltage-switching;coupled inductor; switchedcapacitor

Introduction

Over the past years, renewable energies such as solar and fuel cells have become more andmore popular since the fossil energies are going to run out in the near future. Moreover, theiradverse effect of fossil fuels on the environment leads to renewable energies introducedthemselves as an appropriate alternative to solve some international problems such asenvironmental contaminant and global warming (Femia, Petrone, Spagnuolo, & Vitelli, 2012;Li & Wolfs, 2008). Some sources of renewable energies such as photovoltaic panels and fuelcells are not able to produce high-voltage output that makes them impossible to connectinverter module directly. First solution in order to increase the obtained voltage from the PVpanels is to connect them in series. However, due to the shading effect on the photovoltaicpanels as well as incompatibility and non-identical characteristic of PV panels, make obtainedoutput power become lower than predicted amount (Edwin, Xiao, & Khadkikar, 2014; Evran &Aydemir, 2013). To resolve the aforementioned setbacks, the second solution is using DC–DCconverters. Large margin of voltage level between PV panels and inverter modules results inconventional boost converter that can’t be exploit because of high operating duty cycle, highswitch voltage stress and large switching losses (Patil & Agarwal, 2015; Selvaraj & Rahim, 2009).

CONTACT Navid Salehi [email protected] Department of Electrical Engineering, Najafabad Branch,Islamic Azad University, Najafabad, Iran; Smart Microgrid Research Center, Najafabad Branch, Islamic Azad University,Najafabad, Iran

INTERNATIONAL JOURNAL OF ELECTRONICS LETTERS2018, VOL. 6, NO. 3, 260–271https://doi.org/10.1080/21681724.2017.1357195

© 2017 Informa UK Limited, trading as Taylor & Francis Group

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So, to solve these problems, many high step-up converters introduced by researchers(Liu, Hu, Wu, Xing, & Batarseh, 2016; Tofoli, De Castro Pereira, De Paula, & Júnior, 2015).Although isolated converters could be applied to achieve high voltage gain by adjustingturn ratio of HF transformer, this is not recommended – except for some applications thatgalvanic isolation is essential – because of lower efficiency, higher complexity and cost incomparison with non-isolated converters (Franceschini, Lorenzani, Cavatorta, & Bellini, 2008;Lin, Huang, & Chen, 2009). Cascading boost converters can be used as a high step-upconverter to increase voltage gain. However, switches and diodes voltage stress, reducedefficiency, reverse-recovery problem of output diodes and large number of components canbe considered as some major drawbacks of cascaded boost converters (Lee, Yu, & Chou,2014). One approach to enhance the performance of high step-up converters is applyingcoupled inductor. Reducing duty cycle and input current ripple, also improving reverse-recovery matter of diodes and high voltage gain, are the advantages of coupled-inductor-based boost converter, but still switches and diodes suffer from high voltage stress ofsemiconductor devices because of leakage inductance of coupled inductors (Freitas, Tofoli,Sá Junior, Daher, & Antunes, 2016). In order to reduce the voltage stress, different clampcircuits proposed in Lin, Dong and Chen (2009), Poorali, Jazi and Adib (2016) and Zhao, Li,Deng and He (2011). Although passive clamp circuits are able to reduce the voltage stresssimply, the switches operate under hard switching condition. Utilising active clamp providesoft-switched for active switches result in improving the converter efficiency. In Luo, Zhang,Sun and Zhou (2015), a proposed converter uses an active clamp to provided zero-voltage-switching (ZVS) condition for both the main and clamp switches. One of the methods toincrease the voltage gain of coupled-inductor-based boost converter is combining withswitched-capacitor-based boost converter. In the converter proposed in Hsieh, Chen, Liangand Yang (2012), the energy stored in the coupled inductor charges the capacitors toincrease the voltage gain. The major problem of the coupled inductor-based boost con-verters is the voltage stress of output diodes equal to the at least output voltage. Hence,three level boost converters structure can be applied to alleviate the voltage stress of allsemiconductor devices to half of output voltage.

Anovel high step-up three level coupled inductor-basedboost converter is proposed in thispaper. Compared to converter proposed in Baek, Ryoo, Kim, Yoo and Kim (2005), the voltagestress of switches and diodes in the proposed converter is halved and also the proposedconverter provides ZVS condition for all semiconductor elements. The proposed converter hasall the advantages of the previously mentioned coupled inductor-based boost converters.Also, the voltage stress of semiconductor devices is very low. This paper is organised as follows.First of all the converter is introduced and its steady-state operational analysis are presented.Then the theoretical analysis of the converter performance is discussed. Finally the experi-mental results of a 200-W 40-V-input 400-V-output prototype with 100 kHz switching fre-quency are presented to verify the theoretical analysis.

The proposed converter and operational principles

Circuit configuration

The proposed ZVT high step-up three level coupled inductor-based boost converter isillustrated in Figure 1(a). The proposed converter is composed of three active switches

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S1, S2 and S3, three inductors L1, L2 and L3 which are coupled together, two rectifierdiodes D1 and D2, three snubber capacitors CS1 , CS2 and CA, two output capacitors Co1and Co2 and one clamp capacitor CC. Figure 1(b) shows the proposed converter with theequivalent circuit of the coupled inductors.

Operating intervals of the proposed converter

The proposed converter has 12 distinct operation intervals. The gate pulses of S1 and S2are same as conventional three level boost converter. Since operation of S1 and S2 aresimilar, only six operating intervals which are related to S1 are presented in this section.The following assumptions are made to simplify the circuit analysis

● All of the components are assumed ideal.● The capacitors CC, Co1 and Co2 are large enough so that their voltage variations can

be ignored. Also, Co1 = Co2.● The snubber capacitors CS1 and CS2 are equal.● The duty cycles of switches S1 and S2 are equal.● Inductors L2 and L3 are equal.

Figure 1. The proposed ZVT high step-up three level coupled-inductor-based boost converter (a)proposed converter and (b) equivalent circuit of coupled inductor.

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Figure 2 shows the theoretical waveforms of the operating stages related to S1 andFigure 3 illustrates equivalent circuit of the converter in each operating stage.

(a) Stage 1 [t0–t1], (b) Stage 2 [t1–t2], (c) Stage 3 [t2–t3], (d) Stage 4 [t3–t4], (e) Stage 5[t4–t5], and (f) Stage 6 [t5–t6].

Stage 1 [t0–t1] (Figure 3(a)): In this interval, S1 and S2 are on and SA is off. During thisinterval, iL1k1 and Lm current increases and the capacitors Co1 and Co2 supply the load. Whenone of the main switches turns off, this interval ends. The iL1k1 equation is as follows:

iLlk1 ¼Vin

Llk1 þ Lm� t � t0ð Þ þ iLlk1 t0ð Þ (1)

Stage 2 [t1–t2] (Figure 3(b)): At t1, S1 is turned off, while S2 is in the on-state. In this stage,leakage inductor Llk1 charges and discharges capacitors CS1 and CA, respectively. Snubbercapacitor CS1 is charged to Vin þ VCC , while capacitor CA is discharged. To achieve a ZVSfeature for switch S1, the energy stored in the leakage inductor Llk1 should satisfy thefollowing inequality:

Figure 2. Theoretical key voltage and current waveforms of the proposed converter operation.

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12� LLlk1 � iLlk1 t1ð Þ½ �2 � 1

2� CA==CS1ð Þ � vCA t1ð Þ½ �2 (2)

Stage 3 [t2–t3] (Figure 3(c)): Stage 3 begins when voltage vCA drops to zero at t2. Inductorcurrent iL1k1 forces DA to conduct so that SA can be turned on under ZVS condition. Inorder to achieve ZVS feature, the driving signal of SA should be applied, when DA isconducting. In this mode, voltage vCS1 is clamped to Vin þ VCC . Also, D1 begins to

conduct. The stored energy in Llk1 is recycled to CC. The capacitance of CC is largeenough, so VCC will remain constant. iLm and iL1k1 can be expressed as follows:

iLm ¼ iLm t2ð Þ � Vo=2ð Þ � Vinð Þ � n1= n1 þ n2ð ÞLm

� t � t2ð Þ (3)

iLlk1 ¼ iLlk1 t2ð Þ � Vo=2ð Þ � Vinð Þ � n1= n1 þ n2ð Þð Þ½ � � VCLlk1

� t � t2ð Þ (4)

when iL1k1 drops to zero, stage 3 ends.Stage 4 [t3–t4] (Figure 3(d)): At t3, since SA is on, CC reverses the direction of iL1k1 . During

this stage, D1 is conducting, and Lm is discharged in the load.Stage 5 [t4–t5] (Figure 3(e)): At t4, SA is turned off, and S1 is still in the off state. During

this interval, iL1k1 resonates with CS1 and CA. So, CA is charged towards Vin þ VCC , while CS1

Figure 3. The operation processes of the proposed converter.

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discharges to zero. Once CS1 is completely discharged, S1 turns on under ZVS condition.The stored energy in Llk1 should satisfy the following inequality:

12� LLlk1 � iLlk1 t4ð Þ½ �2 � 1

2� CA==CS1ð Þ � vCA t4ð Þ½ �2 (5)

Stage 6 [t5–t6] (Figure 3(f)): When vCS1 drops to zero at t5, stage 6 begins. In this mode,iL1k1 forces DS1 to conduct so S1 can be turned on under ZVS condition. In order toachieve ZVS condition for S1, the driving signal of S1 should be applied, before DS1 turnsoff. During this stage, iL1k1 increases, while iD1 decrease. Decreasing rate of iD1 is limited bythe leakage inductors Llk1 and Llk2, so reverse recovery losses of D1 is reduced. Theleakage inductor current iL1k1 can be expressed as

iLlk1 ¼ iLlk1 t5ð Þ þ Vin þ Vo � n1=n2ð ÞLlk1

� t � t5ð Þ (6)

The proposed converter features and design considerations

Conversion ratio

In the proposed converter operation when both of the main switches are on, Lm chargesand when one of switches is turned off, Lm starts to transfer its energy to the output. Inone switching cycle of the proposed converter, the clamp switch SA turns on and off twotimes. In the steady state, duration of intervals t1–t2 and t4–t5 are very short as comparedto one switching period. Thus, in order to simplify the analysis of voltage conversionratio, these time intervals are ignored. By applying the volt–second balance principle ofthe inductors to the Lm, the VCC and the converter conversion ratio can be obtained asfollows:

VCC ¼D� 0:51� D

� Vin (7)

G ¼ 2 � n � Dþ 1� n1� D

(8)

where

n2n1

¼ n3n1

¼ n (9)

Considering t1–t2 and t4–t5, time intervals will reduce the effective duty cycle of the mainswitches. In fact, the on time of main switches is lower than the applied on time by gatepulses. This reduction can be expressed as

ΔTS ¼ 2 � Ii � Llk1Vin þ Vo= 2 � nð Þð Þ (10)

where Ii is

Ii ¼ Vo � Ioη � Vi (11)

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where η is the converter efficiency. Therefore, by considering this time duration, theconverter voltage conversion ratio can be expressed as following

G ¼ 2þ 2 � D� ΔTS=Tð Þð Þ½ � � 11� D� ΔTS=Tð Þ½ � ð1þ nÞ (12)

Figure 4 shows the voltage gain for three different values of turn ratio n by considering(8). It can be observed that high voltage gain of proposed converter makes it suitable forhigh step-up applications.

The voltage stress of the switches and diodes

By using (7) which is the voltage of CC and the applying KVL to the Vin–CC–SA–S1–S2 loop,the voltage stress of the switches is

VS1;S2;SA ¼Vin

2 � ð1� DÞ ¼Vo2� nnþ 1

� Vo2� Vin

� �(13)

Also, the voltage stress of diodes can be expressed as

VD1;D2 ¼ n � Vin þ Vo2

(14)

Figure 5 compares the normalised voltage stress of the main switches by input voltagebetween proposed converter and other three converters in Baek et al. (2005), Park, Moonand Youn (2010) and Tang, Wang, and He (2014) for variation of duty cycle from 0.5 to 0.9.It can be observed from Figure 5 that for the proposed converter, duty cycle variation of0.5–0.8 produces voltage stress for switches from 1 to 2.5 times of the input voltage.

Table 1 summarised the results of different types of high step-up converters and theproposed three level coupled-inductor high step-up converter in this paper from theaspects of voltage gain, switches voltage stress and output diode voltage stress. As it isobserved, in the proposed converter, the voltage stress of the switches and output

Figure 4. Voltage gain of the proposed converter for different values of n.

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diodes are reduced in comparison of other mentioned converters except converter inTang et al. (2014) that diode voltage stress is lower.

The achieving conditions of ZVS

Considering (2) and (5), to achieve ZVS turn on condition, the stored energy in Llk1should satisfy the following inequality

Llk1 �Vin þ VCC½ �2 � CS==CA

� �Vo � Ioð Þ= η � Vi � Dð Þ þ 1=2ð Þ � Δið Þ2 (15)

where

Δi ¼ Vi � Lm � D � TLm þ Llk1ð Þ2 (16)

Also, in order to achieve ZVS condition at turn off instants, the snubber capacitors canbe selected similar to any snubber capacitor as follows (Molavi, Esteki, Adib, &Farzanehfard, 2015):

CS>iswtf2 � vsw (17)

Figure 5. Voltage stress of main switches in the proposed converter.

Table 1. Type comparison of the proposed converter with converter proposed in Baek et al. (2005),Park et al. (2010) and Tang et al. (2014).Symbol Voltage gain Switches voltage stress Diodes voltage stress

The proposed converter 2�n�Dþ1�n1�D

Vo2 � n

nþ1 � Vo2 � Vin

� �n � Vin þ Vo

2Converter proposed in Baek et al. (2005) 2�n�Dþ1�n

1�DVo � n

nþ1 � Vo � Vinð Þ n � Vin þ VoConverter proposed in Park et al. (2010) 1þnD

1�DVin1�D

nVin1�D

Converter proposed in Tang et al. (2014) 3þD1�D

Vin1�D

2Vin1�D

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where tf, isw and vsw are the switch current fall time, the switch current before turn offand the switch voltage after turn off, respectively. The capacitors CS1 , CS2 and CA can bedesigned from (17).

Experimental results

To verify the theoretical analysis and performance of the proposed converter, a 100-kHz, 200-W, 40–400-V prototype converter is designed and implemented that isshown in Figure 6. Table 2 reports parameters of the prototype converter. In theproposed converter, the selected MOSFETs voltage stress is very lower than outputvoltage. Figure 7 shows the experimental results of the prototype converter. Figure 7(a) illustrates the gate pulses of S1 and SA; also, the input voltage and output voltageof the converter are presented. It is ascertained that 400 V output voltage is obtainedwhen the duty cycle is about 0.7. The gate pulses of S1 and S2 are 180° out of phasewith the same duty cycle. The ZVT operation of the main switch S1 is shown inFigure 7(b). As it is shown in the figure, the main switches are turned on and offunder ZVS condition. Due to the low voltage stress of switches compared withoutput voltage, using low RDS MOSFETs lead to reduce the conduction losses andconsequently increasing the converter efficiency. The voltage and current waveformsof the switch S2 are the same as S1 because of symmetrical operation of theconverter. Figure 7(c) shows the voltage and current waveforms of the activeclamp switch SA. As it is obvious from the figure, this switch also turns on and offunder ZVS conditions. The voltage and current waveforms of the output diode Do1

are illustrated in Figure 7(d). The waveforms of the output diode Do2 are similar to

Figure 6. Photograph of the implemented converter.

Table 2. Parameters of the proposed converter.Component Specification

Switches S1, S2, SA IRFP260Diodes Do1 and Do2 Mur460Turn ratios n2/n1 and n3/n1 5Leakage inductance Llk1 2 µHOutput capacitors Co1 and Co2 47 µF/250 VClamp capacitor CC 47 µF/50 VSnubber capacitors CS1 , CS2 and CA 2.2 nF/100 V

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Figure 7(d). From Figure 7(d), it is obvious that the reverse recovery problems ofdiodes are reduced.

Figure 8 shows the efficiency of the implemented prototype from 50% to 100% offull-load conditions. As it can be observed, the maximum efficiency achieved in 60% offull-load condition. Increasing conduction losses in the range of 60–100% result inefficiency drop.

Conclusions

In the beginning of this paper, a review of non-isolated high step-up converters isperformed. According to the review, coupled-inductor-based converters are one of thebest options for use in high step-up application. In the existing coupled-inductor-basedhigh step-up converters, the voltage stress of semiconductors is still high. To implementa coupled-inductor-based high step-up boost converter with low voltage stress compo-nents and soft switching condition, an active clamp high step-up three level coupled-inductor-based boost converter is presented in this paper. The proposed converter hasone magnetic core, and consequently, reduced size. The converter operation is dis-cussed and experimental results of a 200-W prototype converter are reported. Accordingto the experimental results, the voltage stress of switches and diodes are low and low-voltage high-performance semiconductor devices can be used.

Figure 7. (a). CH1: Gate pulse of S1, CH2: Gate pulse of SA, CH3: Output voltage. (b). Voltage andcurrent of S1. (c). Voltage and current of SA. (d). Voltage and current of D.

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Disclosure statement

No potential conflict of interest was reported by the authors.

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Figure 8. Efficiency of the proposed converter.

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